

coreboot-4.0-5175-gb32816e-CBET4000 phcoder-20131225 Wed Dec 25 18:18:53 CET 2013 starting...
PM1_CNT: 00001c00
SMBus controller enabled.
Intel ME early init
Intel ME firmware is ready
ME: Requested 32MB UMA
SMBus controller enabled.
find_current_mrc_cache_local: No valid MRC cache found.
Timings:
channel 0, slot 0, rank 0
lane 0: 20 (20) 73 (7e) 61 (61) 80 (80) 
lane 1: 20 (20) 6a (75) 5c (5c) 7a (7a) 
lane 2: 20 (20) 82 (8d) 75 (75) 93 (93) 
lane 3: 20 (20) 5a (65) 4a (4a) 6a (6a) 
lane 4: 20 (20) ca (d5) aa (aa) c9 (c9) 
lane 5: 20 (20) a4 (af) 7c (7c) 9a (9a) 
lane 6: 20 (20) bc (c7) 98 (98) b8 (b8) 
lane 7: 20 (20) bb (c6) 89 (89) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 72 (7d) 5e (5e) 7d (7d) 
lane 1: 20 (20) 6a (75) 58 (58) 74 (74) 
lane 2: 20 (20) 7f (8a) 72 (72) 91 (91) 
lane 3: 20 (20) 5a (65) 47 (47) 68 (68) 
lane 4: 20 (20) ca (d5) a8 (a8) c7 (c7) 
lane 5: 20 (20) a2 (ad) 7a (7a) 97 (97) 
lane 6: 20 (20) b9 (c4) 96 (96) b6 (b6) 
lane 7: 20 (20) b9 (c4) 88 (88) a6 (a6) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 20 (20) 95 (a0) 61 (61) 7c (7c) 
lane 1: 20 (20) 8b (96) 58 (58) 74 (74) 
lane 2: 20 (20) a3 (ae) 70 (70) 8b (8b) 
lane 3: 20 (20) 78 (83) 4c (4c) 6a (6a) 
lane 4: 20 (20) e2 (ed) ae (ae) ca (ca) 
lane 5: 20 (20) be (c9) 80 (80) 9d (9d) 
lane 6: 20 (20) d6 (e1) 97 (97) b3 (b3) 
lane 7: 20 (20) d4 (df) 89 (89) a5 (a5) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 1
lane 0: 20 (20) 96 (a1) 60 (60) 7b (7b) 
lane 1: 20 (20) 8b (96) 58 (58) 74 (74) 
lane 2: 20 (20) a3 (ae) 70 (70) 8c (8c) 
lane 3: 20 (20) 78 (83) 4b (4b) 6a (6a) 
lane 4: 20 (20) e2 (ed) ad (ad) c9 (c9) 
lane 5: 20 (20) be (c9) 7f (7f) 9b (9b) 
lane 6: 20 (20) d5 (e0) 98 (98) b3 (b3) 
lane 7: 20 (20) d2 (dd) 88 (88) a3 (a3) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
[178] = 38 (0)
[10b] = 0 (0)
Timings:
channel 0, slot 0, rank 0
lane 0: 20 (20) 7e (7e) 61 (61) 80 (80) 
lane 1: 20 (20) 75 (75) 5c (5c) 7a (7a) 
lane 2: 20 (20) 8d (8d) 75 (75) 93 (93) 
lane 3: 20 (20) 65 (65) 4a (4a) 6a (6a) 
lane 4: 20 (20) d5 (d5) aa (aa) c9 (c9) 
lane 5: 20 (20) af (af) 7c (7c) 9a (9a) 
lane 6: 20 (20) c7 (c7) 98 (98) b8 (b8) 
lane 7: 20 (20) c6 (c6) 89 (89) a8 (a8) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 0, slot 0, rank 1
lane 0: 20 (20) 7d (7d) 5e (5e) 7d (7d) 
lane 1: 20 (20) 75 (75) 58 (58) 74 (74) 
lane 2: 20 (20) 8a (8a) 72 (72) 91 (91) 
lane 3: 20 (20) 65 (65) 47 (47) 68 (68) 
lane 4: 20 (20) d5 (d5) a8 (a8) c7 (c7) 
lane 5: 20 (20) ad (ad) 7a (7a) 97 (97) 
lane 6: 20 (20) c4 (c4) 96 (96) b6 (b6) 
lane 7: 20 (20) c4 (c4) 88 (88) a6 (a6) 
lane 8: 15 (20) 100 (10b) 80 (80) 80 (80) 
channel 1, slot 0, rank 0
lane 0: 20 (20) a0 (a0) 61 (61) 7c (7c) 
lane 1: 20 (20) 96 (96) 58 (58) 74 (74) 
lane 2: 20 (20) ae (ae) 70 (70) 8b (8b) 
lane 3: 20 (20) 83 (83) 4c (4c) 6a (

*** Log truncated, 62457 characters dropped. ***

Adding CBMEM entry as no. 3
Adding CBMEM entry as no. 4
Adding CBMEM entry as no. 5
Relocate MRC DATA from ff7ff160 to bf6e0800 (1456 bytes)
ME: FW Partition Table      : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : NO
ME: Manufacturing Mode      : NO
ME: Boot Options Present    : NO
ME: Update In Progress      : NO
ME: Current Working State   : Normal
ME: Current Operation State : Bring up
ME: Current Operation Mode  : Normal
ME: Error Code              : No Error
ME: Progress Phase          : BUP Phase
ME: Power Management Event  : Clean Moff->Mx wake
ME: Progress Phase State    : 0x41
Loading image.
CBFS: loading stage fallback/coreboot_ram @ 0x100000 (503872 bytes), entry @ 0x100000
Jumping to image.
WARNING: you need to define get_top_of_ram() for your chipset
coreboot-4.0-5175-gb32816e-CBET4000 phcoder-20131225 Wed Dec 25 18:18:53 CET 2013 booting...
clocks_per_usec: 2527
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
PNP: 00ff.1: enabled 1
PNP: 00ff.2: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:16.2: enabled 1
PCI: 00:19.0: enabled 1
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1d.0: enabled 1
PCI: 00:1f.0: enabled 1
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
Compare with tree...
Root Device: enabled 1
 PNP: 00ff.1: enabled 1
 PNP: 00ff.2: enabled 1
 CPU_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
 DOMAIN: 0000: enabled 1
  PCI: 00:00.0: enabled 1
  PCI: 00:02.0: enabled 1
  PCI: 00:16.2: enabled 1
  PCI: 00:19.0: enabled 1
  PCI: 00:1a.0: enabled 1
  PCI: 00:1b.0: enabled 1
  PCI: 00:1d.0: enabled 1
  PCI: 00:1f.0: enabled 1
  PCI: 00:1f.2: enabled 1
  PCI: 00:1f.3: enabled 1
starting SPI configuration
SPI configured
 ... pmbase = 0x0500
Keyboard init...
Keyboard controller output buffer result timeout
scan_static_bus for Root Device
PNP: 00ff.1 enabled
recv_ec_data: 0x38
recv_ec_data: 0x56
recv_ec_data: 0x48
recv_ec_data: 0x54
recv_ec_data: 0x33
recv_ec_data: 0x33
recv_ec_data: 0x57
recv_ec_data: 0x57
recv_ec_data: 0x14
recv_ec_data: 0x03
recv_ec_data: 0x40
recv_ec_data: 0x11
EC Firmware ID 8VHT33WW-3.20, Version 4.01B
recv_ec_data: 0x00
recv_ec_data: 0x10
recv_ec_data: 0x20
recv_ec_data: 0x30
recv_ec_data: 0x01
recv_ec_data: 0x70
dock is not connected
PNP: 00ff.2 enabled
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/0044] ops
Normal boot.
PCI: 00:00.0 [8086/0044] enabled
Capability: type 0x0d @ 0x88
Capability: type 0x01 @ 0x80
Capability: type 0x05 @ 0x90
Capability: type 0x10 @ 0xa0
Capability: type 0x0d @ 0x88
Capability: type 0x01 @ 0x80
Capability: type 0x05 @ 0x90
Capability: type 0x10 @ 0xa0
PCI: 00:01.0 subordinate bus PCI Express
PCI: 00:01.0 [8086/0045] enabled
PCI: 00:02.0 [8086/0000] ops
PCI: 00:02.0 [8086/0046] enabled
PCI: 00:16.0 [8086/0000] bus ops
PCI: 00:16.0 [8086/3b64] enabled
PCI: Static device PCI: 00:16.2 not found, disabling it.
PCI: 00:19.0 [8086/10ea] enabled
PCI: 00:1a.0 [8086/0000] ops
PCI: 00:1a.0 [8086/3b3c] enabled
PCI: 00:1b.0 [8086/0000] ops
PCI: 00:1b.0 [8086/3b56] enabled
Capability: type 0x10 @ 0x40
Capability: type 0x05 @ 0x80
Capability: type 0x0d @ 0x90
Capability: type 0x01 @ 0xa0
Capability: type 0x10 @ 0x40
PCI: 00:1c.0 subordinate bus PCI Express
PCI: 00:1c.0 [8086/3b42] enabled
Capability: type 0x10 @ 0x40
Capability: type 0x05 @ 0x80
Capability: type 0x0d @ 0x90
Capability: type 0x01 @ 0xa0
Capability: type 0x10 @ 0x40
PCI: 00:1c.3 subordinate bus PCI Express
PCI: 00:1c.3 [8086/3b48] enabled
Capability: type 0x10 @ 0x40
Capability: type 0x05 @ 0x80
Capability: type 0x0d @ 0x90
Capability: type 0x01 @ 0xa0
Capability: type 0x10 @ 0x40
PCI: 00:1c.4 subordinate bus PCI Express
PCI: 00:1c.4 [8086/3b4a] enabled
PCI: 00:1d.0 [8086/0000] ops
PCI: 00:1d.0 [8086/3b34] enabled
PCI: 00:1e.0 [8086/2448] bus ops
PCI: 00:1e.0 [8086/2448] enabled
PCI: 00:1f.0 [8086/0000] bus ops
PCI: 00:1f.0 [8086/3b07] enabled
PCI: 00:1f.2 [8086/0000] ops
PCI: 00:1f.2 [8086/3b2e] enabled
PCI: 00:1f.3 [8086/0000] bus ops
PCI: 00:1f.3 [8086/3b30] enabled
PCI: 00:1f.6 [8086/0000] ops
PCI: 00:1f.6 [8086/3b32] enabled
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
scan_static_bus for PCI: 00:16.0
scan_static_bus for PCI: 00:16.0 done
do_pci_scan_bridge for PCI: 00:1c.0
PCI: pci_scan_bus for bus 02
PCI: pci_scan_bus returning with max=002
do_pci_scan_bridge returns max 2
do_pci_scan_bridge for PCI: 00:1c.3
PCI: pci_scan_bus for bus 03
PCI: pci_scan_bus returning with max=003
do_pci_scan_bridge returns max 3
do_pci_scan_bridge for PCI: 00:1c.4
PCI: pci_scan_bus for bus 04
PCI: 04:00.0 [8086/4238] enabled
PCI: pci_scan_bus returning with max=004
Capability: type 0x01 @ 0xc8
Capability: type 0x05 @ 0xd0
Capability: type 0x10 @ 0xe0
Capability: type 0x10 @ 0x40
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
do_pci_scan_bridge returns max 4
do_pci_scan_bridge for PCI: 00:1e.0
PCI: pci_scan_bus for bus 05
PCI: pci_scan_bus returning with max=005
do_pci_scan_bridge returns max 5
scan_static_bus for PCI: 00:1f.0
scan_static_bus for PCI: 00:1f.0 done
scan_static_bus for PCI: 00:1f.3
scan_static_bus for PCI: 00:1f.3 done
PCI: pci_scan_bus returning with max=005
scan_static_bus for Root Device done
done
found VGA at PCI: 00:02.0
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
PNP: 00ff.1 missing read_resources
PNP: 00ff.2 missing read_resources
CPU_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0
ram_before_4g_top: 0xbf800000
TOUUD: 0x2380
CBMEM region bf6c0000-bf7fffff (cbmem_late_set_table)
PCI: 00:01.0 read_resources bus 1 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0 done
PCI: 00:1a.0 EHCI BAR hook registered
PCI: 00:1c.0 read_resources bus 2 link: 0
PCI: 00:1c.0 read_resources bus 2 link: 0 done
PCI: 00:1c.3 read_resources bus 3 link: 0
PCI: 00:1c.3 read_resources bus 3 link: 0 done
PCI: 00:1c.4 read_resources bus 4 link: 0
PCI: 00:1c.4 read_resources bus 4 link: 0 done
More than one caller of pci_ehci_read_resources from PCI: 00:1d.0
PCI: 00:1e.0 read_resources bus 5 link: 0
PCI: 00:1e.0 read_resources bus 5 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device child on link 0 PNP: 00ff.1
  PNP: 00ff.1
  PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
  PNP: 00ff.2
  PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
  PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
  PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
  PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
  CPU_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
  DOMAIN: 0000 child on link 0 PCI: 00:00.0
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
   PCI: 00:00.0
   PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
   PCI: 00:00.0 resource base c0000 size bf740000 align 0 gran 0 limit 0 flags e0004200 index 4
   PCI: 00:00.0 resource base bf800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 5
   PCI: 00:00.0 resource base c1c00000 size 400000 align 0 gran 0 limit 0 flags f0000200 index 6
   PCI: 00:00.0 resource base c2000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 7
   PCI: 00:00.0 resource base 100000000 size 138000000 align 0 gran 0 limit 0 flags e0004200 index 8
   PCI: 00:00.0 resource base 1fc000000 size 4000000 align 0 gran 0 limit 0 flags f0004200 index 9
   PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index a
   PCI: 00:00.0 resource base fed00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index b
   PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index c
   PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index d
   PCI: 00:01.0
   PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
   PCI: 00:02.0
   PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10
   PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit ffffffffffffffff flags d0001201 index 18
   PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 20
   PCI: 00:16.0
   PCI: 00:16.0 resource base 0 size 10 align 4 gran 4 limit ffffffffffffffff flags 201 index 10
   PCI: 00:16.2
   PCI: 00:19.0
   PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
   PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
   PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
   PCI: 00:1a.0
   PCI: 00:1a.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
   PCI: 00:1b.0
   PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
   PCI: 00:1c.0
   PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
   PCI: 00:1c.3
   PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
   PCI: 00:1c.4 child on link 0 PCI: 04:00.0
   PCI: 00:1c.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 04:00.0
    PCI: 04:00.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
   PCI: 00:1d.0
   PCI: 00:1d.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
   PCI: 00:1e.0
   PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
   PCI: 00:1f.0
   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
   PCI: 00:1f.2
   PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
   PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
   PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
   PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
   PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:1f.2 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24
   PCI: 00:1f.3
   PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
   PCI: 00:1f.3 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 10
   PCI: 00:1f.6
   PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:19.0 18 *  [0x0 - 0x1f] io
PCI: 00:1f.2 20 *  [0x20 - 0x3f] io
PCI: 00:02.0 20 *  [0x40 - 0x47] io
PCI: 00:1f.2 10 *  [0x48 - 0x4f] io
PCI: 00:1f.2 18 *  [0x50 - 0x57] io
PCI: 00:1f.2 14 *  [0x58 - 0x5b] io
PCI: 00:1f.2 1c *  [0x5c - 0x5f] io
DOMAIN: 0000 compute_resources_io: base: 60 size: 60 align: 5 gran: 0 limit: ffff done
DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 04:00.0 10 *  [0x0 - 0x1fff] mem
PCI: 00:1c.4 compute_resources_mem: base: 2000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:02.0 10 *  [0x0 - 0x3fffff] mem
PCI: 00:1c.4 20 *  [0x400000 - 0x4fffff] mem
PCI: 00:19.0 10 *  [0x500000 - 0x51ffff] mem
PCI: 00:1b.0 10 *  [0x520000 - 0x523fff] mem
PCI: 00:19.0 14 *  [0x524000 - 0x524fff] mem
PCI: 00:1f.6 10 *  [0x525000 - 0x525fff] mem
PCI: 00:1f.2 24 *  [0x526000 - 0x5267ff] mem
PCI: 00:1a.0 10 *  [0x526800 - 0x526bff] mem
PCI: 00:1d.0 10 *  [0x526c00 - 0x526fff] mem
PCI: 00:1f.3 10 *  [0x527000 - 0x5270ff] mem
PCI: 00:16.0 10 *  [0x527100 - 0x52710f] mem
DOMAIN: 0000 compute_resources_mem: base: 527110 size: 527110 align: 22 gran: 0 limit: ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 00:02.0
constrain_resources: PCI: 00:16.0
constrain_resources: PCI: 00:19.0
constrain_resources: PCI: 00:1a.0
constrain_resources: PCI: 00:1b.0
constrain_resources: PCI: 00:1c.0
constrain_resources: PCI: 00:1c.3
constrain_resources: PCI: 00:1c.4
constrain_resources: PCI: 04:00.0
constrain_resources: PCI: 00:1d.0
constrain_resources: PCI: 00:1e.0
constrain_resources: PCI: 00:1f.0
constrain_resources: PCI: 00:1f.2
constrain_resources: PCI: 00:1f.3
constrain_resources: PCI: 00:1f.6
avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff
	lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff
	lim->base c4000000 lim->limit cfffffff
Setting resources...
DOMAIN: 0000 allocate_resources_io: base:1000 size:60 align:5 gran:0 limit:ffff
Assigned: PCI: 00:19.0 18 *  [0x1000 - 0x101f] io
Assigned: PCI: 00:1f.2 20 *  [0x1020 - 0x103f] io
Assigned: PCI: 00:02.0 20 *  [0x1040 - 0x1047] io
Assigned: PCI: 00:1f.2 10 *  [0x1048 - 0x104f] io
Assigned: PCI: 00:1f.2 18 *  [0x1050 - 0x1057] io
Assigned: PCI: 00:1f.2 14 *  [0x1058 - 0x105b] io
Assigned: PCI: 00:1f.2 1c *  [0x105c - 0x105f] io
DOMAIN: 0000 allocate_resources_io: next_base: 1060 size: 60 align: 5 gran: 0 done
PCI: 00:01.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:01.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:1c.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1c.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:1c.3 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1c.3 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:1c.4 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1c.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:1e.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1e.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
DOMAIN: 0000 allocate_resources_mem: base:cf800000 size:527110 align:22 gran:0 limit:cfffffff
Assigned: PCI: 00:02.0 10 *  [0xcf800000 - 0xcfbfffff] mem
Assigned: PCI: 00:1c.4 20 *  [0xcfc00000 - 0xcfcfffff] mem
Assigned: PCI: 00:19.0 10 *  [0xcfd00000 - 0xcfd1ffff] mem
Assigned: PCI: 00:1b.0 10 *  [0xcfd20000 - 0xcfd23fff] mem
Assigned: PCI: 00:19.0 14 *  [0xcfd24000 - 0xcfd24fff] mem
Assigned: PCI: 00:1f.6 10 *  [0xcfd25000 - 0xcfd25fff] mem
Assigned: PCI: 00:1f.2 24 *  [0xcfd26000 - 0xcfd267ff] mem
Assigned: PCI: 00:1a.0 10 *  [0xcfd26800 - 0xcfd26bff] mem
Assigned: PCI: 00:1d.0 10 *  [0xcfd26c00 - 0xcfd26fff] mem
Assigned: PCI: 00:1f.3 10 *  [0xcfd27000 - 0xcfd270ff] mem
Assigned: PCI: 00:16.0 10 *  [0xcfd27100 - 0xcfd2710f] mem
DOMAIN: 0000 allocate_resources_mem: next_base: cfd27110 size: 527110 align: 22 gran: 0 done
PCI: 00:01.0 allocate_resources_prefmem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:01.0 allocate_resources_prefmem: next_base: cfffffff size: 0 align: 20 gran: 20 done
PCI: 00:01.0 allocate_resources_mem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:01.0 allocate_resources_mem: next_base: cfffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.0 allocate_resources_prefmem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:1c.0 allocate_resources_prefmem: next_base: cfffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.0 allocate_resources_mem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:1c.0 allocate_resources_mem: next_base: cfffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.3 allocate_resources_prefmem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:1c.3 allocate_resources_prefmem: next_base: cfffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.3 allocate_resources_mem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:1c.3 allocate_resources_mem: next_base: cfffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.4 allocate_resources_prefmem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:1c.4 allocate_resources_prefmem: next_base: cfffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.4 allocate_resources_mem: base:cfc00000 size:100000 align:20 gran:20 limit:cfffffff
Assigned: PCI: 04:00.0 10 *  [0xcfc00000 - 0xcfc01fff] mem
PCI: 00:1c.4 allocate_resources_mem: next_base: cfc02000 size: 100000 align: 20 gran: 20 done
PCI: 00:1e.0 allocate_resources_prefmem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:1e.0 allocate_resources_prefmem: next_base: cfffffff size: 0 align: 20 gran: 20 done
PCI: 00:1e.0 allocate_resources_mem: base:cfffffff size:0 align:20 gran:20 limit:cfffffff
PCI: 00:1e.0 allocate_resources_mem: next_base: cfffffff size: 0 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
PNP: 00ff.1 missing set_resources
PNP: 00ff.2 missing set_resources
DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 01 mem
PCI: 00:02.0 10 <- [0x00cf800000 - 0x00cfbfffff] size 0x00400000 gran 0x16 mem64
PCI: 00:02.0 20 <- [0x0000001040 - 0x0000001047] size 0x00000008 gran 0x03 io
PCI: 00:16.0 10 <- [0x00cfd27100 - 0x00cfd2710f] size 0x00000010 gran 0x04 mem64
PCI: 00:19.0 10 <- [0x00cfd00000 - 0x00cfd1ffff] size 0x00020000 gran 0x11 mem
PCI: 00:19.0 14 <- [0x00cfd24000 - 0x00cfd24fff] size 0x00001000 gran 0x0c mem
PCI: 00:19.0 18 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io
PCI: 00:1a.0 EHCI Debug Port hook triggered
PCI: 00:1a.0 10 <- [0x00cfd26800 - 0x00cfd26bff] size 0x00000400 gran 0x0a mem
PCI: 00:1a.0 10 <- [0x00cfd26800 - 0x00cfd26bff] size 0x00000400 gran 0x0a mem
PCI: 00:1a.0 EHCI Debug Port relocated
PCI: 00:1b.0 10 <- [0x00cfd20000 - 0x00cfd23fff] size 0x00004000 gran 0x0e mem64
PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:1c.0 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:1c.0 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 02 mem
PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io
PCI: 00:1c.3 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 03 prefmem
PCI: 00:1c.3 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 03 mem
PCI: 00:1c.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io
PCI: 00:1c.4 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 04 prefmem
PCI: 00:1c.4 20 <- [0x00cfc00000 - 0x00cfcfffff] size 0x00100000 gran 0x14 bus 04 mem
PCI: 00:1c.4 assign_resources, bus 4 link: 0
PCI: 04:00.0 10 <- [0x00cfc00000 - 0x00cfc01fff] size 0x00002000 gran 0x0d mem64
PCI: 00:1c.4 assign_resources, bus 4 link: 0
PCI: 00:1d.0 10 <- [0x00cfd26c00 - 0x00cfd26fff] size 0x00000400 gran 0x0a mem
PCI: 00:1e.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io
PCI: 00:1e.0 24 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 05 prefmem
PCI: 00:1e.0 20 <- [0x00cfffffff - 0x00cffffffe] size 0x00000000 gran 0x14 bus 05 mem
PCI: 00:1f.2 10 <- [0x0000001048 - 0x000000104f] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 14 <- [0x0000001058 - 0x000000105b] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 18 <- [0x0000001050 - 0x0000001057] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 1c <- [0x000000105c - 0x000000105f] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 20 <- [0x0000001020 - 0x000000103f] size 0x00000020 gran 0x05 io
PCI: 00:1f.2 24 <- [0x00cfd26000 - 0x00cfd267ff] size 0x00000800 gran 0x0b mem
PCI: 00:1f.3 10 <- [0x00cfd27000 - 0x00cfd270ff] size 0x00000100 gran 0x08 mem64
PCI: 00:1f.6 10 <- [0x00cfd25000 - 0x00cfd25fff] size 0x00001000 gran 0x0c mem64
DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device child on link 0 PNP: 00ff.1
  PNP: 00ff.1
  PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
  PNP: 00ff.2
  PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
  PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
  PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
  PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
  CPU_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
  DOMAIN: 0000 child on link 0 PCI: 00:00.0
  DOMAIN: 0000 resource base 1000 size 60 align 5 gran 0 limit ffff flags 40040100 index 10000000
  DOMAIN: 0000 resource base cf800000 size 527110 align 22 gran 0 limit cfffffff flags 40040200 index 10000100
   PCI: 00:00.0
   PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
   PCI: 00:00.0 resource base c0000 size bf740000 align 0 gran 0 limit 0 flags e0004200 index 4
   PCI: 00:00.0 resource base bf800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 5
   PCI: 00:00.0 resource base c1c00000 size 400000 align 0 gran 0 limit 0 flags f0000200 index 6
   PCI: 00:00.0 resource base c2000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 7
   PCI: 00:00.0 resource base 100000000 size 138000000 align 0 gran 0 limit 0 flags e0004200 index 8
   PCI: 00:00.0 resource base 1fc000000 size 4000000 align 0 gran 0 limit 0 flags f0004200 index 9
   PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index a
   PCI: 00:00.0 resource base fed00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index b
   PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index c
   PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index d
   PCI: 00:01.0
   PCI: 00:01.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:01.0 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60081202 index 24
   PCI: 00:01.0 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60080202 index 20
   PCI: 00:02.0
   PCI: 00:02.0 resource base cf800000 size 400000 align 22 gran 22 limit cfffffff flags 60000201 index 10
   PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit ffffffffffffffff flags d0001201 index 18
   PCI: 00:02.0 resource base 1040 size 8 align 3 gran 3 limit ffff flags 60000100 index 20
   PCI: 00:16.0
   PCI: 00:16.0 resource base cfd27100 size 10 align 4 gran 4 limit cfffffff flags 60000201 index 10
   PCI: 00:16.2
   PCI: 00:19.0
   PCI: 00:19.0 resource base cfd00000 size 20000 align 17 gran 17 limit cfffffff flags 60000200 index 10
   PCI: 00:19.0 resource base cfd24000 size 1000 align 12 gran 12 limit cfffffff flags 60000200 index 14
   PCI: 00:19.0 resource base 1000 size 20 align 5 gran 5 limit ffff flags 60000100 index 18
   PCI: 00:1a.0
   PCI: 00:1a.0 resource base cfd26800 size 400 align 10 gran 10 limit cfffffff flags 60000200 index 10
   PCI: 00:1b.0
   PCI: 00:1b.0 resource base cfd20000 size 4000 align 14 gran 14 limit cfffffff flags 60000201 index 10
   PCI: 00:1c.0
   PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:1c.0 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60081202 index 24
   PCI: 00:1c.0 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60080202 index 20
   PCI: 00:1c.3
   PCI: 00:1c.3 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:1c.3 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60081202 index 24
   PCI: 00:1c.3 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60080202 index 20
   PCI: 00:1c.4 child on link 0 PCI: 04:00.0
   PCI: 00:1c.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:1c.4 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60081202 index 24
   PCI: 00:1c.4 resource base cfc00000 size 100000 align 20 gran 20 limit cfffffff flags 60080202 index 20
    PCI: 04:00.0
    PCI: 04:00.0 resource base cfc00000 size 2000 align 13 gran 13 limit cfffffff flags 60000201 index 10
   PCI: 00:1d.0
   PCI: 00:1d.0 resource base cfd26c00 size 400 align 10 gran 10 limit cfffffff flags 60000200 index 10
   PCI: 00:1e.0
   PCI: 00:1e.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:1e.0 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60081202 index 24
   PCI: 00:1e.0 resource base cfffffff size 0 align 20 gran 20 limit cfffffff flags 60080202 index 20
   PCI: 00:1f.0
   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
   PCI: 00:1f.2
   PCI: 00:1f.2 resource base 1048 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
   PCI: 00:1f.2 resource base 1058 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
   PCI: 00:1f.2 resource base 1050 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
   PCI: 00:1f.2 resource base 105c size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
   PCI: 00:1f.2 resource base 1020 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
   PCI: 00:1f.2 resource base cfd26000 size 800 align 11 gran 11 limit cfffffff flags 60000200 index 24
   PCI: 00:1f.3
   PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
   PCI: 00:1f.3 resource base cfd27000 size 100 align 8 gran 8 limit cfffffff flags 60000201 index 10
   PCI: 00:1f.6
   PCI: 00:1f.6 resource base cfd25000 size 1000 align 12 gran 12 limit cfffffff flags 60000201 index 10
Done allocating resources.
Enabling resources...
PCI: 00:00.0 subsystem <- 17aa/2193
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 0003
PCI: 00:01.0 cmd <- 00
PCI: 00:02.0 subsystem <- 17aa/215a
PCI: 00:02.0 cmd <- 03
PCI: 00:16.0 cmd <- 02
PCI: 00:19.0 subsystem <- 17aa/2153
PCI: 00:19.0 cmd <- 03
PCI: 00:1b.0 subsystem <- 17aa/215e
PCI: 00:1b.0 cmd <- 02
PCI: 00:1c.0 bridge ctrl <- 0003
PCI: 00:1c.0 cmd <- 00
PCI: 00:1c.3 bridge ctrl <- 0003
PCI: 00:1c.3 cmd <- 00
PCI: 00:1c.4 bridge ctrl <- 0003
PCI: 00:1c.4 cmd <- 06
PCI: 00:1e.0 bridge ctrl <- 0003
PCI: 00:1e.0 cmd <- 00 (NOT WRITTEN!)
pch_decode_init
PCI: 00:1f.0 subsystem <- 17aa/2166
PCI: 00:1f.0 cmd <- 107
PCI: 00:1f.2 subsystem <- 17aa/2168
PCI: 00:1f.2 cmd <- 03
PCI: 00:1f.3 subsystem <- 17aa/2167
PCI: 00:1f.3 cmd <- 03
PCI: 00:1f.6 cmd <- 02
PCI: 04:00.0 cmd <- 02
done.
Initializing devices...
Root Device init
CPU_CLUSTER: 0 init
start_eip=0x00001000, code_size=0x00000031
Installing SMM handler to 0xbf800000
Installing IED header to 0xbfc00000
Initializing SMM handler... ... pmbase = 0x0500

SMI_STS: MCSMI PM1 
PM1_STS: WAK BM TMROF 
GPE0_STS: GPIO14 GPIO11 GPIO9 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 
ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 
TCO_STS: 
  ... raise SMI#
Initializing CPU #0
CPU: vendor Intel device 20655
CPU: family 06, model 25, stepping 05
Enabling cache
microcode: sig=0x20655 pf=0x10 revision=0x3
CPU: Intel(R) Core(TM) i5 CPU       M 540  @ 2.53GHz.
CPU:lapic=0, boot_cpu=1
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x00000000bf800000 size 0xbf740000 type 6
0x00000000bf800000 - 0x00000000ff800000 size 0x40000000 type 0
0x00000000ff800000 - 0x0000000100000000 size 0x00800000 type 5
0x0000000100000000 - 0x0000000238000000 size 0x138000000 type 6
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
MTRR: default type WB/UC MTRR counts: 9/8.
MTRR: UC selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
MTRR: 1 base 0x0000000080000000 mask 0x0000000fc0000000 type 6
MTRR: 2 base 0x00000000bf800000 mask 0x0000000fff800000 type 0
MTRR: 3 base 0x00000000ff800000 mask 0x0000000fff800000 type 0
MTRR: 4 base 0x0000000100000000 mask 0x0000000f00000000 type 6
MTRR: 5 base 0x0000000200000000 mask 0x0000000fe0000000 type 6
Taking a reserved OS MTRR.
MTRR: 6 base 0x0000000220000000 mask 0x0000000ff0000000 type 6
Taking a reserved OS MTRR.
MTRR: 7 base 0x0000000230000000 mask 0x0000000ff8000000 type 6

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 0x00 done.
Enabling VMX
model_x06ax: frequency set to 2527
Turbo is available and visible
CPU: 0 has 2 cores, 2 threads per core
CPU: 0 has core 1
CPU1: stack_base 00175000, stack_end 00175ff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 1.
After apic_write.
Initializing CPU #1
Startup point 1.
CPU: vendor Intel device 20655
Waiting for send to finish...
CPU: family 06, model 25, stepping 05
+Enabling cache
Sending STARTUP #2 to 1.
After apic_write.
microcode: sig=0x20655 pf=0x10 revision=0x3
CPU: Intel(R) Core(TM) i5 CPU       M 540  @ 2.53GHz.
CPU:lapic=1, boot_cpu=0
Startup point 1.
MTRR: Fixed MSR 0x250 0x0606060606060606
Waiting for send to finish...
MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
After Startup.
MTRR: Fixed MSR 0x268 0x0606060606060606
CPU: 0 has core 4
MTRR: Fixed MSR 0x269 0x0606060606060606
CPU2: stack_base 00174000, stack_end 00174ff8
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
Asserting INIT.
MTRR: Fixed MSR 0x26f 0x0606060606060606
Waiting for send to finish...
call enable_fixed_mtrr()
+Deasserting INIT.
MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
Waiting for send to finish...
MTRR: 1 base 0x0000000080000000 mask 0x0000000fc0000000 type 6
+MTRR: 2 base 0x00000000bf800000 mask 0x0000000fff800000 type 0
#startup loops: 2.
MTRR: 3 base 0x00000000ff800000 mask 0x0000000fff800000 type 0
Sending STARTUP #1 to 4.
MTRR: 4 base 0x0000000100000000 mask 0x0000000f00000000 type 6
After apic_write.
MTRR: 5 base 0x0000000200000000 mask 0x0000000fe0000000 type 6
Initializing CPU #2
Startup point 1.
Taking a reserved OS MTRR.
CPU: vendor Intel device 20655
Waiting for send to finish...
CPU: family 06, model 25, stepping 05
MTRR: 6 base 0x0000000220000000 mask 0x0000000ff0000000 type 6
Enabling cache
Taking a reserved OS MTRR.
microcode: sig=0x20655 pf=0x10 revision=0x0
MTRR: 7 base 0x0000000230000000 mask 0x0000000ff8000000 type 6
microcode: updated to revision 0x3 date=2011-09-01

MTRR check
+Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 0x01 done.
Enabling VMX
model_x06ax: frequency set to 2527
CPU #1 initialized
CPU: Intel(R) Core(TM) i5 CPU       M 540  @ 2.53GHz.
Sending STARTUP #2 to 4.
After apic_write.
CPU:lapic=4, boot_cpu=0
Startup point 1.
Waiting for send to finish...
+After Startup.
CPU: 0 has core 5
CPU3: stack_base 00173000, stack_end 00173ff8
Asserting INIT.
Waiting for send to finish...
+MTRR: Fixed MSR 0x250 0x0606060606060606
Deasserting INIT.
Waiting for send to finish...
+MTRR: Fixed MSR 0x258 0x0606060606060606
#startup loops: 2.
Sending STARTUP #1 to 5.
After apic_write.
MTRR: Fixed MSR 0x259 0x0000000000000000
Startup point 1.
Waiting for send to finish...
+Initializing CPU #3
Sending STARTUP #2 to 5.
After apic_write.
MTRR: Fixed MSR 0x268 0x0606060606060606
Startup point 1.
Waiting for send to finish...
+CPU: vendor Intel device 20655
After Startup.
CPU #0 initialized
Waiting for 2 CPUS to stop
MTRR: Fixed MSR 0x269 0x0606060606060606
CPU: family 06, model 25, stepping 05
MTRR: Fixed MSR 0x26a 0x0606060606060606
Enabling cache
MTRR: Fixed MSR 0x26b 0x0606060606060606
microcode: sig=0x20655 pf=0x10 revision=0x3
MTRR: Fixed MSR 0x26c 0x0606060606060606
CPU: Intel(R) Core(TM) i5 CPU       M 540  @ 2.53GHz.
MTRR: Fixed MSR 0x26d 0x0606060606060606
CPU:lapic=5, boot_cpu=0
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
call enable_fixed_mtrr()
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: 1 base 0x0000000080000000 mask 0x0000000fc0000000 type 6
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: 2 base 0x00000000bf800000 mask 0x0000000fff800000 type 0
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: 3 base 0x00000000ff800000 mask 0x0000000fff800000 type 0
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: 4 base 0x0000000100000000 mask 0x0000000f00000000 type 6
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: 5 base 0x0000000200000000 mask 0x0000000fe0000000 type 6
MTRR: Fixed MSR 0x26d 0x0606060606060606
Taking a reserved OS MTRR.
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: 6 base 0x0000000220000000 mask 0x0000000ff0000000 type 6
MTRR: Fixed MSR 0x26f 0x0606060606060606
Taking a reserved OS MTRR.
call enable_fixed_mtrr()
MTRR: 7 base 0x0000000230000000 mask 0x0000000ff8000000 type 6
MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6

MTRR check
MTRR: 1 base 0x0000000080000000 mask 0x0000000fc0000000 type 6
Fixed MTRRs   : MTRR: 2 base 0x00000000bf800000 mask 0x0000000fff800000 type 0
Enabled
MTRR: 3 base 0x00000000ff800000 mask 0x0000000fff800000 type 0
Variable MTRRs: MTRR: 4 base 0x0000000100000000 mask 0x0000000f00000000 type 6
Enabled
MTRR: 5 base 0x0000000200000000 mask 0x0000000fe0000000 type 6

Taking a reserved OS MTRR.
Setting up local apic...MTRR: 6 base 0x0000000220000000 mask 0x0000000ff0000000 type 6
 apic_id: 0x04 Taking a reserved OS MTRR.
done.
MTRR: 7 base 0x0000000230000000 mask 0x0000000ff8000000 type 6
Enabling VMX

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic...model_x06ax: frequency set to 2527
 apic_id: 0x05 done.
CPU #2 initialized
Enabling VMX
Waiting for 1 CPUS to stop
model_x06ax: frequency set to 2527
CPU #3 initialized
All AP CPUs stopped (8200 loops)
CPU1: stack: 00175000 - 00176000, lowest used address 00175c1c, stack used: 996 bytes
CPU2: stack: 00174000 - 00175000, lowest used address 00174c1c, stack used: 996 bytes
CPU3: stack: 00173000 - 00174000, lowest used address 00173c1c, stack used: 996 bytes
PCI: 00:00.0 init
Set BIOS_RESET_CPL
PCI: 00:02.0 init
GT Power Management Init
IVB GT1 Power Meter Weights
GT init timeout
GT Power Management Init (post VBIOS)
GT init timeout
PCI: 00:16.0 init
ME: FW Partition Table      : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : YES
ME: Manufacturing Mode      : YES
ME: Boot Options Present    : NO
ME: Update In Progress      : NO
ME: Current Working State   : Recovery
ME: Current Operation State : M0 with UMA
ME: Current Operation Mode  : Normal
ME: Error Code              : No Error
ME: Progress Phase          : Host Communication
ME: Power Management Event  : Intel ME reset due to exception
ME: Progress Phase State    : Host communication established
ME: BIOS path: Recovery
PCI: 00:19.0 init
PCI: 00:1a.0 init
EHCI: Setting up controller.. done.
PCI: 00:1b.0 init
Azalia: base = cfd20000
Azalia: V1CTL disabled.
Azalia: codec_mask = 09
Azalia: Initializing codec #3
Azalia: codec viddid: 80862804
Azalia: No verb!
Azalia: Initializing codec #0
Azalia: codec viddid: 14f15069
Azalia: No verb!
PCI: 00:1d.0 init
EHCI: Setting up controller.. done.
PCI: 00:1e.0 init
PCI init.
PCI: 00:1f.0 init
pch: lpc_init
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x01
IOAPIC: Dumping registers
  reg 0x0000: 0x01000000
  reg 0x0001: 0x00170020
  reg 0x0002: 0x00170020
Set power off after power failure.
NMI sources disabled.
Mobile 5 PM init
rtc_failed = 0x0
RTC Init
i8259_configure_irq_trigger: current interrupts are 0x0
i8259_configure_irq_trigger: try to set interrupts 0x200
Enabling BIOS updates outside of SMM... Disabling ACPI via APMC:
done.
Locking SMM.
PCI: 00:1f.2 init
SATA: Initializing...
SATA: Controller in AHCI mode.
ABAR: CFD26000
PCI: 00:1f.3 init
PCI: 00:1f.6 init
Thermal init start.
Thermal init done.
PCI: 04:00.0 init
Devices initialized
Show all devs...After init.
Root Device: enabled 1
PNP: 00ff.1: enabled 1
PNP: 00ff.2: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:16.2: enabled 0
PCI: 00:19.0: enabled 1
PCI: 00:1a.0: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1d.0: enabled 1
PCI: 00:1f.0: enabled 1
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:1c.0: enabled 1
PCI: 00:1c.3: enabled 1
PCI: 00:1c.4: enabled 1
PCI: 00:1e.0: enabled 1
PCI: 00:1f.6: enabled 1
PCI: 04:00.0: enabled 1
APIC: 01: enabled 1
APIC: 04: enabled 1
APIC: 05: enabled 1
CBMEM region bf6c0000-bf7fffff (cbmem_reinit)
Adding CBMEM entry as no. 6
Moving GDT to bf6e0e00...ok
Finalize devices...
Devices finalized
Updating MRC cache data.
find_current_mrc_cache_local: No valid MRC cache found.
SF: Detected MX25L6405D with page size 1000, total 800000
Need to erase the MRC cache region of 0 bytes at fff80000
SF: Successfully erased 0 bytes @ 0x780000
Finally: write MRC cache update to flash at fff80000
CBMEM Base is bf6c0000.
Copying Interrupt Routing Table to 0x000f0000... done.
Adding CBMEM entry as no. 7
Copying Interrupt Routing Table to 0xbf6e1000... done.
PIRQ table: 288 bytes.
Wrote the mp table end at: 000f0410 - 000f05d4
Adding CBMEM entry as no. 8
Wrote the mp table end at: bf6e2010 - bf6e21d4
MP table: 468 bytes.
Adding CBMEM entry as no. 9
ACPI: Writing ACPI tables at bf6e3000.
ACPI:    * HPET
ACPI: added table 1/32, length now 40
ACPI:    * MADT
ACPI: added table 2/32, length now 44
ACPI:    * MCFG
ACPI: added table 3/32, length now 48
ACPI:     * FACS
ACPI: Patching up global NVS in DSDT at offset 0x020d -> 0xbf6e6d20
ACPI:     * DSDT @ bf6e3360 Length 39c0
ACPI:     * FADT
ACPI: added table 4/32, length now 52
ACPI:     * SSDT
Found 1 CPU(s) with 4 core(s) each.
PSS: 2534MHz power 25000 control 0x17 status 0x17
PSS: 2533MHz power 25000 control 0x13 status 0x13
PSS: 2400MHz power 23390 control 0x12 status 0x12
PSS: 2266MHz power 21835 control 0x11 status 0x11
PSS: 2133MHz power 20334 control 0x10 status 0x10
PSS: 2000MHz power 18817 control 0xf status 0xf
PSS: 1866MHz power 17351 control 0xe status 0xe
PSS: 1733MHz power 15937 control 0xd status 0xd
PSS: 1600MHz power 14528 control 0xc status 0xc
PSS: 1466MHz power 13163 control 0xb status 0xb
PSS: 1333MHz power 11835 control 0xa status 0xa
PSS: 1200MHz power 10512 control 0x9 status 0x9
PSS: 2534MHz power 25000 control 0x17 status 0x17
PSS: 2533MHz power 25000 control 0x13 status 0x13
PSS: 2400MHz power 23390 control 0x12 status 0x12
PSS: 2266MHz power 21835 control 0x11 status 0x11
PSS: 2133MHz power 20334 control 0x10 status 0x10
PSS: 2000MHz power 18817 control 0xf status 0xf
PSS: 1866MHz power 17351 control 0xe status 0xe
PSS: 1733MHz power 15937 control 0xd status 0xd
PSS: 1600MHz power 14528 control 0xc status 0xc
PSS: 1466MHz power 13163 control 0xb status 0xb
PSS: 1333MHz power 11835 control 0xa status 0xa
PSS: 1200MHz power 10512 control 0x9 status 0x9
PSS: 2534MHz power 25000 control 0x17 status 0x17
PSS: 2533MHz power 25000 control 0x13 status 0x13
PSS: 2400MHz power 23390 control 0x12 status 0x12
PSS: 2266MHz power 21835 control 0x11 status 0x11
PSS: 2133MHz power 20334 control 0x10 status 0x10
PSS: 2000MHz power 18817 control 0xf status 0xf
PSS: 1866MHz power 17351 control 0xe status 0xe
PSS: 1733MHz power 15937 control 0xd status 0xd
PSS: 1600MHz power 14528 control 0xc status 0xc
PSS: 1466MHz power 13163 control 0xb status 0xb
PSS: 1333MHz power 11835 control 0xa status 0xa
PSS: 1200MHz power 10512 control 0x9 status 0x9
PSS: 2534MHz power 25000 control 0x17 status 0x17
PSS: 2533MHz power 25000 control 0x13 status 0x13
PSS: 2400MHz power 23390 control 0x12 status 0x12
PSS: 2266MHz power 21835 control 0x11 status 0x11
PSS: 2133MHz power 20334 control 0x10 status 0x10
PSS: 2000MHz power 18817 control 0xf status 0xf
PSS: 1866MHz power 17351 control 0xe status 0xe
PSS: 1733MHz power 15937 control 0xd status 0xd
PSS: 1600MHz power 14528 control 0xc status 0xc
PSS: 1466MHz power 13163 control 0xb status 0xb
PSS: 1333MHz power 11835 control 0xa status 0xa
PSS: 1200MHz power 10512 control 0x9 status 0x9
ACPI: added table 5/32, length now 56
current = bf6e7cf0
ACPI: done.
Laptop handling...
ACPI tables: 19696 bytes.
Adding CBMEM entry as no. 10
smbios_write_tables: bf6ee400
Root Device (LENOVO 3626EN1)
PNP: 00ff.1 (Lenovo Power Management Hardware Hub 7)
PNP: 00ff.2 (Lenovo H8 EC)
CPU_CLUSTER: 0 (Intel i7 (Nehalem) integrated Northbridge)
APIC: 00 (unknown)
DOMAIN: 0000 (Intel i7 (Nehalem) integrated Northbridge)
PCI: 00:00.0 (Intel i7 (Nehalem) integrated Northbridge)
PCI: 00:02.0 (Intel i7 (Nehalem) integrated Northbridge)
PCI: 00:16.2 (unknown)
PCI: 00:19.0 (unknown)
PCI: 00:1a.0 (unknown)
PCI: 00:1b.0 (unknown)
PCI: 00:1d.0 (unknown)
PCI: 00:1f.0 (unknown)
PCI: 00:1f.2 (unknown)
PCI: 00:1f.3 (unknown)
PCI: 00:01.0 (unknown)
PCI: 00:16.0 (unknown)
PCI: 00:1c.0 (unknown)
PCI: 00:1c.3 (unknown)
PCI: 00:1c.4 (unknown)
PCI: 00:1e.0 (unknown)
PCI: 00:1f.6 (unknown)
PCI: 04:00.0 (unknown)
APIC: 01 (unknown)
APIC: 04 (unknown)
APIC: 05 (unknown)
SMBIOS tables: 320 bytes.
Adding CBMEM entry as no. 11
Adding CBMEM entry as no. 12
Writing table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 545f
Table forward entry ends at 0x00000528.
... aligned to 0x00001000
Writing coreboot table at 0xbf7eec00
rom_table_end = 0xbf7eec00
... aligned to 0xbf7f0000
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000a0000-00000000000fffff: RESERVED
 3. 0000000000100000-00000000bf6bffff: RAM
 4. 00000000bf6c0000-00000000bf7fffff: CONFIGURATION TABLES
 5. 00000000bf800000-00000000bfffffff: RESERVED
 6. 00000000c1c00000-00000000c3ffffff: RESERVED
 7. 00000000d0000000-00000000efffffff: RESERVED
 8. 00000000fed00000-00000000fedfffff: RESERVED
 9. 0000000100000000-00000001fbffffff: RAM
10. 00000001fc000000-00000001ffffffff: RESERVED
11. 0000000200000000-0000000237ffffff: RAM
Wrote coreboot table at: bf7eec00, 0x2a4 bytes, checksum f4ab
coreboot table: 700 bytes.
Multiboot Information structure has been written.
FREE SPACE  0. bf7f6c00 00009400
CAR GLOBALS 1. bf6c0200 00000200
CONSOLE     2. bf6c0400 00020000
TIME STAMP  3. bf6e0400 00000200
USBDEBUG    4. bf6e0600 00000200
MRC DATA    5. bf6e0800 00000600
GDT         6. bf6e0e00 00000200
IRQ TABLE   7. bf6e1000 00001000
SMP TABLE   8. bf6e2000 00001000
ACPI        9. bf6e3000 0000b400
SMBIOS     10. bf6ee400 00000800
ACPI RESUME11. bf6eec00 00100000
COREBOOT   12. bf7eec00 00008000
Loading segment from rom address 0xfff278f8
  code (compression=1)
  New segment dstaddr 0x8200 memsize 0x17c38 srcaddr 0xfff2794c filesize 0x8312
  (cleaned up) New segment addr 0x8200 size 0x17c38 offset 0xfff2794c filesize 0x8312
Loading segment from rom address 0xfff27914
  code (compression=1)
  New segment dstaddr 0x100000 memsize 0x8c640 srcaddr 0xfff2fc5e filesize 0x2c01a
  (cleaned up) New segment addr 0x100000 size 0x8c640 offset 0xfff2fc5e filesize 0x2c01a
Loading segment from rom address 0xfff27930
  Entry Point 0x00008200
Loading Segment: addr: 0x0000000000008200 memsz: 0x0000000000017c38 filesz: 0x0000000000008312
lb: [0x0000000000100000, 0x000000000017b040)
Post relocation: addr: 0x0000000000008200 memsz: 0x0000000000017c38 filesz: 0x0000000000008312
using LZMA
[ 0x00008200, 00018507, 0x0001fe38) <- fff2794c
Clearing Segment: addr: 0x0000000000018507 memsz: 0x0000000000007931
dest 00008200, end 0001fe38, bouncebuffer bf5b8980
Loading Segment: addr: 0x0000000000100000 memsz: 0x000000000008c640 filesz: 0x000000000002c01a
lb: [0x0000000000100000, 0x000000000017b040)
segment: [0x0000000000100000, 0x000000000012c01a, 0x000000000018c640)
 bounce: [0x00000000bf5b8980, 0x00000000bf5e499a, 0x00000000bf644fc0)
Post relocation: addr: 0x00000000bf5b8980 memsz: 0x000000000008c640 filesz: 0x000000000002c01a
using LZMA
[ 0xbf5b8980, bf644fc0, 0xbf644fc0) <- fff2fc5e
dest bf5b8980, end bf644fc0, bouncebuffer bf5b8980
move suffix around: from bf6339c0, to 17b040, amount: 11600
Loaded segments
PCH watchdog disabled
Jumping to boot code at 00008200
CPU0: stack: 00176000 - 00177000, lowest used address 00176a78, stack used: 1416 bytes
entry    = 0x00008200
lb_start = 0x00100000
lb_size  = 0x0007b040
buffer   = 0xbf5b8980