

coreboot-4.0-6741-g7aa704b Mon Aug 18 00:07:08 CEST 2014 starting...

Mobile Intel(R) 82945GM/GME Express Chipset
(G)MCH capable of up to FSB 800 MHz
(G)MCH capable of up to DDR2-667
Setting up static southbridge registers... GPIOS... done.
Disabling Watchdog reboot... done.
Setting up static northbridge registers... done.
Waiting for MCHBAR to come up...ok
PM1_CNT: 00001c00
SMBus controller enabled.
Setting up RAM controller.
This mainboard supports Dual Channel Operation.
DDR II Channel 0 Socket 0: x16DS
DDR II Channel 1 Socket 0: x16DS
Memory will be driven at 667MHz with CAS=5 clocks
tRAS = 15 cycles
tRP = 5 cycles
tRCD = 5 cycles
Refresh: 7.8us
tWR = 5 cycles
DIMM 0 side 0 = 256 MB
DIMM 0 side 1 = 256 MB
DIMM 2 side 0 = 256 MB
DIMM 2 side 1 = 256 MB
tRFC = 35 cycles
Setting Graphics Frequency...
FSB: 667 MHz Voltage: 1.05V Render: 250MHz Display: 200MHz
Setting Memory Frequency... CLKCFG=0x00010023, CLKCFG=0x00010043, ok
Setting mode of operation for memory channels...Dual Channel Interleaved.
Programming Clock Crossing...MEM=667 FSB=667... ok
Setting RAM size...
C0DRB = 0x10101008
C1DRB = 0x10101008
TOLUD = 0x0040
Setting row attributes... 
C0DRA = 0x0033
C1DRA = 0x0033
one dimm per channel config.. 
Initializing System Memory IO... 
Programming Dual Channel RCOMP
Table Index: 0
Programming DLL Timings... 
Enabling System Memory IO... 
jedec enable sequence: bank 0
jedec enable sequence: bank 1
bankaddr from bank size of rank 0
jedec enable sequence: bank 4
jedec enable sequence: bank 5
bankaddr from bank size of rank 4
receive_enable_autoconfig() for channel 0
  find_strobes_low()
    set_receive_enable() medium=0x3, coarse=0x5
    set_receive_enable() medium=0x1, coarse=0x5
  find_strobes_edge()
    set_receive_enable() medium=0x1, coarse=0x5
  add_quarter_clock() mediumcoarse=15 fine=b6
    set_receive_enable() medium=0x3, coarse=0x5
  find_preamble()
    set_receive_enable() medium=0x3, coarse=0x4
    set_receive_enable() medium=0x3, coarse=0x3
  add_quarter_clock() mediumcoarse=0f fine=36
  normalize()
    set_receive_enable() medium=0x0, coarse=0x4
receive_enable_autoconfig() for channel 1
  find_strobes_low()
    set_receive_enable() medium=0x3, coarse=0x5
    set_receive_enable() medium=0x1, coarse=0x5
  find_strobes_edge()
    set_receive_enable() medium=0x1, coarse=0x5
  add_quarter_clock() mediumcoarse=15 fine=b0
    set_receive_enable() medium=0x3, coarse=0x5
  find_preamble()
    set_receive_enable() medium=0x3, coarse=0x4
    set_receive_enable() medium=0x3, coarse=0x3
  add_quarter_clock() mediumcoarse=0f fine=30
  normalize()
    set_receive_enable() medium=0x0, coarse=0x4
RAM initialization finished.
Setting up Egress Port RCRB
Loading port arbitration table ...ok
Wait for VC1 negotiation ...ok
Setting up DMI RCRB
Wait for VC1 negotiation ...done..
Internal graphics: enabled
Waiting for DMI hardware...ok
Enabling PCI Ex

*** Log truncated, 177 characters dropped. ***

Trying CBFS ramstage loader.
CBFS: loading stage fallback/ramstage @ 0x100000 (270396 bytes), entry @ 0x100000
coreboot-4.0-6741-g7aa704b Mon Aug 18 00:07:08 CEST 2014 booting...
BS: Entering BS_PRE_DEVICE state.
CBMEM: recovering 5/254 entries from root @ 3f7ff000
Moving GDT to 3f7eb000...ok
BS: Exiting BS_PRE_DEVICE state.
BS: BS_PRE_DEVICE times (us): entry 21 run 17 exit 0
BS: Entering BS_DEV_INIT_CHIPS state.
BS: Exiting BS_DEV_INIT_CHIPS state.
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 21 exit 0
BS: Entering BS_DEV_ENUMERATE state.
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:02.1: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 1
PCI: 00:1c.1: enabled 1
PCI: 00:1d.0: enabled 1
PCI: 00:1d.1: enabled 1
PCI: 00:1d.2: enabled 1
PCI: 00:1d.3: enabled 1
PCI: 00:1d.7: enabled 1
PCI: 00:1f.0: enabled 1
PCI: 00:1f.1: enabled 1
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
Compare with tree...
Root Device: enabled 1
 CPU_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
 DOMAIN: 0000: enabled 1
  PCI: 00:00.0: enabled 1
  PCI: 00:02.0: enabled 1
  PCI: 00:02.1: enabled 1
  PCI: 00:1b.0: enabled 1
  PCI: 00:1c.0: enabled 1
  PCI: 00:1c.1: enabled 1
  PCI: 00:1d.0: enabled 1
  PCI: 00:1d.1: enabled 1
  PCI: 00:1d.2: enabled 1
  PCI: 00:1d.3: enabled 1
  PCI: 00:1d.7: enabled 1
  PCI: 00:1f.0: enabled 1
  PCI: 00:1f.1: enabled 1
  PCI: 00:1f.2: enabled 1
  PCI: 00:1f.3: enabled 1
scan_static_bus for Root Device
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/27a0] ops
PCI: 00:00.0 [8086/27a0] enabled
PCI: 00:02.0 [8086/27a2] ops
PCI: 00:02.0 [8086/27a2] enabled
PCI: 00:02.1 [8086/27a6] ops
PCI: 00:02.1 [8086/27a6] enabled
PCI: 00:1b.0 [8086/27d8] ops
PCI: 00:1b.0 [8086/27d8] enabled
PCI: 00:1c.0 [8086/0000] bus ops
PCI: 00:1c.0 [8086/27d0] enabled
PCI: 00:1c.1 [8086/0000] bus ops
PCI: 00:1c.1 [8086/27d2] enabled
PCI: 00:1d.0 [8086/27c8] ops
PCI: 00:1d.0 [8086/27c8] enabled
PCI: 00:1d.1 [8086/27c9] ops
PCI: 00:1d.1 [8086/27c9] enabled
PCI: 00:1d.2 [8086/27ca] ops
PCI: 00:1d.2 [8086/27ca] enabled
PCI: 00:1d.3 [8086/27cb] ops
PCI: 00:1d.3 [8086/27cb] enabled
PCI: 00:1d.7 [8086/27cc] ops
PCI: 00:1d.7 [8086/27cc] enabled
PCI: 00:1e.0 [8086/2448] bus ops
PCI: 00:1e.0 [8086/2448] enabled
PCI: 00:1f.0 [8086/27b9] bus ops
PCI: 00:1f.0 [8086/27b9] enabled
PCI: 00:1f.1 [8086/27df] ops
PCI: 00:1f.1 [8086/27df] enabled
PCI: 00:1f.2 [8086/0000] ops
PCI: 00:1f.2 [8086/27c4] enabled
PCI: 00:1f.3 [8086/27da] bus ops
PCI: 00:1f.3 [8086/27da] enabled
do_pci_scan_bridge for PCI: 00:1c.0
PCI: pci_scan_bus for bus 01
PCI: 01:00.0 [11ab/4362] enabled
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
do_pci_scan_bridge for PCI: 00:1c.1
PCI: pci_scan_bus for bus 02
PCI: 02:00.0 [168c/0024] enabled
PCI: pci_scan_bus returning with max=002
do_pci_scan_bridge returns max 2
do_pci_scan_bridge for PCI: 00:1e.0
PCI: pci_scan_bus for bus 03
PCI: 03:03.0 [11c1/5811] enabled
PCI: pci_scan_bus returning with max=003
do_pci_scan_bridge returns max 3
scan_static_bus for PCI: 00:1f.0
scan_static_bus for PCI: 00:1f.0 done
scan_static_bus for PCI: 00:1f.3
scan_static_bus for PCI: 00:1f.3 done
PCI: pci_scan_bus returning with max=003
scan_static_bus for Root Device done
done
BS: Exiting BS_DEV_ENUMERATE state.
BS: BS_DEV_ENUMERATE times (us): entry 0 run 1775 exit 0
BS: Entering BS_DEV_RESOURCES state.
found VGA at PCI: 00:02.0
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0
Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
PCI: 00:1c.0 read_resources bus 1 link: 0
PCI: 00:1c.0 read_resources bus 1 link: 0 done
PCI: 00:1c.1 read_resources bus 2 link: 0
PCI: 00:1c.1 read_resources bus 2 link: 0 done
PCI: 00:1e.0 read_resources bus 3 link: 0
PCI: 00:1e.0 read_resources bus 3 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device child on link 0 CPU_CLUSTER: 0
  CPU_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
  DOMAIN: 0000 child on link 0 PCI: 00:00.0
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
   PCI: 00:00.0
   PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
   PCI: 00:02.0
   PCI: 00:02.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10
   PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 14
   PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 18
   PCI: 00:02.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 1c
   PCI: 00:02.1
   PCI: 00:02.1 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10
   PCI: 00:1b.0
   PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
   PCI: 00:1c.0 child on link 0 PCI: 01:00.0
   PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 01:00.0
    PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
    PCI: 01:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 18
    PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
   PCI: 00:1c.1 child on link 0 PCI: 02:00.0
   PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 02:00.0
    PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
   PCI: 00:1d.0
   PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:1d.1
   PCI: 00:1d.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:1d.2
   PCI: 00:1d.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:1d.3
   PCI: 00:1d.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:1d.7
   PCI: 00:1d.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
   PCI: 00:1e.0 child on link 0 PCI: 03:03.0
   PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 03:03.0
    PCI: 03:03.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
   PCI: 00:1f.0
   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
   PCI: 00:1f.1
   PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
   PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
   PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
   PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
   PCI: 00:1f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
   PCI: 00:1f.2
   PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
   PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
   PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
   PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
   PCI: 00:1f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
   PCI: 00:1f.2 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24
   PCI: 00:1f.3
   PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 01:00.0 18 *  [0x0 - 0xff] io
PCI: 00:1c.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:1c.0 1c *  [0x0 - 0xfff] io
PCI: 00:1d.0 20 *  [0x1000 - 0x101f] io
PCI: 00:1d.1 20 *  [0x1020 - 0x103f] io
PCI: 00:1d.2 20 *  [0x1040 - 0x105f] io
PCI: 00:1d.3 20 *  [0x1060 - 0x107f] io
PCI: 00:1f.1 20 *  [0x1080 - 0x108f] io
PCI: 00:1f.2 20 *  [0x1090 - 0x109f] io
PCI: 00:02.0 14 *  [0x10a0 - 0x10a7] io
PCI: 00:1f.1 10 *  [0x10a8 - 0x10af] io
PCI: 00:1f.1 18 *  [0x10b0 - 0x10b7] io
PCI: 00:1f.2 10 *  [0x10b8 - 0x10bf] io
PCI: 00:1f.2 18 *  [0x10c0 - 0x10c7] io
PCI: 00:1f.1 14 *  [0x10c8 - 0x10cb] io
PCI: 00:1f.1 1c *  [0x10cc - 0x10cf] io
PCI: 00:1f.2 14 *  [0x10d0 - 0x10d3] io
PCI: 00:1f.2 1c *  [0x10d4 - 0x10d7] io
DOMAIN: 0000 compute_resources_io: base: 10d8 size: 10d8 align: 12 gran: 0 limit: ffff done
DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:00.0 30 *  [0x0 - 0x1ffff] mem
PCI: 01:00.0 10 *  [0x20000 - 0x23fff] mem
PCI: 00:1c.0 compute_resources_mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 02:00.0 10 *  [0x0 - 0xffff] mem
PCI: 00:1c.1 compute_resources_mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 03:03.0 10 *  [0x0 - 0xfff] mem
PCI: 00:1e.0 compute_resources_mem: base: 1000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:02.0 18 *  [0x0 - 0xfffffff] prefmem
PCI: 00:1c.0 20 *  [0x10000000 - 0x100fffff] mem
PCI: 00:1c.1 20 *  [0x10100000 - 0x101fffff] mem
PCI: 00:1e.0 20 *  [0x10200000 - 0x102fffff] mem
PCI: 00:02.0 10 *  [0x10300000 - 0x1037ffff] mem
PCI: 00:02.1 10 *  [0x10380000 - 0x103fffff] mem
PCI: 00:02.0 1c *  [0x10400000 - 0x1043ffff] mem
PCI: 00:1b.0 10 *  [0x10440000 - 0x10443fff] mem
PCI: 00:1d.7 10 *  [0x10444000 - 0x104443ff] mem
PCI: 00:1f.2 24 *  [0x10444400 - 0x104447ff] mem
DOMAIN: 0000 compute_resources_mem: base: 10444800 size: 10444800 align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:02.0
constrain_resources: PCI: 00:02.1
constrain_resources: PCI: 00:1b.0
constrain_resources: PCI: 00:1c.0
constrain_resources: PCI: 01:00.0
constrain_resources: PCI: 00:1c.1
constrain_resources: PCI: 02:00.0
constrain_resources: PCI: 00:1d.0
constrain_resources: PCI: 00:1d.1
constrain_resources: PCI: 00:1d.2
constrain_resources: PCI: 00:1d.3
constrain_resources: PCI: 00:1d.7
constrain_resources: PCI: 00:1e.0
constrain_resources: PCI: 03:03.0
constrain_resources: PCI: 00:1f.0
constrain_resources: PCI: 00:1f.1
constrain_resources: PCI: 00:1f.2
constrain_resources: PCI: 00:1f.3
avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff
	lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff
	lim->base 00000000 lim->limit efffffff
Setting resources...
DOMAIN: 0000 allocate_resources_io: base:1000 size:10d8 align:12 gran:0 limit:ffff
Assigned: PCI: 00:1c.0 1c *  [0x1000 - 0x1fff] io
Assigned: PCI: 00:1d.0 20 *  [0x2000 - 0x201f] io
Assigned: PCI: 00:1d.1 20 *  [0x2020 - 0x203f] io
Assigned: PCI: 00:1d.2 20 *  [0x2040 - 0x205f] io
Assigned: PCI: 00:1d.3 20 *  [0x2060 - 0x207f] io
Assigned: PCI: 00:1f.1 20 *  [0x2080 - 0x208f] io
Assigned: PCI: 00:1f.2 20 *  [0x2090 - 0x209f] io
Assigned: PCI: 00:02.0 14 *  [0x20a0 - 0x20a7] io
Assigned: PCI: 00:1f.1 10 *  [0x20a8 - 0x20af] io
Assigned: PCI: 00:1f.1 18 *  [0x20b0 - 0x20b7] io
Assigned: PCI: 00:1f.2 10 *  [0x20b8 - 0x20bf] io
Assigned: PCI: 00:1f.2 18 *  [0x20c0 - 0x20c7] io
Assigned: PCI: 00:1f.1 14 *  [0x20c8 - 0x20cb] io
Assigned: PCI: 00:1f.1 1c *  [0x20cc - 0x20cf] io
Assigned: PCI: 00:1f.2 14 *  [0x20d0 - 0x20d3] io
Assigned: PCI: 00:1f.2 1c *  [0x20d4 - 0x20d7] io
DOMAIN: 0000 allocate_resources_io: next_base: 20d8 size: 10d8 align: 12 gran: 0 done
PCI: 00:1c.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 01:00.0 18 *  [0x1000 - 0x10ff] io
PCI: 00:1c.0 allocate_resources_io: next_base: 1100 size: 1000 align: 12 gran: 12 done
PCI: 00:1c.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1c.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:1e.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:1e.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:10444800 align:28 gran:0 limit:efffffff
Assigned: PCI: 00:02.0 18 *  [0xd0000000 - 0xdfffffff] prefmem
Assigned: PCI: 00:1c.0 20 *  [0xe0000000 - 0xe00fffff] mem
Assigned: PCI: 00:1c.1 20 *  [0xe0100000 - 0xe01fffff] mem
Assigned: PCI: 00:1e.0 20 *  [0xe0200000 - 0xe02fffff] mem
Assigned: PCI: 00:02.0 10 *  [0xe0300000 - 0xe037ffff] mem
Assigned: PCI: 00:02.1 10 *  [0xe0380000 - 0xe03fffff] mem
Assigned: PCI: 00:02.0 1c *  [0xe0400000 - 0xe043ffff] mem
Assigned: PCI: 00:1b.0 10 *  [0xe0440000 - 0xe0443fff] mem
Assigned: PCI: 00:1d.7 10 *  [0xe0444000 - 0xe04443ff] mem
Assigned: PCI: 00:1f.2 24 *  [0xe0444400 - 0xe04447ff] mem
DOMAIN: 0000 allocate_resources_mem: next_base: e0444800 size: 10444800 align: 28 gran: 0 done
PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.0 allocate_resources_mem: base:e0000000 size:100000 align:20 gran:20 limit:efffffff
Assigned: PCI: 01:00.0 30 *  [0xe0000000 - 0xe001ffff] mem
Assigned: PCI: 01:00.0 10 *  [0xe0020000 - 0xe0023fff] mem
PCI: 00:1c.0 allocate_resources_mem: next_base: e0024000 size: 100000 align: 20 gran: 20 done
PCI: 00:1c.1 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
PCI: 00:1c.1 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
PCI: 00:1c.1 allocate_resources_mem: base:e0100000 size:100000 align:20 gran:20 limit:efffffff
Assigned: PCI: 02:00.0 10 *  [0xe0100000 - 0xe010ffff] mem
PCI: 00:1c.1 allocate_resources_mem: next_base: e0110000 size: 100000 align: 20 gran: 20 done
PCI: 00:1e.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
PCI: 00:1e.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
PCI: 00:1e.0 allocate_resources_mem: base:e0200000 size:100000 align:20 gran:20 limit:efffffff
Assigned: PCI: 03:03.0 10 *  [0xe0200000 - 0xe0200fff] mem
PCI: 00:1e.0 allocate_resources_mem: next_base: e0201000 size: 100000 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
pci_tolm: 0xd0000000
Base of stolen memory: 0x3f800000
Top of Low Used DRAM: 0x40000000
IGD decoded, subtracting 8M UMA
Available memory: 1040384K (1016M)
Adding PCIe config bar
DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem<mmconfig>
PCI: 00:02.0 10 <- [0x00e0300000 - 0x00e037ffff] size 0x00080000 gran 0x13 mem
PCI: 00:02.0 14 <- [0x00000020a0 - 0x00000020a7] size 0x00000008 gran 0x03 io
PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem
PCI: 00:02.0 1c <- [0x00e0400000 - 0x00e043ffff] size 0x00040000 gran 0x12 mem
PCI: 00:02.1 10 <- [0x00e0380000 - 0x00e03fffff] size 0x00080000 gran 0x13 mem
PCI: 00:1b.0 10 <- [0x00e0440000 - 0x00e0443fff] size 0x00004000 gran 0x0e mem64
PCI: 00:1c.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:1c.0 20 <- [0x00e0000000 - 0x00e00fffff] size 0x00100000 gran 0x14 bus 01 mem
PCI: 00:1c.0 assign_resources, bus 1 link: 0
PCI: 01:00.0 10 <- [0x00e0020000 - 0x00e0023fff] size 0x00004000 gran 0x0e mem64
PCI: 01:00.0 18 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 01:00.0 30 <- [0x00e0000000 - 0x00e001ffff] size 0x00020000 gran 0x11 romem
PCI: 00:1c.0 assign_resources, bus 1 link: 0
PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:1c.1 20 <- [0x00e0100000 - 0x00e01fffff] size 0x00100000 gran 0x14 bus 02 mem
PCI: 00:1c.1 assign_resources, bus 2 link: 0
PCI: 02:00.0 10 <- [0x00e0100000 - 0x00e010ffff] size 0x00010000 gran 0x10 mem64
PCI: 00:1c.1 assign_resources, bus 2 link: 0
PCI: 00:1d.0 20 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io
PCI: 00:1d.1 20 <- [0x0000002020 - 0x000000203f] size 0x00000020 gran 0x05 io
PCI: 00:1d.2 20 <- [0x0000002040 - 0x000000205f] size 0x00000020 gran 0x05 io
PCI: 00:1d.3 20 <- [0x0000002060 - 0x000000207f] size 0x00000020 gran 0x05 io
PCI: 00:1d.7 10 <- [0x00e0444000 - 0x00e04443ff] size 0x00000400 gran 0x0a mem
PCI: 00:1e.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io
PCI: 00:1e.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem
PCI: 00:1e.0 20 <- [0x00e0200000 - 0x00e02fffff] size 0x00100000 gran 0x14 bus 03 mem
PCI: 00:1e.0 assign_resources, bus 3 link: 0
PCI: 03:03.0 10 <- [0x00e0200000 - 0x00e0200fff] size 0x00001000 gran 0x0c mem
PCI: 00:1e.0 assign_resources, bus 3 link: 0
PCI: 00:1f.1 10 <- [0x00000020a8 - 0x00000020af] size 0x00000008 gran 0x03 io
PCI: 00:1f.1 14 <- [0x00000020c8 - 0x00000020cb] size 0x00000004 gran 0x02 io
PCI: 00:1f.1 18 <- [0x00000020b0 - 0x00000020b7] size 0x00000008 gran 0x03 io
PCI: 00:1f.1 1c <- [0x00000020cc - 0x00000020cf] size 0x00000004 gran 0x02 io
PCI: 00:1f.1 20 <- [0x0000002080 - 0x000000208f] size 0x00000010 gran 0x04 io
PCI: 00:1f.2 10 <- [0x00000020b8 - 0x00000020bf] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 14 <- [0x00000020d0 - 0x00000020d3] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 18 <- [0x00000020c0 - 0x00000020c7] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 1c <- [0x00000020d4 - 0x00000020d7] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 20 <- [0x0000002090 - 0x000000209f] size 0x00000010 gran 0x04 io
PCI: 00:1f.2 24 <- [0x00e0444400 - 0x00e04447ff] size 0x00000400 gran 0x0a mem
DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device child on link 0 CPU_CLUSTER: 0
  CPU_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
  DOMAIN: 0000 child on link 0 PCI: 00:00.0
  DOMAIN: 0000 resource base 1000 size 10d8 align 12 gran 0 limit ffff flags 40040100 index 10000000
  DOMAIN: 0000 resource base d0000000 size 10444800 align 28 gran 0 limit efffffff flags 40040200 index 10000100
  DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
  DOMAIN: 0000 resource base c0000 size 3ff40000 align 0 gran 0 limit 0 flags e0004200 index 4
  DOMAIN: 0000 resource base 3f800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 5
  DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7
   PCI: 00:00.0
   PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
   PCI: 00:02.0
   PCI: 00:02.0 resource base e0300000 size 80000 align 19 gran 19 limit efffffff flags 60000200 index 10
   PCI: 00:02.0 resource base 20a0 size 8 align 3 gran 3 limit ffff flags 60000100 index 14
   PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001200 index 18
   PCI: 00:02.0 resource base e0400000 size 40000 align 18 gran 18 limit efffffff flags 60000200 index 1c
   PCI: 00:02.1
   PCI: 00:02.1 resource base e0380000 size 80000 align 19 gran 19 limit efffffff flags 60000200 index 10
   PCI: 00:1b.0
   PCI: 00:1b.0 resource base e0440000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10
   PCI: 00:1c.0 child on link 0 PCI: 01:00.0
   PCI: 00:1c.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
   PCI: 00:1c.0 resource base e0000000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20
    PCI: 01:00.0
    PCI: 01:00.0 resource base e0020000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10
    PCI: 01:00.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 18
    PCI: 01:00.0 resource base e0000000 size 20000 align 17 gran 17 limit efffffff flags 60002200 index 30
   PCI: 00:1c.1 child on link 0 PCI: 02:00.0
   PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
   PCI: 00:1c.1 resource base e0100000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20
    PCI: 02:00.0
    PCI: 02:00.0 resource base e0100000 size 10000 align 16 gran 16 limit efffffff flags 60000201 index 10
   PCI: 00:1d.0
   PCI: 00:1d.0 resource base 2000 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
   PCI: 00:1d.1
   PCI: 00:1d.1 resource base 2020 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
   PCI: 00:1d.2
   PCI: 00:1d.2 resource base 2040 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
   PCI: 00:1d.3
   PCI: 00:1d.3 resource base 2060 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
   PCI: 00:1d.7
   PCI: 00:1d.7 resource base e0444000 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10
   PCI: 00:1e.0 child on link 0 PCI: 03:03.0
   PCI: 00:1e.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:1e.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
   PCI: 00:1e.0 resource base e0200000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20
    PCI: 03:03.0
    PCI: 03:03.0 resource base e0200000 size 1000 align 12 gran 12 limit efffffff flags 60000200 index 10
   PCI: 00:1f.0
   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
   PCI: 00:1f.1
   PCI: 00:1f.1 resource base 20a8 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
   PCI: 00:1f.1 resource base 20c8 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
   PCI: 00:1f.1 resource base 20b0 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
   PCI: 00:1f.1 resource base 20cc size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
   PCI: 00:1f.1 resource base 2080 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
   PCI: 00:1f.2
   PCI: 00:1f.2 resource base 20b8 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
   PCI: 00:1f.2 resource base 20d0 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
   PCI: 00:1f.2 resource base 20c0 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
   PCI: 00:1f.2 resource base 20d4 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
   PCI: 00:1f.2 resource base 2090 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
   PCI: 00:1f.2 resource base e0444400 size 400 align 10 gran 10 limit efffffff flags 60000200 index 24
   PCI: 00:1f.3
   PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
Done allocating resources.
BS: Exiting BS_DEV_RESOURCES state.
BS: BS_DEV_RESOURCES times (us): entry 0 run 11610 exit 0
BS: Entering BS_DEV_ENABLE state.
Enabling resources...
PCI: 00:00.0 subsystem <- 8086/7270
PCI: 00:00.0 cmd <- 06
PCI: 00:02.0 subsystem <- 8086/7270
PCI: 00:02.0 cmd <- 03
PCI: 00:02.1 subsystem <- 17aa/201a
PCI: 00:02.1 cmd <- 02
PCI: 00:1b.0 subsystem <- 8384/7680
PCI: 00:1b.0 cmd <- 102
PCI: 00:1c.0 bridge ctrl <- 0003
PCI: 00:1c.0 subsystem <- 0000/0000
PCI: 00:1c.0 cmd <- 107
PCI: 00:1c.1 bridge ctrl <- 0003
PCI: 00:1c.1 subsystem <- 0000/0000
PCI: 00:1c.1 cmd <- 106
PCI: 00:1d.0 subsystem <- 8086/7270
PCI: 00:1d.0 cmd <- 01
PCI: 00:1d.1 subsystem <- 8086/7270
PCI: 00:1d.1 cmd <- 01
PCI: 00:1d.2 subsystem <- 8086/7270
PCI: 00:1d.2 cmd <- 01
PCI: 00:1d.3 subsystem <- 8086/7270
PCI: 00:1d.3 cmd <- 01
PCI: 00:1d.7 subsystem <- 8086/7270
PCI: 00:1d.7 cmd <- 102
PCI: 00:1e.0 bridge ctrl <- 0003
PCI: 00:1e.0 cmd <- 06 (NOT WRITTEN!)
PCI: 00:1f.0 subsystem <- 8086/7270
PCI: 00:1f.0 cmd <- 107
PCI: 00:1f.1 subsystem <- 8086/7270
PCI: 00:1f.1 cmd <- 01
PCI: 00:1f.2 subsystem <- 8086/7270
PCI: 00:1f.2 cmd <- 03
PCI: 00:1f.3 subsystem <- 8086/7270
PCI: 00:1f.3 cmd <- 101
PCI: 01:00.0 cmd <- 03
PCI: 02:00.0 cmd <- 02
PCI: 03:03.0 cmd <- 02
done.
BS: Exiting BS_DEV_ENABLE state.
BS: BS_DEV_ENABLE times (us): entry 0 run 619 exit 0
BS: Entering BS_DEV_INIT state.
Initializing devices...
Root Device init
Root Device init 7 usecs
CPU_CLUSTER: 0 init
start_eip=0x00001000, code_size=0x00000031
Initializing SMM handler... ... pmbase = 0x0500

SMI_STS: PM1 
PM1_STS: WAK PWRBTN 
GPE0_STS: GPIO13 GPIO12 GPIO11 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 
ALT_GP_SMI_STS: GPI13 GPI12 GPI11 GPI9 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 
TCO_STS: 
  ... raise SMI#
Initializing CPU #0
CPU: vendor Intel device 6f6
CPU: family 06, model 0f, stepping 06
Enabling cache
microcode: sig=0x6f6 pf=0x20 revision=0x0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
microcode: updated to revision 0xd1 date=2010-10-01
CPU: Intel(R) Core(TM)2 CPU         T7200  @ 2.00GHz.
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x000000003f800000 size 0x3f740000 type 6
0x000000003f800000 - 0x00000000d0000000 size 0x90800000 type 0
0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
MTRR addr 0x0-0x10 set to 6 type @ 0
MTRR addr 0x10-0x20 set to 6 type @ 1
MTRR addr 0x20-0x30 set to 6 type @ 2
MTRR addr 0x30-0x40 set to 6 type @ 3
MTRR addr 0x40-0x50 set to 6 type @ 4
MTRR addr 0x50-0x60 set to 6 type @ 5
MTRR addr 0x60-0x70 set to 6 type @ 6
MTRR addr 0x70-0x80 set to 6 type @ 7
MTRR addr 0x80-0x84 set to 6 type @ 8
MTRR addr 0x84-0x88 set to 6 type @ 9
MTRR addr 0x88-0x8c set to 6 type @ 10
MTRR addr 0x8c-0x90 set to 6 type @ 11
MTRR addr 0x90-0x94 set to 6 type @ 12
MTRR addr 0x94-0x98 set to 6 type @ 13
MTRR addr 0x98-0x9c set to 6 type @ 14
MTRR addr 0x9c-0xa0 set to 6 type @ 15
MTRR addr 0xa0-0xa4 set to 0 type @ 16
MTRR addr 0xa4-0xa8 set to 0 type @ 17
MTRR addr 0xa8-0xac set to 0 type @ 18
MTRR addr 0xac-0xb0 set to 0 type @ 19
MTRR addr 0xb0-0xb4 set to 0 type @ 20
MTRR addr 0xb4-0xb8 set to 0 type @ 21
MTRR addr 0xb8-0xbc set to 0 type @ 22
MTRR addr 0xbc-0xc0 set to 0 type @ 23
MTRR addr 0xc0-0xc1 set to 6 type @ 24
MTRR addr 0xc1-0xc2 set to 6 type @ 25
MTRR addr 0xc2-0xc3 set to 6 type @ 26
MTRR addr 0xc3-0xc4 set to 6 type @ 27
MTRR addr 0xc4-0xc5 set to 6 type @ 28
MTRR addr 0xc5-0xc6 set to 6 type @ 29
MTRR addr 0xc6-0xc7 set to 6 type @ 30
MTRR addr 0xc7-0xc8 set to 6 type @ 31
MTRR addr 0xc8-0xc9 set to 6 type @ 32
MTRR addr 0xc9-0xca set to 6 type @ 33
MTRR addr 0xca-0xcb set to 6 type @ 34
MTRR addr 0xcb-0xcc set to 6 type @ 35
MTRR addr 0xcc-0xcd set to 6 type @ 36
MTRR addr 0xcd-0xce set to 6 type @ 37
MTRR addr 0xce-0xcf set to 6 type @ 38
MTRR addr 0xcf-0xd0 set to 6 type @ 39
MTRR addr 0xd0-0xd1 set to 6 type @ 40
MTRR addr 0xd1-0xd2 set to 6 type @ 41
MTRR addr 0xd2-0xd3 set to 6 type @ 42
MTRR addr 0xd3-0xd4 set to 6 type @ 43
MTRR addr 0xd4-0xd5 set to 6 type @ 44
MTRR addr 0xd5-0xd6 set to 6 type @ 45
MTRR addr 0xd6-0xd7 set to 6 type @ 46
MTRR addr 0xd7-0xd8 set to 6 type @ 47
MTRR addr 0xd8-0xd9 set to 6 type @ 48
MTRR addr 0xd9-0xda set to 6 type @ 49
MTRR addr 0xda-0xdb set to 6 type @ 50
MTRR addr 0xdb-0xdc set to 6 type @ 51
MTRR addr 0xdc-0xdd set to 6 type @ 52
MTRR addr 0xdd-0xde set to 6 type @ 53
MTRR addr 0xde-0xdf set to 6 type @ 54
MTRR addr 0xdf-0xe0 set to 6 type @ 55
MTRR addr 0xe0-0xe1 set to 6 type @ 56
MTRR addr 0xe1-0xe2 set to 6 type @ 57
MTRR addr 0xe2-0xe3 set to 6 type @ 58
MTRR addr 0xe3-0xe4 set to 6 type @ 59
MTRR addr 0xe4-0xe5 set to 6 type @ 60
MTRR addr 0xe5-0xe6 set to 6 type @ 61
MTRR addr 0xe6-0xe7 set to 6 type @ 62
MTRR addr 0xe7-0xe8 set to 6 type @ 63
MTRR addr 0xe8-0xe9 set to 6 type @ 64
MTRR addr 0xe9-0xea set to 6 type @ 65
MTRR addr 0xea-0xeb set to 6 type @ 66
MTRR addr 0xeb-0xec set to 6 type @ 67
MTRR addr 0xec-0xed set to 6 type @ 68
MTRR addr 0xed-0xee set to 6 type @ 69
MTRR addr 0xee-0xef set to 6 type @ 70
MTRR addr 0xef-0xf0 set to 6 type @ 71
MTRR addr 0xf0-0xf1 set to 6 type @ 72
MTRR addr 0xf1-0xf2 set to 6 type @ 73
MTRR addr 0xf2-0xf3 set to 6 type @ 74
MTRR addr 0xf3-0xf4 set to 6 type @ 75
MTRR addr 0xf4-0xf5 set to 6 type @ 76
MTRR addr 0xf5-0xf6 set to 6 type @ 77
MTRR addr 0xf6-0xf7 set to 6 type @ 78
MTRR addr 0xf7-0xf8 set to 6 type @ 79
MTRR addr 0xf8-0xf9 set to 6 type @ 80
MTRR addr 0xf9-0xfa set to 6 type @ 81
MTRR addr 0xfa-0xfb set to 6 type @ 82
MTRR addr 0xfb-0xfc set to 6 type @ 83
MTRR addr 0xfc-0xfd set to 6 type @ 84
MTRR addr 0xfd-0xfe set to 6 type @ 85
MTRR addr 0xfe-0xff set to 6 type @ 86
MTRR addr 0xff-0x100 set to 6 type @ 87
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR: default type WB/UC MTRR counts: 6/3.
MTRR: UC selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x0000000fc0000000 type 6
MTRR: 1 base 0x000000003f800000 mask 0x0000000fff800000 type 0
MTRR: 2 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 0x00 done.
CPU: 0 2 siblings
CPU: 0 has sibling 1
CPU #0 initialized
CPU1: stack_base 0013c000, stack_end 0013cff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #1
Waiting for 1 CPUS to stop
CPU: vendor Intel device 6f6
CPU: family 06, model 0f, stepping 06
Enabling cache
microcode: sig=0x6f6 pf=0x20 revision=0x0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
Microcode size field is 0
microcode: updated to revision 0xd1 date=2010-10-01
CPU: Intel(R) Core(TM)2 CPU         T7200  @ 2.00GHz.
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR: 0 base 0x0000000000000000 mask 0x0000000fc0000000 type 6
MTRR: 1 base 0x000000003f800000 mask 0x0000000fff800000 type 0
MTRR: 2 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local apic... apic_id: 0x01 done.
CPU: 1 2 siblings
CPU #1 initialized
CPU 1 going down...
All AP CPUs stopped (1915 loops)
CPU1: stack: 0013c000 - 0013d000, lowest used address 0013ccd0, stack used: 816 bytes
CPU_CLUSTER: 0 init 54103 usecs
PCI: 00:00.0 init
Normal boot.
PCI: 00:00.0 init 2 usecs
PCI: 00:02.0 init
Initializing VGA without OPROM.
GMADR=0xd0000008 GTTADR=0xe0400000
i915lightup: graphics d0000000 mmio e0300000 addrport 20a0 physbase 3f820000
EDID:
00 ff ff ff ff ff ff 00 06 10 5f 9c 00 00 00 00 
08 10 01 03 80 1d 12 78 0a 2f 30 97 58 53 8b 29 
25 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 
01 01 01 01 01 01 bc 1b 00 a0 50 20 17 30 30 20 
36 00 1e b3 10 00 00 18 00 00 00 01 00 06 10 20 
00 00 00 00 00 00 00 00 0a 20 00 00 00 fe 00 4c 
50 31 33 33 57 58 31 2d 54 4c 41 31 00 00 00 fe 
00 43 6f 6c 6f 72 20 4c 43 44 0a 20 20 20 00 c2 
Extracted contents:
header:          00 ff ff ff ff ff ff 00
serial number:   06 10 5f 9c 00 00 00 00 08 10
version:         01 03
basic params:    80 1d 12 78 0a
chroma info:     2f 30 97 58 53 8b 29 25 50 54
established:     00 00 00
standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
descriptor 1:    bc 1b 00 a0 50 20 17 30 30 20 36 00 1e b3 10 00 00 18
descriptor 2:    00 00 00 01 00 06 10 20 00 00 00 00 00 00 00 00 0a 20
descriptor 3:    00 00 00 fe 00 4c 50 31 33 33 57 58 31 2d 54 4c 41 31
descriptor 4:    00 00 00 fe 00 43 6f 6c 6f 72 20 4c 43 44 0a 20 20 20
extensions:      00
checksum:        c2

Manufacturer: APP Model 9c5f Serial Number 0
Made week 8 of 2006
EDID version: 1.3
Digital display
Maximum image size: 29 cm x 18 cm
Gamma: 220%
Check DPMS levels
Supported color formats: RGB 4:4:4, YCrCb 4:2:2
First detailed timing is preferred timing
Established timings supported:
Standard timings supported:
Detailed timings
Hex of detail: bc1b00a050201730302036001eb310000018
Did detailed timing
Detailed mode (IN HEX): Clock 71000 KHz, 11e mm x b3 mm
               0500 0530 0550 05a0 hborder 0
               0320 0323 0329 0337 vborder 0
               -hsync -vsync 
Hex of detail: 000000010006102000000000000000000a20
Manufacturer-specified data, tag 1
Hex of detail: 000000fe004c503133335758312d544c4131
ASCII string: LP133WX1
Hex of detail: 000000fe00436f6c6f72204c43440a202020
ASCII string: Color
Checksum
Checksum: 0xc2 (valid)

Unknown extension block

EDID block does NOT conform to EDID 1.3!
	Missing name descriptor
	Missing monitor ranges
	Detailed block string not properly terminated
EDID block does not conform at all!
	Detailed blocks filled with garbage
bringing up panel at resolution 1280 x 800
Borders 0 x 0
Blank 160 x 23
Sync 32 x 6
Front porch 48 x 3
Spread spectrum clock
Single channel
Polarities 1, 1
Pixel N=7, M1=21, M2=11, P1=2
Pixel clock 142040 kHz
waiting for panel powerup
panel powered up
gtt_setup is enabled.
8M UMA
GTT PGETBL_CTL register: 0x3f800001
GTT Enabled
memset d0000000 to 0x00 for 4096000 bytes
PCI: 00:02.0 init 21500 usecs
PCI: 00:02.1 init
PCI: 00:02.1 init 735 usecs
PCI: 00:1b.0 init
Azalia: codec type: Azalia
Azalia: base = e0440000
Azalia: codec_mask = 01
Azalia: Initializing codec #0
Azalia: codec viddid: 83847680
Azalia: verb_size: 44
Azalia: verb loaded.
PCI: 00:1b.0 init 4899 usecs
PCI: 00:1c.0 init
Initializing ICH7 PCIe bridge.
PCI: 00:1c.0 init 19 usecs
PCI: 00:1c.1 init
Initializing ICH7 PCIe bridge.
PCI: 00:1c.1 init 19 usecs
PCI: 00:1d.0 init
UHCI: Setting up controller.. done.
PCI: 00:1d.0 init 6 usecs
PCI: 00:1d.1 init
UHCI: Setting up controller.. done.
PCI: 00:1d.1 init 6 usecs
PCI: 00:1d.2 init
UHCI: Setting up controller.. done.
PCI: 00:1d.2 init 6 usecs
PCI: 00:1d.3 init
UHCI: Setting up controller.. done.
PCI: 00:1d.3 init 6 usecs
PCI: 00:1d.7 init
EHCI: Setting up controller.. done.
PCI: 00:1d.7 init 11 usecs
PCI: 00:1e.0 init
PCI: 00:1e.0 init 12 usecs
PCI: 00:1f.0 init
i82801gx: lpc_init
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x02
IOAPIC: Dumping registers
  reg 0x0000: 0x02000000
  reg 0x0001: 0x00170020
  reg 0x0002: 0x00170020
WARNING: No CMOS option 'power_on_after_fail'.
Set power on after power failure.
NMI sources enabled.
rtc_failed = 0x0
RTC Init
Disabling ACPI via APMC:
done.
Locking SMM.
PCI: 00:1f.0 init 2196 usecs
PCI: 00:1f.1 init
i82801gx_ide: initializing... IDE0 IDE1 
PCI: 00:1f.1 init 11 usecs
PCI: 00:1f.2 init
i82801gx_sata: initializing...
SATA controller in AHCI mode.
PCI: 00:1f.2 init 26 usecs
PCI: 01:00.0 init
PCI: 01:00.0 init 0 usecs
PCI: 02:00.0 init
PCI: 02:00.0 init 0 usecs
PCI: 03:03.0 init
PCI: 03:03.0 init 0 usecs
Devices initialized
Show all devs...After init.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:02.1: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 1
PCI: 00:1c.1: enabled 1
PCI: 00:1d.0: enabled 1
PCI: 00:1d.1: enabled 1
PCI: 00:1d.2: enabled 1
PCI: 00:1d.3: enabled 1
PCI: 00:1d.7: enabled 1
PCI: 00:1f.0: enabled 1
PCI: 00:1f.1: enabled 1
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
PCI: 00:1e.0: enabled 1
PCI: 01:00.0: enabled 1
PCI: 02:00.0: enabled 1
PCI: 03:03.0: enabled 1
APIC: 01: enabled 1
BS: Exiting BS_DEV_INIT state.
BS: BS_DEV_INIT times (us): entry 0 run 83682 exit 0
BS: Entering BS_POST_DEVICE state.
Finalize devices...
Devices finalized
BS: Exiting BS_POST_DEVICE state.
BS: BS_POST_DEVICE times (us): entry 0 run 5 exit 0
BS: Entering BS_OS_RESUME_CHECK state.
BS: Exiting BS_OS_RESUME_CHECK state.
BS: BS_OS_RESUME_CHECK times (us): entry 0 run 3 exit 0
BS: Entering BS_WRITE_TABLES state.
ACPI: Writing ACPI tables at 3f7df000.
ACPI:    * HPET
ACPI: added table 1/32, length now 40
ACPI:    * MADT
ACPI: added table 2/32, length now 44
ACPI:    * MCFG
ACPI: added table 3/32, length now 48
ACPI:     * FACS
ACPI: Patching up global NVS in DSDT at offset 0x01f8 -> 0x3f7e1de0
ACPI:     * DSDT @ 3f7df340 Length 2aa0
ACPI:     * FADT
ACPI: added table 4/32, length now 52
ACPI:     * SSDT
Found 1 CPU(s) with 2 core(s) each.
clocks between 1000 and 2000 MHz.
adding 4 P-States between busratio 6 and c, incl. P0
PSS: 2000MHz power 35000 control 0xc28 status 0xc28
PSS: 1666MHz power 31666 control 0xa21 status 0xa21
PSS: 1333MHz power 28333 control 0x81a status 0x81a
PSS: 1000MHz power 25000 control 0x613 status 0x613
clocks between 1000 and 2000 MHz.
adding 4 P-States between busratio 6 and c, incl. P0
PSS: 2000MHz power 35000 control 0xc28 status 0xc28
PSS: 1666MHz power 31666 control 0xa21 status 0xa21
PSS: 1333MHz power 28333 control 0x81a status 0x81a
PSS: 1000MHz power 25000 control 0x613 status 0x613
ACPI: added table 5/32, length now 56
current = 3f7e2210
ACPI: done.
Laptop handling...
ACPI tables: 12816 bytes.
smbios_write_tables: 3f7de000
Root Device (Apple MacBook2,1)
CPU_CLUSTER: 0 (Intel i945 Northbridge)
APIC: 00 (Socket mFCPGA478 CPU)
DOMAIN: 0000 (Intel i945 Northbridge)
PCI: 00:00.0 (Intel i945 Northbridge)
PCI: 00:02.0 (Intel i945 Northbridge)
PCI: 00:02.1 (Intel i945 Northbridge)
PCI: 00:1b.0 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
PCI: 00:1c.0 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
PCI: 00:1c.1 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
PCI: 00:1d.0 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
PCI: 00:1d.1 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
PCI: 00:1d.2 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
PCI: 00:1d.3 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
PCI: 00:1d.7 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
PCI: 00:1f.0 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
PCI: 00:1f.1 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
PCI: 00:1f.2 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
PCI: 00:1f.3 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge)
PCI: 00:1e.0 (unknown)
PCI: 01:00.0 (unknown)
PCI: 02:00.0 (unknown)
PCI: 03:03.0 (unknown)
APIC: 01 (unknown)
SMBIOS tables: 342 bytes.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 6071
Table forward entry ends at 0x00000528.
... aligned to 0x00001000
Writing coreboot table at 0x3f6d6000
rom_table_end = 0x3f6d6000
... aligned to 0x3f6e0000
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000c0000-000000003f6d5fff: RAM
 3. 000000003f6d6000-000000003f7fffff: CONFIGURATION TABLES
 4. 000000003f800000-000000003fffffff: RESERVED
 5. 00000000f0000000-00000000f3ffffff: RESERVED
Wrote coreboot table at: 3f6d6000, 0x8a4 bytes, checksum feca
coreboot table: 2236 bytes.
CBMEM ROOT  0. 3f7ff000 00001000
CAR GLOBALS 1. 3f7fe000 00001000
CONSOLE     2. 3f7ee000 00010000
TIME STAMP  3. 3f7ed000 00001000
ROMSTAGE    4. 3f7ec000 00001000
GDT         5. 3f7eb000 00001000
ACPI        6. 3f7df000 0000c000
SMBIOS      7. 3f7de000 00001000
ACPI RESUME 8. 3f6de000 00100000
COREBOOT    9. 3f6d6000 00008000
BS: Exiting BS_WRITE_TABLES state.
BS: BS_WRITE_TABLES times (us): entry 0 run 1753 exit 0
BS: Entering BS_PAYLOAD_LOAD state.
CBFS: located payload @ ffe3d878, 245110 bytes.
Loading segment from rom address 0xffe3d878
  code (compression=1)
  New segment dstaddr 0x8200 memsize 0x17d18 srcaddr 0xffe3d8cc filesize 0x83ea
  (cleaned up) New segment addr 0x8200 size 0x17d18 offset 0xffe3d8cc filesize 0x83ea
Loading segment from rom address 0xffe3d894
  code (compression=1)
  New segment dstaddr 0x100000 memsize 0xa33b4 srcaddr 0xffe45cb6 filesize 0x33938
  (cleaned up) New segment addr 0x100000 size 0xa33b4 offset 0xffe45cb6 filesize 0x33938
Loading segment from rom address 0xffe3d8b0
  Entry Point 0x00008200
Bounce Buffer at 3f5f0000, 938992 bytes
Loading Segment: addr: 0x0000000000008200 memsz: 0x0000000000017d18 filesz: 0x00000000000083ea
lb: [0x0000000000100000, 0x000000000014203c)
Post relocation: addr: 0x0000000000008200 memsz: 0x0000000000017d18 filesz: 0x00000000000083ea
using LZMA
[ 0x00008200, 000185e3, 0x0001ff18) <- ffe3d8cc
Clearing Segment: addr: 0x00000000000185e3 memsz: 0x0000000000007935
dest 00008200, end 0001ff18, bouncebuffer 3f5f0000
Loading Segment: addr: 0x0000000000100000 memsz: 0x00000000000a33b4 filesz: 0x0000000000033938
lb: [0x0000000000100000, 0x000000000014203c)
segment: [0x0000000000100000, 0x0000000000133938, 0x00000000001a33b4)
 bounce: [0x000000003f5f0000, 0x000000003f623938, 0x000000003f6933b4)
Post relocation: addr: 0x000000003f5f0000 memsz: 0x00000000000a33b4 filesz: 0x0000000000033938
using LZMA
[ 0x3f5f0000, 3f6933b4, 0x3f6933b4) <- ffe45cb6
dest 3f5f0000, end 3f6933b4, bouncebuffer 3f5f0000
move suffix around: from 3f63203c, to 14203c, amount: 61378
Loaded segments
BS: Exiting BS_PAYLOAD_LOAD state.
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 139103 exit 0
BS: Entering BS_PAYLOAD_BOOT state.
ICH7 watchdog disabled
Jumping to boot code at 00008200
CPU0: stack: 0013d000 - 0013e000, lowest used address 0013dacc, stack used: 1332 bytes
entry    = 0x00008200
lb_start = 0x00100000
lb_size  = 0x0004203c
buffer   = 0x3f5f0000
error: terminal `serial_usb0' isn't found.
error: terminal `serial_usb0' isn't found.
error: file `/boot/grub/i386-coreboot/progress.mod' not found.
error: file `/boot/grub/i386-coreboot/true.mod' not found.
error: file `/boot/grub/i386-coreboot/gfxterm.mod' not found.