amd/gardenia/4.5-762-g49342cd/2017-01-06T16_30_58Z
diff --git a/amd/gardenia/4.5-762-g49342cd/2017-01-06T16_30_58Z/coreboot_console.txt b/amd/gardenia/4.5-762-g49342cd/2017-01-06T16_30_58Z/coreboot_console.txt
new file mode 100644
index 0000000..fe450ab
--- /dev/null
+++ b/amd/gardenia/4.5-762-g49342cd/2017-01-06T16_30_58Z/coreboot_console.txt
@@ -0,0 +1,1022 @@
+
+
+coreboot-4.5-762-g49342cd Fri Jan 6 16:30:58 UTC 2017 ramstage starting...
+BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0
+BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 4 exit 0
+Enumerating buses...
+Show all devs... Before device enumeration.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+APIC: 10: enabled 1
+DOMAIN: 0000: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 1
+PCI: 00:01.1: enabled 1
+PCI: 00:02.0: enabled 1
+PCI: 00:02.1: enabled 1
+PCI: 00:02.2: enabled 1
+PCI: 00:02.3: enabled 1
+PCI: 00:02.4: enabled 1
+PCI: 00:02.5: enabled 1
+PCI: 00:09.0: enabled 1
+PCI: 00:09.2: enabled 1
+PCI: 00:10.0: enabled 1
+PCI: 00:11.0: enabled 1
+PCI: 00:12.0: enabled 1
+PCI: 00:14.0: enabled 1
+I2C: 00:51: enabled 1
+PCI: 00:14.3: enabled 1
+PCI: 00:14.7: enabled 1
+PCI: 00:18.0: enabled 1
+PCI: 00:18.1: enabled 1
+PCI: 00:18.2: enabled 1
+PCI: 00:18.3: enabled 1
+PCI: 00:18.4: enabled 1
+PCI: 00:18.5: enabled 1
+Compare with tree...
+Root Device: enabled 1
+ CPU_CLUSTER: 0: enabled 1
+ APIC: 10: enabled 1
+ DOMAIN: 0000: enabled 1
+ PCI: 00:00.0: enabled 1
+ PCI: 00:01.0: enabled 1
+ PCI: 00:01.1: enabled 1
+ PCI: 00:02.0: enabled 1
+ PCI: 00:02.1: enabled 1
+ PCI: 00:02.2: enabled 1
+ PCI: 00:02.3: enabled 1
+ PCI: 00:02.4: enabled 1
+ PCI: 00:02.5: enabled 1
+ PCI: 00:09.0: enabled 1
+ PCI: 00:09.2: enabled 1
+ PCI: 00:10.0: enabled 1
+ PCI: 00:11.0: enabled 1
+ PCI: 00:12.0: enabled 1
+ PCI: 00:14.0: enabled 1
+ I2C: 00:51: enabled 1
+ PCI: 00:14.3: enabled 1
+ PCI: 00:14.7: enabled 1
+ PCI: 00:18.0: enabled 1
+ PCI: 00:18.1: enabled 1
+ PCI: 00:18.2: enabled 1
+ PCI: 00:18.3: enabled 1
+ PCI: 00:18.4: enabled 1
+ PCI: 00:18.5: enabled 1
+Mainboard GARDENIA Enable.
+Root Device scanning...
+root_dev_scan_bus for Root Device
+setup_bsp_ramtop, TOP MEM: msr.lo = 0xd0000000, msr.hi = 0x00000000
+setup_bsp_ramtop, TOP MEM2: msr.lo = 0x2f000000, msr.hi = 0x00000001
+setup_uma_memory: system memory size 4GB, topmem2 size 4848MB, topmem size 3328MB
+setup_uma_memory: uma size 0x20000000, memory start 0xb0000000
+CPU_CLUSTER: 0 enabled
+DOMAIN: 0000 enabled
+CPU_CLUSTER: 0 scanning...
+CBFS: 'Master Header Locator' located CBFS at [100:7fffc0)
+CBFS: Locating 'AGESA'
+CBFS: Found @ offset 5ffec0 size f38ac
+CBFS: 'Master Header Locator' located CBFS at [100:7fffc0)
+CBFS: Locating 'AGESA'
+CBFS: Found @ offset 5ffec0 size f38ac
+PCI: 00:18.5 family15h, core_max=0x10, core_nums=0xf, siblings=0x1
+lpaicid_start=0x10 node 0x0 core 0x0 apicid=0x10
+CPU: APIC: 10 enabled
+lpaicid_start=0x10 node 0x0 core 0x1 apicid=0x11
+CPU: APIC: 11 enabled
+scan_bus: scanning of bus CPU_CLUSTER: 0 took 21404 usecs
+DOMAIN: 0000 scanning...
+PCI: pci_scan_bus for bus 00
+PCI: 00:00.0 [1022/1576] enabled
+PCI: 00:01.0 [1002/98e4] enabled
+PCI: 00:01.1 [1002/15b3] enabled
+PCI: 00:02.0 [1022/157b] enabled
+PCI: Static device PCI: 00:02.1 not found, disabling it.
+PCI: Static device PCI: 00:02.2 not found, disabling it.
+PCI: Static device PCI: 00:02.3 not found, disabling it.
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Capability: type 0x05 @ 0xa0
+Capability: type 0x0d @ 0xc0
+Capability: type 0x08 @ 0xc8
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+PCI: 00:02.4 subordinate bus PCI Express
+PCI: 00:02.4 [1022/157c] enabled
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Capability: type 0x05 @ 0xa0
+Capability: type 0x0d @ 0xc0
+Capability: type 0x08 @ 0xc8
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+PCI: 00:02.5 subordinate bus PCI Express
+PCI: 00:02.5 [1022/157c] enabled
+PCI: 00:03.0 [1022/157b] enabled
+PCI: 00:08.0 [1022/1578] enabled
+hudson_enable()
+PCI: 00:09.0 [1022/157d] enabled
+hudson_enable()
+PCI: 00:09.2 [1022/0000] ops
+PCI: 00:09.2 [1022/157a] enabled
+hudson_enable()
+PCI: 00:10.0 [1022/0000] ops
+PCI: 00:10.0 [1022/7914] enabled
+hudson_enable()
+PCI: 00:11.0 [1022/7904] enabled
+hudson_enable()
+PCI: 00:12.0 [1022/0000] ops
+PCI: 00:12.0 [1022/7908] enabled
+hudson_enable()
+PCI: 00:14.0 [1022/790b] enabled
+hudson_enable()
+PCI: 00:14.3 [1022/0000] bus ops
+PCI: 00:14.3 [1022/790e] enabled
+hudson_enable()
+PCI: 00:14.7 [1022/7906] enabled
+PCI: 00:18.0 [1022/15b0] ops
+PCI: 00:18.0 [1022/15b0] enabled
+PCI: 00:18.1 [1022/15b1] enabled
+PCI: 00:18.2 [1022/15b2] enabled
+PCI: 00:18.3 [1022/15b3] enabled
+PCI: 00:18.4 [1022/15b4] enabled
+PCI: 00:18.5 [1022/15b5] enabled
+PCI: 00:02.4 scanning...
+do_pci_scan_bridge for PCI: 00:02.4
+PCI: pci_scan_bus for bus 01
+PCI: 01:00.0 [8086/10d3] enabled
+Capability: type 0x01 @ 0xc8
+Capability: type 0x05 @ 0xd0
+Capability: type 0x10 @ 0xe0
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+scan_bus: scanning of bus PCI: 00:02.4 took 12058 usecs
+PCI: 00:02.5 scanning...
+do_pci_scan_bridge for PCI: 00:02.5
+PCI: pci_scan_bus for bus 02
+PCI: 02:00.0 [10ec/5227] enabled
+Capability: type 0x01 @ 0x40
+Capability: type 0x05 @ 0x50
+Capability: type 0x10 @ 0x70
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+scan_bus: scanning of bus PCI: 00:02.5 took 12054 usecs
+PCI: 00:14.3 scanning...
+scan_lpc_bus for PCI: 00:14.3
+scan_lpc_bus for PCI: 00:14.3 done
+scan_bus: scanning of bus PCI: 00:14.3 took 4039 usecs
+scan_bus: scanning of bus DOMAIN: 0000 took 112565 usecs
+root_dev_scan_bus for Root Device done
+scan_bus: scanning of bus Root Device took 157800 usecs
+done
+BS: BS_DEV_ENUMERATE times (us): entry 0 run 228364 exit 0
+found VGA at PCI: 00:01.0
+Setting up VGA for PCI: 00:01.0
+Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
+Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
+Allocating resources...
+Reading resources...
+Root Device read_resources bus 0 link: 0
+CPU_CLUSTER: 0 read_resources bus 0 link: 0
+CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
+fx_devs=0x1
+DOMAIN: 0000 read_resources bus 0 link: 0
+PCI: 00:02.4 read_resources bus 1 link: 0
+PCI: 00:02.4 read_resources bus 1 link: 0 done
+PCI: 00:02.5 read_resources bus 2 link: 0
+PCI: 00:02.5 read_resources bus 2 link: 0 done
+PCI: 00:14.0 read_resources bus 0 link: 0
+I2C: 00:51 missing read_resources
+PCI: 00:14.0 read_resources bus 0 link: 0 done
+Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000.
+PCI: 00:18.0 read_resources bus 0 link: 0
+PCI: 00:18.0 read_resources bus 0 link: 0 done
+PCI: 00:18.0 read_resources bus 0 link: 1
+PCI: 00:18.0 read_resources bus 0 link: 1 done
+PCI: 00:18.0 read_resources bus 0 link: 2
+PCI: 00:18.0 read_resources bus 0 link: 2 done
+PCI: 00:18.0 read_resources bus 0 link: 3
+PCI: 00:18.0 read_resources bus 0 link: 3 done
+DOMAIN: 0000 read_resources bus 0 link: 0 done
+Root Device read_resources bus 0 link: 0 done
+Done reading resources.
+Show resources in subtree (Root Device)...After reading.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 10
+ APIC: 10
+ APIC: 11
+ DOMAIN: 0000 child on link 0 PCI: 00:00.0
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
+ PCI: 00:00.0
+ PCI: 00:01.0
+ PCI: 00:01.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 10
+ PCI: 00:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffffffffffff flags 1201 index 18
+ PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 20
+ PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 24
+ PCI: 00:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
+ PCI: 00:01.1
+ PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:02.0
+ PCI: 00:02.1
+ PCI: 00:02.2
+ PCI: 00:02.3
+ PCI: 00:02.4 child on link 0 PCI: 01:00.0
+ PCI: 00:02.4 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
+ PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 01:00.0
+ PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
+ PCI: 01:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 14
+ PCI: 01:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
+ PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
+ PCI: 01:00.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 2200 index 30
+ PCI: 00:02.5 child on link 0 PCI: 02:00.0
+ PCI: 00:02.5 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
+ PCI: 00:02.5 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:02.5 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 02:00.0
+ PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
+ PCI: 00:03.0
+ PCI: 00:08.0
+ PCI: 00:08.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 1201 index 10
+ PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 18
+ PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c
+ PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 20
+ PCI: 00:08.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 24
+ PCI: 00:09.0
+ PCI: 00:09.2
+ PCI: 00:09.2 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
+ PCI: 00:09.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 14
+ PCI: 00:10.0
+ PCI: 00:10.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:11.0
+ PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
+ PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
+ PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
+ PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
+ PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
+ PCI: 00:11.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 24
+ PCI: 00:12.0
+ PCI: 00:12.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
+ PCI: 00:14.0 child on link 0 I2C: 00:51
+ I2C: 00:51
+ PCI: 00:14.3
+ PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2
+ PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PCI: 00:14.7
+ PCI: 00:14.7 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:18.0
+ PCI: 00:18.0 resource base 0 size 0 align 0 gran 0 limit 0 flags 1 index 10b8
+ PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
+ PCI: 00:18.1
+ PCI: 00:18.2
+ PCI: 00:18.3
+ PCI: 00:18.4
+ PCI: 00:18.5
+DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
+PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
+PCI: 01:00.0 18 * [0x0 - 0x1f] io
+PCI: 00:02.4 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
+PCI: 00:02.5 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
+PCI: 00:02.5 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
+PCI: 00:02.4 1c * [0x0 - 0xfff] io
+PCI: 00:01.0 20 * [0x1000 - 0x10ff] io
+PCI: 00:11.0 20 * [0x1400 - 0x140f] io
+PCI: 00:11.0 10 * [0x1410 - 0x1417] io
+PCI: 00:11.0 18 * [0x1418 - 0x141f] io
+PCI: 00:11.0 14 * [0x1420 - 0x1423] io
+PCI: 00:11.0 1c * [0x1424 - 0x1427] io
+DOMAIN: 0000 io: base: 1428 size: 1428 align: 12 gran: 0 limit: ffff done
+DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
+PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:02.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 01:00.0 14 * [0x0 - 0x7ffff] mem
+PCI: 01:00.0 30 * [0x80000 - 0xbffff] mem
+PCI: 01:00.0 10 * [0xc0000 - 0xdffff] mem
+PCI: 01:00.0 1c * [0xe0000 - 0xe3fff] mem
+PCI: 00:02.4 mem: base: e4000 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:02.5 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:02.5 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:02.5 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 02:00.0 10 * [0x0 - 0xfff] mem
+PCI: 00:02.5 mem: base: 1000 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:01.0 10 * [0x0 - 0xfffffff] prefmem
+PCI: 00:01.0 18 * [0x10000000 - 0x107fffff] prefmem
+PCI: 00:02.4 20 * [0x10800000 - 0x108fffff] mem
+PCI: 00:02.5 20 * [0x10900000 - 0x109fffff] mem
+PCI: 00:08.0 18 * [0x10a00000 - 0x10afffff] mem
+PCI: 00:08.0 20 * [0x10b00000 - 0x10bfffff] mem
+PCI: 00:01.0 24 * [0x10c00000 - 0x10c3ffff] mem
+PCI: 00:01.0 30 * [0x10c40000 - 0x10c5ffff] mem
+PCI: 00:08.0 10 * [0x10c60000 - 0x10c7ffff] prefmem
+PCI: 00:01.1 10 * [0x10c80000 - 0x10c83fff] mem
+PCI: 00:09.2 10 * [0x10c84000 - 0x10c87fff] mem
+PCI: 00:08.0 24 * [0x10c88000 - 0x10c89fff] mem
+PCI: 00:10.0 10 * [0x10c8a000 - 0x10c8bfff] mem
+PCI: 00:08.0 1c * [0x10c8c000 - 0x10c8cfff] mem
+PCI: 00:11.0 24 * [0x10c8d000 - 0x10c8d3ff] mem
+PCI: 00:09.2 14 * [0x10c8e000 - 0x10c8e0ff] mem
+PCI: 00:12.0 10 * [0x10c8f000 - 0x10c8f0ff] mem
+PCI: 00:14.7 10 * [0x10c90000 - 0x10c900ff] mem
+DOMAIN: 0000 mem: base: 10c90100 size: 10c90100 align: 28 gran: 0 limit: ffffffff done
+avoid_fixed_resources: DOMAIN: 0000
+avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
+avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
+constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed)
+constrain_resources: PCI: 00:14.3 10000100 base ff800000 limit ffffffff mem (fixed)
+constrain_resources: PCI: 00:14.3 02 base fec10000 limit fec103ff mem (fixed)
+constrain_resources: PCI: 00:14.3 03 base fec00000 limit fec00fff mem (fixed)
+constrain_resources: PCI: 00:18.0 c0010058 base f8000000 limit fbffffff mem (fixed)
+avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff
+avoid_fixed_resources:@DOMAIN: 0000 10000100 base e0000000 limit f7ffffff
+Setting resources...
+DOMAIN: 0000 io: base:1000 size:1428 align:12 gran:0 limit:ffff
+PCI: 00:02.4 1c * [0x1000 - 0x1fff] io
+PCI: 00:01.0 20 * [0x2000 - 0x20ff] io
+PCI: 00:11.0 20 * [0x2400 - 0x240f] io
+PCI: 00:11.0 10 * [0x2410 - 0x2417] io
+PCI: 00:11.0 18 * [0x2418 - 0x241f] io
+PCI: 00:11.0 14 * [0x2420 - 0x2423] io
+PCI: 00:11.0 1c * [0x2424 - 0x2427] io
+DOMAIN: 0000 io: next_base: 2428 size: 1428 align: 12 gran: 0 done
+PCI: 00:02.4 io: base:1000 size:1000 align:12 gran:12 limit:1fff
+PCI: 01:00.0 18 * [0x1000 - 0x101f] io
+PCI: 00:02.4 io: next_base: 1020 size: 1000 align: 12 gran: 12 done
+PCI: 00:02.5 io: base:ffff size:0 align:12 gran:12 limit:ffff
+PCI: 00:02.5 io: next_base: ffff size: 0 align: 12 gran: 12 done
+DOMAIN: 0000 mem: base:e0000000 size:10c90100 align:28 gran:0 limit:f7ffffff
+PCI: 00:01.0 10 * [0xe0000000 - 0xefffffff] prefmem
+PCI: 00:01.0 18 * [0xf0000000 - 0xf07fffff] prefmem
+PCI: 00:02.4 20 * [0xf0800000 - 0xf08fffff] mem
+PCI: 00:02.5 20 * [0xf0900000 - 0xf09fffff] mem
+PCI: 00:08.0 18 * [0xf0a00000 - 0xf0afffff] mem
+PCI: 00:08.0 20 * [0xf0b00000 - 0xf0bfffff] mem
+PCI: 00:01.0 24 * [0xf0c00000 - 0xf0c3ffff] mem
+PCI: 00:01.0 30 * [0xf0c40000 - 0xf0c5ffff] mem
+PCI: 00:08.0 10 * [0xf0c60000 - 0xf0c7ffff] prefmem
+PCI: 00:01.1 10 * [0xf0c80000 - 0xf0c83fff] mem
+PCI: 00:09.2 10 * [0xf0c84000 - 0xf0c87fff] mem
+PCI: 00:08.0 24 * [0xf0c88000 - 0xf0c89fff] mem
+PCI: 00:10.0 10 * [0xf0c8a000 - 0xf0c8bfff] mem
+PCI: 00:08.0 1c * [0xf0c8c000 - 0xf0c8cfff] mem
+PCI: 00:11.0 24 * [0xf0c8d000 - 0xf0c8d3ff] mem
+PCI: 00:09.2 14 * [0xf0c8e000 - 0xf0c8e0ff] mem
+PCI: 00:12.0 10 * [0xf0c8f000 - 0xf0c8f0ff] mem
+PCI: 00:14.7 10 * [0xf0c90000 - 0xf0c900ff] mem
+DOMAIN: 0000 mem: next_base: f0c90100 size: 10c90100 align: 28 gran: 0 done
+PCI: 00:02.4 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
+PCI: 00:02.4 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
+PCI: 00:02.4 mem: base:f0800000 size:100000 align:20 gran:20 limit:f08fffff
+PCI: 01:00.0 14 * [0xf0800000 - 0xf087ffff] mem
+PCI: 01:00.0 30 * [0xf0880000 - 0xf08bffff] mem
+PCI: 01:00.0 10 * [0xf08c0000 - 0xf08dffff] mem
+PCI: 01:00.0 1c * [0xf08e0000 - 0xf08e3fff] mem
+PCI: 00:02.4 mem: next_base: f08e4000 size: 100000 align: 20 gran: 20 done
+PCI: 00:02.5 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
+PCI: 00:02.5 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
+PCI: 00:02.5 mem: base:f0900000 size:100000 align:20 gran:20 limit:f09fffff
+PCI: 02:00.0 10 * [0xf0900000 - 0xf0900fff] mem
+PCI: 00:02.5 mem: next_base: f0901000 size: 100000 align: 20 gran: 20 done
+Root Device assign_resources, bus 0 link: 0
+node 0: mmio_basek=00340000, basek=00400000, limitk=004a0000
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+PCI: 00:01.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem64
+PCI: 00:01.0 18 <- [0x00f0000000 - 0x00f07fffff] size 0x00800000 gran 0x17 prefmem64
+PCI: 00:01.0 20 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
+PCI: 00:01.0 24 <- [0x00f0c00000 - 0x00f0c3ffff] size 0x00040000 gran 0x12 mem
+PCI: 00:01.0 30 <- [0x00f0c40000 - 0x00f0c5ffff] size 0x00020000 gran 0x11 romem
+PCI: 00:01.1 10 <- [0x00f0c80000 - 0x00f0c83fff] size 0x00004000 gran 0x0e mem64
+PCI: 00:02.4 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
+PCI: 00:02.4 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem
+PCI: 00:02.4 20 <- [0x00f0800000 - 0x00f08fffff] size 0x00100000 gran 0x14 bus 01 mem
+PCI: 00:02.4 assign_resources, bus 1 link: 0
+PCI: 01:00.0 10 <- [0x00f08c0000 - 0x00f08dffff] size 0x00020000 gran 0x11 mem
+PCI: 01:00.0 14 <- [0x00f0800000 - 0x00f087ffff] size 0x00080000 gran 0x13 mem
+PCI: 01:00.0 18 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io
+PCI: 01:00.0 1c <- [0x00f08e0000 - 0x00f08e3fff] size 0x00004000 gran 0x0e mem
+PCI: 01:00.0 30 <- [0x00f0880000 - 0x00f08bffff] size 0x00040000 gran 0x12 romem
+PCI: 00:02.4 assign_resources, bus 1 link: 0
+PCI: 00:02.5 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
+PCI: 00:02.5 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem
+PCI: 00:02.5 20 <- [0x00f0900000 - 0x00f09fffff] size 0x00100000 gran 0x14 bus 02 mem
+PCI: 00:02.5 assign_resources, bus 2 link: 0
+PCI: 02:00.0 10 <- [0x00f0900000 - 0x00f0900fff] size 0x00001000 gran 0x0c mem
+PCI: 00:02.5 assign_resources, bus 2 link: 0
+PCI: 00:08.0 10 <- [0x00f0c60000 - 0x00f0c7ffff] size 0x00020000 gran 0x11 prefmem64
+PCI: 00:08.0 18 <- [0x00f0a00000 - 0x00f0afffff] size 0x00100000 gran 0x14 mem
+PCI: 00:08.0 1c <- [0x00f0c8c000 - 0x00f0c8cfff] size 0x00001000 gran 0x0c mem
+PCI: 00:08.0 20 <- [0x00f0b00000 - 0x00f0bfffff] size 0x00100000 gran 0x14 mem
+PCI: 00:08.0 24 <- [0x00f0c88000 - 0x00f0c89fff] size 0x00002000 gran 0x0d mem
+PCI: 00:09.2 10 <- [0x00f0c84000 - 0x00f0c87fff] size 0x00004000 gran 0x0e mem
+PCI: 00:09.2 14 <- [0x00f0c8e000 - 0x00f0c8e0ff] size 0x00000100 gran 0x08 mem
+PCI: 00:10.0 10 <- [0x00f0c8a000 - 0x00f0c8bfff] size 0x00002000 gran 0x0d mem64
+PCI: 00:11.0 10 <- [0x0000002410 - 0x0000002417] size 0x00000008 gran 0x03 io
+PCI: 00:11.0 14 <- [0x0000002420 - 0x0000002423] size 0x00000004 gran 0x02 io
+PCI: 00:11.0 18 <- [0x0000002418 - 0x000000241f] size 0x00000008 gran 0x03 io
+PCI: 00:11.0 1c <- [0x0000002424 - 0x0000002427] size 0x00000004 gran 0x02 io
+PCI: 00:11.0 20 <- [0x0000002400 - 0x000000240f] size 0x00000010 gran 0x04 io
+PCI: 00:11.0 24 <- [0x00f0c8d000 - 0x00f0c8d3ff] size 0x00000400 gran 0x0a mem
+PCI: 00:12.0 10 <- [0x00f0c8f000 - 0x00f0c8f0ff] size 0x00000100 gran 0x08 mem
+PCI: 00:14.7 10 <- [0x00f0c90000 - 0x00f0c900ff] size 0x00000100 gran 0x08 mem64
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+Root Device assign_resources, bus 0 link: 0
+Done setting resources.
+Show resources in subtree (Root Device)...After assigning values.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 10
+ APIC: 10
+ APIC: 11
+ DOMAIN: 0000 child on link 0 PCI: 00:00.0
+ DOMAIN: 0000 resource base 1000 size 1428 align 12 gran 0 limit ffff flags 40040100 index 10000000
+ DOMAIN: 0000 resource base e0000000 size 10c90100 align 28 gran 0 limit f7ffffff flags 40040200 index 10000100
+ DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
+ DOMAIN: 0000 resource base c0000 size cff40000 align 0 gran 0 limit 0 flags e0004200 index 20
+ DOMAIN: 0000 resource base 100000000 size 2f000000 align 0 gran 0 limit 0 flags e0004200 index 30
+ DOMAIN: 0000 resource base b0000000 size 20000000 align 0 gran 0 limit 0 flags f0000200 index 7
+ PCI: 00:00.0
+ PCI: 00:01.0
+ PCI: 00:01.0 resource base e0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001201 index 10
+ PCI: 00:01.0 resource base f0000000 size 800000 align 23 gran 23 limit f07fffff flags 60001201 index 18
+ PCI: 00:01.0 resource base 2000 size 100 align 8 gran 8 limit 20ff flags 60000100 index 20
+ PCI: 00:01.0 resource base f0c00000 size 40000 align 18 gran 18 limit f0c3ffff flags 60000200 index 24
+ PCI: 00:01.0 resource base f0c40000 size 20000 align 17 gran 17 limit f0c5ffff flags 60002200 index 30
+ PCI: 00:01.1
+ PCI: 00:01.1 resource base f0c80000 size 4000 align 14 gran 14 limit f0c83fff flags 60000201 index 10
+ PCI: 00:02.0
+ PCI: 00:02.1
+ PCI: 00:02.2
+ PCI: 00:02.3
+ PCI: 00:02.4 child on link 0 PCI: 01:00.0
+ PCI: 00:02.4 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c
+ PCI: 00:02.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24
+ PCI: 00:02.4 resource base f0800000 size 100000 align 20 gran 20 limit f08fffff flags 60080202 index 20
+ PCI: 01:00.0
+ PCI: 01:00.0 resource base f08c0000 size 20000 align 17 gran 17 limit f08dffff flags 60000200 index 10
+ PCI: 01:00.0 resource base f0800000 size 80000 align 19 gran 19 limit f087ffff flags 60000200 index 14
+ PCI: 01:00.0 resource base 1000 size 20 align 5 gran 5 limit 101f flags 60000100 index 18
+ PCI: 01:00.0 resource base f08e0000 size 4000 align 14 gran 14 limit f08e3fff flags 60000200 index 1c
+ PCI: 01:00.0 resource base f0880000 size 40000 align 18 gran 18 limit f08bffff flags 60002200 index 30
+ PCI: 00:02.5 child on link 0 PCI: 02:00.0
+ PCI: 00:02.5 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:02.5 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24
+ PCI: 00:02.5 resource base f0900000 size 100000 align 20 gran 20 limit f09fffff flags 60080202 index 20
+ PCI: 02:00.0
+ PCI: 02:00.0 resource base f0900000 size 1000 align 12 gran 12 limit f0900fff flags 60000200 index 10
+ PCI: 00:03.0
+ PCI: 00:08.0
+ PCI: 00:08.0 resource base f0c60000 size 20000 align 17 gran 17 limit f0c7ffff flags 60001201 index 10
+ PCI: 00:08.0 resource base f0a00000 size 100000 align 20 gran 20 limit f0afffff flags 60000200 index 18
+ PCI: 00:08.0 resource base f0c8c000 size 1000 align 12 gran 12 limit f0c8cfff flags 60000200 index 1c
+ PCI: 00:08.0 resource base f0b00000 size 100000 align 20 gran 20 limit f0bfffff flags 60000200 index 20
+ PCI: 00:08.0 resource base f0c88000 size 2000 align 13 gran 13 limit f0c89fff flags 60000200 index 24
+ PCI: 00:09.0
+ PCI: 00:09.2
+ PCI: 00:09.2 resource base f0c84000 size 4000 align 14 gran 14 limit f0c87fff flags 60000200 index 10
+ PCI: 00:09.2 resource base f0c8e000 size 100 align 12 gran 8 limit f0c8e0ff flags 60000200 index 14
+ PCI: 00:10.0
+ PCI: 00:10.0 resource base f0c8a000 size 2000 align 13 gran 13 limit f0c8bfff flags 60000201 index 10
+ PCI: 00:11.0
+ PCI: 00:11.0 resource base 2410 size 8 align 3 gran 3 limit 2417 flags 60000100 index 10
+ PCI: 00:11.0 resource base 2420 size 4 align 2 gran 2 limit 2423 flags 60000100 index 14
+ PCI: 00:11.0 resource base 2418 size 8 align 3 gran 3 limit 241f flags 60000100 index 18
+ PCI: 00:11.0 resource base 2424 size 4 align 2 gran 2 limit 2427 flags 60000100 index 1c
+ PCI: 00:11.0 resource base 2400 size 10 align 4 gran 4 limit 240f flags 60000100 index 20
+ PCI: 00:11.0 resource base f0c8d000 size 400 align 12 gran 10 limit f0c8d3ff flags 60000200 index 24
+ PCI: 00:12.0
+ PCI: 00:12.0 resource base f0c8f000 size 100 align 12 gran 8 limit f0c8f0ff flags 60000200 index 10
+ PCI: 00:14.0 child on link 0 I2C: 00:51
+ I2C: 00:51
+ PCI: 00:14.3
+ PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2
+ PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PCI: 00:14.7
+ PCI: 00:14.7 resource base f0c90000 size 100 align 12 gran 8 limit f0c900ff flags 60000201 index 10
+ PCI: 00:18.0
+ PCI: 00:18.0 resource base 0 size 0 align 0 gran 0 limit 0 flags 1 index 10b8
+ PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
+ PCI: 00:18.1
+ PCI: 00:18.2
+ PCI: 00:18.3
+ PCI: 00:18.4
+ PCI: 00:18.5
+Done allocating resources.
+BS: BS_DEV_RESOURCES times (us): entry 0 run 903734 exit 0
+PCI_INTR tables: Writing registers C00/C01 for PIC mode PCI IRQ routing:
+ PCI_INTR_INDEX PCI_INTR_DATA
+ 0x00 INTA# : 0x03
+ 0x01 INTB# : 0x04
+ 0x02 INTC# : 0x05
+ 0x03 INTD# : 0x07
+ 0x04 INTE# : 0x0B
+ 0x05 INTF# : 0x0A
+ 0x06 INTG# : 0x1F
+ 0x07 INTH# : 0x1F
+ 0x08 Misc : 0xFA
+ 0x09 Misc0 : 0xF1
+ 0x0A Misc1 : 0x00
+ 0x0B Misc2 : 0x00
+ 0x0C Ser IRQ INTA : 0x1F
+ 0x0D Ser IRQ INTB : 0x1F
+ 0x0E Ser IRQ INTC : 0x1F
+ 0x0F Ser IRQ INTD : 0x1F
+ 0x10 SCI : 0x1F
+ 0x11 SMBUS0 : 0x1F
+ 0x12 ASF : 0x1F
+ 0x13 HDA : 0x03
+ 0x14 FC : 0x1F
+ 0x15 GEC : 0x1F
+ 0x16 PerMon : 0x1F
+ 0x17 SD : 0x1F
+ 0x20 IMC INT0 : 0x1F
+ 0x21 IMC INT1 : 0x1F
+ 0x22 IMC INT2 : 0x1F
+ 0x23 IMC INT3 : 0x1F
+ 0x24 IMC INT4 : 0x1F
+ 0x25 IMC INT5 : 0x1F
+ 0x30 Dev18.0 INTA : 0x05
+ 0x31 Dev18.2 INTB : 0x04
+ 0x32 Dev19.0 INTA : 0x05
+ 0x33 Dev19.2 INTB : 0x04
+ 0x34 Dev22.0 INTA : 0x04
+ 0x35 Dev22.2 INTB : 0x05
+ 0x36 Dev20.5 INTC : 0x04
+ 0x40 IDE : 0x04
+ 0x41 SATA : 0x1F
+ 0x50 GPPInt0 : 0x03
+ 0x51 GPPInt1 : 0x04
+ 0x52 GPPInt2 : 0x05
+ 0x53 GPPInt3 : 0x07
+ 0x62 GPIO : 0x07
+ 0x70 I2C0 : 0x03
+ 0x71 I2C1 : 0x0F
+ 0x72 I2C2 : 0x06
+ 0x73 I2C3 : 0x0E
+ 0x74 UART0 : 0x0A
+ 0x75 UART1 : 0x0B
+PCI_INTR tables: Writing registers C00/C01 for APIC mode PCI IRQ routing:
+ PCI_INTR_INDEX PCI_INTR_DATA
+ 0x00 INTA# : 0x10
+ 0x01 INTB# : 0x11
+ 0x02 INTC# : 0x12
+ 0x03 INTD# : 0x13
+ 0x04 INTE# : 0x14
+ 0x05 INTF# : 0x15
+ 0x06 INTG# : 0x16
+ 0x07 INTH# : 0x17
+ 0x08 Misc : 0x00
+ 0x09 Misc0 : 0x00
+ 0x0A Misc1 : 0x00
+ 0x0B Misc2 : 0x00
+ 0x0C Ser IRQ INTA : 0x1F
+ 0x0D Ser IRQ INTB : 0x1F
+ 0x0E Ser IRQ INTC : 0x1F
+ 0x0F Ser IRQ INTD : 0x1F
+ 0x10 SCI : 0x09
+ 0x11 SMBUS0 : 0x1F
+ 0x12 ASF : 0x1F
+ 0x13 HDA : 0x10
+ 0x14 FC : 0x1F
+ 0x15 GEC : 0x1F
+ 0x16 PerMon : 0x1F
+ 0x17 SD : 0x10
+ 0x20 IMC INT0 : 0x1F
+ 0x21 IMC INT1 : 0x1F
+ 0x22 IMC INT2 : 0x1F
+ 0x23 IMC INT3 : 0x1F
+ 0x24 IMC INT4 : 0x1F
+ 0x25 IMC INT5 : 0x1F
+ 0x30 Dev18.0 INTA : 0x12
+ 0x31 Dev18.2 INTB : 0x11
+ 0x32 Dev19.0 INTA : 0x12
+ 0x33 Dev19.2 INTB : 0x11
+ 0x34 Dev22.0 INTA : 0x12
+ 0x35 Dev22.2 INTB : 0x11
+ 0x36 Dev20.5 INTC : 0x12
+ 0x40 IDE : 0x11
+ 0x41 SATA : 0x13
+ 0x50 GPPInt0 : 0x1F
+ 0x51 GPPInt1 : 0x1F
+ 0x52 GPPInt2 : 0x1F
+ 0x53 GPPInt3 : 0x1F
+ 0x62 GPIO : 0x07
+ 0x70 I2C0 : 0x03
+ 0x71 I2C1 : 0x0F
+ 0x72 I2C2 : 0x06
+ 0x73 I2C3 : 0x0E
+ 0x74 UART0 : 0x0A
+ 0x75 UART1 : 0x0B
+Warning: Can't write PCI IRQ assignments because 'mainboard_pirq_data' structure does not exist
+Enabling resources...
+agesawrapper_amdinitmid() entry
+CBFS: 'Master Header Locator' located CBFS at [100:7fffc0)
+CBFS: Locating 'AGESA'
+CBFS: Found @ offset 5ffec0 size f38ac
+CBFS: 'Master Header Locator' located CBFS at [100:7fffc0)
+CBFS: Locating 'AGESA'
+CBFS: Found @ offset 5ffec0 size f38ac
+Done
+CBFS: 'Master Header Locator' located CBFS at [100:7fffc0)
+CBFS: Locating 'AGESA'
+CBFS: Found @ offset 5ffec0 size f38ac
+agesawrapper_amdinitmid() returned AGESA_SUCCESS
+ ader - leaving domain_enable_resources.
+PCI: 00:00.0 subsystem <- 1022/1410
+PCI: 00:00.0 cmd <- 04
+PCI: 00:01.0 subsystem <- 1022/1410
+PCI: 00:01.0 cmd <- 07
+PCI: 00:01.1 subsystem <- 1022/1410
+PCI: 00:01.1 cmd <- 02
+PCI: 00:02.0 subsystem <- 1022/1410
+PCI: 00:02.0 cmd <- 00
+PCI: 00:02.4 bridge ctrl <- 0003
+PCI: 00:02.4 cmd <- 07
+PCI: 00:02.5 bridge ctrl <- 0003
+PCI: 00:02.5 cmd <- 06
+PCI: 00:03.0 cmd <- 00
+PCI: 00:08.0 cmd <- 06
+PCI: 00:09.0 subsystem <- 1022/1410
+PCI: 00:09.0 cmd <- 00
+PCI: 00:09.2 subsystem <- 1022/1410
+PCI: 00:09.2 cmd <- 06
+PCI: 00:10.0 subsystem <- 1022/1410
+PCI: 00:10.0 cmd <- 02
+PCI: 00:11.0 subsystem <- 1022/1410
+PCI: 00:11.0 cmd <- 07
+PCI: 00:12.0 subsystem <- 1022/1410
+PCI: 00:12.0 cmd <- 02
+PCI: 00:14.0 subsystem <- 1022/1410
+PCI: 00:14.0 cmd <- 403
+PCI: 00:14.3 subsystem <- 1022/1410
+PCI: 00:14.3 cmd <- 0f
+PCI: 00:14.7 subsystem <- 1022/1410
+PCI: 00:14.7 cmd <- 06
+PCI: 00:18.0 cmd <- 00
+PCI: 00:18.1 subsystem <- 1022/1410
+PCI: 00:18.1 cmd <- 00
+PCI: 00:18.2 subsystem <- 1022/1410
+PCI: 00:18.2 cmd <- 00
+PCI: 00:18.3 subsystem <- 1022/1410
+PCI: 00:18.3 cmd <- 00
+PCI: 00:18.4 subsystem <- 1022/1410
+PCI: 00:18.4 cmd <- 00
+PCI: 00:18.5 subsystem <- 1022/1410
+PCI: 00:18.5 cmd <- 00
+PCI: 01:00.0 cmd <- 03
+PCI: 02:00.0 cmd <- 02
+done.
+BS: BS_DEV_ENABLE times (us): entry 111273 run 83359 exit 0
+Initializing devices...
+Root Device init ...
+Root Device init finished in 957 usecs
+CPU_CLUSTER: 0 init ...
+start_eip=0x00001000, code_size=0x00000031
+Initializing CPU #0
+CPU: vendor AMD device 670f00
+CPU: family 15, model 70, stepping 00
+Model 15 Init.
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Enabling cache
+Setting up local APIC... apic_id: 0x10 done.
+siblings = 01, Bar3=f0b00000
+CPU #0 initialized
+CPU1: stack_base 0021e000, stack_end 0021eff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 17.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 17.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+Initializing CPU #1
+Waiting for 1 CPUS to stop
+CPU: vendor AMD device 670f00
+CPU: family 15, model 70, stepping 00
+Model 15 Init.
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Enabling cache
+Setting up local APIC... apic_id: 0x11 done.
+siblings = 01, Bar3=f0b00000
+CPU #1 initialized
+All AP CPUs stopped (1088 loops)
+CPU0: stack: 0021f000 - 00220000, lowest used address 0021f5c8, stack used: 2616 bytes
+CPU1: stack: 0021e000 - 0021f000, lowest used address 0021edbc, stack used: 580 bytes
+CPU_CLUSTER: 0 init finished in 66217 usecs
+PCI: 00:00.0 init ...
+PCI: 00:00.0 init finished in 1001 usecs
+PCI: 00:01.0 init ...
+CBFS: 'Master Header Locator' located CBFS at [100:7fffc0)
+CBFS: Locating 'pci1002,98e4.rom'
+CBFS: Found @ offset 127200 size fc00
+Mapping PCI device 100298e4 to 100298e0
+In CBFS, ROM address for PCI: 00:01.0 = ff927348
+PCI expansion ROM, signature 0xaa55, INIT size 0xfc00, data ptr 0x01c0
+PCI ROM image, vendor ID 1002, device ID 98e0,
+PCI ROM image, Class Code 030000, Code Type 00
+Copying VGA ROM Image from ff927348 to 0xc0000, 0xfc00 bytes
+Real mode stub @00000600: 867 bytes
+Calling Option ROM...
+... Option ROM returned.
+VGA Option ROM was run
+PCI: 00:01.0 init finished in 188177 usecs
+PCI: 00:01.1 init ...
+PCI: 00:01.1 init finished in 1010 usecs
+PCI: 00:02.0 init ...
+PCI: 00:02.0 init finished in 1000 usecs
+PCI: 00:03.0 init ...
+PCI: 00:03.0 init finished in 1000 usecs
+PCI: 00:08.0 init ...
+PCI: 00:08.0 init finished in 1000 usecs
+PCI: 00:09.0 init ...
+PCI: 00:09.0 init finished in 1000 usecs
+PCI: 00:09.2 init ...
+PCI: 00:09.2 init finished in 1000 usecs
+PCI: 00:10.0 init ...
+PCI: 00:10.0 init finished in 1005 usecs
+PCI: 00:11.0 init ...
+PCI: 00:11.0 init finished in 1000 usecs
+PCI: 00:12.0 init ...
+PCI: 00:12.0 init finished in 1000 usecs
+PCI: 00:14.0 init ...
+PCI: 00:14.0 init finished in 1000 usecs
+PCI: 00:14.3 init ...
+RTC Init
+PCI: 00:14.3 init finished in 1464 usecs
+PCI: 00:14.7 init ...
+PCI: 00:14.7 init finished in 1000 usecs
+PCI: 00:18.0 init ...
+PCI: 00:18.0 init finished in 1000 usecs
+PCI: 00:18.1 init ...
+PCI: 00:18.1 init finished in 1000 usecs
+PCI: 00:18.2 init ...
+PCI: 00:18.2 init finished in 1000 usecs
+PCI: 00:18.3 init ...
+PCI: 00:18.3 init finished in 1000 usecs
+PCI: 00:18.4 init ...
+PCI: 00:18.4 init finished in 1000 usecs
+PCI: 00:18.5 init ...
+PCI: 00:18.5 init finished in 1000 usecs
+PCI: 01:00.0 init ...
+PCI: 01:00.0 init finished in 1000 usecs
+PCI: 02:00.0 init ...
+PCI: 02:00.0 init finished in 1000 usecs
+Devices initialized
+Show all devs... After init.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+APIC: 10: enabled 1
+DOMAIN: 0000: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 1
+PCI: 00:01.1: enabled 1
+PCI: 00:02.0: enabled 1
+PCI: 00:02.1: enabled 0
+PCI: 00:02.2: enabled 0
+PCI: 00:02.3: enabled 0
+PCI: 00:02.4: enabled 1
+PCI: 00:02.5: enabled 1
+PCI: 00:09.0: enabled 1
+PCI: 00:09.2: enabled 1
+PCI: 00:10.0: enabled 1
+PCI: 00:11.0: enabled 1
+PCI: 00:12.0: enabled 1
+PCI: 00:14.0: enabled 1
+I2C: 00:51: enabled 1
+PCI: 00:14.3: enabled 1
+PCI: 00:14.7: enabled 1
+PCI: 00:18.0: enabled 1
+PCI: 00:18.1: enabled 1
+PCI: 00:18.2: enabled 1
+PCI: 00:18.3: enabled 1
+PCI: 00:18.4: enabled 1
+PCI: 00:18.5: enabled 1
+APIC: 11: enabled 1
+PCI: 00:03.0: enabled 1
+PCI: 00:08.0: enabled 1
+PCI: 01:00.0: enabled 1
+PCI: 02:00.0: enabled 1
+BS: BS_DEV_INIT times (us): entry 0 run 359773 exit 0
+CBMEM:
+IMD: root @ affff000 254 entries.
+IMD: root @ afffec00 62 entries.
+Moving GDT to afffea00...ok
+Finalize devices...
+Devices finalized
+agesawrapper_amdinitlate() entry
+CBFS: 'Master Header Locator' located CBFS at [100:7fffc0)
+CBFS: Locating 'AGESA'
+CBFS: Found @ offset 5ffec0 size f38ac
+CBFS: 'Master Header Locator' located CBFS at [100:7fffc0)
+CBFS: Locating 'AGESA'
+CBFS: Found @ offset 5ffec0 size f38ac
+DmiTable:10011325, AcpiPstatein: 100102b7, AcpiSrat:0,AcpiSlit:0, Mce:0, Cmc:0,Alib:10012568, AcpiIvrs:0 in agesawrapper_amdinitlate
+agesawrapper_amdinitlate() returned AGESA_SUCCESS
+BS: BS_POST_DEVICE times (us): entry 4619 run 1742 exit 22631
+BS: BS_OS_RESUME_CHECK times (us): entry 0 run 0 exit 0
+Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.
+Writing IRQ routing tables to 0xaffd5000...write_pirq_routing_table done.
+PIRQ table: 48 bytes.
+Wrote the mp table end at: 000f0410 - 000f05a4
+Wrote the mp table end at: affd4010 - affd41a4
+MP table: 420 bytes.
+CBFS: 'Master Header Locator' located CBFS at [100:7fffc0)
+CBFS: Locating 'fallback/dsdt.aml'
+CBFS: Found @ offset 13940 size 177a
+CBFS: 'Master Header Locator' located CBFS at [100:7fffc0)
+CBFS: Locating 'fallback/slic'
+CBFS: 'fallback/slic' not found.
+ACPI: Writing ACPI tables at affb0000.
+ACPI: * FACS
+ACPI: * DSDT
+ACPI: * FADT
+pm_base: 0x0800
+ACPI: added table 1/32, length now 40
+ACPI: * SSDT
+ACPI: added table 2/32, length now 44
+ACPI: * MCFG
+ACPI: * TCPA
+TCPA log created at affa0000
+ACPI: added table 3/32, length now 48
+ACPI: * MADT
+ACPI: added table 4/32, length now 52
+current = affb1c40
+ACPI: * HPET
+ACPI: added table 5/32, length now 56
+ACPI: added table 6/32, length now 60
+ACPI: * IVRS at affb1ca8
+ AGESA IVRS table NULL. Skipping.
+ACPI: * SRAT at affb1ca8
+ AGESA SRAT table NULL. Skipping.
+ACPI: * SLIT at affb1ca8
+ AGESA SLIT table NULL. Skipping.
+ACPI: * AGESA ALIB SSDT at affb1cb0
+ACPI: added table 7/32, length now 64
+ACPI: * SSDT at affb6810
+ACPI: added table 8/32, length now 68
+ACPI: * SSDT for PState at affb6ec2
+ACPI: done.
+ACPI tables: 28368 bytes.
+smbios_write_tables: aff9f000
+Root Device (AMD GARDENIA)
+CPU_CLUSTER: 0 (AMD FAM15 Root Complex)
+APIC: 10 (AMD CPU Family 15h Model 70h-7Fh)
+DOMAIN: 0000 (AMD FAM15 Root Complex)
+PCI: 00:00.0 (AMD FAM15 Northbridge)
+PCI: 00:01.0 (AMD FAM15 Northbridge)
+PCI: 00:01.1 (AMD FAM15 Northbridge)
+PCI: 00:02.0 (AMD FAM15 Northbridge)
+PCI: 00:02.1 (AMD FAM15 Northbridge)
+PCI: 00:02.2 (AMD FAM15 Northbridge)
+PCI: 00:02.3 (AMD FAM15 Northbridge)
+PCI: 00:02.4 (AMD FAM15 Northbridge)
+PCI: 00:02.5 (AMD FAM15 Northbridge)
+PCI: 00:09.0 (ATI HUDSON)
+PCI: 00:09.2 (ATI HUDSON)
+PCI: 00:10.0 (ATI HUDSON)
+PCI: 00:11.0 (ATI HUDSON)
+PCI: 00:12.0 (ATI HUDSON)
+PCI: 00:14.0 (ATI HUDSON)
+I2C: 00:51 (unknown)
+PCI: 00:14.3 (ATI HUDSON)
+PCI: 00:14.7 (ATI HUDSON)
+PCI: 00:18.0 (AMD FAM15 Northbridge)
+PCI: 00:18.1 (AMD FAM15 Northbridge)
+PCI: 00:18.2 (AMD FAM15 Northbridge)
+PCI: 00:18.3 (AMD FAM15 Northbridge)
+PCI: 00:18.4 (AMD FAM15 Northbridge)
+PCI: 00:18.5 (AMD FAM15 Northbridge)
+APIC: 11 (unknown)
+PCI: 00:03.0 (unknown)
+PCI: 00:08.0 (unknown)
+PCI: 01:00.0 (unknown)
+PCI: 02:00.0 (unknown)
+SMBIOS tables: 335 bytes.
+Writing table forward entry at 0x00000500
+Wrote coreboot table at: 00000500, 0x10 bytes, checksum efe0
+Writing coreboot table at 0xaffd6000
+ 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
+ 1. 0000000000001000-000000000009ffff: RAM
+ 2. 00000000000c0000-00000000aff9efff: RAM
+ 3. 00000000aff9f000-00000000afffffff: CONFIGURATION TABLES
+ 4. 00000000b0000000-00000000cfffffff: RESERVED
+ 5. 00000000f8000000-00000000fbffffff: RESERVED
+ 6. 0000000100000000-000000012effffff: RAM
+CBFS: 'Master Header Locator' located CBFS at [100:7fffc0)
+FMAP: Found "FLASH" version 1.1 at 0.
+FMAP: base = ff800000 size = 800000 #areas = 3
+Wrote coreboot table at: affd6000, 0x244 bytes, checksum 726f
+coreboot table: 604 bytes.
+IMD ROOT 0. affff000 00001000
+IMD SMALL 1. afffe000 00001000
+CONSOLE 2. affde000 00020000
+COREBOOT 3. affd6000 00008000
+IRQ TABLE 4. affd5000 00001000
+SMP TABLE 5. affd4000 00001000
+ACPI 6. affb0000 00024000
+TCPA LOG 7. affa0000 00010000
+SMBIOS 8. aff9f000 00000800
+IMD small region:
+ IMD ROOT 0. afffec00 00000400
+ GDT 1. afffea00 00000200
+BS: BS_WRITE_TABLES times (us): entry 0 run 163231 exit 0
+CBFS: 'Master Header Locator' located CBFS at [100:7fffc0)
+CBFS: Locating 'fallback/payload'
+CBFS: Found @ offset 136e80 size ebce
+Loading segment from ROM address 0xff936fb8
+ code (compression=1)
+ New segment dstaddr 0xe4660 memsize 0x1b9a0 srcaddr 0xff936ff0 filesize 0xeb96
+Loading segment from ROM address 0xff936fd4
+ Entry Point 0x000ff06e
+Bounce Buffer at afd96000, 2130336 bytes
+Loading Segment: addr: 0x00000000000e4660 memsz: 0x000000000001b9a0 filesz: 0x000000000000eb96
+lb: [0x0000000000200000, 0x00000000003040d0)
+Post relocation: addr: 0x00000000000e4660 memsz: 0x000000000001b9a0 filesz: 0x000000000000eb96
+using LZMA
+[ 0x000e4660, 00100000, 0x00100000) <- ff936ff0
+dest 000e4660, end 00100000, bouncebuffer afd96000
+Loaded segments
+BS: BS_PAYLOAD_LOAD times (us): entry 0 run 38340 exit 0
+Jumping to boot code at 000ff06e(affd6000)
+CPU0: stack: 0021f000 - 00220000, lowest used address 0021f5c8, stack used: 2616 bytes
+entry = 0x000ff06e
+lb_start = 0x00200000
+lb_size = 0x001040d0
+buffer = 0xafd96000
+SeaBIOS (version rel-1.9.3-0-ge2fc41e)
+BUILD: gcc: (coreboot toolchain v1.42 August 11th, 2016) 5.3.0 binutils: (GNU Binutils) 2.26.1
+Found coreboot cbmem console @ affde000
+Found mainboard AMD GARDENIA
+Relocating init from 0x000e5a80 to 0xaff53be0 (size 45952)
+Found CBFS header at 0xff800138
+multiboot: eax=0, ebx=0
+Found 24 PCI devices (max PCI bus is 02)
+Copying SMBIOS entry point from 0xaff9f000 to 0x000f0de0
+Copying ACPI RSDP from 0xaffb0000 to 0x000f0db0
+Copying MPTABLE from 0xaffd4000/affd4010 to 0x000f0c00
+Copying PIR from 0xaffd5000 to 0x000f0bd0
+Using pmtimer, ioport 0x818
+Scan for VGA option rom
+Running option rom at c000:0003
+Turning on vga text mode console
+SeaBIOS (version rel-1.9.3-0-ge2fc41e)
+XHCI init on dev 00:10.0: regs @ 0xf0c8a000, 8 ports, 32 slots, 32 byte contexts
+XHCI extcap 0x1 @ f0c8a500
+XHCI protocol USB 3.00, 4 ports (offset 1), def 0
+XHCI protocol USB 2.00, 4 ports (offset 5), def 18
+XHCI extcap 0xa @ f0c8a540
+EHCI init on dev 00:12.0 (regs=0xf0c8f020)
+Found 0 lpt ports
+Found 0 serial ports
+AHCI controller at 11.0, iobase f0c8d000, irq 0
+Searching bootorder for: /pci@i0cf8/*@14,7
+PS2 keyboard initialized
+XHCI port #5: 0x00200e03, powered, enabled, pls 0, speed 3 [High]
+Initialized USB HUB (0 ports used)
+Searching bootorder for: /pci@i0cf8/usb@10/hub@5/storage@3/*@0/*@0,0
+Searching bootorder for: /pci@i0cf8/usb@10/hub@5/usb-*@3
+USB MSC vendor='Lexar' product='USB Flash Drive' rev='1100' type=0 removable=1
+USB MSC blksize=512 sectors=31285248
+Initialized USB HUB (1 ports used)
+All threads complete.
+Scan for option roms
+Running option rom at d000:0003
+Searching bootorder for: /pci@i0cf8/pci-bridge@2,4/*@0
+
+Press ESC for boot menu.
+
+Searching bootorder for: HALT
+drive 0x000f0b80: PCHS=0/0/0 translation=lba LCHS=1024/255/63 s=31285248
+Space available for UMB: d1000-ee800, f0000-f0b80
+Returned 221184 bytes of ZoneHigh
+e820 map has 7 items:
+ 0: 0000000000000000 - 000000000009fc00 = 1 RAM
+ 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
+ 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
+ 3: 0000000000100000 - 00000000aff95000 = 1 RAM
+ 4: 00000000aff95000 - 00000000d0000000 = 2 RESERVED
+ 5: 00000000f8000000 - 00000000fc000000 = 2 RESERVED
+ 6: 0000000100000000 - 000000012f000000 = 1 RAM
+enter handle_19:
+ NULL
+Booting from Hard Disk...
+Booting from 0000:7c00
+