/*
 * Intel ACPI Component Architecture
 * AML/ASL+ Disassembler version 20160831-64
 * Copyright (c) 2000 - 2016 Intel Corporation
 * 
 * Disassembling to symbolic ASL+ operators
 *
 * Disassembly of ssdt2.dat, Mon Jan  2 15:19:14 2017
 *
 * Original Table Header:
 *     Signature        "SSDT"
 *     Length           0x00000143 (323)
 *     Revision         0x01
 *     Checksum         0x77
 *     OEM ID           "AMI"
 *     OEM Table ID     "CPU2PM"
 *     OEM Revision     0x00000001 (1)
 *     Compiler ID      "INTL"
 *     Compiler Version 0x20060113 (537264403)
 */
DefinitionBlock ("", "SSDT", 1, "AMI", "CPU2PM", 0x00000001)
{
    External (_PR_.CPU1._PPC, IntObj)
    External (_PR_.CPU1._PSS, IntObj)
    External (_PR_.CPU2, DeviceObj)
    External (CFGD, UnknownObj)
    External (NCPU, UnknownObj)
    External (TYPE, UnknownObj)

    Scope (\_PR.CPU2)
    {
        Name (NPCT, Package (0x02)
        {
            ResourceTemplate ()
            {
                Register (FFixedHW, 
                    0x40,               // Bit Width
                    0x00,               // Bit Offset
                    0x0000000000000199, // Address
                    ,)
            }, 

            ResourceTemplate ()
            {
                Register (FFixedHW, 
                    0x10,               // Bit Width
                    0x00,               // Bit Offset
                    0x0000000000000198, // Address
                    ,)
            }
        })
        Name (SPCT, Package (0x02)
        {
            ResourceTemplate ()
            {
                Register (SystemIO, 
                    0x10,               // Bit Width
                    0x00,               // Bit Offset
                    0x0000000000000904, // Address
                    ,)
            }, 

            ResourceTemplate ()
            {
                Register (SystemIO, 
                    0x10,               // Bit Width
                    0x00,               // Bit Offset
                    0x0000000000000906, // Address
                    ,)
            }
        })
        Method (_PCT, 0, NotSerialized)  // _PCT: Performance Control
        {
            If ((TYPE & 0x01) == 0x01)
            {
                Return (NPCT) /* \_PR_.CPU2.NPCT */
            }
            Else
            {
                Return (SPCT) /* \_PR_.CPU2.SPCT */
            }
        }

        Name (XPSS, 0x00)
        Method (_PSS, 0, NotSerialized)  // _PSS: Performance Supported States
        {
            Return (\_PR.CPU1._PSS) /* External reference */
        }

        Method (_PPC, 0, NotSerialized)  // _PPC: Performance Present Capabilities
        {
            Return (\_PR.CPU1._PPC) /* External reference */
        }

        Method (_PSD, 0, NotSerialized)  // _PSD: Power State Dependencies
        {
            If (CFGD & 0x01000000)
            {
                If (TYPE & 0x0800)
                {
                    Return (Package (0x01)
                    {
                        Package (0x05)
                        {
                            0x05, 
                            0x00, 
                            0x00, 
                            0xFE, 
                            NCPU
                        }
                    })
                }

                Return (Package (0x01)
                {
                    Package (0x05)
                    {
                        0x05, 
                        0x00, 
                        0x00, 
                        0xFC, 
                        NCPU
                    }
                })
            }

            Return (Package (0x01)
            {
                Package (0x05)
                {
                    0x05, 
                    0x00, 
                    0x00, 
                    0xFC, 
                    NCPU
                }
            })
        }
    }
}