asus/m4a785t-m/4.1-782-ga4ffe8a/2015-10-22T18:20:48Z
I only tested booting with a 32bit GNU/Linux installation:
* Serial console works fine.
* I didn't test without blacklisting the snd_hda_intel module.
* It does boot up to the desktop environment (xfce4).
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
diff --git a/asus/m4a785t-m/4.1-782-ga4ffe8a/2015-10-22T18:20:48Z/coreboot_console.txt b/asus/m4a785t-m/4.1-782-ga4ffe8a/2015-10-22T18:20:48Z/coreboot_console.txt
new file mode 100644
index 0000000..26f0bef
--- /dev/null
+++ b/asus/m4a785t-m/4.1-782-ga4ffe8a/2015-10-22T18:20:48Z/coreboot_console.txt
@@ -0,0 +1,1530 @@
+
+
+coreboot-4.1-782-ga4ffe8a Thu Oct 22 18:20:48 UTC 2015 romstage starting...
+BSP Family_Model: 00100f62
+*sysinfo range: [000c4d20,000c8954]
+bsp_apicid = 00
+cpu_init_detectedx = 00000000
+CBFS @ 0 size ffa00
+CBFS: Locating 'microcode_amd.bin'
+CBFS: Found @ offset 3040 size 318c
+[microcode] patch id to apply = 0x010000c7
+[microcode] updated to patch id = 0x010000c7 success
+CBFS @ 0 size ffa00
+CBFS: Locating 'microcode_amd_fam15h.bin'
+CBFS: 'microcode_amd_fam15h.bin' not found.
+[microcode] microcode file not found. Skipping updates.
+cpuSetAMDMSR done
+Enter amd_ht_init()
+CBFS @ 0 size ffa00
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 140 size 590
+WARNING: No CMOS option 'hypertransport_speed_limit'.
+Exit amd_ht_init()
+cpuSetAMDPCI 00 done
+Prep FID/VID Node:00
+ F3x80: e600e681
+ F3x84: 80e641e6
+ F3xD4: c8810f26
+ F3xD8: 03001016
+ F3xDC: 0000532a
+core0 started:
+start_other_cores()
+init node: 00 cores: 01
+Start other core - nodeid: 00 cores: 01
+started ap apicid: * AP 01started
+
+rs780_early_setup()
+fam10_optimization()
+rs780_por_init
+sb700_early_setup()
+sb700_devices_por_init()
+sb700_devices_por_init(): SMBus Device, BDF:0-20-0
+SMBus controller enabled, sb revision is A14
+sb700_devices_por_init(): IDE Device, BDF:0-20-1
+sb700_devices_por_init(): LPC Device, BDF:0-20-3
+sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
+sb700_devices_por_init(): SATA Device, BDF:0-18-0
+sb700_pmio_por_init()
+
+Begin FIDVID MSR 0xc0010071 0x30bc0073 0x3c005440
+End FIDVIDMSR 0xc0010071 0x30bc0073 0x3c001c0e
+rs780_htinit cpu_ht_freq=b.
+rs780_htinit: HT3 mode
+fill_mem_ctrl()
+raminit_amdmct()
+raminit_amdmct begin:
+ DIMMPresence: DIMMValid=8
+ DIMMPresence: DIMMPresent=8
+ DIMMPresence: RegDIMMPresent=0
+ DIMMPresence: DimmECCPresent=0
+ DIMMPresence: DimmPARPresent=0
+ DIMMPresence: Dimmx4Present=0
+ DIMMPresence: Dimmx8Present=8
+ DIMMPresence: Dimmx16Present=0
+ DIMMPresence: DimmPlPresent=0
+ DIMMPresence: DimmDRPresent=0
+ DIMMPresence: DimmQRPresent=0
+ DIMMPresence: DATAload[0]=0
+ DIMMPresence: MAload[0]=0
+ DIMMPresence: MAdimms[0]=0
+ DIMMPresence: DATAload[1]=1
+ DIMMPresence: MAload[1]=8
+ DIMMPresence: MAdimms[1]=1
+ DIMMPresence: Status 1000
+ DIMMPresence: ErrStatus 0
+ DIMMPresence: ErrCode 0
+ DIMMPresence: Done
+
+ DCTInit_D: mct_DIMMPresence Done
+SPDCalcWidth: Status 1000
+SPDCalcWidth: ErrStatus 0
+SPDCalcWidth: ErrCode 0
+SPDCalcWidth: Done
+ DCTInit_D: mct_SPDCalcWidth Done
+CBFS @ 0 size ffa00
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 140 size 590
+SPDGetTCL_D: DIMMCASL 4
+SPDGetTCL_D: DIMMAutoSpeed 4
+SPDGetTCL_D: Status 1000
+SPDGetTCL_D: ErrStatus 0
+SPDGetTCL_D: ErrCode 0
+SPDGetTCL_D: Done
+
+AutoCycTiming: Status 1000
+AutoCycTiming: ErrStatus 0
+AutoCycTiming: ErrCode 2
+AutoCycTiming: Done
+
+ DCTInit_D: mct_DIMMPresence Done
+SPDCalcWidth: Status 1000
+SPDCalcWidth: ErrStatus 0
+SPDCalcWidth: ErrCode 0
+SPDCalcWidth: Done
+ DCTInit_D: mct_SPDCalcWidth Done
+AutoCycTiming: Status 1000
+AutoCycTiming: ErrStatus 0
+AutoCycTi
+
+*** Log truncated, 4046 characters dropped. ***
+
+amdmct_cbmem_store_info: Storing AMDMCT configuration in CBMEM
+CBFS @ 0 size ffa00
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 140 size 590
+WARNING: No CMOS option 'ecc_scrub_rate'.
+Prepare CAR migration and stack regions... Fill [003fbc00-003fffff] ... Done
+Copying data from cache to RAM... Copy [000c4c00-000c897f] to [003fc280 - 003fffff] ... Done
+Switching to use RAM as stack... Top about 003fc26c ... Done
+Disabling cache as ram now
+Prepare ramstage memory region... Fill [00000000-003fbbff] ... CBFS @ 0 size ffa00
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 140 size 590
+
+
+coreboot-4.1-782-ga4ffe8a Thu Oct 22 18:20:48 UTC 2015 ramstage starting...
+Moving GDT to 6fffe700...ok
+BS: Entering BS_PRE_DEVICE state.
+BS: Exiting BS_PRE_DEVICE state.
+BS: BS_PRE_DEVICE times (us): entry 0 run 2962 exit 0
+BS: Entering BS_DEV_INIT_CHIPS state.
+BS: Exiting BS_DEV_INIT_CHIPS state.
+BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3311 exit 0
+BS: Entering BS_DEV_ENUMERATE state.
+Enumerating buses...
+Show all devs... Before device enumeration.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+APIC: 00: enabled 1
+DOMAIN: 0000: enabled 1
+PCI: 00:18.0: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 1
+PCI: 00:05.0: enabled 1
+PCI: 00:02.0: enabled 1
+PCI: 00:03.0: enabled 0
+PCI: 00:04.0: enabled 0
+PCI: 00:05.0: enabled 0
+PCI: 00:06.0: enabled 0
+PCI: 00:07.0: enabled 0
+PCI: 00:08.0: enabled 0
+PCI: 00:09.0: enabled 0
+PCI: 00:0a.0: enabled 1
+PCI: 00:11.0: enabled 1
+PCI: 00:12.0: enabled 1
+PCI: 00:12.1: enabled 1
+PCI: 00:12.2: enabled 1
+PCI: 00:13.0: enabled 1
+PCI: 00:13.1: enabled 1
+PCI: 00:13.2: enabled 1
+PCI: 00:14.0: enabled 1
+I2C: 00:50: enabled 1
+I2C: 00:51: enabled 1
+I2C: 00:52: enabled 1
+I2C: 00:53: enabled 1
+PCI: 00:14.1: enabled 1
+PCI: 00:14.2: enabled 1
+PCI: 00:14.3: enabled 1
+PNP: 002e.0: enabled 0
+PNP: 002e.1: enabled 1
+PNP: 002e.2: enabled 0
+PNP: 002e.3: enabled 0
+PNP: 002e.4: enabled 0
+PNP: 002e.5: enabled 1
+PNP: 002e.6: enabled 1
+PNP: 002e.7: enabled 0
+PNP: 002e.8: enabled 0
+PNP: 002e.9: enabled 0
+PNP: 002e.a: enabled 0
+PCI: 00:14.4: enabled 1
+PCI: 00:14.5: enabled 1
+PCI: 00:18.1: enabled 1
+PCI: 00:18.2: enabled 1
+PCI: 00:18.3: enabled 1
+PCI: 00:18.4: enabled 1
+Compare with tree...
+Root Device: enabled 1
+ CPU_CLUSTER: 0: enabled 1
+ APIC: 00: enabled 1
+ DOMAIN: 0000: enabled 1
+ PCI: 00:18.0: enabled 1
+ PCI: 00:00.0: enabled 1
+ PCI: 00:01.0: enabled 1
+ PCI: 00:05.0: enabled 1
+ PCI: 00:02.0: enabled 1
+ PCI: 00:03.0: enabled 0
+ PCI: 00:04.0: enabled 0
+ PCI: 00:05.0: enabled 0
+ PCI: 00:06.0: enabled 0
+ PCI: 00:07.0: enabled 0
+ PCI: 00:08.0: enabled 0
+ PCI: 00:09.0: enabled 0
+ PCI: 00:0a.0: enabled 1
+ PCI: 00:11.0: enabled 1
+ PCI: 00:12.0: enabled 1
+ PCI: 00:12.1: enabled 1
+ PCI: 00:12.2: enabled 1
+ PCI: 00:13.0: enabled 1
+ PCI: 00:13.1: enabled 1
+ PCI: 00:13.2: enabled 1
+ PCI: 00:14.0: enabled 1
+ I2C: 00:50: enabled 1
+ I2C: 00:51: enabled 1
+ I2C: 00:52: enabled 1
+ I2C: 00:53: enabled 1
+ PCI: 00:14.1: enabled 1
+ PCI: 00:14.2: enabled 1
+ PCI: 00:14.3: enabled 1
+ PNP: 002e.0: enabled 0
+ PNP: 002e.1: enabled 1
+ PNP: 002e.2: enabled 0
+ PNP: 002e.3: enabled 0
+ PNP: 002e.4: enabled 0
+ PNP: 002e.5: enabled 1
+ PNP: 002e.6: enabled 1
+ PNP: 002e.7: enabled 0
+ PNP: 002e.8: enabled 0
+ PNP: 002e.9: enabled 0
+ PNP: 002e.a: enabled 0
+ PCI: 00:14.4: enabled 1
+ PCI: 00:14.5: enabled 1
+ PCI: 00:18.1: enabled 1
+ PCI: 00:18.2: enabled 1
+ PCI: 00:18.3: enabled 1
+ PCI: 00:18.4: enabled 1
+Mainboard enable. dev=0x0011e3a0
+Init adt7461 end , status 0x02 fd
+Root Device scanning...
+root_dev_scan_bus for Root Device
+setup_bsp_ramtop, TOP MEM: msr.lo = 0x80000000, msr.hi = 0x00000000
+setup_bsp_ramtop, TOP MEM2: msr.lo = 0x00000000, msr.hi = 0x00000000
+setup_uma_memory: uma size 0x10000000, memory start 0x70000000
+CPU_CLUSTER: 0 enabled
+DOMAIN: 0000 enabled
+CPU_CLUSTER: 0 scanning...
+CBFS @ 0 size ffa00
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 140 size 590
+ PCI: 00:18.3 siblings=1
+CPU: APIC: 00 enabled
+CPU: APIC: 01 enabled
+DOMAIN: 0000 scanning...
+PCI: pci_scan_bus for bus 00
+PCI: 00:18.0 [1022/1200] bus ops
+PCI: 00:18.0 [1022/1200] enabled
+PCI: 00:18.1 [1022/1201] enabled
+PCI: 00:18.2 [1022/1202] enabled
+PCI: 00:18.3 [1022/1203] ops
+PCI: 00:18.3 [1022/1203] enabled
+PCI: 00:18.4 [1022/1204] enabled
+PCI: 00:18.0 scanning...
+rs780_enable: dev=0011ff40, VID_DID=0x96011022
+Bus-0, Dev-0, Fun-0.
+enable_pcie_bar3()
+addr=e0000000,bus=0,devfn=40
+gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
+NB_PCI_REG04 = 6.
+NB_PCI_REG84 = 3000095.
+NB_PCI_REG4C = 52042.
+PCI: 00:00.0 [1022/9601] enabled
+Capability: type 0x08 @ 0xc4
+flags: 0x0181
+PCI: pci_scan_bus for bus 00
+PCI: pci_scan_bus limits devfn 0 - devfn ffffffff
+PCI: pci_scan_bus upper limit too big. Using 0xff.
+rs780_enable: dev=0011ff40, VID_DID=0x96011022
+Bus-0, Dev-0, Fun-0.
+enable_pcie_bar3()
+gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
+NB_PCI_REG04 = 6.
+NB_PCI_REG84 = 3000095.
+NB_PCI_REG4C = 52042.
+PCI: 00:00.0 [1022/9601] enabled
+rs780_enable: dev=0011fea0, VID_DID=0x96021022
+Bus-0, Dev-1, Fun-0.
+GC is accessible from now on.
+Capability: type 0x08 @ 0x44
+Capability: type 0x0d @ 0xb0
+Capability: type 0x08 @ 0x44
+Capability: type 0x08 @ 0x44
+Capability: type 0x0d @ 0xb0
+Capability: type 0x08 @ 0x44
+Capability: type 0x0d @ 0xb0
+PCI: 00:01.0 [1022/9602] enabled
+rs780_enable: dev=0011fdc0, VID_DID=0x96031022
+Bus-0, Dev-2,3, Fun-0. enable=1
+rs780_gfx_init, nb_dev=0x0011ff40, dev=0x0011fdc0, port=0x2.
+misc 28 = 1
+rs780_gfx_init step5.9.12.1.
+rs780_gfx_init step5.9.12.3.
+rs780_gfx_init step5.9.12.9.
+rs780_gfx_init step1.
+device = 2
+rs780_gfx_init single_port_configuration.
+PcieLinkTraining port=2:lc current state=a0b0f10
+addr=e0000000,bus=0,devfn=10
+PcieTrainPort reg=0x10000
+rs780_gfx_init single_port_configuration step12.
+GFX Inactive Lanes = 0x0.
+rs780_gfx_init single_port_configuration step13.
+rs780_gfx_init single_port_configuration step14.
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Capability: type 0x05 @ 0xa0
+Capability: type 0x0d @ 0xb0
+Capability: type 0x08 @ 0xb8
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Capability: type 0x05 @ 0xa0
+Capability: type 0x0d @ 0xb0
+Capability: type 0x08 @ 0xb8
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Capability: type 0x05 @ 0xa0
+Capability: type 0x0d @ 0xb0
+Capability: type 0x08 @ 0xb8
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+PCI: 00:02.0 subordinate bus PCI Express
+PCI: 00:02.0 [1022/9603] enabled
+rs780_enable: dev=0011fd20, VID_DID=0xffffffff
+Bus-0, Dev-2,3, Fun-0. enable=0
+rs780_enable: dev=0011fc80, VID_DID=0xffffffff
+Bus-0, Dev-4,5,6,7, Fun-0. enable=0
+rs780_enable: dev=0011fbe0, VID_DID=0xffffffff
+Bus-0, Dev-4,5,6,7, Fun-0. enable=0
+rs780_enable: dev=0011fb40, VID_DID=0xffffffff
+Bus-0, Dev-4,5,6,7, Fun-0. enable=0
+rs780_enable: dev=0011faa0, VID_DID=0xffffffff
+Bus-0, Dev-4,5,6,7, Fun-0. enable=0
+rs780_enable: dev=0011fa00, VID_DID=0x960a1022
+Bus-0, Dev-8, Fun-0. enable=0
+rs780_enable: dev=0011f960, VID_DID=0x96081022
+Bus-0, Dev-9, 10, Fun-0. enable=0
+rs780_enable: dev=0011f8c0, VID_DID=0x96091022
+Bus-0, Dev-9, 10, Fun-0. enable=1
+gpp_sb_init nb_dev=0x0, dev=0x50, port=0xa
+PcieLinkTraining port=a:lc current state=a0b0f10
+addr=e0000000,bus=0,devfn=50
+PcieTrainPort reg=0x10000
+PcieTrainPort port=0xa result=1
+disable_pcie_bar3()
+rs780 unused GPP ports bitmap=0x2f8, force disabled
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Capability: type 0x05 @ 0xa0
+Capability: type 0x0d @ 0xb0
+Capability: type 0x08 @ 0xb8
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Capability: type 0x05 @ 0xa0
+Capability: type 0x0d @ 0xb0
+Capability: type 0x08 @ 0xb8
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Capability: type 0x05 @ 0xa0
+Capability: type 0x0d @ 0xb0
+Capability: type 0x08 @ 0xb8
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+PCI: 00:0a.0 subordinate bus PCI Express
+PCI: 00:0a.0 [1022/9609] enabled
+sb7xx_51xx_enable()
+PCI: 00:11.0 [1002/4390] ops
+PCI: 00:11.0 [1002/4390] enabled
+sb7xx_51xx_enable()
+PCI: 00:12.0 [1002/4397] ops
+PCI: 00:12.0 [1002/4397] enabled
+sb7xx_51xx_enable()
+PCI: 00:12.1 [1002/4398] ops
+PCI: 00:12.1 [1002/4398] enabled
+sb7xx_51xx_enable()
+PCI: 00:12.2 [1002/4396] ops
+PCI: 00:12.2 [1002/4396] enabled
+sb7xx_51xx_enable()
+PCI: 00:13.0 [1002/4397] ops
+PCI: 00:13.0 [1002/4397] enabled
+sb7xx_51xx_enable()
+PCI: 00:13.1 [1002/4398] ops
+PCI: 00:13.1 [1002/4398] enabled
+sb7xx_51xx_enable()
+PCI: 00:13.2 [1002/4396] ops
+PCI: 00:13.2 [1002/4396] enabled
+sb7xx_51xx_enable()
+PCI: 00:14.0 [1002/4385] bus ops
+PCI: 00:14.0 [1002/4385] enabled
+sb7xx_51xx_enable()
+PCI: 00:14.1 [1002/439c] ops
+PCI: 00:14.1 [1002/439c] enabled
+sb7xx_51xx_enable()
+PCI: 00:14.2 [1002/4383] ops
+PCI: 00:14.2 [1002/4383] enabled
+sb7xx_51xx_enable()
+PCI: 00:14.3 [1002/439d] bus ops
+PCI: 00:14.3 [1002/439d] enabled
+sb7xx_51xx_enable()
+PCI: 00:14.4 [1002/4384] bus ops
+PCI: 00:14.4 [1002/4384] enabled
+sb7xx_51xx_enable()
+PCI: 00:14.5 [1002/4399] ops
+PCI: 00:14.5 [1002/4399] enabled
+PCI: 00:18.0 [1022/1200] bus ops
+PCI: 00:18.0 [1022/1200] enabled
+PCI: 00:18.1 [1022/1201] enabled
+PCI: 00:18.2 [1022/1202] enabled
+PCI: 00:18.3 [1022/1203] ops
+PCI: 00:18.3 [1022/1203] enabled
+PCI: 00:18.4 [1022/1204] enabled
+PCI: 00:01.0 scanning...
+do_pci_scan_bridge for PCI: 00:01.0
+PCI: pci_scan_bus for bus 01
+rs780_enable: dev=0011f820, VID_DID=0x97101002
+Bus-0, Dev-4,5,6,7, Fun-0. enable=1
+gpp_sb_init nb_dev=0x0, dev=0x28, port=0x5
+PcieLinkTraining port=5:lc current state=0
+PcieTrainPort port=0x5 result=0
+PCI: 01:05.0 [1002/0000] ops
+rs780_internal_gfx_enable dev = 0x0011f820, nb_dev = 0x0011ff40.
+Sysmem TOM = 0_80000000
+Sysmem TOM2 = 0_0
+PCI: 01:05.0 [1002/9710] enabled
+PCI: 00:02.0 scanning...
+do_pci_scan_bridge for PCI: 00:02.0
+PCI: pci_scan_bus for bus 02
+PCI: 02:00.0 [10de/0a65] enabled
+PCI: 02:00.1 [10de/0be3] enabled
+Capability: type 0x01 @ 0x60
+Capability: type 0x05 @ 0x68
+Capability: type 0x10 @ 0x78
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Enabling Common Clock Configuration
+ASPM: Enabled L0s and L1
+Capability: type 0x01 @ 0x60
+Capability: type 0x05 @ 0x68
+Capability: type 0x10 @ 0x78
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Enabling Common Clock Configuration
+ASPM: Enabled L0s and L1
+PCI: 00:0a.0 scanning...
+do_pci_scan_bridge for PCI: 00:0a.0
+PCI: pci_scan_bus for bus 03
+PCI: 03:00.0 [10ec/8168] enabled
+Capability: type 0x01 @ 0x40
+Capability: type 0x05 @ 0x50
+Capability: type 0x10 @ 0x70
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Enabling Common Clock Configuration
+ASPM: Enabled L0s and L1
+PCI: 00:14.0 scanning...
+scan_smbus for PCI: 00:14.0
+smbus: PCI: 00:14.0[0]->I2C: 01:50 enabled
+smbus: PCI: 00:14.0[0]->I2C: 01:51 enabled
+smbus: PCI: 00:14.0[0]->I2C: 01:52 enabled
+smbus: PCI: 00:14.0[0]->I2C: 01:53 enabled
+scan_smbus for PCI: 00:14.0 done
+PCI: 00:14.3 scanning...
+scan_lpc_bus for PCI: 00:14.3
+PNP: 002e.0 disabled
+PNP: 002e.1 enabled
+PNP: 002e.2 disabled
+PNP: 002e.3 disabled
+PNP: 002e.4 disabled
+PNP: 002e.5 enabled
+PNP: 002e.6 enabled
+PNP: 002e.7 disabled
+PNP: 002e.8 disabled
+PNP: 002e.9 disabled
+PNP: 002e.a disabled
+scan_lpc_bus for PCI: 00:14.3 done
+PCI: 00:14.4 scanning...
+do_pci_scan_bridge for PCI: 00:14.4
+PCI: pci_scan_bus for bus 04
+PCI: 00:18.0 scanning...
+DOMAIN: 0000 passpw: enabled
+root_dev_scan_bus for Root Device done
+done
+BS: Exiting BS_DEV_ENUMERATE state.
+BS: BS_DEV_ENUMERATE times (us): entry 0 run 1095378 exit 0
+BS: Entering BS_DEV_RESOURCES state.
+found VGA at PCI: 01:05.0
+found VGA at PCI: 02:00.0
+Use plugin graphics over integrated.
+Setting up VGA for PCI: 02:00.0
+Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:02.0
+Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
+Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
+Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
+Allocating resources...
+Reading resources...
+Root Device read_resources bus 0 link: 0
+CPU_CLUSTER: 0 read_resources bus 0 link: 0
+APIC: 00 missing read_resources
+APIC: 01 missing read_resources
+CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
+DOMAIN: 0000 read_resources bus 0 link: 0
+PCI: 00:18.0 read_resources bus 0 link: 0
+PCI: 00:00.0 register 1c(00000004), read-only ignoring it
+PCI: 00:01.0 read_resources bus 1 link: 0
+PCI: 00:01.0 read_resources bus 1 link: 0 done
+PCI: 00:02.0 read_resources bus 2 link: 0
+PCI: 00:02.0 read_resources bus 2 link: 0 done
+PCI: 00:0a.0 read_resources bus 3 link: 0
+PCI: 00:0a.0 read_resources bus 3 link: 0 done
+PCI: 00:14.0 read_resources bus 1 link: 0
+I2C: 01:50 missing read_resources
+I2C: 01:51 missing read_resources
+I2C: 01:52 missing read_resources
+I2C: 01:53 missing read_resources
+PCI: 00:14.0 read_resources bus 1 link: 0 done
+PCI: 00:14.3 read_resources bus 0 link: 0
+PCI: 00:14.3 read_resources bus 0 link: 0 done
+PCI: 00:14.4 read_resources bus 4 link: 0
+PCI: 00:14.4 read_resources bus 4 link: 0 done
+CBFS @ 0 size ffa00
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 140 size 590
+PCI: 00:18.0 read_resources bus 0 link: 0 done
+PCI: 00:18.0 read_resources bus 0 link: 1
+PCI: 00:18.0 read_resources bus 0 link: 1 done
+PCI: 00:18.0 read_resources bus 0 link: 2
+PCI: 00:18.0 read_resources bus 0 link: 2 done
+PCI: 00:18.0 read_resources bus 0 link: 3
+PCI: 00:18.0 read_resources bus 0 link: 3 done
+CBFS @ 0 size ffa00
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 140 size 590
+PCI: 00:18.4 read_resources bus 0 link: 0
+PCI: 00:18.4 read_resources bus 0 link: 0 done
+PCI: 00:18.4 read_resources bus 0 link: 1
+PCI: 00:18.4 read_resources bus 0 link: 1 done
+PCI: 00:18.4 read_resources bus 0 link: 2
+PCI: 00:18.4 read_resources bus 0 link: 2 done
+PCI: 00:18.4 read_resources bus 0 link: 3
+PCI: 00:18.4 read_resources bus 0 link: 3 done
+DOMAIN: 0000 read_resources bus 0 link: 0 done
+Root Device read_resources bus 0 link: 0 done
+Done reading resources.
+Show resources in subtree (Root Device)...After reading.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 00
+ APIC: 00
+ APIC: 01
+ DOMAIN: 0000 child on link 0 PCI: 00:18.0
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
+ DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
+ DOMAIN: 0000 resource base 0 size 80000000 align 0 gran 0 limit 0 flags e0004200 index 7
+ PCI: 00:18.0 child on link 0 PCI: 00:00.0
+ PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 10d8
+ PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 10b8
+ PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 10b0
+ PCI: 00:00.0
+ PCI: 00:01.0 child on link 0 PCI: 01:05.0
+ PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit 1ffffff flags 80102 index 1c
+ PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81202 index 24
+ PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 01:05.0
+ PCI: 00:02.0 child on link 0 PCI: 02:00.0
+ PCI: 00:02.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
+ PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 02:00.0
+ PCI: 02:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10
+ PCI: 02:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 14
+ PCI: 02:00.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffffffffffff flags 1201 index 1c
+ PCI: 02:00.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 24
+ PCI: 02:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30
+ PCI: 02:00.1
+ PCI: 02:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
+ PCI: 00:03.0
+ PCI: 00:04.0
+ PCI: 00:05.0
+ PCI: 00:06.0
+ PCI: 00:07.0
+ PCI: 00:08.0
+ PCI: 00:09.0
+ PCI: 00:0a.0 child on link 0 PCI: 03:00.0
+ PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
+ PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 03:00.0
+ PCI: 03:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
+ PCI: 03:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 1201 index 18
+ PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
+ PCI: 03:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
+ PCI: 00:11.0
+ PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
+ PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
+ PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
+ PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
+ PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
+ PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24
+ PCI: 00:12.0
+ PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
+ PCI: 00:12.1
+ PCI: 00:12.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
+ PCI: 00:12.2
+ PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
+ PCI: 00:13.0
+ PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
+ PCI: 00:13.1
+ PCI: 00:13.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
+ PCI: 00:13.2
+ PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
+ PCI: 00:14.0 child on link 0 I2C: 01:50
+ PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
+ PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
+ PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
+ I2C: 01:50
+ I2C: 01:51
+ I2C: 01:52
+ I2C: 01:53
+ PCI: 00:14.1
+ PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
+ PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
+ PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
+ PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
+ PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
+ PCI: 00:14.2
+ PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:14.3 child on link 0 PNP: 002e.0
+ PCI: 00:14.3 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 200 index a0
+ PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PNP: 002e.0
+ PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
+ PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
+ PNP: 002e.1
+ PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
+ PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.2
+ PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
+ PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.3
+ PNP: 002e.3 resource base 378 size 4 align 2 gran 2 limit fff flags c0000100 index 60
+ PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
+ PNP: 002e.4
+ PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
+ PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
+ PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 002e.5
+ PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
+ PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
+ PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.6
+ PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.7
+ PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
+ PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
+ PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 64
+ PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 002e.8
+ PNP: 002e.8 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
+ PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 002e.9
+ PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
+ PNP: 002e.a
+ PNP: 002e.a resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
+ PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PCI: 00:14.4
+ PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
+ PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 00:14.5
+ PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
+ PCI: 00:18.0
+ PCI: 00:18.1
+ PCI: 00:18.2
+ PCI: 00:18.3
+ PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
+ PCI: 00:18.4
+ PCI: 00:18.1
+ PCI: 00:18.2
+ PCI: 00:18.3
+ PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
+ PCI: 00:18.4
+DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
+PCI: 00:18.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: 1ffffff
+PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: 1ffffff done
+PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
+PCI: 02:00.0 24 * [0x0 - 0x7f] io
+PCI: 00:02.0 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done
+PCI: 00:0a.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
+PCI: 03:00.0 10 * [0x0 - 0xff] io
+PCI: 00:0a.0 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
+PCI: 00:14.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:14.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
+PCI: 00:02.0 1c * [0x0 - 0xfff] io
+PCI: 00:0a.0 1c * [0x1000 - 0x1fff] io
+PCI: 00:11.0 20 * [0x2000 - 0x200f] io
+PCI: 00:14.1 20 * [0x2010 - 0x201f] io
+PCI: 00:11.0 10 * [0x2020 - 0x2027] io
+PCI: 00:11.0 18 * [0x2028 - 0x202f] io
+PCI: 00:14.1 10 * [0x2030 - 0x2037] io
+PCI: 00:14.1 18 * [0x2038 - 0x203f] io
+PCI: 00:11.0 14 * [0x2040 - 0x2043] io
+PCI: 00:11.0 1c * [0x2044 - 0x2047] io
+PCI: 00:14.1 14 * [0x2048 - 0x204b] io
+PCI: 00:14.1 1c * [0x204c - 0x204f] io
+PCI: 00:18.0 io: base: 2050 size: 3000 align: 12 gran: 12 limit: ffff done
+PCI: 00:18.0 10d8 * [0x0 - 0x2fff] io
+DOMAIN: 0000 io: base: 3000 size: 3000 align: 12 gran: 0 limit: ffff done
+DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
+PCI: 00:18.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
+PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
+PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff done
+PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 02:00.0 14 * [0x0 - 0xfffffff] prefmem
+PCI: 02:00.0 1c * [0x10000000 - 0x11ffffff] prefmem
+PCI: 00:02.0 prefmem: base: 12000000 size: 12000000 align: 28 gran: 20 limit: ffffffffffffffff done
+PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 03:00.0 20 * [0x0 - 0x3fff] prefmem
+PCI: 03:00.0 18 * [0x4000 - 0x4fff] prefmem
+PCI: 00:0a.0 prefmem: base: 5000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:02.0 24 * [0x0 - 0x11ffffff] prefmem
+PCI: 00:0a.0 24 * [0x12000000 - 0x120fffff] prefmem
+PCI: 00:18.0 prefmem: base: 12100000 size: 12100000 align: 28 gran: 20 limit: ffffffffff done
+PCI: 00:18.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
+PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 02:00.0 10 * [0x0 - 0xffffff] mem
+PCI: 02:00.0 30 * [0x1000000 - 0x107ffff] mem
+PCI: 02:00.1 10 * [0x1080000 - 0x1083fff] mem
+PCI: 00:02.0 mem: base: 1084000 size: 1100000 align: 24 gran: 20 limit: ffffffff done
+PCI: 00:0a.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 03:00.0 30 * [0x0 - 0xffff] mem
+PCI: 00:0a.0 mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:18.3 94 * [0x0 - 0x3ffffff] mem
+PCI: 00:02.0 20 * [0x4000000 - 0x50fffff] mem
+PCI: 00:0a.0 20 * [0x5100000 - 0x51fffff] mem
+PCI: 00:14.2 10 * [0x5200000 - 0x5203fff] mem
+PCI: 00:12.0 10 * [0x5204000 - 0x5204fff] mem
+PCI: 00:12.1 10 * [0x5205000 - 0x5205fff] mem
+PCI: 00:13.0 10 * [0x5206000 - 0x5206fff] mem
+PCI: 00:13.1 10 * [0x5207000 - 0x5207fff] mem
+PCI: 00:14.5 10 * [0x5208000 - 0x5208fff] mem
+PCI: 00:11.0 24 * [0x5209000 - 0x52093ff] mem
+PCI: 00:12.2 10 * [0x5209400 - 0x52094ff] mem
+PCI: 00:13.2 10 * [0x5209500 - 0x52095ff] mem
+PCI: 00:14.3 a0 * [0x5209600 - 0x5209600] mem
+PCI: 00:18.0 mem: base: 5209601 size: 5300000 align: 26 gran: 20 limit: ffffffff done
+PCI: 00:18.0 10b8 * [0x0 - 0x120fffff] prefmem
+PCI: 00:18.0 10b0 * [0x14000000 - 0x192fffff] mem
+PCI: 00:18.3 94 * [0x1c000000 - 0x1fffffff] mem
+DOMAIN: 0000 mem: base: 20000000 size: 20000000 align: 28 gran: 0 limit: ffffffff done
+avoid_fixed_resources: DOMAIN: 0000
+avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
+avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
+constrain_resources: DOMAIN: 0000 c0010058 base c0000000 limit cfffffff mem (fixed)
+constrain_resources: DOMAIN: 0000 07 base 00000000 limit 7fffffff mem (fixed)
+constrain_resources: PCI: 00:14.0 90 base 00000b00 limit 00000b0f io (fixed)
+constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed)
+avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff
+avoid_fixed_resources:@DOMAIN: 0000 10000100 base a0000000 limit bfffffff
+Setting resources...
+DOMAIN: 0000 io: base:1000 size:3000 align:12 gran:0 limit:ffff
+PCI: 00:18.0 10d8 * [0x1000 - 0x3fff] io
+DOMAIN: 0000 io: next_base: 4000 size: 3000 align: 12 gran: 0 done
+PCI: 00:18.0 io: base:1000 size:3000 align:12 gran:12 limit:3fff
+PCI: 00:02.0 1c * [0x1000 - 0x1fff] io
+PCI: 00:0a.0 1c * [0x2000 - 0x2fff] io
+PCI: 00:11.0 20 * [0x3000 - 0x300f] io
+PCI: 00:14.1 20 * [0x3010 - 0x301f] io
+PCI: 00:11.0 10 * [0x3020 - 0x3027] io
+PCI: 00:11.0 18 * [0x3028 - 0x302f] io
+PCI: 00:14.1 10 * [0x3030 - 0x3037] io
+PCI: 00:14.1 18 * [0x3038 - 0x303f] io
+PCI: 00:11.0 14 * [0x3040 - 0x3043] io
+PCI: 00:11.0 1c * [0x3044 - 0x3047] io
+PCI: 00:14.1 14 * [0x3048 - 0x304b] io
+PCI: 00:14.1 1c * [0x304c - 0x304f] io
+PCI: 00:18.0 io: next_base: 3050 size: 3000 align: 12 gran: 12 done
+PCI: 00:01.0 io: base:3fff size:0 align:12 gran:12 limit:3fff
+PCI: 00:01.0 io: next_base: 3fff size: 0 align: 12 gran: 12 done
+PCI: 00:02.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff
+PCI: 02:00.0 24 * [0x1000 - 0x107f] io
+PCI: 00:02.0 io: next_base: 1080 size: 1000 align: 12 gran: 12 done
+PCI: 00:0a.0 io: base:2000 size:1000 align:12 gran:12 limit:2fff
+PCI: 03:00.0 10 * [0x2000 - 0x20ff] io
+PCI: 00:0a.0 io: next_base: 2100 size: 1000 align: 12 gran: 12 done
+PCI: 00:14.4 io: base:3fff size:0 align:12 gran:12 limit:3fff
+PCI: 00:14.4 io: next_base: 3fff size: 0 align: 12 gran: 12 done
+DOMAIN: 0000 mem: base:a0000000 size:20000000 align:28 gran:0 limit:bfffffff
+PCI: 00:18.0 10b8 * [0xa0000000 - 0xb20fffff] prefmem
+PCI: 00:18.0 10b0 * [0xb4000000 - 0xb92fffff] mem
+PCI: 00:18.3 94 * [0xbc000000 - 0xbfffffff] mem
+DOMAIN: 0000 mem: next_base: c0000000 size: 20000000 align: 28 gran: 0 done
+PCI: 00:18.0 prefmem: base:a0000000 size:12100000 align:28 gran:20 limit:b20fffff
+PCI: 00:02.0 24 * [0xa0000000 - 0xb1ffffff] prefmem
+PCI: 00:0a.0 24 * [0xb2000000 - 0xb20fffff] prefmem
+PCI: 00:18.0 prefmem: next_base: b2100000 size: 12100000 align: 28 gran: 20 done
+PCI: 00:01.0 prefmem: base:b20fffff size:0 align:20 gran:20 limit:b20fffff
+PCI: 00:01.0 prefmem: next_base: b20fffff size: 0 align: 20 gran: 20 done
+PCI: 00:02.0 prefmem: base:a0000000 size:12000000 align:28 gran:20 limit:b1ffffff
+PCI: 02:00.0 14 * [0xa0000000 - 0xafffffff] prefmem
+PCI: 02:00.0 1c * [0xb0000000 - 0xb1ffffff] prefmem
+PCI: 00:02.0 prefmem: next_base: b2000000 size: 12000000 align: 28 gran: 20 done
+PCI: 00:0a.0 prefmem: base:b2000000 size:100000 align:20 gran:20 limit:b20fffff
+PCI: 03:00.0 20 * [0xb2000000 - 0xb2003fff] prefmem
+PCI: 03:00.0 18 * [0xb2004000 - 0xb2004fff] prefmem
+PCI: 00:0a.0 prefmem: next_base: b2005000 size: 100000 align: 20 gran: 20 done
+PCI: 00:14.4 prefmem: base:b20fffff size:0 align:20 gran:20 limit:b20fffff
+PCI: 00:14.4 prefmem: next_base: b20fffff size: 0 align: 20 gran: 20 done
+PCI: 00:18.0 mem: base:b4000000 size:5300000 align:26 gran:20 limit:b92fffff
+PCI: 00:18.3 94 * [0xb4000000 - 0xb7ffffff] mem
+PCI: 00:02.0 20 * [0xb8000000 - 0xb90fffff] mem
+PCI: 00:0a.0 20 * [0xb9100000 - 0xb91fffff] mem
+PCI: 00:14.2 10 * [0xb9200000 - 0xb9203fff] mem
+PCI: 00:12.0 10 * [0xb9204000 - 0xb9204fff] mem
+PCI: 00:12.1 10 * [0xb9205000 - 0xb9205fff] mem
+PCI: 00:13.0 10 * [0xb9206000 - 0xb9206fff] mem
+PCI: 00:13.1 10 * [0xb9207000 - 0xb9207fff] mem
+PCI: 00:14.5 10 * [0xb9208000 - 0xb9208fff] mem
+PCI: 00:11.0 24 * [0xb9209000 - 0xb92093ff] mem
+PCI: 00:12.2 10 * [0xb9209400 - 0xb92094ff] mem
+PCI: 00:13.2 10 * [0xb9209500 - 0xb92095ff] mem
+PCI: 00:14.3 a0 * [0xb9209600 - 0xb9209600] mem
+PCI: 00:18.0 mem: next_base: b9209601 size: 5300000 align: 26 gran: 20 done
+PCI: 00:01.0 mem: base:b92fffff size:0 align:20 gran:20 limit:b92fffff
+PCI: 00:01.0 mem: next_base: b92fffff size: 0 align: 20 gran: 20 done
+PCI: 00:02.0 mem: base:b8000000 size:1100000 align:24 gran:20 limit:b90fffff
+PCI: 02:00.0 10 * [0xb8000000 - 0xb8ffffff] mem
+PCI: 02:00.0 30 * [0xb9000000 - 0xb907ffff] mem
+PCI: 02:00.1 10 * [0xb9080000 - 0xb9083fff] mem
+PCI: 00:02.0 mem: next_base: b9084000 size: 1100000 align: 24 gran: 20 done
+PCI: 00:0a.0 mem: base:b9100000 size:100000 align:20 gran:20 limit:b91fffff
+PCI: 03:00.0 30 * [0xb9100000 - 0xb910ffff] mem
+PCI: 00:0a.0 mem: next_base: b9110000 size: 100000 align: 20 gran: 20 done
+PCI: 00:14.4 mem: base:b92fffff size:0 align:20 gran:20 limit:b92fffff
+PCI: 00:14.4 mem: next_base: b92fffff size: 0 align: 20 gran: 20 done
+Root Device assign_resources, bus 0 link: 0
+0: mmio_basek=00280000, basek=00000300, limitk=00200000
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device
+PCI: 00:18.0 11b8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem <node 0 link 0>
+PCI: 00:18.0 10d8 <- [0x0000001000 - 0x0000003fff] size 0x00003000 gran 0x0c io <node 0 link 0>
+PCI: 00:18.0 10b8 <- [0x00a0000000 - 0x00b20fffff] size 0x12100000 gran 0x14 prefmem <node 0 link 0>
+PCI: 00:18.0 10b0 <- [0x00b4000000 - 0x00b92fffff] size 0x05300000 gran 0x14 mem <node 0 link 0>
+PCI: 00:18.0 assign_resources, bus 0 link: 0
+PCI: 00:01.0 1c <- [0x0000003fff - 0x0000003ffe] size 0x00000000 gran 0x0c bus 01 io
+PCI: 00:01.0 24 <- [0x00b20fffff - 0x00b20ffffe] size 0x00000000 gran 0x14 bus 01 prefmem
+PCI: 00:01.0 20 <- [0x00b92fffff - 0x00b92ffffe] size 0x00000000 gran 0x14 bus 01 mem
+PCI: 00:01.0 assign_resources, bus 1 link: 0
+PCI: 00:01.0 assign_resources, bus 1 link: 0
+PCI: 00:02.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 02 io
+PCI: 00:02.0 24 <- [0x00a0000000 - 0x00b1ffffff] size 0x12000000 gran 0x14 bus 02 prefmem
+PCI: 00:02.0 20 <- [0x00b8000000 - 0x00b90fffff] size 0x01100000 gran 0x14 bus 02 mem
+PCI: 00:02.0 assign_resources, bus 2 link: 0
+PCI: 02:00.0 10 <- [0x00b8000000 - 0x00b8ffffff] size 0x01000000 gran 0x18 mem
+PCI: 02:00.0 14 <- [0x00a0000000 - 0x00afffffff] size 0x10000000 gran 0x1c prefmem64
+PCI: 02:00.0 1c <- [0x00b0000000 - 0x00b1ffffff] size 0x02000000 gran 0x19 prefmem64
+PCI: 02:00.0 24 <- [0x0000001000 - 0x000000107f] size 0x00000080 gran 0x07 io
+PCI: 02:00.0 30 <- [0x00b9000000 - 0x00b907ffff] size 0x00080000 gran 0x13 romem
+PCI: 02:00.1 10 <- [0x00b9080000 - 0x00b9083fff] size 0x00004000 gran 0x0e mem
+PCI: 00:02.0 assign_resources, bus 2 link: 0
+PCI: 00:0a.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 03 io
+PCI: 00:0a.0 24 <- [0x00b2000000 - 0x00b20fffff] size 0x00100000 gran 0x14 bus 03 prefmem
+PCI: 00:0a.0 20 <- [0x00b9100000 - 0x00b91fffff] size 0x00100000 gran 0x14 bus 03 mem
+PCI: 00:0a.0 assign_resources, bus 3 link: 0
+PCI: 03:00.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
+PCI: 03:00.0 18 <- [0x00b2004000 - 0x00b2004fff] size 0x00001000 gran 0x0c prefmem64
+PCI: 03:00.0 20 <- [0x00b2000000 - 0x00b2003fff] size 0x00004000 gran 0x0e prefmem64
+PCI: 03:00.0 30 <- [0x00b9100000 - 0x00b910ffff] size 0x00010000 gran 0x10 romem
+PCI: 00:0a.0 assign_resources, bus 3 link: 0
+PCI: 00:11.0 10 <- [0x0000003020 - 0x0000003027] size 0x00000008 gran 0x03 io
+PCI: 00:11.0 14 <- [0x0000003040 - 0x0000003043] size 0x00000004 gran 0x02 io
+PCI: 00:11.0 18 <- [0x0000003028 - 0x000000302f] size 0x00000008 gran 0x03 io
+PCI: 00:11.0 1c <- [0x0000003044 - 0x0000003047] size 0x00000004 gran 0x02 io
+PCI: 00:11.0 20 <- [0x0000003000 - 0x000000300f] size 0x00000010 gran 0x04 io
+PCI: 00:11.0 24 <- [0x00b9209000 - 0x00b92093ff] size 0x00000400 gran 0x0a mem
+PCI: 00:12.0 10 <- [0x00b9204000 - 0x00b9204fff] size 0x00001000 gran 0x0c mem
+PCI: 00:12.1 10 <- [0x00b9205000 - 0x00b9205fff] size 0x00001000 gran 0x0c mem
+PCI: 00:12.2 10 <- [0x00b9209400 - 0x00b92094ff] size 0x00000100 gran 0x08 mem
+PCI: 00:13.0 10 <- [0x00b9206000 - 0x00b9206fff] size 0x00001000 gran 0x0c mem
+PCI: 00:13.1 10 <- [0x00b9207000 - 0x00b9207fff] size 0x00001000 gran 0x0c mem
+PCI: 00:13.2 10 <- [0x00b9209500 - 0x00b92095ff] size 0x00000100 gran 0x08 mem
+PCI: 00:14.0 assign_resources, bus 1 link: 0
+PCI: 00:14.0 assign_resources, bus 1 link: 0
+PCI: 00:14.1 10 <- [0x0000003030 - 0x0000003037] size 0x00000008 gran 0x03 io
+PCI: 00:14.1 14 <- [0x0000003048 - 0x000000304b] size 0x00000004 gran 0x02 io
+PCI: 00:14.1 18 <- [0x0000003038 - 0x000000303f] size 0x00000008 gran 0x03 io
+PCI: 00:14.1 1c <- [0x000000304c - 0x000000304f] size 0x00000004 gran 0x02 io
+PCI: 00:14.1 20 <- [0x0000003010 - 0x000000301f] size 0x00000010 gran 0x04 io
+PCI: 00:14.2 10 <- [0x00b9200000 - 0x00b9203fff] size 0x00004000 gran 0x0e mem64
+PCI: 00:14.3 a0 <- [0x00b9209600 - 0x00b9209600] size 0x00000001 gran 0x00 mem
+PCI: 00:14.3 assign_resources, bus 0 link: 0
+PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
+PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
+PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
+PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
+PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
+PNP: 002e.6 70 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
+PCI: 00:14.3 assign_resources, bus 0 link: 0
+PCI: 00:14.4 1c <- [0x0000003fff - 0x0000003ffe] size 0x00000000 gran 0x0c bus 04 io
+PCI: 00:14.4 24 <- [0x00b20fffff - 0x00b20ffffe] size 0x00000000 gran 0x14 bus 04 prefmem
+PCI: 00:14.4 20 <- [0x00b92fffff - 0x00b92ffffe] size 0x00000000 gran 0x14 bus 04 mem
+PCI: 00:14.5 10 <- [0x00b9208000 - 0x00b9208fff] size 0x00001000 gran 0x0c mem
+PCI: 00:18.3 94 <- [0x00b4000000 - 0x00b7ffffff] size 0x04000000 gran 0x1a mem <gart>
+PCI: 00:18.3 94 <- [0x00b4000000 - 0x00b7ffffff] size 0x04000000 gran 0x1a mem <gart>
+PCI: 00:18.0 assign_resources, bus 0 link: 0
+PCI: 00:18.3 94 <- [0x00bc000000 - 0x00bfffffff] size 0x04000000 gran 0x1a mem <gart>
+PCI: 00:18.3 94 <- [0x00bc000000 - 0x00bfffffff] size 0x04000000 gran 0x1a mem <gart>
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+Root Device assign_resources, bus 0 link: 0
+Done setting resources.
+Show resources in subtree (Root Device)...After assigning values.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 00
+ APIC: 00
+ APIC: 01
+ DOMAIN: 0000 child on link 0 PCI: 00:18.0
+ DOMAIN: 0000 resource base 1000 size 3000 align 12 gran 0 limit ffff flags 40040100 index 10000000
+ DOMAIN: 0000 resource base a0000000 size 20000000 align 28 gran 0 limit bfffffff flags 40040200 index 10000100
+ DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
+ DOMAIN: 0000 resource base 70000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 7
+ DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
+ DOMAIN: 0000 resource base c0000 size 7ff40000 align 0 gran 0 limit 0 flags e0004200 index 20
+ PCI: 00:18.0 child on link 0 PCI: 00:00.0
+ PCI: 00:18.0 resource base 1000 size 3000 align 12 gran 12 limit 3fff flags 60080100 index 10d8
+ PCI: 00:18.0 resource base a0000000 size 12100000 align 28 gran 20 limit b20fffff flags 60081200 index 10b8
+ PCI: 00:18.0 resource base b4000000 size 5300000 align 26 gran 20 limit b92fffff flags 60080200 index 10b0
+ PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags e0000200 index 11b8
+ PCI: 00:00.0
+ PCI: 00:01.0 child on link 0 PCI: 01:05.0
+ PCI: 00:01.0 resource base 3fff size 0 align 12 gran 12 limit 3fff flags 60080102 index 1c
+ PCI: 00:01.0 resource base b20fffff size 0 align 20 gran 20 limit b20fffff flags 60081202 index 24
+ PCI: 00:01.0 resource base b92fffff size 0 align 20 gran 20 limit b92fffff flags 60080202 index 20
+ PCI: 01:05.0
+ PCI: 00:02.0 child on link 0 PCI: 02:00.0
+ PCI: 00:02.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c
+ PCI: 00:02.0 resource base a0000000 size 12000000 align 28 gran 20 limit b1ffffff flags 60081202 index 24
+ PCI: 00:02.0 resource base b8000000 size 1100000 align 24 gran 20 limit b90fffff flags 60080202 index 20
+ PCI: 02:00.0
+ PCI: 02:00.0 resource base b8000000 size 1000000 align 24 gran 24 limit b8ffffff flags 60000200 index 10
+ PCI: 02:00.0 resource base a0000000 size 10000000 align 28 gran 28 limit afffffff flags 60001201 index 14
+ PCI: 02:00.0 resource base b0000000 size 2000000 align 25 gran 25 limit b1ffffff flags 60001201 index 1c
+ PCI: 02:00.0 resource base 1000 size 80 align 7 gran 7 limit 107f flags 60000100 index 24
+ PCI: 02:00.0 resource base b9000000 size 80000 align 19 gran 19 limit b907ffff flags 60002200 index 30
+ PCI: 02:00.1
+ PCI: 02:00.1 resource base b9080000 size 4000 align 14 gran 14 limit b9083fff flags 60000200 index 10
+ PCI: 00:03.0
+ PCI: 00:04.0
+ PCI: 00:05.0
+ PCI: 00:06.0
+ PCI: 00:07.0
+ PCI: 00:08.0
+ PCI: 00:09.0
+ PCI: 00:0a.0 child on link 0 PCI: 03:00.0
+ PCI: 00:0a.0 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c
+ PCI: 00:0a.0 resource base b2000000 size 100000 align 20 gran 20 limit b20fffff flags 60081202 index 24
+ PCI: 00:0a.0 resource base b9100000 size 100000 align 20 gran 20 limit b91fffff flags 60080202 index 20
+ PCI: 03:00.0
+ PCI: 03:00.0 resource base 2000 size 100 align 8 gran 8 limit 20ff flags 60000100 index 10
+ PCI: 03:00.0 resource base b2004000 size 1000 align 12 gran 12 limit b2004fff flags 60001201 index 18
+ PCI: 03:00.0 resource base b2000000 size 4000 align 14 gran 14 limit b2003fff flags 60001201 index 20
+ PCI: 03:00.0 resource base b9100000 size 10000 align 16 gran 16 limit b910ffff flags 60002200 index 30
+ PCI: 00:11.0
+ PCI: 00:11.0 resource base 3020 size 8 align 3 gran 3 limit 3027 flags 60000100 index 10
+ PCI: 00:11.0 resource base 3040 size 4 align 2 gran 2 limit 3043 flags 60000100 index 14
+ PCI: 00:11.0 resource base 3028 size 8 align 3 gran 3 limit 302f flags 60000100 index 18
+ PCI: 00:11.0 resource base 3044 size 4 align 2 gran 2 limit 3047 flags 60000100 index 1c
+ PCI: 00:11.0 resource base 3000 size 10 align 4 gran 4 limit 300f flags 60000100 index 20
+ PCI: 00:11.0 resource base b9209000 size 400 align 10 gran 10 limit b92093ff flags 60000200 index 24
+ PCI: 00:12.0
+ PCI: 00:12.0 resource base b9204000 size 1000 align 12 gran 12 limit b9204fff flags 60000200 index 10
+ PCI: 00:12.1
+ PCI: 00:12.1 resource base b9205000 size 1000 align 12 gran 12 limit b9205fff flags 60000200 index 10
+ PCI: 00:12.2
+ PCI: 00:12.2 resource base b9209400 size 100 align 8 gran 8 limit b92094ff flags 60000200 index 10
+ PCI: 00:13.0
+ PCI: 00:13.0 resource base b9206000 size 1000 align 12 gran 12 limit b9206fff flags 60000200 index 10
+ PCI: 00:13.1
+ PCI: 00:13.1 resource base b9207000 size 1000 align 12 gran 12 limit b9207fff flags 60000200 index 10
+ PCI: 00:13.2
+ PCI: 00:13.2 resource base b9209500 size 100 align 8 gran 8 limit b92095ff flags 60000200 index 10
+ PCI: 00:14.0 child on link 0 I2C: 01:50
+ PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
+ PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
+ PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
+ I2C: 01:50
+ I2C: 01:51
+ I2C: 01:52
+ I2C: 01:53
+ PCI: 00:14.1
+ PCI: 00:14.1 resource base 3030 size 8 align 3 gran 3 limit 3037 flags 60000100 index 10
+ PCI: 00:14.1 resource base 3048 size 4 align 2 gran 2 limit 304b flags 60000100 index 14
+ PCI: 00:14.1 resource base 3038 size 8 align 3 gran 3 limit 303f flags 60000100 index 18
+ PCI: 00:14.1 resource base 304c size 4 align 2 gran 2 limit 304f flags 60000100 index 1c
+ PCI: 00:14.1 resource base 3010 size 10 align 4 gran 4 limit 301f flags 60000100 index 20
+ PCI: 00:14.2
+ PCI: 00:14.2 resource base b9200000 size 4000 align 14 gran 14 limit b9203fff flags 60000201 index 10
+ PCI: 00:14.3 child on link 0 PNP: 002e.0
+ PCI: 00:14.3 resource base b9209600 size 1 align 0 gran 0 limit b9209600 flags 60000200 index a0
+ PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PNP: 002e.0
+ PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
+ PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
+ PNP: 002e.1
+ PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
+ PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.2
+ PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
+ PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.3
+ PNP: 002e.3 resource base 378 size 4 align 2 gran 2 limit fff flags c0000100 index 60
+ PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
+ PNP: 002e.4
+ PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
+ PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
+ PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 002e.5
+ PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
+ PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
+ PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.6
+ PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.7
+ PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
+ PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
+ PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 64
+ PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 002e.8
+ PNP: 002e.8 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
+ PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 002e.9
+ PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
+ PNP: 002e.a
+ PNP: 002e.a resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
+ PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PCI: 00:14.4
+ PCI: 00:14.4 resource base 3fff size 0 align 12 gran 12 limit 3fff flags 60080102 index 1c
+ PCI: 00:14.4 resource base b20fffff size 0 align 20 gran 20 limit b20fffff flags 60081202 index 24
+ PCI: 00:14.4 resource base b92fffff size 0 align 20 gran 20 limit b92fffff flags 60080202 index 20
+ PCI: 00:14.5
+ PCI: 00:14.5 resource base b9208000 size 1000 align 12 gran 12 limit b9208fff flags 60000200 index 10
+ PCI: 00:18.0
+ PCI: 00:18.1
+ PCI: 00:18.2
+ PCI: 00:18.3
+ PCI: 00:18.3 resource base b4000000 size 4000000 align 26 gran 26 limit b7ffffff flags 60000200 index 94
+ PCI: 00:18.4
+ PCI: 00:18.1
+ PCI: 00:18.2
+ PCI: 00:18.3
+ PCI: 00:18.3 resource base bc000000 size 4000000 align 26 gran 26 limit bfffffff flags 60000200 index 94
+ PCI: 00:18.4
+Done allocating resources.
+BS: Exiting BS_DEV_RESOURCES state.
+BS: BS_DEV_RESOURCES times (us): entry 0 run 3163996 exit 0
+BS: Entering BS_DEV_ENABLE state.
+Enabling resources...
+PCI: 00:18.0 cmd <- 00
+PCI: 00:18.1 subsystem <- 1043/83a2
+PCI: 00:18.1 cmd <- 00
+PCI: 00:18.2 subsystem <- 1043/83a2
+PCI: 00:18.2 cmd <- 00
+PCI: 00:18.3 cmd <- 00
+PCI: 00:18.4 subsystem <- 1043/83a2
+PCI: 00:18.4 cmd <- 00
+PCI: 00:00.0 subsystem <- 1043/83a2
+PCI: 00:00.0 cmd <- 06
+PCI: 00:01.0 bridge ctrl <- 0003
+PCI: 00:01.0 cmd <- 00
+PCI: 00:02.0 bridge ctrl <- 000b
+PCI: 00:02.0 cmd <- 07
+PCI: 00:0a.0 bridge ctrl <- 0003
+PCI: 00:0a.0 cmd <- 07
+PCI: 00:11.0 subsystem <- 1043/83a2
+PCI: 00:11.0 cmd <- 03
+PCI: 00:12.0 subsystem <- 1043/83a2
+PCI: 00:12.0 cmd <- 02
+PCI: 00:12.1 subsystem <- 1043/83a2
+PCI: 00:12.1 cmd <- 02
+PCI: 00:12.2 subsystem <- 1043/83a2
+PCI: 00:12.2 cmd <- 02
+PCI: 00:13.0 subsystem <- 1043/83a2
+PCI: 00:13.0 cmd <- 02
+PCI: 00:13.1 subsystem <- 1043/83a2
+PCI: 00:13.1 cmd <- 02
+PCI: 00:13.2 subsystem <- 1043/83a2
+PCI: 00:13.2 cmd <- 02
+PCI: 00:14.0 subsystem <- 1043/83a2
+PCI: 00:14.0 cmd <- 403
+PCI: 00:14.1 subsystem <- 1043/83a2
+PCI: 00:14.1 cmd <- 01
+PCI: 00:14.2 subsystem <- 1043/83a2
+PCI: 00:14.2 cmd <- 02
+PCI: 00:14.3 subsystem <- 1043/83a2
+PCI: 00:14.3 cmd <- 0f
+sb700 lpc decode:PNP: 002e.1, base=0x000003f8, end=0x000003ff
+sb700 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060
+sb700 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064
+PCI: 00:14.4 bridge ctrl <- 0003
+PCI: 00:14.4 cmd <- 01
+PCI: 00:14.5 subsystem <- 1043/83a2
+PCI: 00:14.5 cmd <- 02
+PCI: 00:18.0 cmd <- 00
+PCI: 00:18.1 cmd <- 00
+PCI: 00:18.2 cmd <- 00
+PCI: 00:18.3 cmd <- 00
+PCI: 00:18.4 cmd <- 00
+PCI: 02:00.0 cmd <- 03
+PCI: 02:00.1 cmd <- 02
+PCI: 03:00.0 cmd <- 03
+done.
+BS: Exiting BS_DEV_ENABLE state.
+BS: BS_DEV_ENABLE times (us): entry 0 run 148540 exit 0
+BS: Entering BS_DEV_INIT state.
+Initializing devices...
+Root Device init ...
+Root Device init finished in 1921 usecs
+CPU_CLUSTER: 0 init ...
+start_eip=0x00001000, code_size=0x00000031
+Initializing CPU #0
+CPU: vendor AMD device 100f62
+CPU: family 10, model 06, stepping 02
+nodeid = 00, coreid = 00
+Enabling cache
+CPU ID 0x80000001: 100f62
+CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
+MTRR: Physical address space:
+0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
+0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
+0x00000000000c0000 - 0x0000000070000000 size 0x6ff40000 type 6
+0x0000000070000000 - 0x00000000a0000000 size 0x30000000 type 0
+0x00000000a0000000 - 0x00000000b2000000 size 0x12000000 type 1
+0x00000000b2000000 - 0x0000000100000000 size 0x4e000000 type 0
+MTRR addr 0x0-0x10 set to 6 type @ 0
+MTRR addr 0x10-0x20 set to 6 type @ 1
+MTRR addr 0x20-0x30 set to 6 type @ 2
+MTRR addr 0x30-0x40 set to 6 type @ 3
+MTRR addr 0x40-0x50 set to 6 type @ 4
+MTRR addr 0x50-0x60 set to 6 type @ 5
+MTRR addr 0x60-0x70 set to 6 type @ 6
+MTRR addr 0x70-0x80 set to 6 type @ 7
+MTRR addr 0x80-0x84 set to 6 type @ 8
+MTRR addr 0x84-0x88 set to 6 type @ 9
+MTRR addr 0x88-0x8c set to 6 type @ 10
+MTRR addr 0x8c-0x90 set to 6 type @ 11
+MTRR addr 0x90-0x94 set to 6 type @ 12
+MTRR addr 0x94-0x98 set to 6 type @ 13
+MTRR addr 0x98-0x9c set to 6 type @ 14
+MTRR addr 0x9c-0xa0 set to 6 type @ 15
+MTRR addr 0xa0-0xa4 set to 0 type @ 16
+MTRR addr 0xa4-0xa8 set to 0 type @ 17
+MTRR addr 0xa8-0xac set to 0 type @ 18
+MTRR addr 0xac-0xb0 set to 0 type @ 19
+MTRR addr 0xb0-0xb4 set to 0 type @ 20
+MTRR addr 0xb4-0xb8 set to 0 type @ 21
+MTRR addr 0xb8-0xbc set to 0 type @ 22
+MTRR addr 0xbc-0xc0 set to 0 type @ 23
+MTRR addr 0xc0-0xc1 set to 6 type @ 24
+MTRR addr 0xc1-0xc2 set to 6 type @ 25
+MTRR addr 0xc2-0xc3 set to 6 type @ 26
+MTRR addr 0xc3-0xc4 set to 6 type @ 27
+MTRR addr 0xc4-0xc5 set to 6 type @ 28
+MTRR addr 0xc5-0xc6 set to 6 type @ 29
+MTRR addr 0xc6-0xc7 set to 6 type @ 30
+MTRR addr 0xc7-0xc8 set to 6 type @ 31
+MTRR addr 0xc8-0xc9 set to 6 type @ 32
+MTRR addr 0xc9-0xca set to 6 type @ 33
+MTRR addr 0xca-0xcb set to 6 type @ 34
+MTRR addr 0xcb-0xcc set to 6 type @ 35
+MTRR addr 0xcc-0xcd set to 6 type @ 36
+MTRR addr 0xcd-0xce set to 6 type @ 37
+MTRR addr 0xce-0xcf set to 6 type @ 38
+MTRR addr 0xcf-0xd0 set to 6 type @ 39
+MTRR addr 0xd0-0xd1 set to 6 type @ 40
+MTRR addr 0xd1-0xd2 set to 6 type @ 41
+MTRR addr 0xd2-0xd3 set to 6 type @ 42
+MTRR addr 0xd3-0xd4 set to 6 type @ 43
+MTRR addr 0xd4-0xd5 set to 6 type @ 44
+MTRR addr 0xd5-0xd6 set to 6 type @ 45
+MTRR addr 0xd6-0xd7 set to 6 type @ 46
+MTRR addr 0xd7-0xd8 set to 6 type @ 47
+MTRR addr 0xd8-0xd9 set to 6 type @ 48
+MTRR addr 0xd9-0xda set to 6 type @ 49
+MTRR addr 0xda-0xdb set to 6 type @ 50
+MTRR addr 0xdb-0xdc set to 6 type @ 51
+MTRR addr 0xdc-0xdd set to 6 type @ 52
+MTRR addr 0xdd-0xde set to 6 type @ 53
+MTRR addr 0xde-0xdf set to 6 type @ 54
+MTRR addr 0xdf-0xe0 set to 6 type @ 55
+MTRR addr 0xe0-0xe1 set to 6 type @ 56
+MTRR addr 0xe1-0xe2 set to 6 type @ 57
+MTRR addr 0xe2-0xe3 set to 6 type @ 58
+MTRR addr 0xe3-0xe4 set to 6 type @ 59
+MTRR addr 0xe4-0xe5 set to 6 type @ 60
+MTRR addr 0xe5-0xe6 set to 6 type @ 61
+MTRR addr 0xe6-0xe7 set to 6 type @ 62
+MTRR addr 0xe7-0xe8 set to 6 type @ 63
+MTRR addr 0xe8-0xe9 set to 6 type @ 64
+MTRR addr 0xe9-0xea set to 6 type @ 65
+MTRR addr 0xea-0xeb set to 6 type @ 66
+MTRR addr 0xeb-0xec set to 6 type @ 67
+MTRR addr 0xec-0xed set to 6 type @ 68
+MTRR addr 0xed-0xee set to 6 type @ 69
+MTRR addr 0xee-0xef set to 6 type @ 70
+MTRR addr 0xef-0xf0 set to 6 type @ 71
+MTRR addr 0xf0-0xf1 set to 6 type @ 72
+MTRR addr 0xf1-0xf2 set to 6 type @ 73
+MTRR addr 0xf2-0xf3 set to 6 type @ 74
+MTRR addr 0xf3-0xf4 set to 6 type @ 75
+MTRR addr 0xf4-0xf5 set to 6 type @ 76
+MTRR addr 0xf5-0xf6 set to 6 type @ 77
+MTRR addr 0xf6-0xf7 set to 6 type @ 78
+MTRR addr 0xf7-0xf8 set to 6 type @ 79
+MTRR addr 0xf8-0xf9 set to 6 type @ 80
+MTRR addr 0xf9-0xfa set to 6 type @ 81
+MTRR addr 0xfa-0xfb set to 6 type @ 82
+MTRR addr 0xfb-0xfc set to 6 type @ 83
+MTRR addr 0xfc-0xfd set to 6 type @ 84
+MTRR addr 0xfd-0xfe set to 6 type @ 85
+MTRR addr 0xfe-0xff set to 6 type @ 86
+MTRR addr 0xff-0x100 set to 6 type @ 87
+MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
+MTRR: default type WB/UC MTRR counts: 8/5.
+MTRR: UC selected as default type.
+MTRR: 0 base 0x0000000000000000 mask 0x0000ffffc0000000 type 6
+MTRR: 1 base 0x0000000040000000 mask 0x0000ffffe0000000 type 6
+MTRR: 2 base 0x0000000060000000 mask 0x0000fffff0000000 type 6
+MTRR: 3 base 0x00000000a0000000 mask 0x0000fffff0000000 type 1
+MTRR: 4 base 0x00000000b0000000 mask 0x0000fffffe000000 type 1
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local apic... apic_id: 0x00 done.
+CPU model: AMD Athlon(tm) II X2 250 Processor
+siblings = 01, Disabling SMM ASeg memory
+CPU #0 initialized
+CPU1: stack_base 00127000, stack_end 00127ff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 1.
+Sending STARTUP #1 to 1.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+Waiting for 1 CPUS to stop
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local apic... apic_id: 0x01 done.
+CPU model: AMD Athlon(tm) II X2 250 Processor
+siblings = 01, Disabling SMM ASeg memory
+CPU #1 initialized
+All AP CPUs stopped (7845 loops)
+CPU1: stack: 00127000 - 00128000, lowest used address 00127d08, stack used: 760 bytes
+CPU_CLUSTER: 0 init finished in 582120 usecs
+PCI: 00:18.0 init ...
+PCI: 00:18.0 init finished in 2011 usecs
+PCI: 00:18.1 init ...
+PCI: 00:18.1 init finished in 2011 usecs
+PCI: 00:18.2 init ...
+PCI: 00:18.2 init finished in 2010 usecs
+PCI: 00:18.3 init ...
+NB: Function 3 Misc Control.. done.
+PCI: 00:18.3 init finished in 5251 usecs
+PCI: 00:18.4 init ...
+PCI: 00:18.4 init finished in 2010 usecs
+PCI: 00:00.0 init ...
+PCI: 00:00.0 init finished in 2009 usecs
+PCI: 00:11.0 init ...
+sata_bar0=3020
+sata_bar1=3040
+sata_bar2=3028
+sata_bar3=3044
+sata_bar4=3000
+sata_bar5=b9209000
+SATA port 0 status = 0
+No Primary Master SATA drive on Slot0
+SATA port 1 status = 0
+No Primary Slave SATA drive on Slot1
+SATA port 2 status = 0
+No Secondary Master SATA drive on Slot2
+SATA port 3 status = 23
+drive detection done after 0 ms
+Secondary Slave device is ready after 1 tries
+PCI: 00:11.0 init finished in 36540 usecs
+PCI: 00:12.0 init ...
+PCI: 00:12.0 init finished in 2042 usecs
+PCI: 00:12.1 init ...
+PCI: 00:12.1 init finished in 2043 usecs
+PCI: 00:12.2 init ...
+usb2_bar0=0xb9209400
+rpr 6.23, final dword=809e01c8
+PCI: 00:12.2 init finished in 6734 usecs
+PCI: 00:13.0 init ...
+PCI: 00:13.0 init finished in 2041 usecs
+PCI: 00:13.1 init ...
+PCI: 00:13.1 init finished in 2042 usecs
+PCI: 00:13.2 init ...
+usb2_bar0=0xb9209500
+rpr 6.23, final dword=809e01c8
+PCI: 00:13.2 init finished in 6734 usecs
+PCI: 00:14.0 init ...
+sm_init().
+IOAPIC: Clearing IOAPIC at fec00000
+IOAPIC: 24 interrupts
+IOAPIC: reg 0x00000000 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
+IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
+CBFS @ 0 size ffa00
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 140 size 590
+set power off after power fail
+CBFS @ 0 size ffa00
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 140 size 590
+++++++++++set NMI+++++
+RTC Init
+sm_init() end
+PCI: 00:14.0 init finished in 141213 usecs
+PCI: 00:14.1 init ...
+PCI: 00:14.1 init finished in 2016 usecs
+PCI: 00:14.2 init ...
+base = 0xb9200000
+codec_mask = 05
+2(th) codec viddid: ffffffff
+0(th) codec viddid: ffffffff
+PCI: 00:14.2 init finished in 13432 usecs
+PCI: 00:14.3 init ...
+Skipping isa_dma_init() to avoid getting stuck.
+PCI: 00:14.3 init finished in 6284 usecs
+PCI: 00:14.4 init ...
+PCI: 00:14.4 init finished in 2036 usecs
+PCI: 00:14.5 init ...
+PCI: 00:14.5 init finished in 2042 usecs
+PCI: 00:18.0 init ...
+PCI: 00:18.0 init finished in 2010 usecs
+PCI: 00:18.1 init ...
+PCI: 00:18.1 init finished in 2008 usecs
+PCI: 00:18.2 init ...
+PCI: 00:18.2 init finished in 2010 usecs
+PCI: 00:18.3 init ...
+NB: Function 3 Misc Control.. done.
+PCI: 00:18.3 init finished in 5252 usecs
+PCI: 00:18.4 init ...
+PCI: 00:18.4 init finished in 2011 usecs
+PCI: 02:00.0 init ...
+PCI: 02:00.0 init finished in 2009 usecs
+PCI: 02:00.1 init ...
+PCI: 02:00.1 init finished in 2011 usecs
+PCI: 03:00.0 init ...
+PCI: 03:00.0 init finished in 2008 usecs
+PNP: 002e.1 init ...
+PNP: 002e.1 init finished in 1924 usecs
+PNP: 002e.5 init ...
+Keyboard init...
+No PS/2 keyboard detected.
+PNP: 002e.5 init finished in 292527 usecs
+PNP: 002e.6 init ...
+PNP: 002e.6 init finished in 1923 usecs
+Devices initialized
+Show all devs... After init.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+APIC: 00: enabled 1
+DOMAIN: 0000: enabled 1
+PCI: 00:18.0: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 1
+PCI: 01:05.0: enabled 0
+PCI: 00:02.0: enabled 1
+PCI: 00:03.0: enabled 0
+PCI: 00:04.0: enabled 0
+PCI: 00:05.0: enabled 0
+PCI: 00:06.0: enabled 0
+PCI: 00:07.0: enabled 0
+PCI: 00:08.0: enabled 0
+PCI: 00:09.0: enabled 0
+PCI: 00:0a.0: enabled 1
+PCI: 00:11.0: enabled 1
+PCI: 00:12.0: enabled 1
+PCI: 00:12.1: enabled 1
+PCI: 00:12.2: enabled 1
+PCI: 00:13.0: enabled 1
+PCI: 00:13.1: enabled 1
+PCI: 00:13.2: enabled 1
+PCI: 00:14.0: enabled 1
+I2C: 01:50: enabled 1
+I2C: 01:51: enabled 1
+I2C: 01:52: enabled 1
+I2C: 01:53: enabled 1
+PCI: 00:14.1: enabled 1
+PCI: 00:14.2: enabled 1
+PCI: 00:14.3: enabled 1
+PNP: 002e.0: enabled 0
+PNP: 002e.1: enabled 1
+PNP: 002e.2: enabled 0
+PNP: 002e.3: enabled 0
+PNP: 002e.4: enabled 0
+PNP: 002e.5: enabled 1
+PNP: 002e.6: enabled 1
+PNP: 002e.7: enabled 0
+PNP: 002e.8: enabled 0
+PNP: 002e.9: enabled 0
+PNP: 002e.a: enabled 0
+PCI: 00:14.4: enabled 1
+PCI: 00:14.5: enabled 1
+PCI: 00:18.1: enabled 1
+PCI: 00:18.2: enabled 1
+PCI: 00:18.3: enabled 1
+PCI: 00:18.4: enabled 1
+APIC: 01: enabled 1
+PCI: 00:18.0: enabled 1
+PCI: 00:18.1: enabled 1
+PCI: 00:18.2: enabled 1
+PCI: 00:18.3: enabled 1
+PCI: 00:18.4: enabled 1
+PCI: 02:00.0: enabled 1
+PCI: 02:00.1: enabled 1
+PCI: 03:00.0: enabled 1
+BS: Exiting BS_DEV_INIT state.
+BS: BS_DEV_INIT times (us): entry 0 run 1391613 exit 0
+BS: Entering BS_POST_DEVICE state.
+Finalize devices...
+Devices finalized
+BS: Exiting BS_POST_DEVICE state.
+BS: BS_POST_DEVICE times (us): entry 0 run 6551 exit 0
+BS: Entering BS_OS_RESUME_CHECK state.
+BS: Exiting BS_OS_RESUME_CHECK state.
+BS: BS_OS_RESUME_CHECK times (us): entry 0 run 3398 exit 0
+BS: Entering BS_WRITE_TABLES state.
+Copying Interrupt Routing Table to 0x000f0000... done.
+Copying Interrupt Routing Table to 0x6ffe6000... done.
+PIRQ table: 336 bytes.
+CBFS @ 0 size ffa00
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 140 size 590
+Wrote the mp table end at: 000f0410 - 000f051c
+Wrote the mp table end at: 6ffe5010 - 6ffe511c
+MP table: 284 bytes.
+CBFS @ 0 size ffa00
+CBFS: Locating 'fallback/dsdt.aml'
+CBFS: Found @ offset 740 size 289d
+CBFS @ 0 size ffa00
+CBFS: Locating 'fallback/slic'
+CBFS: 'fallback/slic' not found.
+ACPI: Writing ACPI tables at 6ffc1000.
+ACPI: * FACS
+ACPI: * DSDT
+ACPI: * FADT
+pm_base: 0x0800
+ACPI: added table 1/32, length now 40
+ACPI: * SSDT
+processor_brand=AMD Athlon(tm) II X2 250 Processor
+Pstates algorithm ...
+Pstate_freq[0] = 3000MHz Pstate_power[0] = 30937mw
+Pstate_latency[0] = 5us
+Pstate_freq[1] = 2300MHz Pstate_power[1] = 26010mw
+Pstate_latency[1] = 5us
+Pstate_freq[2] = 1800MHz Pstate_power[2] = 22207mw
+Pstate_latency[2] = 5us
+PSS: 3000MHz power 30937 control 0x0 status 0x0
+PSS: 2300MHz power 26010 control 0x1 status 0x1
+PSS: 1800MHz power 22207 control 0x2 status 0x2
+PSS: 3000MHz power 30937 control 0x0 status 0x0
+PSS: 2300MHz power 26010 control 0x1 status 0x1
+PSS: 1800MHz power 22207 control 0x2 status 0x2
+ACPI: added table 2/32, length now 44
+ACPI: * MCFG
+ACPI: * TCPA
+TCPA log created at 6ffb1000
+ACPI: added table 3/32, l
+7759 bytes lost