system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z
diff --git a/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/cbfs.txt b/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/cbfs.txt
new file mode 100644
index 0000000..544ed62
--- /dev/null
+++ b/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/cbfs.txt
@@ -0,0 +1,23 @@
+FMAP REGION: COREBOOT
+Name                           Offset     Type           Size   Comp
+cbfs master header             0x0        cbfs header        32 none
+fallback/romstage              0x80       stage           58384 none
+cpu_microcode_blob.bin         0xe540     microcode      198656 none
+intel_fit                      0x3ed80    raw                80 none
+fallback/ramstage              0x3ee00    stage          117672 LZMA (264336 decompressed)
+config                         0x5ba00    raw              1541 none
+revision                       0x5c040    raw               717 none
+build_info                     0x5c340    raw                96 none
+bootsplash.jpg                 0x5c400    bootsplash      49873 none
+fallback/dsdt.aml              0x68700    raw             13517 none
+cmos.default                   0x6bc00    cmos_default      256 none
+(empty)                        0x6bd40    null              100 none
+fspm.bin                       0x6bdc0    fsp            581632 none
+vbt.bin                        0xf9e00    raw              1177 LZMA (4608 decompressed)
+cmos_layout.bin                0xfa300    cmos_layout       648 none
+(empty)                        0xfa5c0    null             2020 none
+fsps.bin                       0xfadc0    fsp            191132 LZMA (212992 decompressed)
+fallback/postcar               0x1298c0   stage           27164 none
+fallback/payload               0x130340   simple elf    5473836 none
+(empty)                        0x6689c0   null          3407204 none
+bootblock                      0x9a8740   bootblock       30336 none
diff --git a/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/config.short.txt b/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/config.short.txt
new file mode 100644
index 0000000..fead97a
--- /dev/null
+++ b/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/config.short.txt
@@ -0,0 +1,35 @@
+# This image was built using coreboot 4.14-2062-ge54b508db8
+CONFIG_USE_OPTION_TABLE=y
+CONFIG_BOOTSPLASH_IMAGE=y
+CONFIG_BOOTSPLASH_FILE="../darp6/boot-darp6.jpg"
+CONFIG_VENDOR_SYSTEM76=y
+CONFIG_NO_POST=y
+CONFIG_CBFS_SIZE=0xA00000
+CONFIG_IFD_BIN_PATH="../darp6/fd.rom"
+CONFIG_ME_BIN_PATH="../darp6/me.rom"
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+# CONFIG_CONSOLE_SERIAL is not set
+CONFIG_USE_LEGACY_8254_TIMER=y
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_PCIEXP_HOTPLUG_BUSES=32
+CONFIG_PCIEXP_HOTPLUG_MEM=0x2000000
+CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
+CONFIG_BOARD_SYSTEM76_DARP6=y
+CONFIG_UART_PCI_ADDR=0x0
+CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
+CONFIG_HAVE_ME_BIN=y
+CONFIG_BOOTSPLASH=y
+CONFIG_PCIEXP_HOTPLUG_IO=0x2000
+CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
+CONFIG_SUBSYSTEM_DEVICE_ID=0x1404
+CONFIG_SMMSTORE=y
+CONFIG_SMMSTORE_SIZE=0x40000
+CONFIG_USE_PC_CMOS_ALTCENTURY=y
+CONFIG_TPM_MEASURED_BOOT=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+CONFIG_PAYLOAD_LINUXBOOT=y
+CONFIG_LINUXBOOT_COMPILE_KERNEL=y
+CONFIG_LINUXBOOT_KERNEL_CUSTOM_CONFIG=y
+CONFIG_LINUXBOOT_KERNEL_CONFIGFILE="../../../linux-defconfig"
+CONFIG_LINUXBOOT_BUILD_INITRAMFS=y
+CONFIG_LINUXBOOT_UROOT_COMMANDS="boot coreboot-app github.com/u-root/u-root/cmds/core/mkdir github.com/u-root/u-root/cmds/core/blkid github.com/u-root/u-root/cmds/core/hexdump github.com/u-root/u-root/cmds/core/gzip github.com/u-root/u-root/cmds/core/md5sum github.com/u-root/u-root/cmds/core/shasum github.com/u-root/u-root/cmds/core/umount github.com/u-root/u-root/cmds/core/more github.com/u-root/u-root/cmds/core/kexec"
diff --git a/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/config.txt b/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/config.txt
new file mode 100644
index 0000000..ffd25a2
--- /dev/null
+++ b/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/config.txt
@@ -0,0 +1,748 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# coreboot configuration
+#
+
+#
+# General setup
+#
+CONFIG_COREBOOT_BUILD=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+# CONFIG_ANY_TOOLCHAIN is not set
+# CONFIG_CCACHE is not set
+# CONFIG_FMD_GENPARSER is not set
+# CONFIG_UTIL_GENPARSER is not set
+# CONFIG_OPTION_BACKEND_NONE is not set
+CONFIG_USE_OPTION_TABLE=y
+# CONFIG_STATIC_OPTION_TABLE is not set
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_INCLUDE_CONFIG_FILE=y
+CONFIG_COLLECT_TIMESTAMPS=y
+# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
+CONFIG_USE_BLOBS=y
+# CONFIG_USE_AMD_BLOBS is not set
+# CONFIG_USE_QC_BLOBS is not set
+# CONFIG_COVERAGE is not set
+# CONFIG_UBSAN is not set
+CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
+# CONFIG_ASAN is not set
+# CONFIG_NO_STAGE_CACHE is not set
+CONFIG_TSEG_STAGE_CACHE=y
+# CONFIG_UPDATE_IMAGE is not set
+CONFIG_BOOTSPLASH_IMAGE=y
+CONFIG_BOOTSPLASH_FILE="../darp6/boot-darp6.jpg"
+# CONFIG_FW_CONFIG is not set
+# end of General setup
+
+#
+# Mainboard
+#
+
+#
+# Important: Run 'make distclean' before switching boards
+#
+# CONFIG_VENDOR_51NB is not set
+# CONFIG_VENDOR_ACER is not set
+# CONFIG_VENDOR_ADLINK is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_AOPEN is not set
+# CONFIG_VENDOR_APPLE is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_BAP is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BOSTENTECH is not set
+# CONFIG_VENDOR_CAVIUM is not set
+# CONFIG_VENDOR_CLEVO is not set
+# CONFIG_VENDOR_COMPULAB is not set
+# CONFIG_VENDOR_DELL is not set
+# CONFIG_VENDOR_ELMEX is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_EXAMPLE is not set
+# CONFIG_VENDOR_FACEBOOK is not set
+# CONFIG_VENDOR_FOXCONN is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_GIZMOSPHERE is not set
+# CONFIG_VENDOR_GOOGLE is not set
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LENOVO is not set
+# CONFIG_VENDOR_LIBRETREND is not set
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_OCP is not set
+# CONFIG_VENDOR_OPENCELLULAR is not set
+# CONFIG_VENDOR_PACKARDBELL is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_PINE64 is not set
+# CONFIG_VENDOR_PORTWELL is not set
+# CONFIG_VENDOR_PRODRIVE is not set
+# CONFIG_VENDOR_PROTECTLI is not set
+# CONFIG_VENDOR_PURISM is not set
+# CONFIG_VENDOR_RAZER is not set
+# CONFIG_VENDOR_RODA is not set
+# CONFIG_VENDOR_SAMSUNG is not set
+# CONFIG_VENDOR_SAPPHIRE is not set
+# CONFIG_VENDOR_SCALEWAY is not set
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SIFIVE is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+CONFIG_VENDOR_SYSTEM76=y
+# CONFIG_VENDOR_TI is not set
+# CONFIG_VENDOR_UP is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_PART_NUMBER="darp6"
+CONFIG_MAINBOARD_VERSION="darp6"
+CONFIG_MAINBOARD_DIR="system76/cml-u"
+CONFIG_VGA_BIOS_ID="8086,9b41"
+CONFIG_DIMM_MAX=2
+CONFIG_DIMM_SPD_SIZE=512
+CONFIG_FMDFILE=""
+CONFIG_NO_POST=y
+CONFIG_MAINBOARD_VENDOR="System76"
+CONFIG_CBFS_SIZE=0xA00000
+CONFIG_ONBOARD_VGA_IS_PRIMARY=y
+CONFIG_MAX_CPUS=12
+# CONFIG_VBOOT is not set
+CONFIG_VARIANT_DIR="darp6"
+CONFIG_DEVICETREE="devicetree.cb"
+# CONFIG_VGA_BIOS is not set
+CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="System76"
+CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
+CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xe00
+CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
+CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
+CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
+CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
+CONFIG_UART_FOR_CONSOLE=2
+CONFIG_CONSOLE_POST=y
+CONFIG_TPM_PIRQ=0x0
+CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
+CONFIG_DCACHE_RAM_BASE=0xfef00000
+CONFIG_DCACHE_RAM_SIZE=0x40000
+CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
+CONFIG_DCACHE_BSP_STACK_SIZE=0x20400
+CONFIG_MMCONF_BASE_ADDRESS=0xe0000000
+CONFIG_MMCONF_BUS_NUMBER=256
+CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
+CONFIG_HAVE_INTEL_FIRMWARE=y
+CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
+CONFIG_DRIVERS_INTEL_WIFI=y
+CONFIG_IFD_BIN_PATH="../darp6/fd.rom"
+CONFIG_ME_BIN_PATH="../darp6/me.rom"
+CONFIG_USE_PM_ACPI_TIMER=y
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+# CONFIG_CONSOLE_SERIAL is not set
+CONFIG_USE_LEGACY_8254_TIMER=y
+CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Darter Pro"
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_PCIEXP_HOTPLUG_BUSES=32
+CONFIG_PCIEXP_HOTPLUG_MEM=0x2000000
+CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x20000000
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
+CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y
+CONFIG_PCIEXP_L1_SUB_STATE=y
+CONFIG_PCIEXP_CLK_PM=y
+# CONFIG_DRIVERS_UART_8250IO is not set
+CONFIG_HEAP_SIZE=0x8000
+# CONFIG_BOARD_SYSTEM76_ADDW1 is not set
+# CONFIG_BOARD_SYSTEM76_ADDW2 is not set
+# CONFIG_BOARD_SYSTEM76_GALP4 is not set
+CONFIG_BOARD_SYSTEM76_DARP6=y
+# CONFIG_BOARD_SYSTEM76_DARP7 is not set
+# CONFIG_BOARD_SYSTEM76_GALP5 is not set
+# CONFIG_BOARD_SYSTEM76_GAZE15 is not set
+# CONFIG_BOARD_SYSTEM76_LEMP10 is not set
+# CONFIG_BOARD_SYSTEM76_LEMP9 is not set
+# CONFIG_BOARD_SYSTEM76_ORYP5 is not set
+# CONFIG_BOARD_SYSTEM76_ORYP6 is not set
+# CONFIG_BOARD_SYSTEM76_GALP3_C is not set
+# CONFIG_BOARD_SYSTEM76_DARP5 is not set
+CONFIG_LINUX_COMMAND_LINE=""
+CONFIG_BOARD_ROMSIZE_KB_16384=y
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_16384=y
+# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=16384
+CONFIG_ROM_SIZE=0x01000000
+CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
+CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
+# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set
+CONFIG_POWER_STATE_ON_AFTER_FAILURE=y
+# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
+CONFIG_MAINBOARD_POWER_FAILURE_STATE=1
+# end of Mainboard
+
+CONFIG_SYSTEM_TYPE_LAPTOP=y
+
+#
+# Chipset
+#
+
+#
+# SoC
+#
+CONFIG_ARCH_ALL_STAGES_X86=y
+CONFIG_CHIPSET_DEVICETREE=""
+CONFIG_CBFS_MCACHE_SIZE=0x4000
+CONFIG_ROMSTAGE_ADDR=0x2000000
+CONFIG_FSP_TEMP_RAM_SIZE=0x10000
+CONFIG_VERSTAGE_ADDR=0x2000000
+CONFIG_RAMBASE=0xe00000
+CONFIG_CPU_ADDR_BITS=36
+CONFIG_CONSOLE_UART_BASE_ADDRESS=0xfe032000
+CONFIG_SMM_TSEG_SIZE=0x800000
+CONFIG_SMM_RESERVED_SIZE=0x200000
+CONFIG_SMM_MODULE_STACK_SIZE=0x800
+CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=216
+CONFIG_CPU_SPECIFIC_OPTIONS=y
+CONFIG_FSP_M_FILE="$(obj)/Fsp_M.fd"
+CONFIG_FSP_S_FILE="$(obj)/Fsp_S.fd"
+CONFIG_ACPI_CPU_STRING="\\_SB.CP%02d"
+CONFIG_STACK_SIZE=0x1000
+CONFIG_IFD_CHIPSET="cnl"
+CONFIG_IED_REGION_SIZE=0x400000
+CONFIG_MAX_ROOT_PORTS=16
+CONFIG_MAX_PCIE_CLOCK_SRC=6
+CONFIG_PCR_BASE_ADDRESS=0xfd000000
+CONFIG_CPU_BCLK_MHZ=100
+CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120
+CONFIG_CPU_XTAL_HZ=24000000
+CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=3
+CONFIG_SOC_INTEL_I2C_DEV_MAX=6
+CONFIG_VBT_DATA_SIZE_KB=8
+CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30
+CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35
+CONFIG_FSP_HEADER_PATH="3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/"
+CONFIG_FSP_FD_PATH="3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Fsp.fd"
+CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8258
+CONFIG_INTEL_GMA_BCLV_WIDTH=32
+CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8254
+CONFIG_INTEL_GMA_BCLM_WIDTH=32
+CONFIG_PCIEXP_ASPM=y
+CONFIG_PCIEXP_COMMON_CLOCK=y
+CONFIG_SOC_INTEL_CANNONLAKE_BASE=y
+CONFIG_SOC_INTEL_COMETLAKE=y
+CONFIG_SOC_INTEL_COMETLAKE_1=y
+CONFIG_SOC_INTEL_CANNONLAKE_DEBUG_CONSENT=0
+CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
+CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=4
+CONFIG_UART_PCI_ADDR=0x0
+CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y
+CONFIG_SOC_INTEL_COMMON=y
+
+#
+# Intel SoC Common Code for IP blocks
+#
+CONFIG_SOC_INTEL_COMMON_BLOCK=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPPC=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_CNVI=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y
+CONFIG_INTEL_CAR_NEM_ENHANCED=y
+# CONFIG_USE_INTEL_FSP_MP_INIT is not set
+# CONFIG_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI is not set
+CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y
+CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME"
+CONFIG_SOC_INTEL_CSE_RW_A_FMAP_NAME="ME_RW_A"
+CONFIG_SOC_INTEL_CSE_RW_B_FMAP_NAME="ME_RW_B"
+CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw"
+CONFIG_SOC_INTEL_CSE_RW_METADATA_CBFS_NAME="me_rw.metadata"
+CONFIG_SOC_INTEL_CSE_RW_FILE=""
+CONFIG_SOC_INTEL_CSE_RW_VERSION=""
+CONFIG_SOC_INTEL_COMMON_BLOCK_DMI=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y
+CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y
+CONFIG_SOC_INTEL_CONFIGURE_DDI_A_4_LANES=y
+# CONFIG_SOC_INTEL_DISABLE_IGD is not set
+CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y
+CONFIG_AZALIA_MAX_CODECS=4
+CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_IRQ=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y
+CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y
+CONFIG_PM_ACPI_TIMER_OPTIONAL=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y
+# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE is not set
+CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0
+CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y
+CONFIG_INTEL_LPSS_UART_FOR_CONSOLE=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
+CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
+
+#
+# Intel SoC Common PCH Code
+#
+CONFIG_SOC_INTEL_COMMON_PCH_BASE=y
+CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y
+CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y
+CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y
+
+#
+# Intel SoC Common coreboot stages and non-IP blocks
+#
+CONFIG_SOC_INTEL_COMMON_RESET=y
+CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y
+CONFIG_PAVP=y
+CONFIG_SOC_INTEL_COMMON_NHLT=y
+# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set
+
+#
+# CPU
+#
+CONFIG_SSE2=y
+CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
+CONFIG_CPU_INTEL_COMMON=y
+CONFIG_ENABLE_VMX=y
+CONFIG_SET_IA32_FC_LOCK_BIT=y
+CONFIG_SET_MSR_AESNI_LOCK_BIT=y
+CONFIG_CPU_INTEL_COMMON_SMM=y
+CONFIG_MICROCODE_UPDATE_PRE_RAM=y
+CONFIG_PARALLEL_MP=y
+CONFIG_PARALLEL_MP_AP_WORK=y
+CONFIG_XAPIC_ONLY=y
+# CONFIG_X2APIC_ONLY is not set
+# CONFIG_X2APIC_RUNTIME is not set
+CONFIG_UDELAY_TSC=y
+CONFIG_TSC_MONOTONIC_TIMER=y
+CONFIG_LOGICAL_CPUS=y
+CONFIG_HAVE_SMI_HANDLER=y
+CONFIG_SMM_TSEG=y
+CONFIG_SMM_MODULE_HEAP_SIZE=0x4000
+CONFIG_SMM_STUB_STACK_SIZE=0x400
+CONFIG_SMP=y
+CONFIG_SSE=y
+CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
+CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
+# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
+# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
+# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
+
+#
+# Northbridge
+#
+
+#
+# Southbridge
+#
+CONFIG_PCIEXP_HOTPLUG=y
+CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
+CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
+CONFIG_VALIDATE_INTEL_DESCRIPTOR=y
+CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
+CONFIG_RCBA_LENGTH=0x4000
+CONFIG_FIXED_SMBUS_IO_BASE=0x400
+
+#
+# Super I/O
+#
+
+#
+# Embedded Controllers
+#
+CONFIG_EC_SYSTEM76_EC=y
+CONFIG_EC_SYSTEM76_EC_BAT_THRESHOLDS=y
+CONFIG_EC_SYSTEM76_EC_COLOR_KEYBOARD=y
+
+#
+# Intel Firmware
+#
+CONFIG_HAVE_ME_BIN=y
+# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
+# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
+# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
+CONFIG_UNLOCK_FLASH_REGIONS=y
+CONFIG_UDK_2017_BINDING=y
+CONFIG_UDK_2013_VERSION=2013
+CONFIG_UDK_2015_VERSION=2015
+CONFIG_UDK_2017_VERSION=2017
+CONFIG_UDK_202005_VERSION=202005
+CONFIG_UDK_VERSION=2017
+CONFIG_ARCH_X86=y
+CONFIG_ARCH_BOOTBLOCK_X86_32=y
+CONFIG_ARCH_VERSTAGE_X86_32=y
+CONFIG_ARCH_ROMSTAGE_X86_32=y
+CONFIG_ARCH_POSTCAR_X86_32=y
+CONFIG_ARCH_RAMSTAGE_X86_32=y
+CONFIG_ARCH_ALL_STAGES_X86_32=y
+CONFIG_RAMTOP=0x1000000
+CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_NUM_IPI_STARTS=2
+CONFIG_PC80_SYSTEM=y
+CONFIG_HAVE_CMOS_DEFAULT=y
+CONFIG_HPET_ADDRESS=0xfed00000
+CONFIG_POSTCAR_STAGE=y
+CONFIG_BOOTBLOCK_SIMPLE=y
+# CONFIG_BOOTBLOCK_NORMAL is not set
+CONFIG_COLLECT_TIMESTAMPS_TSC=y
+CONFIG_IDT_IN_EVERY_STAGE=y
+CONFIG_HAVE_CF9_RESET=y
+# end of Chipset
+
+#
+# Devices
+#
+CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
+CONFIG_HAVE_FSP_GOP=y
+# CONFIG_VGA_ROM_RUN is not set
+CONFIG_RUN_FSP_GOP=y
+# CONFIG_NO_GFX_INIT is not set
+
+#
+# Display
+#
+CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
+CONFIG_LINEAR_FRAMEBUFFER=y
+CONFIG_BOOTSPLASH=y
+# end of Display
+
+CONFIG_PCI=y
+CONFIG_MMCONF_SUPPORT=y
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+CONFIG_AZALIA_PLUGIN_SUPPORT=y
+CONFIG_AZALIA_LOCK_DOWN_R_WO_GCAP=y
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+CONFIG_MMCONF_LENGTH=0x10000000
+CONFIG_PCI_ALLOW_BUS_MASTER=y
+CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
+CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
+CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y
+CONFIG_PCIEXP_HOTPLUG_IO=0x2000
+# CONFIG_EARLY_PCI_BRIDGE is not set
+CONFIG_SUBSYSTEM_VENDOR_ID=0x1558
+CONFIG_SUBSYSTEM_DEVICE_ID=0x1404
+CONFIG_INTEL_GMA_HAVE_VBT=y
+CONFIG_INTEL_GMA_ADD_VBT=y
+# CONFIG_SOFTWARE_I2C is not set
+CONFIG_RESOURCE_ALLOCATOR_V4=y
+# end of Devices
+
+#
+# Generic Drivers
+#
+CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
+# CONFIG_ELOG is not set
+CONFIG_CACHE_MRC_SETTINGS=y
+CONFIG_MRC_SETTINGS_PROTECT=y
+CONFIG_SMMSTORE=y
+# CONFIG_SMMSTORE_V2 is not set
+CONFIG_SMMSTORE_REGION="SMMSTORE"
+CONFIG_SMMSTORE_FILENAME="smm_store"
+CONFIG_SMMSTORE_SIZE=0x40000
+CONFIG_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
+CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
+CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
+CONFIG_SPI_FLASH_SMM=y
+# CONFIG_SPI_FLASH_NO_FAST_READ is not set
+CONFIG_TPM_INIT_RAMSTAGE=y
+# CONFIG_TPM_PPI is not set
+CONFIG_DRIVERS_UART=y
+CONFIG_NO_UART_ON_SUPERIO=y
+CONFIG_DRIVERS_UART_8250MEM=y
+CONFIG_DRIVERS_UART_8250MEM_32=y
+# CONFIG_VPD is not set
+# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
+CONFIG_DRIVERS_I2C_DESIGNWARE=y
+CONFIG_DRIVERS_I2C_GENERIC=y
+CONFIG_DRIVERS_I2C_HID=y
+CONFIG_FSP_USE_REPO=y
+# CONFIG_DISPLAY_HOBS is not set
+# CONFIG_DISPLAY_UPD_DATA is not set
+# CONFIG_BMP_LOGO is not set
+CONFIG_PLATFORM_USES_FSP2_0=y
+CONFIG_PLATFORM_USES_FSP2_X86_32=y
+CONFIG_HAVE_INTEL_FSP_REPO=y
+CONFIG_ADD_FSP_BINARIES=y
+CONFIG_FSP_T_LOCATION=0xfffe0000
+CONFIG_FSP_S_CBFS="fsps.bin"
+CONFIG_FSP_M_CBFS="fspm.bin"
+CONFIG_FSP_FULL_FD=y
+CONFIG_FSP_T_RESERVED_SIZE=0x0
+CONFIG_FSP_M_XIP=y
+CONFIG_FSP_USES_CB_STACK=y
+CONFIG_HAVE_FSP_LOGO_SUPPORT=y
+CONFIG_FSP_COMPRESS_FSP_S_LZMA=y
+CONFIG_FSP_STATUS_GLOBAL_RESET_REQUIRED_3=y
+CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003
+CONFIG_SOC_INTEL_COMMON_FSP_RESET=y
+CONFIG_INTEL_GMA_ACPI=y
+CONFIG_INTEL_GMA_OPREGION_2_0=y
+# CONFIG_DRIVERS_PS2_KEYBOARD is not set
+CONFIG_DRIVERS_MC146818=y
+CONFIG_USE_PC_CMOS_ALTCENTURY=y
+CONFIG_MAINBOARD_HAS_LPC_TPM=y
+CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
+# CONFIG_DRIVERS_SIL_3114 is not set
+CONFIG_DRIVERS_WIFI_GENERIC=y
+# end of Generic Drivers
+
+#
+# Security
+#
+
+#
+# Verified Boot (vboot)
+#
+CONFIG_VBOOT_LIB=y
+# end of Verified Boot (vboot)
+
+#
+# Trusted Platform Module
+#
+# CONFIG_NO_TPM is not set
+CONFIG_TPM2=y
+CONFIG_TPM=y
+CONFIG_MAINBOARD_HAS_TPM2=y
+# CONFIG_DEBUG_TPM is not set
+# CONFIG_TPM_RDRESP_NEED_DELAY is not set
+CONFIG_TPM_MEASURED_BOOT=y
+CONFIG_TPM_MEASURED_BOOT_RUNTIME_DATA=""
+# end of Trusted Platform Module
+
+#
+# Memory initialization
+#
+CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
+# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set
+# end of Memory initialization
+
+# CONFIG_INTEL_TXT is not set
+# CONFIG_STM is not set
+# CONFIG_INTEL_CBNT_SUPPORT is not set
+CONFIG_BOOTMEDIA_LOCK_NONE=y
+# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
+# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
+# CONFIG_BOOTMEDIA_SMM_BWP is not set
+# end of Security
+
+CONFIG_ACPI_HAVE_PCAT_8259=y
+CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
+CONFIG_ACPI_SOC_NVS=y
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_ACPI_LPIT=y
+CONFIG_BOOT_DEVICE_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
+CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_RTC=y
+
+#
+# Console
+#
+CONFIG_BOOTBLOCK_CONSOLE=y
+CONFIG_POSTCAR_CONSOLE=y
+CONFIG_SQUELCH_EARLY_SMP=y
+CONFIG_FIXED_UART_FOR_CONSOLE=y
+# CONFIG_SPKMODEM is not set
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM=y
+# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
+# CONFIG_CONSOLE_SPI_FLASH is not set
+# CONFIG_CONSOLE_SYSTEM76_EC is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+CONFIG_HWBASE_DEBUG_CB=y
+# end of Console
+
+CONFIG_HAVE_ACPI_RESUME=y
+CONFIG_RESUME_PATH_SAME_AS_BOOT=y
+CONFIG_HAVE_MONOTONIC_TIMER=y
+CONFIG_HAVE_OPTION_TABLE=y
+CONFIG_IOAPIC=y
+CONFIG_ACPI_NHLT=y
+
+#
+# System tables
+#
+CONFIG_GENERATE_SMBIOS_TABLES=y
+CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
+# end of System tables
+
+#
+# Payload
+#
+# CONFIG_PAYLOAD_NONE is not set
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_BOOTBOOT is not set
+# CONFIG_PAYLOAD_FILO is not set
+# CONFIG_PAYLOAD_GRUB2 is not set
+CONFIG_PAYLOAD_LINUXBOOT=y
+# CONFIG_PAYLOAD_SEABIOS is not set
+# CONFIG_PAYLOAD_UBOOT is not set
+# CONFIG_PAYLOAD_YABITS is not set
+# CONFIG_PAYLOAD_LINUX is not set
+# CONFIG_PAYLOAD_TIANOCORE is not set
+CONFIG_PAYLOAD_FILE="payloads/external/LinuxBoot/linuxboot/bzImage"
+CONFIG_LINUXBOOT_X86_64=y
+# CONFIG_LINUXBOOT_X86 is not set
+
+#
+# Linux kernel
+#
+CONFIG_LINUXBOOT_COMPILE_KERNEL=y
+
+#
+# parse linux crosscompiler with: LINUXBOOT_CROSS_COMPILE
+#
+# CONFIG_LINUXBOOT_KERNEL_MAINLINE is not set
+CONFIG_LINUXBOOT_KERNEL_STABLE=y
+# CONFIG_LINUXBOOT_KERNEL_LONGTERM is not set
+# CONFIG_LINUXBOOT_KERNEL_CUSTOM is not set
+# CONFIG_LINUXBOOT_KERNEL_ARCH_DEFAULT_CONFIG is not set
+CONFIG_LINUXBOOT_KERNEL_CUSTOM_CONFIG=y
+CONFIG_LINUXBOOT_KERNEL_CONFIGFILE="../../../linux-defconfig"
+CONFIG_LINUXBOOT_KERNEL_BZIMAGE=y
+
+#
+# Linux initramfs
+#
+CONFIG_LINUXBOOT_BUILD_INITRAMFS=y
+CONFIG_LINUXBOOT_UROOT=y
+# CONFIG_LINUXBOOT_UROOT_CUSTOM is not set
+CONFIG_LINUXBOOT_UROOT_MASTER=y
+# CONFIG_LINUXBOOT_UROOT_V3_0_0 is not set
+# CONFIG_LINUXBOOT_UROOT_V2_0_0 is not set
+# CONFIG_LINUXBOOT_UROOT_V1_0_0 is not set
+CONFIG_LINUXBOOT_UROOT_VERSION="master"
+CONFIG_LINUXBOOT_UROOT_BB=y
+# CONFIG_LINUXBOOT_UROOT_SOURCE is not set
+CONFIG_LINUXBOOT_UROOT_FORMAT="bb"
+CONFIG_LINUXBOOT_UROOT_FILES=""
+CONFIG_LINUXBOOT_UROOT_INITCMD="init"
+CONFIG_LINUXBOOT_UROOT_SHELL="elvish"
+CONFIG_LINUXBOOT_UROOT_COMMANDS="boot coreboot-app github.com/u-root/u-root/cmds/core/mkdir github.com/u-root/u-root/cmds/core/blkid github.com/u-root/u-root/cmds/core/hexdump github.com/u-root/u-root/cmds/core/gzip github.com/u-root/u-root/cmds/core/md5sum github.com/u-root/u-root/cmds/core/shasum github.com/u-root/u-root/cmds/core/umount github.com/u-root/u-root/cmds/core/more github.com/u-root/u-root/cmds/core/kexec"
+# CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_NONE is not set
+CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ=y
+CONFIG_LINUX_INITRD="payloads/external/LinuxBoot/linuxboot/initramfs_u-root.cpio"
+CONFIG_LINUXBOOT_INITRAMFS_SUFFIX=".xz"
+CONFIG_PAYLOAD_OPTIONS=""
+# CONFIG_PXE is not set
+CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
+
+#
+# Secondary Payloads
+#
+# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set
+# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set
+# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set
+# CONFIG_TINT_SECONDARY_PAYLOAD is not set
+# end of Secondary Payloads
+# end of Payload
+
+#
+# Debugging
+#
+
+#
+# CPU Debug Settings
+#
+CONFIG_HAVE_DISPLAY_MTRRS=y
+# CONFIG_DISPLAY_MTRRS is not set
+
+#
+# BLOB Debug Settings
+#
+# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set
+# CONFIG_DISPLAY_FSP_HEADER is not set
+# CONFIG_VERIFY_HOBS is not set
+CONFIG_DISPLAY_FSP_VERSION_INFO=y
+CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y
+# CONFIG_CHECK_GPIO_CONFIG_CHANGES is not set
+
+#
+# General Debug Settings
+#
+# CONFIG_GDB_STUB is not set
+# CONFIG_FATAL_ASSERTS is not set
+CONFIG_HAVE_DEBUG_GPIO=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_DEBUG_CBFS is not set
+CONFIG_HAVE_DEBUG_SMBUS=y
+# CONFIG_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_SMI is not set
+# CONFIG_DEBUG_MALLOC is not set
+# CONFIG_DEBUG_RESOURCES is not set
+# CONFIG_DEBUG_CONSOLE_INIT is not set
+# CONFIG_DEBUG_SPI_FLASH is not set
+# CONFIG_DEBUG_FUNC is not set
+# CONFIG_DEBUG_BOOT_STATE is not set
+# CONFIG_DEBUG_ADA_CODE is not set
+CONFIG_HAVE_EM100_SUPPORT=y
+# CONFIG_EM100 is not set
+# end of Debugging
+
+CONFIG_SPD_READ_BY_WORD=y
+CONFIG_WARNINGS_ARE_ERRORS=y
+CONFIG_REG_SCRIPT=y
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_RELOCATABLE_MODULES=y
+CONFIG_GENERIC_GPIO_LIB=y
+CONFIG_HAVE_BOOTBLOCK=y
+CONFIG_HAVE_ROMSTAGE=y
+CONFIG_HAVE_RAMSTAGE=y
diff --git a/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/coreboot_console.txt b/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/coreboot_console.txt
new file mode 100644
index 0000000..55d06be
--- /dev/null
+++ b/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/coreboot_console.txt
@@ -0,0 +1,1443 @@
+42 entries total:
+
+11:start of bootblock					9,797 (0)
+0:1st timestamp						9,797 (0)
+12:end of bootblock					15,925 (6,127)
+13:starting to load romstage				15,925 (0)
+14:finished loading romstage				23,089 (7,164)
+1:start of romstage					23,096 (6)
+970:[0x3ca]						24,083 (987)
+2:before RAM initialization				95,528 (71,445)
+950:calling FspMemoryInit				96,270 (741)
+951:returning from FspMemoryInit			142,443 (46,173)
+3:after RAM initialization				144,515 (2,072)
+4:end of romstage					150,910 (6,395)
+100:start of postcar					153,659 (2,748)
+101:end of postcar					153,659 (0)
+8:starting to load ramstage				153,662 (2)
+15:starting LZMA decompress (ignore for x86)		170,616 (16,954)
+16:finished LZMA decompress (ignore for x86)		192,125 (21,508)
+9:finished loading ramstage				192,228 (103)
+10:start of ramstage					193,121 (892)
+15:starting LZMA decompress (ignore for x86)		238,819 (45,698)
+16:finished LZMA decompress (ignore for x86)		272,331 (33,512)
+30:device enumeration					284,718 (12,386)
+971:[0x3cb]						298,305 (13,587)
+15:starting LZMA decompress (ignore for x86)		298,740 (434)
+16:finished LZMA decompress (ignore for x86)		298,970 (229)
+954:calling FspSiliconInit				299,354 (384)
+955:returning from FspSiliconInit			1,534,877 (1,235,523)
+40:device configuration					1,542,574 (7,697)
+956:calling FspNotify(AfterPciEnumeration)		1,545,197 (2,623)
+957:returning from FspNotify(AfterPciEnumeration)	1,545,372 (174)
+50:device enable					1,545,373 (1)
+60:device initialization				1,584,539 (39,166)
+70:device setup done					1,592,873 (8,333)
+75:cbmem post						1,592,878 (5)
+80:write tables						1,592,885 (7)
+85:finalize chips					1,609,337 (16,451)
+90:load payload						1,610,381 (1,043)
+958:calling FspNotify(ReadyToBoot)			5,230,697 (3,620,316)
+959:returning from FspNotify(ReadyToBoot)		5,234,049 (3,352)
+960:calling FspNotify(EndOfFirmware)			5,234,049 (0)
+961:returning from FspNotify(EndOfFirmware)		5,234,641 (591)
+99:selfboot jump					5,235,551 (910)
+
+
+coreboot-4.14-2062-ge54b508db8 Wed Sep 29 19:06:54 UTC 2021 bootblock starting (log level: 8)...
+CPU: Intel(R) Core(TM) i7-10510U CPU @ 1.80GHz
+CPU: ID 806ec, Whiskeylake V0, ucode: 000000e9
+CPU: AES supported, TXT NOT supported, VT supported
+MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
+PCH: device id 0284 (rev 00) is Cometlake-U Premium
+IGD: device id 9b41 (rev 02) is CometLake ULT GT2
+CBFS: Found 'fallback/romstage' @0x80 size 0xe410 in mcache @0xfef21c2c
+FMAP: area COREBOOT found @ 650200 (10157568 bytes)
+TPM: Digest of FMAP: COREBOOT CBFS: fallback/romstage to PCR 2 logged
+BS: bootblock times (exec / console): total (unknown) / 0 ms
+
+
+coreboot-4.14-2062-ge54b508db8 Wed Sep 29 19:06:54 UTC 2021 romstage starting (log level: 0)...
+pm1_sts: 8900 pm1_en: 0000 pm1_cnt: 00001c00
+gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
+gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
+gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
+gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000
+TCO_STS:   0000 0000
+GEN_PMCON: e0015039 00000200
+GBLRST_CAUSE: 00000000 00000000
+prev_sleep_state 5
+CBFS: Found 'fspm.bin' @0x6bdc0 size 0x8e000 in mcache @0xfef21e44
+FMAP: area COREBOOT found @ 650200 (10157568 bytes)
+TPM: Digest of FMAP: COREBOOT CBFS: fspm.bin to PCR 2 logged
+FMAP: area RW_MRC_CACHE found @ 600000 (65536 bytes)
+CBMEM:
+IMD: root @ 0x99eff000 254 entries.
+IMD: root @ 0x99efec00 62 entries.
+External stage cache:
+IMD: root @ 0x9abff000 254 entries.
+IMD: root @ 0x9abfec00 62 entries.
+FMAP: area RW_MRC_CACHE found @ 600000 (65536 bytes)
+MRC: Checking cached data update for 'RW_MRC_CACHE'.
+SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
+MRC: 'RW_MRC_CACHE' does not need update.
+2 DIMMs found
+SMM Memory Map
+SMRAM       : 0x9a000000 0x1000000
+ Subregion 0: 0x9a000000 0xa00000
+ Subregion 1: 0x9aa00000 0x200000
+ Subregion 2: 0x9ac00000 0x400000
+top_of_ram = 0x9a000000
+MTRR Range: Start=99000000 End=9a000000 (Size 1000000)
+MTRR Range: Start=9a000000 End=9b000000 (Size 1000000)
+MTRR Range: Start=ff000000 End=0 (Size 1000000)
+Normal boot
+CBFS: Found 'fallback/postcar' @0x1298c0 size 0x6a1c in mcache @0xfef21f1c
+FMAP: area COREBOOT found @ 650200 (10157568 bytes)
+TPM: Digest of FMAP: COREBOOT CBFS: fallback/postcar to PCR 2 logged
+Loading module at 0x99b1e000 with entry 0x99b1e031. filesize: 0x6590 memsize: 0xa8a0
+Processing 275 relocs. Offset value of 0x97b1e000
+BS: romstage times (exec / console): total (unknown) / 0 ms
+
+
+coreboot-4.14-2062-ge54b508db8 Wed Sep 29 19:06:54 UTC 2021 postcar starting (log level: 0)...
+Normal boot
+CBFS: Found 'fallback/ramstage' @0x3ee00 size 0x1cba8 in mcache @0x99b2d10c
+FMAP: area COREBOOT found @ 650200 (10157568 bytes)
+TPM: Digest of FMAP: COREBOOT CBFS: fallback/ramstage to PCR 2 logged
+Loading module at 0x99abe000 with entry 0x99abe000. filesize: 0x3c648 memsize: 0x5ed90
+Processing 4226 relocs. Offset value of 0x98cbe000
+BS: postcar times (exec / console): total (unknown) / 0 ms
+
+
+coreboot-4.14-2062-ge54b508db8 Wed Sep 29 19:06:54 UTC 2021 ramstage starting (log level: 0)...
+Normal boot
+ACPI _SWS is PM1 Index 8 GPE Index -1
+CBFS: Found 'cpu_microcode_blob.bin' @0xe540 size 0x30800 in mcache @0x99b2d0ac
+FMAP: area COREBOOT found @ 650200 (10157568 bytes)
+TPM: Digest of FMAP: COREBOOT CBFS: cpu_microcode_blob.bin to PCR 2 logged
+microcode: sig=0x806ec pf=0x4 revision=0xe9
+Skip microcode update
+CBFS: Found 'fsps.bin' @0xfadc0 size 0x2ea9c in mcache @0x99b2d2dc
+FMAP: area COREBOOT found @ 650200 (10157568 bytes)
+TPM: Digest of FMAP: COREBOOT CBFS: fsps.bin to PCR 2 logged
+Detected 4 core, 8 thread CPU.
+Setting up SMI for CPU
+IED base = 0x9ac00000
+IED size = 0x00400000
+Will perform SMM setup.
+CPU: Intel(R) Core(TM) i7-10510U CPU @ 1.80GHz.
+Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
+Processing 16 relocs. Offset value of 0x00030000
+Attempting to start 7 APs
+Starting CPUs in xapic mode
+Waiting for 10ms after sending INIT.
+Waiting for 1st SIPI to complete...done.
+Waiting for 2nd SIPI to complete...done.
+AP: slot 2 apic_id 1, MCU rev: 0x000000e9
+AP: slot 1 apic_id 3, MCU rev: 0x000000e9
+AP: slot 3 apic_id 2, MCU rev: 0x000000e9
+AP: slot 4 apic_id 6, MCU rev: 0x000000e9
+AP: slot 5 apic_id 7, MCU rev: 0x000000e9
+AP: slot 6 apic_id 4, MCU rev: 0x000000e9
+AP: slot 7 apic_id 5, MCU rev: 0x000000e9
+smm_stub_place_stacks: cpus: 8 : stack space: needed -> 2000
+smm_stub_place_stacks: exit, stack_top 0x9a002000
+Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1f0 memsize: 0x1f0
+Processing 11 relocs. Offset value of 0x00038000
+smm_module_setup_stub: stack_end = 0x9a000000
+smm_module_setup_stub: stack_top = 0x9a002000
+smm_module_setup_stub: stack_size = 0x400
+smm_module_setup_stub: runtime.start32_offset = 0x4c
+smm_module_setup_stub: runtime.smm_size = 0x10000
+SMM Module: stub loaded at 0x00038000. Will call 0x99ad896e
+Installing permanent SMM handler to 0x9a000000
+smm_load_module: total_smm_space_needed bdd8, available -> a00000
+Loading module at 0x9a9f9000 with entry 0x9a9f9c33. filesize: 0x2d10 memsize: 0x6dd8
+Processing 170 relocs. Offset value of 0x9a9f9000
+smm_load_module: smram_start: 0x0x9a000000
+smm_load_module: smram_end: 0x9aa00000
+smm_load_module: stack_top: 0x9a004000
+smm_load_module: handler start 0x9a9f9c33
+smm_load_module: handler_size 7bb0
+smm_load_module: fxsave_area 0x9a9ff000
+smm_load_module: fxsave_size 1000
+smm_load_module: CONFIG_MSEG_SIZE 0x0
+smm_load_module: CONFIG_BIOS_RESOURCE_LIST_SIZE 0x0
+smm_load_module: handler_mod_params.smbase = 0x9a000000
+smm_load_module: per_cpu_save_state_size = 0x400
+smm_load_module: num_cpus = 0x8
+smm_load_module: total_save_state_size = 0x2000
+smm_load_module: cpu0 entry: 0x9a9e9000
+smm_create_map: cpus allowed in one segment 30
+smm_create_map: min # of segments needed 1
+CPU 0x0
+    smbase 9a9e9000  entry 9a9f1000
+           ss_start 9a9f8c00  code_end 9a9f11f0
+CPU 0x1
+    smbase 9a9e8c00  entry 9a9f0c00
+           ss_start 9a9f8800  code_end 9a9f0df0
+CPU 0x2
+    smbase 9a9e8800  entry 9a9f0800
+           ss_start 9a9f8400  code_end 9a9f09f0
+CPU 0x3
+    smbase 9a9e8400  entry 9a9f0400
+           ss_start 9a9f8000  code_end 9a9f05f0
+CPU 0x4
+    smbase 9a9e8000  entry 9a9f0000
+           ss_start 9a9f7c00  code_end 9a9f01f0
+CPU 0x5
+    smbase 9a9e7c00  entry 9a9efc00
+           ss_start 9a9f7800  code_end 9a9efdf0
+CPU 0x6
+    smbase 9a9e7800  entry 9a9ef800
+           ss_start 9a9f7400  code_end 9a9ef9f0
+CPU 0x7
+    smbase 9a9e7400  entry 9a9ef400
+           ss_start 9a9f7000  code_end 9a9ef5f0
+smm_stub_place_stacks: cpus: 8 : stack space: needed -> 4000
+smm_stub_place_stacks: exit, stack_top 0x9a004000
+Loading module at 0x9a9f1000 with entry 0x9a9f1000. filesize: 0x1f0 memsize: 0x1f0
+Processing 11 relocs. Offset value of 0x9a9f1000
+smm_place_entry_code: smbase 9a9e7400, stack_top 9a004000
+SMM Module: placing smm entry code at 9a9f0c00,  cpu # 0x1
+smm_place_entry_code: copying from 9a9f1000 to 9a9f0c00 0x1f0 bytes
+SMM Module: placing smm entry code at 9a9f0800,  cpu # 0x2
+smm_place_entry_code: copying from 9a9f1000 to 9a9f0800 0x1f0 bytes
+SMM Module: placing smm entry code at 9a9f0400,  cpu # 0x3
+smm_place_entry_code: copying from 9a9f1000 to 9a9f0400 0x1f0 bytes
+SMM Module: placing smm entry code at 9a9f0000,  cpu # 0x4
+smm_place_entry_code: copying from 9a9f1000 to 9a9f0000 0x1f0 bytes
+SMM Module: placing smm entry code at 9a9efc00,  cpu # 0x5
+smm_place_entry_code: copying from 9a9f1000 to 9a9efc00 0x1f0 bytes
+SMM Module: placing smm entry code at 9a9ef800,  cpu # 0x6
+smm_place_entry_code: copying from 9a9f1000 to 9a9ef800 0x1f0 bytes
+SMM Module: placing smm entry code at 9a9ef400,  cpu # 0x7
+smm_place_entry_code: copying from 9a9f1000 to 9a9ef400 0x1f0 bytes
+smm_module_setup_stub: stack_end = 0x9a000000
+smm_module_setup_stub: stack_top = 0x9a004000
+smm_module_setup_stub: stack_size = 0x800
+smm_module_setup_stub: runtime.start32_offset = 0x4c
+smm_module_setup_stub: runtime.smm_size = 0xa00000
+SMM Module: stub loaded at 0x9a9f1000. Will call 0x9a9f9c33
+Clearing SMI status registers
+SMI_STS: PM1 
+WAK PRBTNOR PWRBTN smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x9a9e9000, cpu = 0
+In relocation handler: CPU 0
+New SMBASE=0x9a9e9000 IEDBASE=0x9ac00000
+Writing SMRR. base = 0x9a000006, mask=0xff000800
+Relocation complete.
+smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x9a9e8800, cpu = 2
+In relocation handler: CPU 2
+New SMBASE=0x9a9e8800 IEDBASE=0x9ac00000
+Relocation complete.
+smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x9a9e8000, cpu = 4
+In relocation handler: CPU 4
+New SMBASE=0x9a9e8000 IEDBASE=0x9ac00000
+Writing SMRR. base = 0x9a000006, mask=0xff000800
+Relocation complete.
+smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x9a9e7c00, cpu = 5
+In relocation handler: CPU 5
+New SMBASE=0x9a9e7c00 IEDBASE=0x9ac00000
+Relocation complete.
+smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x9a9e8c00, cpu = 1
+In relocation handler: CPU 1
+New SMBASE=0x9a9e8c00 IEDBASE=0x9ac00000
+Relocation complete.
+smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x9a9e8400, cpu = 3
+In relocation handler: CPU 3
+New SMBASE=0x9a9e8400 IEDBASE=0x9ac00000
+Writing SMRR. base = 0x9a000006, mask=0xff000800
+Relocation complete.
+smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x9a9e7800, cpu = 6
+In relocation handler: CPU 6
+New SMBASE=0x9a9e7800 IEDBASE=0x9ac00000
+Writing SMRR. base = 0x9a000006, mask=0xff000800
+Relocation complete.
+smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x9a9e7400, cpu = 7
+In relocation handler: CPU 7
+New SMBASE=0x9a9e7400 IEDBASE=0x9ac00000
+Relocation complete.
+Initializing CPU #0
+CPU: vendor Intel device 806ec
+CPU: family 06, model 8e, stepping 0c
+Clearing out pending MCEs
+Setting up local APIC...
+ apic_id: 0x0 done.
+Turbo is available but hidden
+Turbo is available and visible
+VMX status: enabled
+IA32_FEATURE_CONTROL status: locked
+Skip microcode update
+CPU #0 initialized
+Initializing CPU #2
+Initializing CPU #1
+Initializing CPU #3
+CPU: vendor Intel device 806ec
+CPU: family 06, model 8e, stepping 0c
+CPU: vendor Intel device 806ec
+CPU: family 06, model 8e, stepping 0c
+Clearing out pending MCEs
+CPU: vendor Intel device 806ec
+CPU: family 06, model 8e, stepping 0c
+Initializing CPU #7
+Initializing CPU #6
+CPU: vendor Intel device 806ec
+CPU: family 06, model 8e, stepping 0c
+CPU: vendor Intel device 806ec
+CPU: family 06, model 8e, stepping 0c
+Clearing out pending MCEs
+Clearing out pending MCEs
+Clearing out pending MCEs
+Initializing CPU #5
+Initializing CPU #4
+CPU: vendor Intel device 806ec
+CPU: family 06, model 8e, stepping 0c
+CPU: vendor Intel device 806ec
+CPU: family 06, model 8e, stepping 0c
+Clearing out pending MCEs
+Clearing out pending MCEs
+Clearing out pending MCEs
+Setting up local APIC...
+Setting up local APIC...
+ apic_id: 0x3 done.
+Setting up local APIC...
+ apic_id: 0x1 done.
+Setting up local APIC...
+ apic_id: 0x5 done.
+ apic_id: 0x4 done.
+Setting up local APIC...
+Setting up local APIC...
+Setting up local APIC...
+ apic_id: 0x7 done.
+ apic_id: 0x2 done.
+VMX status: enabled
+ apic_id: 0x6 done.
+IA32_FEATURE_CONTROL status: locked
+VMX status: enabled
+VMX status: enabled
+Skip microcode update
+CPU #2 initialized
+IA32_FEATURE_CONTROL status: locked
+IA32_FEATURE_CONTROL status: locked
+Skip microcode update
+CPU #1 initialized
+Skip microcode update
+CPU #7 initialized
+VMX status: enabled
+VMX status: enabled
+VMX status: enabled
+IA32_FEATURE_CONTROL status: locked
+IA32_FEATURE_CONTROL status: locked
+IA32_FEATURE_CONTROL status: locked
+Skip microcode update
+CPU #3 initialized
+Skip microcode update
+CPU #6 initialized
+VMX status: enabled
+Skip microcode update
+CPU #5 initialized
+IA32_FEATURE_CONTROL status: locked
+Skip microcode update
+CPU #4 initialized
+bsp_do_flight_plan done after 1 msecs.
+CPU: frequency set to 4900 MHz
+Enabling SMIs.
+Locking SMM.
+BS: BS_DEV_INIT_CHIPS entry times (exec / console): 91 / 0 ms
+gpio_pad_reset_config_override: Logical to Chipset mapping not found
+CBFS: Found 'vbt.bin' @0xf9e00 size 0x499 in mcache @0x99b2d284
+FMAP: area COREBOOT found @ 650200 (10157568 bytes)
+TPM: Digest of FMAP: COREBOOT CBFS: vbt.bin to PCR 2 logged
+Found a VBT of 4608 bytes after decompression
+WEAK: src/soc/intel/cannonlake/fsp_params.c/mainboard_silicon_init_params called
+No CMOS option 'legacy_8254_timer'.
+VR config[0]:
+  Psi1Threshold:  80
+  Psi2Threshold:  20
+  Psi3Threshold:  4
+  Psi3Enable:     1
+  Psi4Enable:     1
+  ImonSlope:      0
+  ImonOffset:     0
+  VrVoltageLimit: 1520
+  IccMax:         24
+  AcLoadline:     1030
+  DcLoadline:     1030
+  TdcEnable:      1
+  TdcPowerLimit:  32
+VR config[1]:
+  Psi1Threshold:  80
+  Psi2Threshold:  20
+  Psi3Threshold:  4
+  Psi3Enable:     1
+  Psi4Enable:     1
+  ImonSlope:      0
+  ImonOffset:     0
+  VrVoltageLimit: 1520
+  IccMax:         280
+  AcLoadline:     180
+  DcLoadline:     180
+  TdcEnable:      1
+  TdcPowerLimit:  384
+VR config[2]:
+  Psi1Threshold:  80
+  Psi2Threshold:  20
+  Psi3Threshold:  4
+  Psi3Enable:     1
+  Psi4Enable:     1
+  ImonSlope:      0
+  ImonOffset:     0
+  VrVoltageLimit: 1520
+  IccMax:         124
+  AcLoadline:     310
+  DcLoadline:     310
+  TdcEnable:      1
+  TdcPowerLimit:  176
+VR config[3]:
+  Psi1Threshold:  80
+  Psi2Threshold:  20
+  Psi3Threshold:  4
+  Psi3Enable:     1
+  Psi4Enable:     1
+  ImonSlope:      0
+  ImonOffset:     0
+  VrVoltageLimit: 1520
+  IccMax:         124
+  AcLoadline:     310
+  DcLoadline:     310
+  TdcEnable:      1
+  TdcPowerLimit:  176
+PCI  1.0, PIN A, using IRQ #16
+PCI  1.1, PIN B, using IRQ #17
+PCI  1.2, PIN C, using IRQ #18
+PCI  2.0, PIN A, using IRQ #19
+PCI  4.0, PIN A, using IRQ #20
+PCI  5.0, PIN A, using IRQ #21
+PCI  8.0, PIN A, using IRQ #22
+PCI 12.0, PIN B, using IRQ #23
+PCI 12.5, PIN C, using IRQ #16
+PCI 12.6, PIN A, using IRQ #24
+PCI 13.0, PIN A, using IRQ #25
+PCI 14.0, PIN A, using IRQ #17
+PCI 14.1, PIN B, using IRQ #18
+PCI 14.3, PIN C, using IRQ #19
+PCI 14.5, PIN D, using IRQ #20
+PCI 15.0, PIN A, using IRQ #26
+PCI 15.1, PIN B, using IRQ #27
+PCI 15.2, PIN C, using IRQ #28
+PCI 15.3, PIN D, using IRQ #29
+PCI 16.0, PIN A, using IRQ #21
+PCI 16.1, PIN B, using IRQ #22
+PCI 16.2, PIN C, using IRQ #23
+PCI 16.3, PIN D, using IRQ #16
+PCI 16.4, PIN A, using IRQ #21
+PCI 16.5, PIN B, using IRQ #22
+PCI 17.0, PIN A, using IRQ #17
+PCI 19.0, PIN A, using IRQ #30
+PCI 19.1, PIN B, using IRQ #31
+PCI 19.2, PIN C, using IRQ #32
+PCI 1A.0, PIN A, using IRQ #18
+PCI 1C.0, PIN A, using IRQ #16
+PCI 1C.1, PIN B, using IRQ #17
+PCI 1C.2, PIN C, using IRQ #18
+PCI 1C.3, PIN D, using IRQ #19
+PCI 1C.4, PIN A, using IRQ #16
+PCI 1C.5, PIN B, using IRQ #17
+PCI 1C.6, PIN C, using IRQ #18
+PCI 1C.7, PIN D, using IRQ #19
+PCI 1D.0, PIN A, using IRQ #16
+PCI 1D.1, PIN B, using IRQ #17
+PCI 1D.2, PIN C, using IRQ #18
+PCI 1D.3, PIN D, using IRQ #19
+PCI 1D.4, PIN A, using IRQ #16
+PCI 1D.5, PIN B, using IRQ #17
+PCI 1D.6, PIN C, using IRQ #18
+PCI 1D.7, PIN D, using IRQ #19
+PCI 1E.0, PIN A, using IRQ #33
+PCI 1E.1, PIN B, using IRQ #34
+PCI 1E.2, PIN C, using IRQ #35
+PCI 1E.3, PIN D, using IRQ #36
+PCI 1F.3, PIN B, using IRQ #21
+PCI 1F.4, PIN C, using IRQ #22
+PCI 1F.6, PIN D, using IRQ #23
+PCI 1F.7, PIN A, using IRQ #20
+IRQ: Using dynamically assigned PCI IO-APIC IRQs
+FSPS returned 0
+Display FSP Version Info HOB
+Reference Code - CPU = 9.0.7b.20
+uCode Version = 0.0.0.ea
+TXT ACM version = ff.ff.ff.ffff
+Reference Code - ME = 9.0.7b.20
+MEBx version = 0.0.0.0
+ME Firmware Version = Consumer SKU
+Reference Code - CML PCH = 9.0.7b.20
+PCH-CRID Status = Disabled
+PCH-CRID Original Value = ff.ff.ff.ffff
+PCH-CRID New Value = ff.ff.ff.ffff
+OPROM - RST - RAID = ff.ff.ff.ffff
+ChipsetInit Base Version = ff.ff.ff.ffff
+ChipsetInit Oem Version = ff.ff.ff.ffff
+Reference Code - SA - System Agent = 9.0.7b.20
+Reference Code - MRC = 0.0.0.53
+SA - PCIe Version = 9.0.7b.20
+SA-CRID Status = Disabled
+SA-CRID Original Value = 0.0.0.c
+SA-CRID New Value = 0.0.0.c
+OPROM - VBIOS = ff.ff.ff.ffff
+Found PCIe Root Port #5 at PCI: 00:1c.0.
+Found PCIe Root Port #9 at PCI: 00:1d.0.
+Found PCIe Root Port #10 at PCI: 00:1d.1.
+Found PCIe Root Port #13 at PCI: 00:1d.4.
+pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
+Remapping PCIe Root Port #5 from PCI: 00:1c.4 to new function number 0.
+BS: BS_DEV_INIT_CHIPS run times (exec / console): 1250 / 0 ms
+Enumerating buses...
+Root Device scanning...
+CPU_CLUSTER: 0 enabled
+DOMAIN: 0000 enabled
+DOMAIN: 0000 scanning...
+PCI: pci_scan_bus for bus 00
+PCI: 00:00.0 [8086/9b61] enabled
+PCI: 00:02.0 [8086/9b41] enabled
+PCI: 00:04.0 [8086/1903] enabled
+PCI: 00:08.0 [8086/1911] enabled
+PCI: 00:12.0 [8086/02f9] enabled
+PCI: 00:14.0 [8086/02ed] enabled
+PCI: 00:14.2 [8086/02ef] enabled
+PCI: 00:14.3 [8086/02f0] enabled
+PCI: 00:15.0 [8086/02e8] enabled
+PCI: 00:16.0 [8086/02e0] disabled
+PCI: 00:17.0 [8086/02d3] enabled
+PCI: 00:19.0 [8086/02c5] disabled
+PCI: 00:19.2 [8086/02c7] enabled
+PCI: 00:1c.0 [8086/02bc] enabled
+PCI: 00:1d.0 [8086/02b0] enabled
+PCI: 00:1d.1 [8086/02b1] enabled
+PCI: 00:1d.4 [8086/02b4] enabled
+PCI: 00:1f.0 [8086/0284] enabled
+RTC Init
+Set power off after power failure.
+Disabling Deep S3
+Disabling Deep S3
+Disabling Deep S4
+Disabling Deep S4
+Disabling Deep S5
+Disabling Deep S5
+PCI: 00:1f.2 [0000/0000] hidden
+PCI: 00:1f.3 [8086/02c8] enabled
+PCI: 00:1f.4 [8086/02a3] enabled
+PCI: 00:1f.5 [8086/02a4] enabled
+PCI: Leftover static devices:
+PCI: 00:12.5
+PCI: 00:12.6
+PCI: 00:13.0
+PCI: 00:14.1
+PCI: 00:14.5
+PCI: 00:15.1
+PCI: 00:15.2
+PCI: 00:15.3
+PCI: 00:16.1
+PCI: 00:16.2
+PCI: 00:16.3
+PCI: 00:16.4
+PCI: 00:16.5
+PCI: 00:19.1
+PCI: 00:1a.0
+PCI: 00:1e.0
+PCI: 00:1e.1
+PCI: 00:1e.2
+PCI: 00:1e.3
+PCI: 00:1f.1
+PCI: 00:1f.6
+PCI: Check your devicetree.cb.
+PCI: 00:02.0 scanning...
+scan_bus: bus PCI: 00:02.0 finished in 0 msecs
+PCI: 00:14.0 scanning...
+scan_bus: bus PCI: 00:14.0 finished in 0 msecs
+PCI: 00:14.3 scanning...
+GENERIC: 0.0 enabled
+scan_bus: bus PCI: 00:14.3 finished in 0 msecs
+PCI: 00:15.0 scanning...
+PNP0C50 IRQ is not level triggered.
+ERROR: BUG ENCOUNTERED at file 'src/drivers/i2c/hid/hid.c', line 82
+I2C: 00:2c enabled
+scan_bus: bus PCI: 00:15.0 finished in 0 msecs
+PCI: 00:1c.0 scanning...
+PCI: pci_scan_bus for bus 01
+PCI: 01:00.0 subordinate bus PCI Express
+PCI: 01:00.0 [8086/15e7] enabled
+PCI: 01:00.0 scanning...
+PCI: pci_scan_bus for bus 02
+PCI: 02:00.0 subordinate bus PCI Express
+PCI: 02:00.0 [8086/15e7] enabled
+PCI: 02:01.0 subordinate bus PCI Express
+PCI: 02:01.0 hot-plug capable
+PCI: 02:01.0 [8086/15e7] enabled
+PCI: 02:02.0 subordinate bus PCI Express
+PCI: 02:02.0 [8086/15e7] enabled
+PCI: 02:00.0 scanning...
+PCI: pci_scan_bus for bus 03
+PCI: 03:00.0 [8086/15e8] enabled
+Enabling Common Clock Configuration
+ASPM: Enabled L1
+PCIe: Max_Payload_Size adjusted to 128
+scan_bus: bus PCI: 02:00.0 finished in 0 msecs
+PCI: 02:01.0 scanning...
+PCI: pci_scan_bus for bus 04
+scan_bus: bus PCI: 02:01.0 finished in 0 msecs
+PCI: 02:02.0 scanning...
+PCI: pci_scan_bus for bus 25
+PCI: 25:00.0 [8086/15e9] enabled
+Enabling Common Clock Configuration
+ASPM: Enabled L1
+PCIe: Max_Payload_Size adjusted to 128
+scan_bus: bus PCI: 02:02.0 finished in 0 msecs
+Enabling Common Clock Configuration
+PCIE CLK PM is not supported by endpoint
+ASPM: Enabled None
+PCIe: Max_Payload_Size adjusted to 128
+Enabling Common Clock Configuration
+PCIE CLK PM is not supported by endpoint
+ASPM: Enabled None
+PCIe: Max_Payload_Size adjusted to 128
+Enabling Common Clock Configuration
+PCIE CLK PM is not supported by endpoint
+ASPM: Enabled None
+PCIe: Max_Payload_Size adjusted to 128
+scan_bus: bus PCI: 01:00.0 finished in 0 msecs
+Enabling Common Clock Configuration
+L1 Sub-State supported from root port 28
+L1 Sub-State Support = 0xf
+CommonModeRestoreTime = 0x28
+Power On Value = 0x16, Power On Scale = 0x0
+ASPM: Enabled None
+PCIe: Max_Payload_Size adjusted to 128
+PCI: 01:00.0: Enabled LTR
+PCI: 01:00.0: Programmed LTR max latencies
+scan_bus: bus PCI: 00:1c.0 finished in 1 msecs
+PCI: 00:1d.0 scanning...
+PCI: pci_scan_bus for bus 26
+PCI: 26:00.0 [10ec/5287] enabled
+PCI: 26:00.1 [10ec/8168] enabled
+Enabling Common Clock Configuration
+L1 Sub-State supported from root port 29
+L1 Sub-State Support = 0xf
+CommonModeRestoreTime = 0x96
+Power On Value = 0xf, Power On Scale = 0x1
+ASPM: Enabled L1
+PCIe: Max_Payload_Size adjusted to 128
+PCI: 26:00.0: Enabled LTR
+PCI: 26:00.0: Programmed LTR max latencies
+Enabling Common Clock Configuration
+ASPM: Enabled L1
+PCIe: Max_Payload_Size adjusted to 128
+PCI: 26:00.1: Enabled LTR
+PCI: 26:00.1: Programmed LTR max latencies
+scan_bus: bus PCI: 00:1d.0 finished in 0 msecs
+PCI: 00:1d.1 scanning...
+PCI: 00:1d.1: No LTR support
+PCI: pci_scan_bus for bus 27
+scan_bus: bus PCI: 00:1d.1 finished in 0 msecs
+PCI: 00:1d.4 scanning...
+PCI: pci_scan_bus for bus 28
+PCI: 28:00.0 [144d/a808] enabled
+Enabling Common Clock Configuration
+L1 Sub-State supported from root port 29
+L1 Sub-State Support = 0xf
+CommonModeRestoreTime = 0x28
+Power On Value = 0x16, Power On Scale = 0x0
+ASPM: Enabled L1
+PCIe: Max_Payload_Size adjusted to 128
+PCI: 28:00.0: Enabled LTR
+PCI: 28:00.0: Programmed LTR max latencies
+scan_bus: bus PCI: 00:1d.4 finished in 0 msecs
+PCI: 00:1f.0 scanning...
+PNP: 0c31.0 enabled
+scan_bus: bus PCI: 00:1f.0 finished in 0 msecs
+PCI: 00:1f.2 scanning...
+scan_bus: bus PCI: 00:1f.2 finished in 0 msecs
+PCI: 00:1f.3 scanning...
+scan_bus: bus PCI: 00:1f.3 finished in 0 msecs
+PCI: 00:1f.4 scanning...
+scan_bus: bus PCI: 00:1f.4 finished in 0 msecs
+PCI: 00:1f.5 scanning...
+scan_bus: bus PCI: 00:1f.5 finished in 0 msecs
+scan_bus: bus DOMAIN: 0000 finished in 7 msecs
+scan_bus: bus Root Device finished in 7 msecs
+done
+BS: BS_DEV_ENUMERATE run times (exec / console): 7 / 0 ms
+MRC: Could not find region 'UNIFIED_MRC_CACHE'
+FMAP: area RW_MRC_CACHE found @ 600000 (65536 bytes)
+MRC: NOT enabling PRR for 'RW_MRC_CACHE'.
+found VGA at PCI: 00:02.0
+Setting up VGA for PCI: 00:02.0
+Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
+Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
+Allocating resources...
+Reading resources...
+Done reading resources.
+=== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
+   PCI: 02:00.0 io: size: 0 align: 12 gran: 12 limit: ffffffff
+   PCI: 02:00.0 io: size: 0 align: 12 gran: 12 limit: ffffffff done
+   PCI: 02:01.0 io: size: 0 align: 12 gran: 12 limit: ffffffff
+    NONE 18 *  [0x0 - 0x1fff] io
+   PCI: 02:01.0 io: size: 2000 align: 12 gran: 12 limit: ffff done
+   PCI: 02:02.0 io: size: 0 align: 12 gran: 12 limit: ffffffff
+   PCI: 02:02.0 io: size: 0 align: 12 gran: 12 limit: ffffffff done
+  PCI: 01:00.0 io: size: 0 align: 12 gran: 12 limit: ffffffff
+   PCI: 02:01.0 1c *  [0x0 - 0x1fff] io
+  PCI: 01:00.0 io: size: 2000 align: 12 gran: 12 limit: ffff done
+ PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
+  PCI: 01:00.0 1c *  [0x0 - 0x1fff] io
+ PCI: 00:1c.0 io: size: 2000 align: 12 gran: 12 limit: ffff done
+   PCI: 02:00.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
+    PCI: 03:00.0 10 *  [0x0 - 0x3ffff] mem
+    PCI: 03:00.0 14 *  [0x40000 - 0x40fff] mem
+   PCI: 02:00.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
+   PCI: 02:01.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
+    NONE 10 *  [0x0 - 0x1ffffff] mem
+   PCI: 02:01.0 mem: size: 2000000 align: 20 gran: 20 limit: ffffffff done
+   PCI: 02:02.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
+    PCI: 25:00.0 10 *  [0x0 - 0xffff] mem
+   PCI: 02:02.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
+  PCI: 01:00.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
+   PCI: 02:01.0 20 *  [0x0 - 0x1ffffff] mem
+   PCI: 02:00.0 20 *  [0x2000000 - 0x20fffff] mem
+   PCI: 02:02.0 20 *  [0x2100000 - 0x21fffff] mem
+  PCI: 01:00.0 mem: size: 2200000 align: 20 gran: 20 limit: ffffffff done
+ PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
+  PCI: 01:00.0 20 *  [0x0 - 0x21fffff] mem
+ PCI: 00:1c.0 mem: size: 2200000 align: 20 gran: 20 limit: ffffffff done
+   PCI: 02:00.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+   PCI: 02:00.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+   PCI: 02:01.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+    NONE 14 *  [0x0 - 0x1fffffff] prefmem
+   PCI: 02:01.0 prefmem: size: 20000000 align: 20 gran: 20 limit: ffffffffffffffff done
+   PCI: 02:02.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+   PCI: 02:02.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+  PCI: 01:00.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+   PCI: 02:01.0 24 *  [0x0 - 0x1fffffff] prefmem
+  PCI: 01:00.0 prefmem: size: 20000000 align: 20 gran: 20 limit: ffffffffffffffff done
+ PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+  PCI: 01:00.0 24 *  [0x0 - 0x1fffffff] prefmem
+ PCI: 00:1c.0 prefmem: size: 20000000 align: 20 gran: 20 limit: ffffffffffffffff done
+ PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
+  PCI: 26:00.1 10 *  [0x0 - 0xff] io
+ PCI: 00:1d.0 io: size: 1000 align: 12 gran: 12 limit: ffff done
+ PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
+  PCI: 26:00.0 30 *  [0x0 - 0xffff] mem
+  PCI: 26:00.1 20 *  [0x10000 - 0x13fff] mem
+  PCI: 26:00.0 10 *  [0x14000 - 0x14fff] mem
+  PCI: 26:00.1 18 *  [0x15000 - 0x15fff] mem
+ PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
+ PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+ PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+ PCI: 00:1d.4 io: size: 0 align: 12 gran: 12 limit: ffff
+ PCI: 00:1d.4 io: size: 0 align: 12 gran: 12 limit: ffff done
+ PCI: 00:1d.4 mem: size: 0 align: 20 gran: 20 limit: ffffffff
+  PCI: 28:00.0 10 *  [0x0 - 0x3fff] mem
+ PCI: 00:1d.4 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
+ PCI: 00:1d.4 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+ PCI: 00:1d.4 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+=== Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
+DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
+ update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
+ update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
+ update_constraints: PCI: 00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
+ DOMAIN: 0000: Resource ranges:
+ * Base: 1000, Size: 800, Tag: 100
+ * Base: 1900, Size: d6a0, Tag: 100
+ * Base: efc0, Size: 1040, Tag: 100
+  PCI: 00:1c.0 1c *  [0x2000 - 0x3fff] limit: 3fff io
+  PCI: 00:1d.0 1c *  [0x4000 - 0x4fff] limit: 4fff io
+  PCI: 00:02.0 20 *  [0x1000 - 0x103f] limit: 103f io
+  PCI: 00:17.0 20 *  [0x1040 - 0x105f] limit: 105f io
+  PCI: 00:17.0 18 *  [0x1060 - 0x1067] limit: 1067 io
+  PCI: 00:17.0 1c *  [0x1068 - 0x106b] limit: 106b io
+DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
+DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
+ update_constraints: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed)
+ update_constraints: PCI: 00:00.0 01 base fed10000 limit fed17fff mem (fixed)
+ update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
+ update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
+ update_constraints: PCI: 00:00.0 04 base fc000000 limit fc000fff mem (fixed)
+ update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
+ update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
+ update_constraints: PCI: 00:00.0 07 base fed91000 limit fed91fff mem (fixed)
+ update_constraints: PCI: 00:00.0 08 base 00000000 limit 0009ffff mem (fixed)
+ update_constraints: PCI: 00:00.0 09 base 000c0000 limit 99efffff mem (fixed)
+ update_constraints: PCI: 00:00.0 0a base 99f00000 limit 9f7fffff mem (fixed)
+ update_constraints: PCI: 00:00.0 0b base 100000000 limit 85e7fffff mem (fixed)
+ update_constraints: PCI: 00:00.0 0c base 000a0000 limit 000bffff mem (fixed)
+ update_constraints: PCI: 00:00.0 0d base 000c0000 limit 000fffff mem (fixed)
+ update_constraints: PCI: 00:19.2 10 base fe032000 limit fe032fff mem (fixed)
+ update_constraints: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed)
+ update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
+ DOMAIN: 0000: Resource ranges:
+ * Base: 9f800000, Size: 40800000, Tag: 200
+ * Base: f0000000, Size: c000000, Tag: 200
+ * Base: fc001000, Size: 1fff000, Tag: 200
+ * Base: fe010000, Size: 22000, Tag: 200
+ * Base: fe033000, Size: cdd000, Tag: 200
+ * Base: fed18000, Size: 28000, Tag: 200
+ * Base: fed45000, Size: 3b000, Tag: 200
+ * Base: fed84000, Size: c000, Tag: 200
+ * Base: fed92000, Size: e000, Tag: 200
+ * Base: feda2000, Size: 125e000, Tag: 200
+ * Base: 85e800000, Size: 77a1800000, Tag: 100200
+  PCI: 00:02.0 18 *  [0xa0000000 - 0xafffffff] limit: afffffff prefmem
+  PCI: 00:02.0 10 *  [0xb0000000 - 0xb0ffffff] limit: b0ffffff mem
+  PCI: 00:1c.0 24 *  [0xb1000000 - 0xd0ffffff] limit: d0ffffff prefmem
+  PCI: 00:1c.0 20 *  [0xd1000000 - 0xd31fffff] limit: d31fffff mem
+  PCI: 00:1d.0 20 *  [0x9f800000 - 0x9f8fffff] limit: 9f8fffff mem
+  PCI: 00:1d.4 20 *  [0x9f900000 - 0x9f9fffff] limit: 9f9fffff mem
+  PCI: 00:1f.3 20 *  [0x9fa00000 - 0x9fafffff] limit: 9fafffff mem
+  PCI: 00:14.0 10 *  [0x9fb00000 - 0x9fb0ffff] limit: 9fb0ffff mem
+  PCI: 00:04.0 10 *  [0x9fb10000 - 0x9fb17fff] limit: 9fb17fff mem
+  PCI: 00:14.3 10 *  [0x9fb18000 - 0x9fb1bfff] limit: 9fb1bfff mem
+  PCI: 00:1f.3 10 *  [0x9fb1c000 - 0x9fb1ffff] limit: 9fb1ffff mem
+  PCI: 00:14.2 10 *  [0x9fb20000 - 0x9fb21fff] limit: 9fb21fff mem
+  PCI: 00:17.0 10 *  [0x9fb22000 - 0x9fb23fff] limit: 9fb23fff mem
+  PCI: 00:08.0 10 *  [0x9fb24000 - 0x9fb24fff] limit: 9fb24fff mem
+  PCI: 00:12.0 10 *  [0x9fb25000 - 0x9fb25fff] limit: 9fb25fff mem
+  PCI: 00:14.2 18 *  [0x9fb26000 - 0x9fb26fff] limit: 9fb26fff mem
+  PCI: 00:15.0 10 *  [0x9fb27000 - 0x9fb27fff] limit: 9fb27fff mem
+  PCI: 00:19.2 18 *  [0x9fb28000 - 0x9fb28fff] limit: 9fb28fff mem
+  PCI: 00:1f.5 10 *  [0x9fb29000 - 0x9fb29fff] limit: 9fb29fff mem
+  PCI: 00:17.0 24 *  [0x9fb2a000 - 0x9fb2a7ff] limit: 9fb2a7ff mem
+  PCI: 00:17.0 14 *  [0x9fb2b000 - 0x9fb2b0ff] limit: 9fb2b0ff mem
+  PCI: 00:1f.4 10 *  [0x9fb2c000 - 0x9fb2c0ff] limit: 9fb2c0ff mem
+DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
+PCI: 00:1c.0 io: base: 2000 size: 2000 align: 12 gran: 12 limit: 3fff
+ PCI: 00:1c.0: Resource ranges:
+ * Base: 2000, Size: 2000, Tag: 100
+  PCI: 01:00.0 1c *  [0x2000 - 0x3fff] limit: 3fff io
+PCI: 00:1c.0 io: base: 2000 size: 2000 align: 12 gran: 12 limit: 3fff done
+PCI: 00:1c.0 prefmem: base: b1000000 size: 20000000 align: 20 gran: 20 limit: d0ffffff
+ PCI: 00:1c.0: Resource ranges:
+ * Base: b1000000, Size: 20000000, Tag: 1200
+  PCI: 01:00.0 24 *  [0xb1000000 - 0xd0ffffff] limit: d0ffffff prefmem
+PCI: 00:1c.0 prefmem: base: b1000000 size: 20000000 align: 20 gran: 20 limit: d0ffffff done
+PCI: 00:1c.0 mem: base: d1000000 size: 2200000 align: 20 gran: 20 limit: d31fffff
+ PCI: 00:1c.0: Resource ranges:
+ * Base: d1000000, Size: 2200000, Tag: 200
+  PCI: 01:00.0 20 *  [0xd1000000 - 0xd31fffff] limit: d31fffff mem
+PCI: 00:1c.0 mem: base: d1000000 size: 2200000 align: 20 gran: 20 limit: d31fffff done
+PCI: 01:00.0 io: base: 2000 size: 2000 align: 12 gran: 12 limit: 3fff
+ PCI: 01:00.0: Resource ranges:
+ * Base: 2000, Size: 2000, Tag: 100
+  PCI: 02:01.0 1c *  [0x2000 - 0x3fff] limit: 3fff io
+PCI: 01:00.0 io: base: 2000 size: 2000 align: 12 gran: 12 limit: 3fff done
+PCI: 01:00.0 prefmem: base: b1000000 size: 20000000 align: 20 gran: 20 limit: d0ffffff
+ PCI: 01:00.0: Resource ranges:
+ * Base: b1000000, Size: 20000000, Tag: 1200
+  PCI: 02:01.0 24 *  [0xb1000000 - 0xd0ffffff] limit: d0ffffff prefmem
+PCI: 01:00.0 prefmem: base: b1000000 size: 20000000 align: 20 gran: 20 limit: d0ffffff done
+PCI: 01:00.0 mem: base: d1000000 size: 2200000 align: 20 gran: 20 limit: d31fffff
+ PCI: 01:00.0: Resource ranges:
+ * Base: d1000000, Size: 2200000, Tag: 200
+  PCI: 02:01.0 20 *  [0xd1000000 - 0xd2ffffff] limit: d2ffffff mem
+  PCI: 02:00.0 20 *  [0xd3000000 - 0xd30fffff] limit: d30fffff mem
+  PCI: 02:02.0 20 *  [0xd3100000 - 0xd31fffff] limit: d31fffff mem
+PCI: 01:00.0 mem: base: d1000000 size: 2200000 align: 20 gran: 20 limit: d31fffff done
+PCI: 02:00.0 mem: base: d3000000 size: 100000 align: 20 gran: 20 limit: d30fffff
+ PCI: 02:00.0: Resource ranges:
+ * Base: d3000000, Size: 100000, Tag: 200
+  PCI: 03:00.0 10 *  [0xd3000000 - 0xd303ffff] limit: d303ffff mem
+  PCI: 03:00.0 14 *  [0xd3040000 - 0xd3040fff] limit: d3040fff mem
+PCI: 02:00.0 mem: base: d3000000 size: 100000 align: 20 gran: 20 limit: d30fffff done
+PCI: 02:01.0 io: base: 2000 size: 2000 align: 12 gran: 12 limit: 3fff
+ PCI: 02:01.0: Resource ranges:
+ * Base: 2000, Size: 2000, Tag: 100
+  NONE 18 *  [0x2000 - 0x3fff] limit: 3fff io
+PCI: 02:01.0 io: base: 2000 size: 2000 align: 12 gran: 12 limit: 3fff done
+PCI: 02:01.0 prefmem: base: b1000000 size: 20000000 align: 20 gran: 20 limit: d0ffffff
+ PCI: 02:01.0: Resource ranges:
+ * Base: b1000000, Size: 20000000, Tag: 1200
+  NONE 14 *  [0xb1000000 - 0xd0ffffff] limit: d0ffffff prefmem
+PCI: 02:01.0 prefmem: base: b1000000 size: 20000000 align: 20 gran: 20 limit: d0ffffff done
+PCI: 02:01.0 mem: base: d1000000 size: 2000000 align: 20 gran: 20 limit: d2ffffff
+ PCI: 02:01.0: Resource ranges:
+ * Base: d1000000, Size: 2000000, Tag: 200
+  NONE 10 *  [0xd1000000 - 0xd2ffffff] limit: d2ffffff mem
+PCI: 02:01.0 mem: base: d1000000 size: 2000000 align: 20 gran: 20 limit: d2ffffff done
+PCI: 02:02.0 mem: base: d3100000 size: 100000 align: 20 gran: 20 limit: d31fffff
+ PCI: 02:02.0: Resource ranges:
+ * Base: d3100000, Size: 100000, Tag: 200
+  PCI: 25:00.0 10 *  [0xd3100000 - 0xd310ffff] limit: d310ffff mem
+PCI: 02:02.0 mem: base: d3100000 size: 100000 align: 20 gran: 20 limit: d31fffff done
+PCI: 00:1d.0 io: base: 4000 size: 1000 align: 12 gran: 12 limit: 4fff
+ PCI: 00:1d.0: Resource ranges:
+ * Base: 4000, Size: 1000, Tag: 100
+  PCI: 26:00.1 10 *  [0x4000 - 0x40ff] limit: 40ff io
+PCI: 00:1d.0 io: base: 4000 size: 1000 align: 12 gran: 12 limit: 4fff done
+PCI: 00:1d.0 mem: base: 9f800000 size: 100000 align: 20 gran: 20 limit: 9f8fffff
+ PCI: 00:1d.0: Resource ranges:
+ * Base: 9f800000, Size: 100000, Tag: 200
+  PCI: 26:00.0 30 *  [0x9f800000 - 0x9f80ffff] limit: 9f80ffff mem
+  PCI: 26:00.1 20 *  [0x9f810000 - 0x9f813fff] limit: 9f813fff mem
+  PCI: 26:00.0 10 *  [0x9f814000 - 0x9f814fff] limit: 9f814fff mem
+  PCI: 26:00.1 18 *  [0x9f815000 - 0x9f815fff] limit: 9f815fff mem
+PCI: 00:1d.0 mem: base: 9f800000 size: 100000 align: 20 gran: 20 limit: 9f8fffff done
+PCI: 00:1d.4 mem: base: 9f900000 size: 100000 align: 20 gran: 20 limit: 9f9fffff
+ PCI: 00:1d.4: Resource ranges:
+ * Base: 9f900000, Size: 100000, Tag: 200
+  PCI: 28:00.0 10 *  [0x9f900000 - 0x9f903fff] limit: 9f903fff mem
+PCI: 00:1d.4 mem: base: 9f900000 size: 100000 align: 20 gran: 20 limit: 9f9fffff done
+=== Resource allocator: DOMAIN: 0000 - resource allocation complete ===
+PCI: 00:02.0 10 <- [0x00b0000000 - 0x00b0ffffff] size 0x01000000 gran 0x18 mem64
+PCI: 00:02.0 18 <- [0x00a0000000 - 0x00afffffff] size 0x10000000 gran 0x1c prefmem64
+PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
+PCI: 00:04.0 10 <- [0x009fb10000 - 0x009fb17fff] size 0x00008000 gran 0x0f mem64
+PCI: 00:08.0 10 <- [0x009fb24000 - 0x009fb24fff] size 0x00001000 gran 0x0c mem64
+PCI: 00:12.0 10 <- [0x009fb25000 - 0x009fb25fff] size 0x00001000 gran 0x0c mem64
+PCI: 00:14.0 10 <- [0x009fb00000 - 0x009fb0ffff] size 0x00010000 gran 0x10 mem64
+PCI: 00:14.2 10 <- [0x009fb20000 - 0x009fb21fff] size 0x00002000 gran 0x0d mem64
+PCI: 00:14.2 18 <- [0x009fb26000 - 0x009fb26fff] size 0x00001000 gran 0x0c mem64
+PCI: 00:14.3 10 <- [0x009fb18000 - 0x009fb1bfff] size 0x00004000 gran 0x0e mem64
+PCI: 00:15.0 10 <- [0x009fb27000 - 0x009fb27fff] size 0x00001000 gran 0x0c mem64
+PCI: 00:17.0 10 <- [0x009fb22000 - 0x009fb23fff] size 0x00002000 gran 0x0d mem
+PCI: 00:17.0 14 <- [0x009fb2b000 - 0x009fb2b0ff] size 0x00000100 gran 0x08 mem
+PCI: 00:17.0 18 <- [0x0000001060 - 0x0000001067] size 0x00000008 gran 0x03 io
+PCI: 00:17.0 1c <- [0x0000001068 - 0x000000106b] size 0x00000004 gran 0x02 io
+PCI: 00:17.0 20 <- [0x0000001040 - 0x000000105f] size 0x00000020 gran 0x05 io
+PCI: 00:17.0 24 <- [0x009fb2a000 - 0x009fb2a7ff] size 0x00000800 gran 0x0b mem
+PCI: 00:19.2 18 <- [0x009fb28000 - 0x009fb28fff] size 0x00001000 gran 0x0c mem64
+PCI: 00:1c.0 1c <- [0x0000002000 - 0x0000003fff] size 0x00002000 gran 0x0c bus 01 io
+PCI: 00:1c.0 24 <- [0x00b1000000 - 0x00d0ffffff] size 0x20000000 gran 0x14 bus 01 prefmem
+PCI: 00:1c.0 20 <- [0x00d1000000 - 0x00d31fffff] size 0x02200000 gran 0x14 bus 01 mem
+PCI: 01:00.0 1c <- [0x0000002000 - 0x0000003fff] size 0x00002000 gran 0x0c bus 02 io
+PCI: 01:00.0 24 <- [0x00b1000000 - 0x00d0ffffff] size 0x20000000 gran 0x14 bus 02 prefmem
+PCI: 01:00.0 20 <- [0x00d1000000 - 0x00d31fffff] size 0x02200000 gran 0x14 bus 02 mem
+PCI: 02:00.0 1c <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x0c bus 03 io
+PCI: 02:00.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 03 prefmem
+PCI: 02:00.0 20 <- [0x00d3000000 - 0x00d30fffff] size 0x00100000 gran 0x14 bus 03 mem
+PCI: 03:00.0 10 <- [0x00d3000000 - 0x00d303ffff] size 0x00040000 gran 0x12 mem
+PCI: 03:00.0 14 <- [0x00d3040000 - 0x00d3040fff] size 0x00001000 gran 0x0c mem
+PCI: 02:01.0 1c <- [0x0000002000 - 0x0000003fff] size 0x00002000 gran 0x0c bus 04 io
+PCI: 02:01.0 24 <- [0x00b1000000 - 0x00d0ffffff] size 0x20000000 gran 0x14 bus 04 prefmem
+PCI: 02:01.0 20 <- [0x00d1000000 - 0x00d2ffffff] size 0x02000000 gran 0x14 bus 04 mem
+NONE missing set_resources
+PCI: 02:02.0 1c <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x0c bus 25 io
+PCI: 02:02.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 25 prefmem
+PCI: 02:02.0 20 <- [0x00d3100000 - 0x00d31fffff] size 0x00100000 gran 0x14 bus 25 mem
+PCI: 25:00.0 10 <- [0x00d3100000 - 0x00d310ffff] size 0x00010000 gran 0x10 mem
+PCI: 00:1d.0 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 26 io
+PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 26 prefmem
+PCI: 00:1d.0 20 <- [0x009f800000 - 0x009f8fffff] size 0x00100000 gran 0x14 bus 26 mem
+PCI: 26:00.0 10 <- [0x009f814000 - 0x009f814fff] size 0x00001000 gran 0x0c mem
+PCI: 26:00.0 30 <- [0x009f800000 - 0x009f80ffff] size 0x00010000 gran 0x10 romem
+PCI: 26:00.1 10 <- [0x0000004000 - 0x00000040ff] size 0x00000100 gran 0x08 io
+PCI: 26:00.1 18 <- [0x009f815000 - 0x009f815fff] size 0x00001000 gran 0x0c mem64
+PCI: 26:00.1 20 <- [0x009f810000 - 0x009f813fff] size 0x00004000 gran 0x0e mem64
+PCI: 00:1d.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 27 io
+PCI: 00:1d.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 27 prefmem
+PCI: 00:1d.1 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 27 mem
+PCI: 00:1d.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 28 io
+PCI: 00:1d.4 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 28 prefmem
+PCI: 00:1d.4 20 <- [0x009f900000 - 0x009f9fffff] size 0x00100000 gran 0x14 bus 28 mem
+PCI: 28:00.0 10 <- [0x009f900000 - 0x009f903fff] size 0x00004000 gran 0x0e mem64
+PCI: 00:1f.3 10 <- [0x009fb1c000 - 0x009fb1ffff] size 0x00004000 gran 0x0e mem64
+PCI: 00:1f.3 20 <- [0x009fa00000 - 0x009fafffff] size 0x00100000 gran 0x14 mem64
+PCI: 00:1f.4 10 <- [0x009fb2c000 - 0x009fb2c0ff] size 0x00000100 gran 0x08 mem64
+PCI: 00:1f.5 10 <- [0x009fb29000 - 0x009fb29fff] size 0x00001000 gran 0x0c mem
+Done setting resources.
+Done allocating resources.
+BS: BS_DEV_RESOURCES run times (exec / console): 2 / 0 ms
+Enabling resources...
+PCI: 00:00.0 subsystem <- 1558/1404
+PCI: 00:00.0 cmd <- 06
+PCI: 00:02.0 subsystem <- 1558/1404
+PCI: 00:02.0 cmd <- 03
+PCI: 00:04.0 subsystem <- 1558/1404
+PCI: 00:04.0 cmd <- 02
+PCI: 00:08.0 cmd <- 06
+PCI: 00:12.0 subsystem <- 1558/1404
+PCI: 00:12.0 cmd <- 02
+PCI: 00:14.0 subsystem <- 1558/1404
+PCI: 00:14.0 cmd <- 02
+PCI: 00:14.2 cmd <- 02
+PCI: 00:14.3 subsystem <- 1558/1404
+PCI: 00:14.3 cmd <- 02
+PCI: 00:15.0 subsystem <- 1558/1404
+PCI: 00:15.0 cmd <- 02
+PCI: 00:17.0 subsystem <- 1558/1404
+PCI: 00:17.0 cmd <- 03
+PCI: 00:19.2 subsystem <- 1558/1404
+PCI: 00:19.2 cmd <- 06
+PCI: 00:1c.0 bridge ctrl <- 0013
+PCI: 00:1c.0 subsystem <- 1558/1404
+PCI: 00:1c.0 cmd <- 07
+PCI: 00:1d.0 bridge ctrl <- 0013
+PCI: 00:1d.0 subsystem <- 1558/1404
+PCI: 00:1d.0 cmd <- 07
+PCI: 00:1d.1 bridge ctrl <- 0013
+PCI: 00:1d.1 subsystem <- 1558/1404
+PCI: 00:1d.1 cmd <- 00
+PCI: 00:1d.4 bridge ctrl <- 0013
+PCI: 00:1d.4 subsystem <- 1558/1404
+PCI: 00:1d.4 cmd <- 06
+PCI: 00:1f.0 subsystem <- 1558/1404
+PCI: 00:1f.0 cmd <- 07
+PCI: 00:1f.3 subsystem <- 1558/1404
+PCI: 00:1f.3 cmd <- 02
+PCI: 00:1f.4 subsystem <- 1558/1404
+PCI: 00:1f.4 cmd <- 03
+PCI: 00:1f.5 subsystem <- 1558/1404
+PCI: 00:1f.5 cmd <- 406
+PCI: 01:00.0 bridge ctrl <- 0013
+PCI: 01:00.0 cmd <- 07
+PCI: 02:00.0 bridge ctrl <- 0013
+PCI: 02:00.0 cmd <- 06
+PCI: 02:01.0 bridge ctrl <- 0013
+PCI: 02:01.0 cmd <- 07
+PCI: 02:02.0 bridge ctrl <- 0013
+PCI: 02:02.0 cmd <- 06
+PCI: 03:00.0 cmd <- 06
+PCI: 25:00.0 cmd <- 02
+PCI: 26:00.0 cmd <- 02
+PCI: 26:00.1 cmd <- 03
+PCI: 28:00.0 cmd <- 02
+done.
+Found TPM SLB9670 TT 2.0 by Infineon
+tlcl_send_startup: Startup return code is 0
+TPM: Write digests cached in TCPA log to PCR
+TPM: Write digest for FMAP: FMAP into PCR 2
+tlcl_extend: response is 0
+TPM: Write digest for FMAP: COREBOOT CBFS: bootblock into PCR 2
+tlcl_extend: response is 0
+TPM: Write digest for FMAP: COREBOOT CBFS: cmos.default into PCR 2
+tlcl_extend: response is 0
+TPM: Write digest for FMAP: COREBOOT CBFS: fallback/romstage into PCR 2
+tlcl_extend: response is 0
+TPM: Write digest for FMAP: COREBOOT CBFS: cmos_layout.bin into PCR 2
+tlcl_extend: response is 0
+TPM: Write digest for FMAP: COREBOOT CBFS: fspm.bin into PCR 2
+tlcl_extend: response is 0
+TPM: Write digest for FMAP: COREBOOT CBFS: fallback/postcar into PCR 2
+tlcl_extend: response is 0
+TPM: Write digest for FMAP: COREBOOT CBFS: fallback/ramstage into PCR 2
+tlcl_extend: response is 0
+TPM: Write digest for FMAP: COREBOOT CBFS: cpu_microcode_blob.bin into PCR 2
+tlcl_extend: response is 0
+TPM: Write digest for FMAP: COREBOOT CBFS: fsps.bin into PCR 2
+tlcl_extend: response is 0
+TPM: Write digest for FMAP: COREBOOT CBFS: vbt.bin into PCR 2
+tlcl_extend: response is 0
+TPM: setup succeeded
+BS: BS_DEV_INIT entry times (exec / console): 39 / 0 ms
+Initializing devices...
+PCI: 00:00.0 init
+CPU TDP = 15 Watts
+CPU PL1 = 20 Watts
+CPU PL2 = 30 Watts
+PCI: 00:00.0 init finished in 1 msecs
+PCI: 00:02.0 init
+GMA: Found VBT in CBFS
+GMA: Found valid VBT in CBFS
+framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
+                   x_res x y_res: 1920 x 1080, size: 8294400 at 0xa0000000
+PCI: 00:02.0 init finished in 0 msecs
+PCI: 00:04.0 init
+PCI: 00:04.0 init finished in 0 msecs
+PCI: 00:08.0 init
+PCI: 00:08.0 init finished in 0 msecs
+PCI: 00:12.0 init
+PCI: 00:12.0 init finished in 0 msecs
+PCI: 00:14.0 init
+PCI: 00:14.0 init finished in 0 msecs
+PCI: 00:14.2 init
+PCI: 00:14.2 init finished in 0 msecs
+PCI: 00:15.0 init
+I2C bus 0 version 0x3132322a
+DW I2C bus 0 at 0x9fb27000 (400 KHz)
+PCI: 00:15.0 init finished in 0 msecs
+PCI: 00:1c.0 init
+Initializing PCH PCIe bridge.
+PCI: 00:1c.0 init finished in 0 msecs
+PCI: 00:1d.0 init
+Initializing PCH PCIe bridge.
+PCI: 00:1d.0 init finished in 0 msecs
+PCI: 00:1d.1 init
+Initializing PCH PCIe bridge.
+PCI: 00:1d.1 init finished in 0 msecs
+PCI: 00:1d.4 init
+Initializing PCH PCIe bridge.
+PCI: 00:1d.4 init finished in 0 msecs
+PCI: 00:1f.0 init
+IOAPIC: Initializing IOAPIC at 0xfec00000
+IOAPIC: ID = 0x02
+PCI: 00:1f.0 init finished in 0 msecs
+PCI: 00:1f.2 init
+apm_control: Disabling ACPI.
+APMC done.
+PCI: 00:1f.2 init finished in 0 msecs
+PCI: 00:1f.3 init
+azalia_audio: base = 0x9fb1c000
+azalia_audio: codec_mask = 05
+azalia_audio: Initializing codec #2
+azalia_audio: codec viddid: 8086280b
+azalia_audio: verb_size: 16
+azalia_audio: verb loaded.
+azalia_audio: Initializing codec #0
+azalia_audio: codec viddid: 10ec0293
+azalia_audio: verb_size: 48
+azalia_audio: verb loaded.
+PCI: 00:1f.3 init finished in 6 msecs
+PCI: 00:1f.4 init
+PCI: 00:1f.4 init finished in 0 msecs
+PCI: 03:00.0 init
+PCI: 03:00.0 init finished in 0 msecs
+PCI: 25:00.0 init
+PCI: 25:00.0 init finished in 0 msecs
+PCI: 26:00.0 init
+PCI: 26:00.0 init finished in 0 msecs
+PCI: 26:00.1 init
+PCI: 26:00.1 init finished in 0 msecs
+PCI: 28:00.0 init
+PCI: 28:00.0 init finished in 0 msecs
+Devices initialized
+BS: BS_DEV_INIT run times (exec / console): 8 / 0 ms
+Finalize devices...
+PCI: 00:17.0 final
+Devices finalized
+HECI: No CSE device
+CBFS: Found 'fallback/dsdt.aml' @0x68700 size 0x34cd in mcache @0x99b2d1f0
+FMAP: area COREBOOT found @ 650200 (10157568 bytes)
+TPM: Extending digest for FMAP: COREBOOT CBFS: fallback/dsdt.aml into PCR 2
+tlcl_extend: response is 0
+TPM: Digest of FMAP: COREBOOT CBFS: fallback/dsdt.aml to PCR 2 measured
+CBFS: 'fallback/slic' not found.
+ACPI: Writing ACPI tables at 99a4b000.
+ACPI:    * FACS
+ACPI:    * DSDT
+PCI space above 4GB MMIO is at 0x85e800000, len = 0x77a1800000
+ACPI:    * FADT
+SCI is IRQ9
+ACPI: added table 1/32, length now 40
+ACPI:     * SSDT
+Found 1 CPU(s) with 4/8 physical/logical core(s) each.
+PSS: 1801MHz power 15000 control 0x3100 status 0x3100
+PSS: 1800MHz power 15000 control 0x1200 status 0x1200
+PSS: 1600MHz power 13013 control 0x1000 status 0x1000
+PSS: 1300MHz power 10212 control 0xd00 status 0xd00
+PSS: 1000MHz power 7584 control 0xa00 status 0xa00
+PSS: 700MHz power 5109 control 0x700 status 0x700
+PSS: 400MHz power 2820 control 0x400 status 0x400
+PSS: 1801MHz power 15000 control 0x3100 status 0x3100
+PSS: 1800MHz power 15000 control 0x1200 status 0x1200
+PSS: 1600MHz power 13013 control 0x1000 status 0x1000
+PSS: 1300MHz power 10212 control 0xd00 status 0xd00
+PSS: 1000MHz power 7584 control 0xa00 status 0xa00
+PSS: 700MHz power 5109 control 0x700 status 0x700
+PSS: 400MHz power 2820 control 0x400 status 0x400
+PSS: 1801MHz power 15000 control 0x3100 status 0x3100
+PSS: 1800MHz power 15000 control 0x1200 status 0x1200
+PSS: 1600MHz power 13013 control 0x1000 status 0x1000
+PSS: 1300MHz power 10212 control 0xd00 status 0xd00
+PSS: 1000MHz power 7584 control 0xa00 status 0xa00
+PSS: 700MHz power 5109 control 0x700 status 0x700
+PSS: 400MHz power 2820 control 0x400 status 0x400
+PSS: 1801MHz power 15000 control 0x3100 status 0x3100
+PSS: 1800MHz power 15000 control 0x1200 status 0x1200
+PSS: 1600MHz power 13013 control 0x1000 status 0x1000
+PSS: 1300MHz power 10212 control 0xd00 status 0xd00
+PSS: 1000MHz power 7584 control 0xa00 status 0xa00
+PSS: 700MHz power 5109 control 0x700 status 0x700
+PSS: 400MHz power 2820 control 0x400 status 0x400
+PSS: 1801MHz power 15000 control 0x3100 status 0x3100
+PSS: 1800MHz power 15000 control 0x1200 status 0x1200
+PSS: 1600MHz power 13013 control 0x1000 status 0x1000
+PSS: 1300MHz power 10212 control 0xd00 status 0xd00
+PSS: 1000MHz power 7584 control 0xa00 status 0xa00
+PSS: 700MHz power 5109 control 0x700 status 0x700
+PSS: 400MHz power 2820 control 0x400 status 0x400
+PSS: 1801MHz power 15000 control 0x3100 status 0x3100
+PSS: 1800MHz power 15000 control 0x1200 status 0x1200
+PSS: 1600MHz power 13013 control 0x1000 status 0x1000
+PSS: 1300MHz power 10212 control 0xd00 status 0xd00
+PSS: 1000MHz power 7584 control 0xa00 status 0xa00
+PSS: 700MHz power 5109 control 0x700 status 0x700
+PSS: 400MHz power 2820 control 0x400 status 0x400
+PSS: 1801MHz power 15000 control 0x3100 status 0x3100
+PSS: 1800MHz power 15000 control 0x1200 status 0x1200
+PSS: 1600MHz power 13013 control 0x1000 status 0x1000
+PSS: 1300MHz power 10212 control 0xd00 status 0xd00
+PSS: 1000MHz power 7584 control 0xa00 status 0xa00
+PSS: 700MHz power 5109 control 0x700 status 0x700
+PSS: 400MHz power 2820 control 0x400 status 0x400
+PSS: 1801MHz power 15000 control 0x3100 status 0x3100
+PSS: 1800MHz power 15000 control 0x1200 status 0x1200
+PSS: 1600MHz power 13013 control 0x1000 status 0x1000
+PSS: 1300MHz power 10212 control 0xd00 status 0xd00
+PSS: 1000MHz power 7584 control 0xa00 status 0xa00
+PSS: 700MHz power 5109 control 0x700 status 0x700
+PSS: 400MHz power 2820 control 0x400 status 0x400
+\_SB.PCI0.PEPD: Intel Power Engine Plug-in
+\_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
+\_SB.PCI0.I2C0.H02C: Synaptics Touchpad at I2C: 00:2c
+\_SB.PCI0.LPCB.TPM.TPM: LPC TPM PNP: 0c31.0
+ACPI: added table 2/32, length now 44
+ACPI:    * MCFG
+ACPI: added table 3/32, length now 48
+ACPI:    * TPM2
+TPM2 log created at 0x99a3b000
+ACPI: added table 4/32, length now 52
+ACPI:     * LPIT
+ACPI: added table 5/32, length now 56
+ACPI:    * MADT
+SCI is IRQ9
+ACPI: added table 6/32, length now 60
+current = 99a508f0
+ACPI:    * DMAR
+ACPI: added table 7/32, length now 64
+ACPI: added table 8/32, length now 68
+ACPI:    * HPET
+ACPI: added table 9/32, length now 72
+ACPI: done.
+ACPI tables: 23072 bytes.
+smbios_write_tables: 99a3a000
+SMBIOS firmware version is set to coreboot_version: '4.14-2062-ge54b508db8'
+Create SMBIOS type 16
+Create SMBIOS type 17
+GENERIC: 0.0 (WIFI Device)
+SMBIOS tables: 963 bytes.
+Writing table forward entry at 0x00000500
+Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 7637
+Writing coreboot table at 0x99a6f000
+CBFS: Found 'cmos_layout.bin' @0xfa300 size 0x288 in mcache @0x99b2d2b4
+FMAP: area COREBOOT found @ 650200 (10157568 bytes)
+TPM: Extending digest for FMAP: COREBOOT CBFS: cmos_layout.bin into PCR 2
+tlcl_extend: response is 0
+TPM: Digest of FMAP: COREBOOT CBFS: cmos_layout.bin to PCR 2 measured
+ 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
+ 1. 0000000000001000-000000000009ffff: RAM
+ 2. 00000000000a0000-00000000000fffff: RESERVED
+ 3. 0000000000100000-0000000099a39fff: RAM
+ 4. 0000000099a3a000-0000000099abdfff: CONFIGURATION TABLES
+ 5. 0000000099abe000-0000000099b1cfff: RAMSTAGE
+ 6. 0000000099b1d000-0000000099efffff: CONFIGURATION TABLES
+ 7. 0000000099f00000-000000009f7fffff: RESERVED
+ 8. 00000000e0000000-00000000efffffff: RESERVED
+ 9. 00000000fc000000-00000000fc000fff: RESERVED
+10. 00000000fe000000-00000000fe00ffff: RESERVED
+11. 00000000fed10000-00000000fed17fff: RESERVED
+12. 00000000fed40000-00000000fed44fff: RESERVED
+13. 00000000fed80000-00000000fed83fff: RESERVED
+14. 00000000fed90000-00000000fed91fff: RESERVED
+15. 00000000feda0000-00000000feda1fff: RESERVED
+16. 0000000100000000-000000085e7fffff: RAM
+Setting up bootsplash in 1920x1080@32
+CBFS: Found 'bootsplash.jpg' @0x5c400 size 0xc2d1 in mcache @0x99b2d1c8
+FMAP: area COREBOOT found @ 650200 (10157568 bytes)
+TPM: Extending digest for FMAP: COREBOOT CBFS: bootsplash.jpg into PCR 2
+tlcl_extend: response is 0
+TPM: Digest of FMAP: COREBOOT CBFS: bootsplash.jpg to PCR 2 measured
+Bootsplash image resolution: 1920x1080
+Bootsplash could not be decoded. jpeg_decode returned 3.
+SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
+Wrote coreboot table at: 0x99a6f000, 0x76c bytes, checksum 2126
+coreboot table: 1924 bytes.
+IMD ROOT    0. 0x99eff000 0x00001000
+IMD SMALL   1. 0x99efe000 0x00001000
+FSP MEMORY  2. 0x99b4e000 0x003b0000
+CONSOLE     3. 0x99b2e000 0x00020000
+RO MCACHE   4. 0x99b2d000 0x000003d0
+TIME STAMP  5. 0x99b2c000 0x00000910
+TCPA LOG    6. 0x99b2a000 0x000019cc
+ROMSTG STCK 7. 0x99b29000 0x00001000
+AFTER CAR   8. 0x99b1d000 0x0000c000
+RAMSTAGE    9. 0x99abd000 0x00060000
+REFCODE    10. 0x99a89000 0x00034000
+SMM BACKUP 11. 0x99a79000 0x00010000
+4f444749   12. 0x99a77000 0x00002000
+COREBOOT   13. 0x99a6f000 0x00008000
+ACPI       14. 0x99a4b000 0x00024000
+TPM2 TCGLOG15. 0x99a3b000 0x00010000
+SMBIOS     16. 0x99a3a000 0x00000800
+IMD small region:
+  IMD ROOT    0. 0x99efec00 0x00000400
+  FSP RUNTIME 1. 0x99efebe0 0x00000004
+  FMAP        2. 0x99efeac0 0x0000010a
+  POWER STATE 3. 0x99efea80 0x00000040
+  ROMSTAGE    4. 0x99efea60 0x00000004
+  MEM INFO    5. 0x99efe880 0x000001e0
+  ACPI GNVS   6. 0x99efe820 0x00000048
+BS: BS_WRITE_TABLES run times (exec / console): 16 / 0 ms
+MTRR: Physical address space:
+0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
+0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
+0x00000000000c0000 - 0x0000000099f00000 size 0x99e40000 type 6
+0x0000000099f00000 - 0x00000000a0000000 size 0x06100000 type 0
+0x00000000a0000000 - 0x00000000b0000000 size 0x10000000 type 1
+0x00000000b0000000 - 0x0000000100000000 size 0x50000000 type 0
+0x0000000100000000 - 0x000000085e800000 size 0x75e800000 type 6
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+CPU physical address size: 39 bits
+MTRR: default type WB/UC MTRR counts: 6/10.
+MTRR: WB selected as default type.
+MTRR: 0 base 0x0000000099f00000 mask 0x0000007ffff00000 type 0
+MTRR: 1 base 0x000000009a000000 mask 0x0000007ffe000000 type 0
+MTRR: 2 base 0x000000009c000000 mask 0x0000007ffc000000 type 0
+MTRR: 3 base 0x00000000a0000000 mask 0x0000007ff0000000 type 1
+MTRR: 4 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0
+MTRR: 5 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+
+MTRR check
+Fixed MTRRs   : Enabled
+Variable MTRRs: Enabled
+
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+BS: BS_WRITE_TABLES exit times (exec / console): 1 / 0 ms
+CBFS: Found 'fallback/payload' @0x130340 size 0x53862c in mcache @0x99b2d360
+FMAP: area COREBOOT found @ 650200 (10157568 bytes)
+CPU physical address size: 39 bits
+CPU physical address size: 39 bits
+CPU physical address size: 39 bits
+CPU physical address size: 39 bits
+CPU physical address size: 39 bits
+CPU physical address size: 39 bits
+CPU physical address size: 39 bits
+TPM: Extending digest for FMAP: COREBOOT CBFS: fallback/payload into PCR 2
+tlcl_extend: response is 0
+TPM: Digest of FMAP: COREBOOT CBFS: fallback/payload to PCR 2 measured
+Checking segment from ROM address 0xff78056c
+Checking segment from ROM address 0xff780588
+Checking segment from ROM address 0xff7805a4
+Checking segment from ROM address 0xff7805c0
+Checking segment from ROM address 0xff7805dc
+Loading segment from ROM address 0xff78056c
+  data (compression=0)
+  New segment dstaddr 0x00090000 memsize 0x1080 srcaddr 0xff7805f8 filesize 0x1080
+Loading Segment: addr: 0x00090000 memsz: 0x0000000000001080 filesz: 0x0000000000001080
+it's not compressed!
+Loading segment from ROM address 0xff780588
+  code (compression=0)
+  New segment dstaddr 0x01000000 memsize 0x250a20 srcaddr 0xff781678 filesize 0x250a20
+Loading Segment: addr: 0x01000000 memsz: 0x0000000000250a20 filesz: 0x0000000000250a20
+it's not compressed!
+Loading segment from ROM address 0xff7805a4
+  code (compression=0)
+  New segment dstaddr 0x00040000 memsize 0xd4 srcaddr 0xff9d2098 filesize 0xd4
+Loading Segment: addr: 0x00040000 memsz: 0x00000000000000d4 filesz: 0x00000000000000d4
+it's not compressed!
+Loading segment from ROM address 0xff7805c0
+  data (compression=0)
+  New segment dstaddr 0x04000000 memsize 0x2e6a2c srcaddr 0xff9d216c filesize 0x2e6a2c
+Loading Segment: addr: 0x04000000 memsz: 0x00000000002e6a2c filesz: 0x00000000002e6a2c
+it's not compressed!
+Loading segment from ROM address 0xff7805dc
+  Entry Point 0x00040000
+BS: BS_PAYLOAD_LOAD run times (exec / console): 3620 / 0 ms
+Finalizing chipset.
+apm_control: Finalizing SMM.
+APMC done.
+BS: BS_PAYLOAD_LOAD exit times (exec / console): 4 / 0 ms
+coreboot TCPA measurements:
+
+ PCR-2 0f5a3c7890d93c797c73042205984351199a8064e8e985a5b551a1e78939299e SHA256 [FMAP: FMAP]
+ PCR-2 c291a598d0453d3fa5a45d2241d76a81c0826d6e5a9299e5da52785078c73c9d SHA256 [FMAP: COREBOOT CBFS: bootblock]
+ PCR-2 6f662f79fff2bc42c6c283f717772448a778ae8b9b34eb864e26e2e9b70bdd93 SHA256 [FMAP: COREBOOT CBFS: cmos.default]
+ PCR-2 d57e8a29104f15f1087d1d0858d91d0866ee89d4a5e785bb7b785192c66207d4 SHA256 [FMAP: COREBOOT CBFS: fallback/romstage]
+ PCR-2 0a2d102a5cab92ac378b80856811c0569da20a1708560aba938926cc44f21416 SHA256 [FMAP: COREBOOT CBFS: cmos_layout.bin]
+ PCR-2 0a083bfc5589d3e7304848b2132134fb9fb385bbcf10fa9df5e646701f7ad9a3 SHA256 [FMAP: COREBOOT CBFS: fspm.bin]
+ PCR-2 1ccc0cc7fe8e3f590d2fe6d1f0ca622df3baca068ec8528ebb3ecda38435d85e SHA256 [FMAP: COREBOOT CBFS: fallback/postcar]
+ PCR-2 07d84b724c7aa8834615b0f60e003c13dde528b3349605c3a6fc7bc5d42b2486 SHA256 [FMAP: COREBOOT CBFS: fallback/ramstage]
+ PCR-2 57c0c4da1f71de4a9135461f082ecd0b60a1eb62fbfe5a59627c009f2b633625 SHA256 [FMAP: COREBOOT CBFS: cpu_microcode_blob.bin]
+ PCR-2 5748885bffbf7b859e4d2b251751b88b9be953cffae99d1c2c1fbd77df86797b SHA256 [FMAP: COREBOOT CBFS: fsps.bin]
+ PCR-2 a45fceed6d7abeb8115604cd5511c6273109d78af22b807a2994a244b2a50499 SHA256 [FMAP: COREBOOT CBFS: vbt.bin]
+ PCR-2 8ed558edb4859346fc69b7db399fd58c1dbe63b2b8c5ed53932ff6617fba459f SHA256 [FMAP: COREBOOT CBFS: fallback/dsdt.aml]
+ PCR-2 0a2d102a5cab92ac378b80856811c0569da20a1708560aba938926cc44f21416 SHA256 [FMAP: COREBOOT CBFS: cmos_layout.bin]
+ PCR-2 a5dcb646f2b63c7e4a986aa7ee85704e7c98d26f6f237d18da6befdecd3e68fc SHA256 [FMAP: COREBOOT CBFS: bootsplash.jpg]
+ PCR-2 f30a7a27226562b38e190cfe4c87e1dbce720ea370a0b73bd51f14306b8b0385 SHA256 [FMAP: COREBOOT CBFS: fallback/payload]
+
+BS: BS_PAYLOAD_BOOT entry times (exec / console): 1 / 0 ms
+mp_park_aps done after 0 msecs.
+Jumping to boot code at 0x00040000(0x99a6f000)
diff --git a/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/coreboot_timestamps.txt b/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/coreboot_timestamps.txt
new file mode 100644
index 0000000..57ec30e
--- /dev/null
+++ b/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/coreboot_timestamps.txt
@@ -0,0 +1,44 @@
+42 entries total:
+
+11:start of bootblock					9,797 (0)
+0:1st timestamp						9,797 (0)
+12:end of bootblock					15,925 (6,127)
+13:starting to load romstage				15,925 (0)
+14:finished loading romstage				23,089 (7,164)
+1:start of romstage					23,096 (6)
+970:[0x3ca]						24,083 (987)
+2:before RAM initialization				95,528 (71,445)
+950:calling FspMemoryInit				96,270 (741)
+951:returning from FspMemoryInit			142,443 (46,173)
+3:after RAM initialization				144,515 (2,072)
+4:end of romstage					150,910 (6,395)
+100:start of postcar					153,659 (2,748)
+101:end of postcar					153,659 (0)
+8:starting to load ramstage				153,662 (2)
+15:starting LZMA decompress (ignore for x86)		170,616 (16,954)
+16:finished LZMA decompress (ignore for x86)		192,125 (21,508)
+9:finished loading ramstage				192,228 (103)
+10:start of ramstage					193,121 (892)
+15:starting LZMA decompress (ignore for x86)		238,819 (45,698)
+16:finished LZMA decompress (ignore for x86)		272,331 (33,512)
+30:device enumeration					284,718 (12,386)
+971:[0x3cb]						298,305 (13,587)
+15:starting LZMA decompress (ignore for x86)		298,740 (434)
+16:finished LZMA decompress (ignore for x86)		298,970 (229)
+954:calling FspSiliconInit				299,354 (384)
+955:returning from FspSiliconInit			1,534,877 (1,235,523)
+40:device configuration					1,542,574 (7,697)
+956:calling FspNotify(AfterPciEnumeration)		1,545,197 (2,623)
+957:returning from FspNotify(AfterPciEnumeration)	1,545,372 (174)
+50:device enable					1,545,373 (1)
+60:device initialization				1,584,539 (39,166)
+70:device setup done					1,592,873 (8,333)
+75:cbmem post						1,592,878 (5)
+80:write tables						1,592,885 (7)
+85:finalize chips					1,609,337 (16,451)
+90:load payload						1,610,381 (1,043)
+958:calling FspNotify(ReadyToBoot)			5,230,697 (3,620,316)
+959:returning from FspNotify(ReadyToBoot)		5,234,049 (3,352)
+960:calling FspNotify(EndOfFirmware)			5,234,049 (0)
+961:returning from FspNotify(EndOfFirmware)		5,234,641 (591)
+99:selfboot jump					5,235,551 (910)
diff --git a/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/kernel_log.txt b/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/kernel_log.txt
new file mode 100644
index 0000000..7d8d083
--- /dev/null
+++ b/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/kernel_log.txt
@@ -0,0 +1,495 @@
+<5>Linux version 5.14.9 (coreboot@reproducible) (gcc (Ubuntu 10.3.0-1ubuntu1) 10.3.0, GNU ld (GNU Binutils for Ubuntu) 2.36.1) #0 PREEMPT Wed Sep 29 19:06:54 2021
+<6>Command line: 
+<6>x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers'
+<6>x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
+<6>x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers'
+<6>x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers'
+<6>x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR'
+<6>x86/fpu: xstate_offset[2]:  576, xstate_sizes[2]:  256
+<6>x86/fpu: xstate_offset[3]:  832, xstate_sizes[3]:   64
+<6>x86/fpu: xstate_offset[4]:  896, xstate_sizes[4]:   64
+<6>x86/fpu: Enabled xstate features 0x1f, context size is 960 bytes, using 'compacted' format.
+<6>signal: max sigframe size: 1616
+<6>BIOS-provided physical RAM map:
+<6>BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] reserved
+<6>BIOS-e820: [mem 0x0000000000001000-0x000000000009ffff] usable
+<6>BIOS-e820: [mem 0x00000000000a0000-0x00000000000fffff] reserved
+<6>BIOS-e820: [mem 0x0000000000100000-0x0000000099a39fff] usable
+<6>BIOS-e820: [mem 0x0000000099a3a000-0x000000009f7fffff] reserved
+<6>BIOS-e820: [mem 0x00000000e0000000-0x00000000efffffff] reserved
+<6>BIOS-e820: [mem 0x00000000fc000000-0x00000000fc000fff] reserved
+<6>BIOS-e820: [mem 0x00000000fe000000-0x00000000fe00ffff] reserved
+<6>BIOS-e820: [mem 0x00000000fed10000-0x00000000fed17fff] reserved
+<6>BIOS-e820: [mem 0x00000000fed40000-0x00000000fed44fff] reserved
+<6>BIOS-e820: [mem 0x00000000fed80000-0x00000000fed83fff] reserved
+<6>BIOS-e820: [mem 0x00000000fed90000-0x00000000fed91fff] reserved
+<6>BIOS-e820: [mem 0x00000000feda0000-0x00000000feda1fff] reserved
+<6>BIOS-e820: [mem 0x0000000100000000-0x000000085e7fffff] usable
+<6>NX (Execute Disable) protection: active
+<6>tsc: Detected 2300.000 MHz processor
+<6>tsc: Detected 2299.968 MHz TSC
+<7>e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
+<7>e820: remove [mem 0x000a0000-0x000fffff] usable
+<6>last_pfn = 0x85e800 max_arch_pfn = 0x400000000
+<6>x86/PAT: Configuration [0-7]: WB  WT  UC- UC  WB  WT  UC- UC  
+<6>last_pfn = 0x99a3a max_arch_pfn = 0x400000000
+<6>Using GB pages for direct mapping
+<6>RAMDISK: [mem 0x04000000-0x042e6fff]
+<6>ACPI: Early table checksum verification disabled
+<6>ACPI: RSDP 0x00000000000F0000 000024 (v02 COREv4)
+<6>ACPI: XSDT 0x0000000099A4B0E0 00006C (v01 COREv4 COREBOOT 00000000 CORE 20210331)
+<6>ACPI: FACP 0x0000000099A4E770 000114 (v06 COREv4 COREBOOT 00000000 CORE 20210331)
+<6>ACPI: DSDT 0x0000000099A4B280 0034E1 (v02 COREv4 COREBOOT 20110725 INTL 20210331)
+<6>ACPI: FACS 0x0000000099A4B240 000040
+<6>ACPI: FACS 0x0000000099A4B240 000040
+<6>ACPI: SSDT 0x0000000099A4E890 001E8F (v02 COREv4 COREBOOT 0000002A CORE 20210331)
+<6>ACPI: MCFG 0x0000000099A50720 00003C (v01 COREv4 COREBOOT 00000000 CORE 20210331)
+<6>ACPI: TPM2 0x0000000099A50760 00004C (v04 COREv4 COREBOOT 00000000 CORE 20210331)
+<6>ACPI: LPIT 0x0000000099A507B0 000094 (v00 COREv4 COREBOOT 0000002A CORE 20210331)
+<6>ACPI: APIC 0x0000000099A50850 000092 (v03 COREv4 COREBOOT 00000000 CORE 20210331)
+<6>ACPI: DMAR 0x0000000099A508F0 000088 (v01 COREv4 COREBOOT 00000000 CORE 20210331)
+<6>ACPI: DBG2 0x0000000099A50980 000054 (v00 COREv4 COREBOOT 00000000 CORE 20210331)
+<6>ACPI: HPET 0x0000000099A509E0 000038 (v01 COREv4 COREBOOT 00000000 CORE 20210331)
+<6>ACPI: Reserving FACP table memory at [mem 0x99a4e770-0x99a4e883]
+<6>ACPI: Reserving DSDT table memory at [mem 0x99a4b280-0x99a4e760]
+<6>ACPI: Reserving FACS table memory at [mem 0x99a4b240-0x99a4b27f]
+<6>ACPI: Reserving FACS table memory at [mem 0x99a4b240-0x99a4b27f]
+<6>ACPI: Reserving SSDT table memory at [mem 0x99a4e890-0x99a5071e]
+<6>ACPI: Reserving MCFG table memory at [mem 0x99a50720-0x99a5075b]
+<6>ACPI: Reserving TPM2 table memory at [mem 0x99a50760-0x99a507ab]
+<6>ACPI: Reserving LPIT table memory at [mem 0x99a507b0-0x99a50843]
+<6>ACPI: Reserving APIC table memory at [mem 0x99a50850-0x99a508e1]
+<6>ACPI: Reserving DMAR table memory at [mem 0x99a508f0-0x99a50977]
+<6>ACPI: Reserving DBG2 table memory at [mem 0x99a50980-0x99a509d3]
+<6>ACPI: Reserving HPET table memory at [mem 0x99a509e0-0x99a50a17]
+<6>Zone ranges:
+<6>  DMA32    [mem 0x0000000000001000-0x00000000ffffffff]
+<6>  Normal   [mem 0x0000000100000000-0x000000085e7fffff]
+<6>Movable zone start for each node
+<6>Early memory node ranges
+<6>  node   0: [mem 0x0000000000001000-0x000000000009ffff]
+<6>  node   0: [mem 0x0000000000100000-0x0000000099a39fff]
+<6>  node   0: [mem 0x0000000100000000-0x000000085e7fffff]
+<6>Initmem setup node 0 [mem 0x0000000000001000-0x000000085e7fffff]
+<6>On node 0, zone DMA32: 1 pages in unavailable ranges
+<6>On node 0, zone DMA32: 96 pages in unavailable ranges
+<6>On node 0, zone Normal: 26054 pages in unavailable ranges
+<6>On node 0, zone Normal: 6144 pages in unavailable ranges
+<6>Reserving Intel graphics memory at [mem 0x9b800000-0x9f7fffff]
+<4>APIC: NR_CPUS/possible_cpus limit of 1 reached. Processor 1/0x1 ignored.
+<4>APIC: NR_CPUS/possible_cpus limit of 1 reached. Processor 2/0x2 ignored.
+<4>APIC: NR_CPUS/possible_cpus limit of 1 reached. Processor 3/0x3 ignored.
+<4>APIC: NR_CPUS/possible_cpus limit of 1 reached. Processor 4/0x4 ignored.
+<4>APIC: NR_CPUS/possible_cpus limit of 1 reached. Processor 5/0x5 ignored.
+<4>APIC: NR_CPUS/possible_cpus limit of 1 reached. Processor 6/0x6 ignored.
+<4>APIC: NR_CPUS/possible_cpus limit of 1 reached. Processor 7/0x7 ignored.
+<6>ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1])
+<6>IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-119
+<6>ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
+<6>ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
+<6>ACPI: Using ACPI (MADT) for SMP configuration information
+<6>ACPI: HPET id: 0x8086a701 base: 0xfed00000
+<6>TSC deadline timer available
+<6>[mem 0x9f800000-0xdfffffff] available for PCI devices
+<6>clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645519600211568 ns
+<7>pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
+<7>pcpu-alloc: [0] 0 
+<6>Built 1 zonelists, mobility grouping on.  Total pages: 8225586
+<5>Kernel command line: 
+<6>Dentry cache hash table entries: 4194304 (order: 13, 33554432 bytes, linear)
+<6>Inode-cache hash table entries: 2097152 (order: 12, 16777216 bytes, linear)
+<6>mem auto-init: stack:off, heap alloc:off, heap free:off
+<6>Memory: 32767176K/33425252K available (8194K kernel code, 1030K rwdata, 888K rodata, 640K init, 372K bss, 657820K reserved, 0K cma-reserved)
+<6>rcu: Preemptible hierarchical RCU implementation.
+<6>rcu: 	RCU event tracing is enabled.
+<6>	Trampoline variant of Tasks RCU enabled.
+<6>	Tracing variant of Tasks RCU enabled.
+<6>rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
+<6>NR_IRQS: 4352, nr_irqs: 256, preallocated irqs: 16
+<5>random: get_random_bytes called from 0xffffffff81d03efd with crng_init=0
+<6>Console: colour dummy device 80x25
+<6>printk: console [tty0] enabled
+<6>ACPI: Core revision 20210604
+<6>clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635855245 ns
+<6>APIC: Switch to symmetric I/O mode setup
+<6>..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
+<6>clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x212717146a7, max_idle_ns: 440795291431 ns
+<6>Calibrating delay loop (skipped), value calculated using timer frequency.. 4599.93 BogoMIPS (lpj=9199872)
+<6>pid_max: default: 4096 minimum: 301
+<6>Mount-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
+<6>Mountpoint-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
+<6>process: using mwait in idle threads
+<6>Last level iTLB entries: 4KB 64, 2MB 8, 4MB 8
+<6>Last level dTLB entries: 4KB 64, 2MB 0, 4MB 0, 1GB 4
+<6>CPU: Intel(R) Core(TM) i7-10510U CPU @ 1.80GHz (family: 0x6, model: 0x8e, stepping: 0xc)
+<6>Spectre V1 : Mitigation: usercopy/swapgs barriers and __user pointer sanitization
+<6>Spectre V2 : Mitigation: Enhanced IBRS
+<6>Spectre V2 : Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch
+<6>Spectre V2 : mitigation: Enabling conditional Indirect Branch Prediction Barrier
+<6>Speculative Store Bypass: Mitigation: Speculative Store Bypass disabled via prctl and seccomp
+<6>SRBDS: Mitigation: TSX disabled
+<6>Performance Events: PEBS fmt3+, Skylake events, 32-deep LBR, full-width counters, Intel PMU driver.
+<6>... version:                4
+<6>... bit width:              48
+<6>... generic registers:      4
+<6>... value mask:             0000ffffffffffff
+<6>... max period:             00007fffffffffff
+<6>... fixed-purpose events:   3
+<6>... event mask:             000000070000000f
+<6>rcu: Hierarchical SRCU implementation.
+<6>devtmpfs: initialized
+<6>clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
+<6>futex hash table entries: 16 (order: -4, 384 bytes, linear)
+<6>NET: Registered PF_NETLINK/PF_ROUTE protocol family
+<6>ACPI: bus type PCI registered
+<6>PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
+<6>PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in E820
+<6>PCI: Using configuration type 1 for base access
+<6>ACPI: Added _OSI(Module Device)
+<6>ACPI: Added _OSI(Processor Device)
+<6>ACPI: Added _OSI(3.0 _SCP Extensions)
+<6>ACPI: Added _OSI(Processor Aggregator Device)
+<6>ACPI: Added _OSI(Linux-Dell-Video)
+<6>ACPI: Added _OSI(Linux-Lenovo-NV-HDMI-Audio)
+<6>ACPI: Added _OSI(Linux-HPI-Hybrid-Graphics)
+<6>ACPI: 2 ACPI AML tables successfully acquired and loaded
+<6>ACPI: EC: EC started
+<6>ACPI: EC: interrupt blocked
+<6>ACPI: EC: EC_CMD/EC_SC=0x66, EC_DATA=0x62
+<6>ACPI: \_SB_.PCI0.LPCB.EC0_: Boot DSDT EC used to handle transactions
+<6>ACPI: Interpreter enabled
+<6>ACPI: PM: (supports S0 S5)
+<6>ACPI: Using IOAPIC for interrupt routing
+<6>PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
+<6>ACPI: Enabled 1 GPEs in block 00 to 7F
+<6>ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
+<6>acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3]
+<6>acpi PNP0A08:00: _OSC: OS now controls [PME PCIeCapability LTR]
+<6>PCI host bridge to bus 0000:00
+<6>pci_bus 0000:00: root bus resource [io  0x0000-0x0cf7 window]
+<6>pci_bus 0000:00: root bus resource [io  0x0d00-0xffff window]
+<6>pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
+<6>pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000c3fff window]
+<6>pci_bus 0000:00: root bus resource [mem 0x000c4000-0x000c7fff window]
+<6>pci_bus 0000:00: root bus resource [mem 0x000c8000-0x000cbfff window]
+<6>pci_bus 0000:00: root bus resource [mem 0x000cc000-0x000cffff window]
+<6>pci_bus 0000:00: root bus resource [mem 0x000d0000-0x000d3fff window]
+<6>pci_bus 0000:00: root bus resource [mem 0x000d4000-0x000d7fff window]
+<6>pci_bus 0000:00: root bus resource [mem 0x000d8000-0x000dbfff window]
+<6>pci_bus 0000:00: root bus resource [mem 0x000dc000-0x000dffff window]
+<6>pci_bus 0000:00: root bus resource [mem 0x000e0000-0x000e3fff window]
+<6>pci_bus 0000:00: root bus resource [mem 0x000e4000-0x000e7fff window]
+<6>pci_bus 0000:00: root bus resource [mem 0x000e8000-0x000ebfff window]
+<6>pci_bus 0000:00: root bus resource [mem 0x000ec000-0x000effff window]
+<6>pci_bus 0000:00: root bus resource [mem 0x000f0000-0x000fffff window]
+<6>pci_bus 0000:00: root bus resource [mem 0x9f800000-0xdfffffff window]
+<6>pci_bus 0000:00: root bus resource [mem 0x85e800000-0x7fffffffff window]
+<6>pci_bus 0000:00: root bus resource [mem 0xfc800000-0xfe7fffff window]
+<6>pci_bus 0000:00: root bus resource [mem 0xfed40000-0xfed47fff window]
+<6>pci_bus 0000:00: root bus resource [bus 00-ff]
+<6>pci 0000:00:00.0: [8086:9b61] type 00 class 0x060000
+<6>pci 0000:00:02.0: [8086:9b41] type 00 class 0x030000
+<6>pci 0000:00:02.0: reg 0x10: [mem 0xb0000000-0xb0ffffff 64bit]
+<6>pci 0000:00:02.0: reg 0x18: [mem 0xa0000000-0xafffffff 64bit pref]
+<6>pci 0000:00:02.0: reg 0x20: [io  0x1000-0x103f]
+<6>pci 0000:00:04.0: [8086:1903] type 00 class 0x118000
+<6>pci 0000:00:04.0: reg 0x10: [mem 0x9fb10000-0x9fb17fff 64bit]
+<6>pci 0000:00:08.0: [8086:1911] type 00 class 0x088000
+<6>pci 0000:00:08.0: reg 0x10: [mem 0x9fb24000-0x9fb24fff 64bit]
+<6>pci 0000:00:12.0: [8086:02f9] type 00 class 0x118000
+<6>pci 0000:00:12.0: reg 0x10: [mem 0x9fb25000-0x9fb25fff 64bit]
+<6>pci 0000:00:14.0: [8086:02ed] type 00 class 0x0c0330
+<6>pci 0000:00:14.0: reg 0x10: [mem 0x9fb00000-0x9fb0ffff 64bit]
+<6>pci 0000:00:14.0: PME# supported from D3hot D3cold
+<6>pci 0000:00:14.2: [8086:02ef] type 00 class 0x050000
+<6>pci 0000:00:14.2: reg 0x10: [mem 0x9fb20000-0x9fb21fff 64bit]
+<6>pci 0000:00:14.2: reg 0x18: [mem 0x9fb26000-0x9fb26fff 64bit]
+<6>pci 0000:00:14.3: [8086:02f0] type 00 class 0x028000
+<6>pci 0000:00:14.3: reg 0x10: [mem 0x9fb18000-0x9fb1bfff 64bit]
+<6>pci 0000:00:14.3: PME# supported from D0 D3hot D3cold
+<6>pci 0000:00:15.0: [8086:02e8] type 00 class 0x0c8000
+<6>pci 0000:00:15.0: reg 0x10: [mem 0x9fb27000-0x9fb27fff 64bit]
+<6>pci 0000:00:17.0: [8086:02d3] type 00 class 0x010601
+<6>pci 0000:00:17.0: reg 0x10: [mem 0x9fb22000-0x9fb23fff]
+<6>pci 0000:00:17.0: reg 0x14: [mem 0x9fb2b000-0x9fb2b0ff]
+<6>pci 0000:00:17.0: reg 0x18: [io  0x1060-0x1067]
+<6>pci 0000:00:17.0: reg 0x1c: [io  0x1068-0x106b]
+<6>pci 0000:00:17.0: reg 0x20: [io  0x1040-0x105f]
+<6>pci 0000:00:17.0: reg 0x24: [mem 0x9fb2a000-0x9fb2a7ff]
+<6>pci 0000:00:17.0: PME# supported from D3hot
+<6>pci 0000:00:19.0: [8086:02c5] type 00 class 0x0c8000
+<6>pci 0000:00:19.0: reg 0x10: [mem 0x00000000-0x00000fff 64bit]
+<6>pci 0000:00:19.2: [8086:02c7] type 00 class 0x078000
+<6>pci 0000:00:19.2: reg 0x10: [mem 0xfe032000-0xfe032fff 64bit]
+<6>pci 0000:00:19.2: reg 0x18: [mem 0x9fb28000-0x9fb28fff 64bit]
+<6>pci 0000:00:1c.0: [8086:02bc] type 01 class 0x060400
+<6>pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
+<6>pci 0000:00:1d.0: [8086:02b0] type 01 class 0x060400
+<6>pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold
+<6>pci 0000:00:1d.1: [8086:02b1] type 01 class 0x060400
+<6>pci 0000:00:1d.1: PME# supported from D0 D3hot D3cold
+<6>pci 0000:00:1d.4: [8086:02b4] type 01 class 0x060400
+<6>pci 0000:00:1d.4: PME# supported from D0 D3hot D3cold
+<6>pci 0000:00:1f.0: [8086:0284] type 00 class 0x060100
+<6>pci 0000:00:1f.3: [8086:02c8] type 00 class 0x040300
+<6>pci 0000:00:1f.3: reg 0x10: [mem 0x9fb1c000-0x9fb1ffff 64bit]
+<6>pci 0000:00:1f.3: reg 0x20: [mem 0x9fa00000-0x9fafffff 64bit]
+<6>pci 0000:00:1f.3: PME# supported from D3hot D3cold
+<6>pci 0000:00:1f.4: [8086:02a3] type 00 class 0x0c0500
+<6>pci 0000:00:1f.4: reg 0x10: [mem 0x9fb2c000-0x9fb2c0ff 64bit]
+<6>pci 0000:00:1f.4: reg 0x20: [io  0xefa0-0xefbf]
+<6>pci 0000:00:1f.5: [8086:02a4] type 00 class 0x0c8000
+<6>pci 0000:00:1f.5: reg 0x10: [mem 0xfe010000-0xfe010fff]
+<6>pci 0000:01:00.0: [8086:15e7] type 01 class 0x060400
+<6>pci 0000:01:00.0: enabling Extended Tags
+<6>pci 0000:01:00.0: supports D1 D2
+<6>pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
+<6>pci 0000:00:1c.0: PCI bridge to [bus 01-25]
+<6>pci 0000:00:1c.0:   bridge window [io  0x2000-0x3fff]
+<6>pci 0000:00:1c.0:   bridge window [mem 0xd1000000-0xd31fffff]
+<6>pci 0000:00:1c.0:   bridge window [mem 0xb1000000-0xd0ffffff 64bit pref]
+<6>pci 0000:02:00.0: [8086:15e7] type 01 class 0x060400
+<6>pci 0000:02:00.0: enabling Extended Tags
+<6>pci 0000:02:00.0: supports D1 D2
+<6>pci 0000:02:00.0: PME# supported from D0 D1 D2 D3hot D3cold
+<6>pci 0000:02:01.0: [8086:15e7] type 01 class 0x060400
+<6>pci 0000:02:01.0: enabling Extended Tags
+<6>pci 0000:02:01.0: supports D1 D2
+<6>pci 0000:02:01.0: PME# supported from D0 D1 D2 D3hot D3cold
+<6>pci 0000:02:02.0: [8086:15e7] type 01 class 0x060400
+<6>pci 0000:02:02.0: enabling Extended Tags
+<6>pci 0000:02:02.0: supports D1 D2
+<6>pci 0000:02:02.0: PME# supported from D0 D1 D2 D3hot D3cold
+<6>pci 0000:01:00.0: PCI bridge to [bus 02-25]
+<6>pci 0000:01:00.0:   bridge window [io  0x2000-0x3fff]
+<6>pci 0000:01:00.0:   bridge window [mem 0xd1000000-0xd31fffff]
+<6>pci 0000:01:00.0:   bridge window [mem 0xb1000000-0xd0ffffff 64bit pref]
+<6>pci 0000:03:00.0: [8086:15e8] type 00 class 0x088000
+<6>pci 0000:03:00.0: reg 0x10: [mem 0xd3000000-0xd303ffff]
+<6>pci 0000:03:00.0: reg 0x14: [mem 0xd3040000-0xd3040fff]
+<6>pci 0000:03:00.0: enabling Extended Tags
+<6>pci 0000:03:00.0: supports D1 D2
+<6>pci 0000:03:00.0: PME# supported from D0 D1 D2 D3hot D3cold
+<6>pci 0000:02:00.0: PCI bridge to [bus 03]
+<6>pci 0000:02:00.0:   bridge window [mem 0xd3000000-0xd30fffff]
+<6>pci 0000:02:01.0: PCI bridge to [bus 04-24]
+<6>pci 0000:02:01.0:   bridge window [io  0x2000-0x3fff]
+<6>pci 0000:02:01.0:   bridge window [mem 0xd1000000-0xd2ffffff]
+<6>pci 0000:02:01.0:   bridge window [mem 0xb1000000-0xd0ffffff 64bit pref]
+<6>pci 0000:25:00.0: [8086:15e9] type 00 class 0x0c0330
+<6>pci 0000:25:00.0: reg 0x10: [mem 0xd3100000-0xd310ffff]
+<6>pci 0000:25:00.0: enabling Extended Tags
+<6>pci 0000:25:00.0: supports D1 D2
+<6>pci 0000:25:00.0: PME# supported from D0 D1 D2 D3hot D3cold
+<6>pci 0000:25:00.0: 8.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s PCIe x4 link at 0000:02:02.0 (capable of 31.504 Gb/s with 8.0 GT/s PCIe x4 link)
+<6>pci 0000:02:02.0: PCI bridge to [bus 25]
+<6>pci 0000:02:02.0:   bridge window [mem 0xd3100000-0xd31fffff]
+<6>pci 0000:26:00.0: [10ec:5287] type 00 class 0xff0000
+<6>pci 0000:26:00.0: reg 0x10: [mem 0x9f814000-0x9f814fff]
+<6>pci 0000:26:00.0: reg 0x30: [mem 0x9f800000-0x9f80ffff pref]
+<6>pci 0000:26:00.0: supports D1 D2
+<6>pci 0000:26:00.0: PME# supported from D1 D2 D3hot D3cold
+<6>pci 0000:26:00.1: [10ec:8168] type 00 class 0x020000
+<6>pci 0000:26:00.1: reg 0x10: [io  0x4000-0x40ff]
+<6>pci 0000:26:00.1: reg 0x18: [mem 0x9f815000-0x9f815fff 64bit]
+<6>pci 0000:26:00.1: reg 0x20: [mem 0x9f810000-0x9f813fff 64bit]
+<6>pci 0000:26:00.1: supports D1 D2
+<6>pci 0000:26:00.1: PME# supported from D0 D1 D2 D3hot D3cold
+<6>pci 0000:00:1d.0: PCI bridge to [bus 26]
+<6>pci 0000:00:1d.0:   bridge window [io  0x4000-0x4fff]
+<6>pci 0000:00:1d.0:   bridge window [mem 0x9f800000-0x9f8fffff]
+<6>pci 0000:00:1d.1: PCI bridge to [bus 27]
+<6>pci 0000:28:00.0: [144d:a808] type 00 class 0x010802
+<6>pci 0000:28:00.0: reg 0x10: [mem 0x9f900000-0x9f903fff 64bit]
+<6>pci 0000:00:1d.4: PCI bridge to [bus 28]
+<6>pci 0000:00:1d.4:   bridge window [mem 0x9f900000-0x9f9fffff]
+<7>pci_bus 0000:00: on NUMA node 0
+<6>ACPI: EC: interrupt unblocked
+<6>ACPI: EC: event unblocked
+<6>ACPI: EC: EC_CMD/EC_SC=0x66, EC_DATA=0x62
+<6>ACPI: EC: GPE=0x50
+<6>ACPI: \_SB_.PCI0.LPCB.EC0_: Boot DSDT EC initialization complete
+<6>ACPI: \_SB_.PCI0.LPCB.EC0_: EC: Used to handle transactions and events
+<6>pci 0000:00:02.0: vgaarb: setting as boot VGA device
+<6>pci 0000:00:02.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none
+<6>pci 0000:00:02.0: vgaarb: bridge control possible
+<6>vgaarb: loaded
+<5>SCSI subsystem initialized
+<7>libata version 3.00 loaded.
+<6>PCI: Using ACPI for IRQ routing
+<7>PCI: pci_cache_line_size set to 64 bytes
+<7>e820: reserve RAM buffer [mem 0x99a3a000-0x9bffffff]
+<7>e820: reserve RAM buffer [mem 0x85e800000-0x85fffffff]
+<6>clocksource: Switched to clocksource tsc-early
+<6>pnp: PnP ACPI init
+<6>system 00:00: [mem 0xfed10000-0xfed17fff] has been reserved
+<6>system 00:00: [mem 0xfed18000-0xfed18fff] has been reserved
+<6>system 00:00: [mem 0xfed19000-0xfed19fff] has been reserved
+<6>system 00:00: [mem 0xe0000000-0xefffffff] has been reserved
+<6>system 00:00: [mem 0xfed90000-0xfed93fff] could not be reserved
+<6>system 00:00: [mem 0xff000000-0xffffffff] has been reserved
+<6>system 00:00: [mem 0xfee00000-0xfeefffff] has been reserved
+<6>system 00:00: [mem 0xfed00000-0xfed003ff] has been reserved
+<6>system 00:01: [mem 0xfed00000-0xfed003ff] has been reserved
+<6>system 00:02: [io  0x1800-0x18fe] has been reserved
+<6>pnp: PnP ACPI: found 6 devices
+<6>NET: Registered PF_INET protocol family
+<6>IP idents hash table entries: 262144 (order: 9, 2097152 bytes, linear)
+<6>tcp_listen_portaddr_hash hash table entries: 16384 (order: 6, 262144 bytes, linear)
+<6>TCP established hash table entries: 262144 (order: 9, 2097152 bytes, linear)
+<6>TCP bind hash table entries: 65536 (order: 7, 524288 bytes, linear)
+<6>TCP: Hash tables configured (established 262144 bind 65536)
+<6>UDP hash table entries: 16384 (order: 7, 524288 bytes, linear)
+<6>UDP-Lite hash table entries: 16384 (order: 7, 524288 bytes, linear)
+<6>pci 0000:00:19.0: BAR 0: assigned [mem 0x85e800000-0x85e800fff 64bit]
+<6>pci 0000:02:00.0: PCI bridge to [bus 03]
+<6>pci 0000:02:00.0:   bridge window [mem 0xd3000000-0xd30fffff]
+<6>pci 0000:02:01.0: PCI bridge to [bus 04-24]
+<6>pci 0000:02:01.0:   bridge window [io  0x2000-0x3fff]
+<6>pci 0000:02:01.0:   bridge window [mem 0xd1000000-0xd2ffffff]
+<6>pci 0000:02:01.0:   bridge window [mem 0xb1000000-0xd0ffffff 64bit pref]
+<6>pci 0000:02:02.0: PCI bridge to [bus 25]
+<6>pci 0000:02:02.0:   bridge window [mem 0xd3100000-0xd31fffff]
+<6>pci 0000:01:00.0: PCI bridge to [bus 02-25]
+<6>pci 0000:01:00.0:   bridge window [io  0x2000-0x3fff]
+<6>pci 0000:01:00.0:   bridge window [mem 0xd1000000-0xd31fffff]
+<6>pci 0000:01:00.0:   bridge window [mem 0xb1000000-0xd0ffffff 64bit pref]
+<6>pci 0000:00:1c.0: PCI bridge to [bus 01-25]
+<6>pci 0000:00:1c.0:   bridge window [io  0x2000-0x3fff]
+<6>pci 0000:00:1c.0:   bridge window [mem 0xd1000000-0xd31fffff]
+<6>pci 0000:00:1c.0:   bridge window [mem 0xb1000000-0xd0ffffff 64bit pref]
+<6>pci 0000:00:1d.0: PCI bridge to [bus 26]
+<6>pci 0000:00:1d.0:   bridge window [io  0x4000-0x4fff]
+<6>pci 0000:00:1d.0:   bridge window [mem 0x9f800000-0x9f8fffff]
+<6>pci 0000:00:1d.1: PCI bridge to [bus 27]
+<6>pci 0000:00:1d.4: PCI bridge to [bus 28]
+<6>pci 0000:00:1d.4:   bridge window [mem 0x9f900000-0x9f9fffff]
+<6>pci_bus 0000:00: resource 4 [io  0x0000-0x0cf7 window]
+<6>pci_bus 0000:00: resource 5 [io  0x0d00-0xffff window]
+<6>pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff window]
+<6>pci_bus 0000:00: resource 7 [mem 0x000c0000-0x000c3fff window]
+<6>pci_bus 0000:00: resource 8 [mem 0x000c4000-0x000c7fff window]
+<6>pci_bus 0000:00: resource 9 [mem 0x000c8000-0x000cbfff window]
+<6>pci_bus 0000:00: resource 10 [mem 0x000cc000-0x000cffff window]
+<6>pci_bus 0000:00: resource 11 [mem 0x000d0000-0x000d3fff window]
+<6>pci_bus 0000:00: resource 12 [mem 0x000d4000-0x000d7fff window]
+<6>pci_bus 0000:00: resource 13 [mem 0x000d8000-0x000dbfff window]
+<6>pci_bus 0000:00: resource 14 [mem 0x000dc000-0x000dffff window]
+<6>pci_bus 0000:00: resource 15 [mem 0x000e0000-0x000e3fff window]
+<6>pci_bus 0000:00: resource 16 [mem 0x000e4000-0x000e7fff window]
+<6>pci_bus 0000:00: resource 17 [mem 0x000e8000-0x000ebfff window]
+<6>pci_bus 0000:00: resource 18 [mem 0x000ec000-0x000effff window]
+<6>pci_bus 0000:00: resource 19 [mem 0x000f0000-0x000fffff window]
+<6>pci_bus 0000:00: resource 20 [mem 0x9f800000-0xdfffffff window]
+<6>pci_bus 0000:00: resource 21 [mem 0x85e800000-0x7fffffffff window]
+<6>pci_bus 0000:00: resource 22 [mem 0xfc800000-0xfe7fffff window]
+<6>pci_bus 0000:00: resource 23 [mem 0xfed40000-0xfed47fff window]
+<6>pci_bus 0000:01: resource 0 [io  0x2000-0x3fff]
+<6>pci_bus 0000:01: resource 1 [mem 0xd1000000-0xd31fffff]
+<6>pci_bus 0000:01: resource 2 [mem 0xb1000000-0xd0ffffff 64bit pref]
+<6>pci_bus 0000:02: resource 0 [io  0x2000-0x3fff]
+<6>pci_bus 0000:02: resource 1 [mem 0xd1000000-0xd31fffff]
+<6>pci_bus 0000:02: resource 2 [mem 0xb1000000-0xd0ffffff 64bit pref]
+<6>pci_bus 0000:03: resource 1 [mem 0xd3000000-0xd30fffff]
+<6>pci_bus 0000:04: resource 0 [io  0x2000-0x3fff]
+<6>pci_bus 0000:04: resource 1 [mem 0xd1000000-0xd2ffffff]
+<6>pci_bus 0000:04: resource 2 [mem 0xb1000000-0xd0ffffff 64bit pref]
+<6>pci_bus 0000:25: resource 1 [mem 0xd3100000-0xd31fffff]
+<6>pci_bus 0000:26: resource 0 [io  0x4000-0x4fff]
+<6>pci_bus 0000:26: resource 1 [mem 0x9f800000-0x9f8fffff]
+<6>pci_bus 0000:28: resource 1 [mem 0x9f900000-0x9f9fffff]
+<6>pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff]
+<6>PCI: CLS 64 bytes, default 64
+<6>PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
+<6>software IO TLB: mapped [mem 0x0000000095a3a000-0x0000000099a3a000] (64MB)
+<6>RAPL PMU: API unit is 2^-32 Joules, 5 fixed counters, 655360 ms ovfl timer
+<6>RAPL PMU: hw unit of domain pp0-core 2^-14 Joules
+<6>RAPL PMU: hw unit of domain package 2^-14 Joules
+<6>RAPL PMU: hw unit of domain dram 2^-14 Joules
+<6>RAPL PMU: hw unit of domain pp1-gpu 2^-14 Joules
+<6>RAPL PMU: hw unit of domain psys 2^-14 Joules
+<6>Unpacking initramfs...
+<6>workingset: timestamp_bits=46 max_order=23 bucket_order=0
+<6>input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input0
+<6>ACPI: button: Power Button [PWRB]
+<6>input: Sleep Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0E:00/input/input1
+<6>ACPI: button: Sleep Button [SLPB]
+<6>input: Lid Switch as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0D:00/input/input2
+<6>ACPI: button: Lid Switch [LID0]
+<6>input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input3
+<6>ACPI: button: Power Button [PWRF]
+<6>Serial: 8250/16550 driver, 32 ports, IRQ sharing disabled
+<6>tpm_tis MSFT0101:00: 2.0 TPM (device-id 0x1B, rev-id 22)
+<6>Freeing initrd memory: 2972K
+<6>loop: module loaded
+<4>intel-lpss 0000:00:15.0: Failed to create debugfs entries
+<6>intel-lpss 0000:00:19.0: enabling device (0000 -> 0002)
+<4>intel-lpss 0000:00:19.0: Failed to create debugfs entries
+<4>intel-lpss 0000:00:19.2: Failed to create debugfs entries
+<6>dw-apb-uart.2: ttyS4 at MMIO 0xfe032000 (irq = 32, base_baud = 115200) is a 16550A
+<6>nvme nvme0: pci function 0000:28:00.0
+<6>libphy: Fixed MDIO Bus: probed
+<4>nvme nvme0: missing or invalid SUBNQN field.
+<6>nvme nvme0: Shutdown timeout set to 8 seconds
+<6>nvme nvme0: 1/0/0 default/read/poll queues
+<6> nvme0n1: p1 p2 p3
+<6>libphy: r8169: probed
+<6>r8169 0000:26:00.1 eth0: RTL8411b, 80:fa:5b:74:be:17, XID 5c8, IRQ 129
+<6>r8169 0000:26:00.1 eth0: jumbo features [frames: 9194 bytes, tx checksumming: ko]
+<6>i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f13:PS2M] at 0x60,0x64 irq 1,12
+<6>i8042: Detected active multiplexing controller, rev 1.1
+<6>serio: i8042 KBD port at 0x60,0x64 irq 1
+<6>serio: i8042 AUX0 port at 0x60,0x64 irq 12
+<6>serio: i8042 AUX1 port at 0x60,0x64 irq 12
+<6>serio: i8042 AUX2 port at 0x60,0x64 irq 12
+<6>serio: i8042 AUX3 port at 0x60,0x64 irq 12
+<6>device-mapper: ioctl: 4.45.0-ioctl (2021-03-22) initialised: dm-devel@redhat.com
+<6>sdhci: Secure Digital Host Controller Interface driver
+<6>sdhci: Copyright(c) Pierre Ossman
+<6>sdhci-pltfm: SDHCI platform and OF driver helper
+<6>simple-framebuffer simple-framebuffer.0: framebuffer at 0xa0000000, 0x7e9000 bytes
+<6>simple-framebuffer simple-framebuffer.0: format=a8r8g8b8, mode=1920x1080x32, linelength=7680
+<6>input: AT Raw Set 2 keyboard as /devices/platform/i8042/serio0/input/input4
+<6>Console: switching to colour frame buffer device 240x67
+<6>simple-framebuffer simple-framebuffer.0: fb0: simplefb registered!
+<6>NET: Registered PF_INET6 protocol family
+<6>Segment Routing with IPv6
+<6>sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
+<6>NET: Registered PF_PACKET protocol family
+<6>sched_clock: Marking stable (963018164, 5127569)->(970596829, -2451096)
+<6>Freeing unused kernel image (initmem) memory: 640K
+<6>Write protecting the kernel read-only data: 12288k
+<6>Freeing unused kernel image (text/rodata gap) memory: 2044K
+<6>Freeing unused kernel image (rodata/data gap) memory: 1160K
+<6>Run /init as init process
+<7>  with arguments:
+<7>    /init
+<7>  with environment:
+<7>    HOME=/
+<7>    TERM=linux
+<3>cgroup: Unknown subsys name 'freezer'
+<14>u-root init [optional]: warning creating mount -t "cgroup" -o freezer "cgroup" "/sys/fs/cgroup/freezer" flags 0x0: invalid argument
+<3>cgroup: Unknown subsys name 'cpuset'
+<14>u-root init [optional]: warning creating mount -t "cgroup" -o cpuset "cgroup" "/sys/fs/cgroup/cpuset" flags 0x0: invalid argument
+<3>cgroup: Unknown subsys name 'net_cls'
+<14>u-root init [optional]: warning creating mount -t "cgroup" -o net_cls,net_prio "cgroup" "/sys/fs/cgroup/net_cls,net_prio" flags 0x0: invalid argument
+<3>cgroup: Unknown subsys name 'hugetlb'
+<14>u-root init [optional]: warning creating mount -t "cgroup" -o hugetlb "cgroup" "/sys/fs/cgroup/hugetlb" flags 0x0: invalid argument
+<6>tsc: Refined TSC clocksource calibration: 2303.999 MHz
+<6>clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x2135f6faae8, max_idle_ns: 440795313647 ns
+<6>clocksource: Switched to clocksource tsc
+<6>psmouse serio2: synaptics: queried max coordinates: x [..5658], y [..4722]
+<6>psmouse serio2: synaptics: queried min coordinates: x [1284..], y [1130..]
+<4>psmouse serio2: synaptics: The touchpad can support a better bus than the too old PS/2 protocol. Make sure MOUSE_PS2_SYNAPTICS_SMBUS and RMI4_SMB are enabled to get a better touchpad experience.
+<5>random: fast init done
+<6>psmouse serio2: synaptics: Touchpad model: 1, fw: 9.16, id: 0x1e2a1, caps: 0xf00123/0x840300/0x2e800/0x500000, board id: 3429, fw id: 2840755
+<6>input: SynPS/2 Synaptics TouchPad as /devices/platform/i8042/serio2/input/input10
+<4>r8169 0000:26:00.1: Direct firmware load for rtl_nic/rtl8411-2.fw failed with error -2
+<3>r8169 0000:26:00.1: Unable to load firmware rtl_nic/rtl8411-2.fw (-2)
+<6>Generic FE-GE Realtek PHY r8169-0-2601:00: attached PHY driver (mii_bus:phy_addr=r8169-0-2601:00, irq=MAC)
+<6>r8169 0000:26:00.1 eth0: Link is Down
+<6>r8169 0000:26:00.1 eth0: Link is Up - 1Gbps/Full - flow control off
+<6>IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
+<6>r8169 0000:26:00.1 eth0: Link is Down
+<6>r8169 0000:26:00.1 eth0: Link is Up - 1Gbps/Full - flow control off
+<5>random: crng init done
diff --git a/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/revision.txt b/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/revision.txt
new file mode 100644
index 0000000..b15017e
--- /dev/null
+++ b/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/revision.txt
@@ -0,0 +1,5 @@
+Local revision: 9de5d8dd39-dirty
+Tagged revision: 4.14-2061-g9de5d8dd39
+Upstream revision: 9de5d8dd39
+Upstream URL: https://review.coreboot.org/coreboot
+Timestamp: 2021-09-30T12_45_08Z
diff --git a/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/rom_checksum.txt b/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/rom_checksum.txt
new file mode 100644
index 0000000..b917ada
--- /dev/null
+++ b/system76/cml-u/4.14-2061-g9de5d8dd39/2021-09-30T12_45_08Z/rom_checksum.txt
@@ -0,0 +1 @@
+f48f33dc436fc20b3eacdc54ac027f2f *build/coreboot.rom