diff --git a/coreboot_board_status.6Zyk98Xx/4.3-315-g2a5a2fb-dirty/2016-02-25T07_00_33Z/coreboot_console.txt b/coreboot_board_status.6Zyk98Xx/4.3-315-g2a5a2fb-dirty/2016-02-25T07_00_33Z/coreboot_console.txt
new file mode 100644
index 0000000..0419af5
--- /dev/null
+++ b/coreboot_board_status.6Zyk98Xx/4.3-315-g2a5a2fb-dirty/2016-02-25T07_00_33Z/coreboot_console.txt
@@ -0,0 +1,2376 @@
+
+
+coreboot-4.3-315-g2a5a2fb-MattDevo Tue Feb 23 05:05:45 UTC 2016 romstage starting...
+Disabling Watchdog reboot... done.
+SMBus controller enabled.
+Setting up static northbridge registers... done.
+Initializing Graphics...
+Back from haswell_early_initialization()
+CPU id(40651) ucode:0000001c Intel(R) Celeron(R) 2957U @ 1.40GHz
+AES NOT supported, TXT NOT supported, VT supported
+PCH type: LP Mainstream, device id: 9c45, rev id 4
+Starting UEFI PEI System Agent
+CBFS: 'Master Header Locator' located CBFS at [700100:7fffc0)
+CBFS: Locating 'mrc.cache'
+CBFS: Found @ offset fec0 size 10000
+find_current_mrc_cache_local: picked entry 0 from cache block
+prepare_mrc_cache: at fff10010, size fe0 checksum be21
+CBFS: 'Master Header Locator' located CBFS at [700100:7fffc0)
+CBFS: Locating 'mrc.bin'
+CBFS: Found @ offset 9fec0 size 2eb04
+System Agent: Starting up...
+System Agent: Initializing PCH
+install_ppi: overwrite GUID {ed097352-9041-445a-80b6-b29d509e8845}
+install_ppi: overwrite GUID {908c7f8b-5c48-47fb-8357-f5fd4e235276}
+System Agent: Initializing PCH (SMBUS)
+System Agent: Initializing PCH (USB)
+System Agent: Initializing PCH (SA Init)
+System Agent: Initializing PCH (Me UMA)
+System Agent: Initializing Memory
+System Agent: Done.
+Sanity checking heap.
+System Agent Version 1.6.1 Build 2
+memcfg DDR3 clock 1600 MHz
+memcfg channel assignment: A: 0, B  1, C  2
+memcfg channel[0] config (00780008):
+   ECC inactive
+   enhanced interleave mode on
+   rank interleave on
+   DIMMA 2048 MB width x16 single rank, selected
+   DIMMB 0 MB width x16 single rank
+memcfg channel[1] config (00600000):
+   ECC inactive
+   enhanced interleave mode on
+   rank interleave on
+   DIMMA 0 MB width x8 or x32 single rank, selected
+   DIMMB 0 MB width x8 or x32 single rank
+ME: FW Partition Table      : OK
+ME: Bringup Loader Failure  : NO
+ME: Firmware Init Complete  : NO
+ME: Manufacturing Mode      : NO
+ME: Boot Options Present    : NO
+ME: Update In Progress      : NO
+ME: Current Working State   : Normal
+ME: Current Operation State : Bring up
+ME: Current Operation Mode  : Normal
+ME: Error Code              : No Error
+ME: Progress Phase          : BUP Phase
+ME: Power Management Event  : Pseudo-global reset
+ME: Progress Phase State    : 0x2b
+CBMEM:
+IMD: root @ 7bfff000 254 entries.
+IMD: root @ 7bffec00 62 entries.
+Relocate MRC DATA from ff7d0320 to 7bfdc000 (4064 bytes)
+CBFS: 'Master Header Locator' located CBFS at [700100:7fffc0)
+CBFS: Locating 'fallback/ramstage'
+CBFS: Found @ offset 2a380 size 1248d
+Decompressing stage fallback/ramstage @ 0x7bf9efc0 (227568 bytes)
+Loading module at 7bf9f000 with entry 7bf9f000. filesize: 0x26370 memsize: 0x378b0
+Processing 2533 relocs. Offset value of 0x7be9f000
+
+
+coreboot-4.3-315-g2a5a2fb-MattDevo Tue Feb 23 05:05:45 UTC 2016 ramstage starting...
+Moving GDT to 7bffe880...ok
+Normal boot.
+BS: BS_PRE_DEVICE times (us): entry 4 run 4 exit 4
+BS: BS_DEV_INIT_CHIPS times (us): entry 4 run 5 exit 4
+Enumerating buses...
+CPU_CLUSTER: 0 enabled
+DOMAIN: 0000 enabled
+PCI: pci_scan_bus for bus 00
+PCI: 00:00.0 [8086/0a04] enabled
+PCI: 00:02.0 [8086/0a06] enabled
+PCI: 00:03.0 [8086/0a0c] enabled
+PCI: 00:13.0: Disabling device
+PCI: 00:13.0 [8086/9c36] disabled No operations
+PCI: 00:14.0 [8086/9c31] enabled
+PCI: 00:15.0: Disabling device
+IOBP: set 0xce00aa07 to 0x00000100
+PCI: 00:15.1: Disabling device
+IOBP: set 0xce00aa47 to 0x00000100
+PCI: 00:15.2: Disabling device
+IOBP: set 0xce00aa87 to 0x00000100
+PCI: 00:15.3: Disabling device
+IOBP: set 0xce00aac7 to 0x00000100
+PCI: 00:15.4: Disabling device
+IOBP: set 0xce00ab07 to 0x00000100
+PCI: 00:15.5: Disabling device
+IOBP: set 0xce00ab47 to 0x00000100
+PCI: 00:15.6: Disabling device
+IOBP: set 0xce00ab87 to 0x00000100
+PCI: 00:16.0 [8086/9c3a] enabled
+PCI: 00:16.1: Disabling device
+PCI: 00:16.1 [8086/9c3b] disabled No operations
+PCI: 00:16.2: Disabling device
+PCI: 00:16.3: Disabling device
+PCI: 00:17.0: Disabling device
+IOBP: set 0xce00ae07 to 0x00000100
+PCI: 00:19.0: Disabling device
+PCI: 00:1b.0 [8086/9c20] enabled
+PCI: 00:1c.0 [8086/9c10] disabled
+PCI: 00:1c.1 [8086/9c12] disabled
+PCIe Root Port 3 ASPM is disabled
+PCI: 00:1c.2 [8086/9c14] enabled
+PCIe Root Port 4 ASPM is disabled
+PCI: 00:1c.3 [8086/9c16] enabled
+PCIe Root Port 5 ASPM is enabled
+IOBP: set 0xe9000c40 to 0x05050e00
+IOBP: set 0xe9000e40 to 0x05050e00
+IOBP: set 0xe9001040 to 0x05050e00
+IOBP: set 0xe9001240 to 0x05050e00
+PCI: 00:1c.4 [8086/9c18] enabled
+PCI: 00:1c.0: Disabling device
+PCI: 00:1c.1: Disabling device
+PCI: 00:1c.5: Disabling device
+PCH: PCIe map 1c.2 -> 1c.0
+PCH: PCIe map 1c.3 -> 1c.1
+PCH: PCIe map 1c.4 -> 1c.2
+PCH: PCIe map 1c.0 -> 1c.3
+PCH: PCIe map 1c.1 -> 1c.4
+PCI: 00:1c.5 [8086/9c1a] disabled
+PCI: 00:1d.0 [8086/9c26] enabled
+PCI: 00:1e.0: Disabling device
+PCI: 00:1f.0 [8086/9c45] enabled
+PCI: 00:1f.2 [8086/9c03] enabled
+PCI: 00:1f.3 [8086/9c22] enabled
+PCI: 00:1f.6 [8086/9c24] enabled
+PCI: pci_scan_bus for bus 01
+PCI: 01:00.0 [10ec/8168] enabled
+Enabling Common Clock Configuration
+ASPM: Enabled L1
+scan_bus: scanning of bus PCI: 00:1c.0 took 169 usecs
+PCI: pci_scan_bus for bus 02
+PCI: 02:00.0 [168c/0034] enabled
+Enabling Common Clock Configuration
+ASPM: Enabled L0s and L1
+scan_bus: scanning of bus PCI: 00:1c.1 took 170 usecs
+PCI: pci_scan_bus for bus 03
+scan_bus: scanning of bus PCI: 00:1c.2 took 30 usecs
+PNP: 002e.0 disabled
+PNP: 002e.1 enabled
+PNP: 002e.4 enabled
+PNP: 002e.7 enabled
+PNP: 002e.5 disabled
+PNP: 002e.6 disabled
+PNP: 002e.a disabled
+scan_bus: scanning of bus PCI: 00:1f.0 took 184 usecs
+scan_bus: scanning of bus PCI: 00:1f.3 took 6 usecs
+scan_bus: scanning of bus DOMAIN: 0000 took 1364 usecs
+scan_bus: scanning of bus Root Device took 1378 usecs
+done
+BS: BS_DEV_ENUMERATE times (us): entry 3 run 1419 exit 4
+found VGA at PCI: 00:02.0
+Setting up VGA for PCI: 00:02.0
+Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
+Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
+Allocating resources...
+Reading resources...
+mc_add_fixed_mmio_resources: Adding PCIEXBAR @ 60 0xf0000000-0xf3ffffff.
+mc_add_fixed_mmio_resources: Adding MCHBAR @ 48 0xfed10000-0xfed17fff.
+mc_add_fixed_mmio_resources: Adding DMIBAR @ 68 0xfed18000-0xfed18fff.
+mc_add_fixed_mmio_resources: Adding EPBAR @ 40 0xfed19000-0xfed19fff.
+mc_add_fixed_mmio_resources: Adding GDXCBAR @ 5420 0xfed84000-0xfed84fff.
+MC MAP: TOM: 0x80000000
+MC MAP: TOUUD: 0x100600000
+MC MAP: MESEG_BASE: 0x7f000000
+MC MAP: MESEG_LIMIT: 0x7fff0fffff
+MC MAP: REMAP_BASE: 0x100000000
+MC MAP: REMAP_LIMIT: 0x1005fffff
+MC MAP: TOLUD: 0x7ea00000
+MC MAP: BGSM: 0x7c800000
+MC MAP: BDSM: 0x7ca00000
+MC MAP: TESGMB: 0x7c000000
+MC MAP: GGC: 0x209
+Done reading resources.
+skipping PNP: 002e.4@f2 fixed resource, size=0!
+Setting resources...
+PCI: 00:02.0 10 <- [0x00e0000000 - 0x00e03fffff] size 0x00400000 gran 0x16 mem64
+PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64
+PCI: 00:02.0 20 <- [0x0000003000 - 0x000000303f] size 0x00000040 gran 0x06 io
+PCI: 00:03.0 10 <- [0x00e0710000 - 0x00e0713fff] size 0x00004000 gran 0x0e mem64
+PCI: 00:14.0 10 <- [0x00e0700000 - 0x00e070ffff] size 0x00010000 gran 0x10 mem64
+PCI: 00:16.0 10 <- [0x00e071c000 - 0x00e071c01f] size 0x00000020 gran 0x05 mem64
+PCI: 00:1b.0 10 <- [0x00e0714000 - 0x00e0717fff] size 0x00004000 gran 0x0e mem64
+PCI: 00:1c.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 01 io
+PCI: 00:1c.0 24 <- [0x00e0400000 - 0x00e04fffff] size 0x00100000 gran 0x14 bus 01 prefmem
+PCI: 00:1c.0 20 <- [0x00e0500000 - 0x00e05fffff] size 0x00100000 gran 0x14 bus 01 mem
+PCI: 01:00.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
+PCI: 01:00.0 18 <- [0x00e0500000 - 0x00e0500fff] size 0x00001000 gran 0x0c mem64
+PCI: 01:00.0 20 <- [0x00e0400000 - 0x00e0403fff] size 0x00004000 gran 0x0e prefmem64
+PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
+PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem
+PCI: 00:1c.1 20 <- [0x00e0600000 - 0x00e06fffff] size 0x00100000 gran 0x14 bus 02 mem
+PCI: 02:00.0 10 <- [0x00e0600000 - 0x00e067ffff] size 0x00080000 gran 0x13 mem64
+PCI: 02:00.0 30 <- [0x00e0680000 - 0x00e068ffff] size 0x00010000 gran 0x10 romem
+PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io
+PCI: 00:1c.2 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem
+PCI: 00:1c.2 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem
+PCI: 00:1d.0 10 <- [0x00e071a000 - 0x00e071a3ff] size 0x00000400 gran 0x0a mem
+PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
+PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
+PNP: 002e.4 60 <- [0x0000000700 - 0x0000000707] size 0x00000008 gran 0x03 io
+PNP: 002e.4 62 <- [0x0000000710 - 0x0000000713] size 0x00000004 gran 0x02 io
+PNP: 002e.4 70 <- [0x0000000009 - 0x0000000009] size 0x00000001 gran 0x00 irq
+PNP: 002e.4 f2 <- [0x0000000020 - 0x000000001f] size 0x00000000 gran 0x00 irq
+PNP: 002e.4 f4 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 irq
+PNP: 002e.4 fa <- [0x0000000012 - 0x0000000012] size 0x00000001 gran 0x00 irq
+PNP: 002e.7 60 <- [0x0000000720 - 0x0000000720] size 0x00000001 gran 0x00 io
+PNP: 002e.7 62 <- [0x0000000730 - 0x0000000737] size 0x00000008 gran 0x03 io
+PCI: 00:1f.2 10 <- [0x0000003060 - 0x0000003067] size 0x00000008 gran 0x03 io
+PCI: 00:1f.2 14 <- [0x0000003070 - 0x0000003073] size 0x00000004 gran 0x02 io
+PCI: 00:1f.2 18 <- [0x0000003068 - 0x000000306f] size 0x00000008 gran 0x03 io
+PCI: 00:1f.2 1c <- [0x0000003074 - 0x0000003077] size 0x00000004 gran 0x02 io
+PCI: 00:1f.2 20 <- [0x0000003040 - 0x000000305f] size 0x00000020 gran 0x05 io
+PCI: 00:1f.2 24 <- [0x00e0719000 - 0x00e07197ff] size 0x00000800 gran 0x0b mem
+PCI: 00:1f.3 10 <- [0x00e071b000 - 0x00e071b0ff] size 0x00000100 gran 0x08 mem64
+PCI: 00:1f.6 10 <- [0x00e0718000 - 0x00e0718fff] size 0x00001000 gran 0x0c mem64
+Done setting resources.
+Done allocating resources.
+BS: BS_DEV_RESOURCES times (us): entry 3 run 1292 exit 4
+Enabling resources...
+PCI: 00:00.0 subsystem <- 1ae0/c000
+PCI: 00:00.0 cmd <- 06
+PCI: 00:02.0 subsystem <- 1ae0/c000
+PCI: 00:02.0 cmd <- 03
+PCI: 00:03.0 subsystem <- 1ae0/c000
+PCI: 00:03.0 cmd <- 02
+PCI: 00:14.0 subsystem <- 1ae0/c000
+PCI: 00:14.0 cmd <- 102
+PCI: 00:16.0 subsystem <- 1ae0/c000
+PCI: 00:16.0 cmd <- 02
+PCI: 00:1b.0 subsystem <- 1ae0/c000
+PCI: 00:1b.0 cmd <- 102
+PCI: 00:1c.0 bridge ctrl <- 0003
+PCI: 00:1c.0 subsystem <- 1ae0/c000
+PCI: 00:1c.0 cmd <- 07
+PCI: 00:1c.1 bridge ctrl <- 0003
+PCI: 00:1c.1 subsystem <- 1ae0/c000
+PCI: 00:1c.1 cmd <- 06
+PCI: 00:1c.2 bridge ctrl <- 0003
+PCI: 00:1c.2 subsystem <- 1ae0/c000
+PCI: 00:1c.2 cmd <- 00
+PCI: 00:1d.0 subsystem <- 1ae0/c000
+PCI: 00:1d.0 cmd <- 102
+PCI: 00:1f.0 subsystem <- 1ae0/c000
+PCI: 00:1f.0 cmd <- 107
+PCI: 00:1f.2 subsystem <- 1ae0/c000
+PCI: 00:1f.2 cmd <- 103
+PCI: 00:1f.3 subsystem <- 1ae0/c000
+PCI: 00:1f.3 cmd <- 103
+PCI: 00:1f.6 subsystem <- 1ae0/c000
+PCI: 00:1f.6 cmd <- 102
+PCI: 01:00.0 cmd <- 03
+PCI: 02:00.0 cmd <- 02
+done.
+BS: BS_DEV_ENABLE times (us): entry 4 run 174 exit 4
+Initializing devices...
+Root Device init ...
+CBFS: 'Master Header Locator' located CBFS at [700100:7fffc0)
+CBFS: Locating 'vpd.bin'
+CBFS: Found @ offset 57580 size 4000
+Located 'ethernet_mac' in VPD
+Realtek NIC io_base = 0x2000
+Programming MAC Address
+Root Device init finished in 2050 usecs
+CPU_CLUSTER: 0 init ...
+CPU has 2 cores, 2 threads enabled.
+MTRR: Physical address space:
+0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
+0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
+0x00000000000c0000 - 0x000000007c800000 size 0x7c740000 type 6
+0x000000007c800000 - 0x00000000d0000000 size 0x53800000 type 0
+0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
+0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
+0x0000000100000000 - 0x0000000100600000 size 0x00600000 type 6
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+MTRR: default type WB/UC MTRR counts: 7/6.
+MTRR: UC selected as default type.
+MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
+MTRR: 1 base 0x000000007c800000 mask 0x0000007fff800000 type 0
+MTRR: 2 base 0x000000007d000000 mask 0x0000007fff000000 type 0
+MTRR: 3 base 0x000000007e000000 mask 0x0000007ffe000000 type 0
+MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
+MTRR: 5 base 0x0000000100000000 mask 0x0000007f00000000 type 6
+
+MTRR check
+Fixed MTRRs   : Enabled
+Variable MTRRs: Enabled
+
+Initializing VR config.
+PCODE: 24MHz BLCK calibration response: 0
+PCODE: 24MHz BLCK calibration value: 0x85000000
+PCH Power: PCODE Levels 0x3f1c50c2 0x004cd2c9
+CBFS: 'Master Header Locator' located CBFS at [700100:7fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 1ff00 size a400
+microcode: sig=0x40651 pf=0x40 revision=0x1c
+Setting up SMI for CPU
+Loading module at 00038000 with entry 00038000. filesize: 0x160 memsize: 0x160
+Processing 10 relocs. Offset value of 0x00038000
+SMM Module: stub loaded at 00038000. Will call 7bfb3fa0(7bfd2820)
+Installing SMM handler to 0x7c000000
+Loading module at 7c010000 with entry 7c0100a0. filesize: 0x11d0 memsize: 0x51f0
+Processing 45 relocs. Offset value of 0x7c010000
+Loading module at 7c008000 with entry 7c008000. filesize: 0x160 memsize: 0x160
+Processing 10 relocs. Offset value of 0x7c008000
+SMM Module: placing jmp sequence at 7c007c00 rel16 0x03fd
+SMM Module: stub loaded at 7c008000. Will call 7c0100a0(00000000)
+Initializing Southbridge SMI...
+In relocation handler: cpu 0
+New SMBASE=0x7c000000 IEDBASE=0x7c400000
+Writing SMRR. base = 0x7c000006, mask=0xff800800
+Relocation complete.
+CPU: Intel(R) Celeron(R) 2957U @ 1.40GHz.
+Loading module at 00030000 with entry 00030000. filesize: 0x130 memsize: 0x130
+Processing 16 relocs. Offset value of 0x00030000
+Attempting to start 1 APs
+Waiting for 10ms after sending INIT.
+Waiting for 1st SIPI to complete...done.
+Waiting for 2nd SIPI to complete...done.
+AP: slot 1 apic_id 2.
+In relocation handler: cpu 1
+New SMBASE=0x7bfffc00 IEDBASE=0x7c400000
+Writing SMRR. base = 0x7c000006, mask=0xff800800
+Relocation complete.
+Initializing CPU #0
+CPU: vendor Intel device 40651
+CPU: family 06, model 45, stepping 01
+Setting up local apic... apic_id: 0x00 done.
+VMX is locked, so enable_vmx will do nothing
+haswell: energy policy set to 6
+haswell: frequency set to 1400
+Turbo is unavailable
+CPU #0 initialized
+Initializing CPU #1
+CPU: vendor Intel device 40651
+CPU: family 06, model 45, stepping 01
+Setting up local apic... apic_id: 0x02 done.
+VMX is locked, so enable_vmx will do nothing
+haswell: energy policy set to 6
+haswell: frequency set to 1400
+CPU #1 initialized
+Enabling SMIs.
+Locking SMM.
+CPU_CLUSTER: 0 init finished in 14360 usecs
+PCI: 00:00.0 init ...
+Set BIOS_RESET_CPL
+CPU TDP: 15 Watts
+PCI: 00:00.0 init finished in 1013 usecs
+PCI: 00:02.0 init ...
+GT Power Management Init
+GT Power Management Init (post VBIOS)
+PCI: 00:02.0 init finished in 131 usecs
+PCI: 00:03.0 init ...
+Mini-HD: base = e0710000
+HDA: Initializing codec #0
+HDA: codec viddid: 80862807
+HDA: verb loaded.
+PCI: 00:03.0 init finished in 1360 usecs
+PCI: 00:14.0 init ...
+IOBP: set 0xe5004001 to 0x000000ce
+PCI: 00:14.0 init finished in 1096 usecs
+PCI: 00:16.0 init ...
+ME: FW Partition Table      : OK
+ME: Bringup Loader Failure  : NO
+ME: Firmware Init Complete  : NO
+ME: Manufacturing Mode      : NO
+ME: Boot Options Present    : NO
+ME: Update In Progress      : NO
+ME: Current Working State   : Normal
+ME: Current Operation State : M0 with UMA
+ME: Current Operation Mode  : Normal
+ME: Error Code              : No Error
+ME: Progress Phase          : uKernel Phase
+ME: Power Management Event  : Pseudo-global reset
+ME: Progress Phase State    : Unknown phase: 0x02 sate: 0x00
+ME: BIOS path: Normal
+ME: Extend SHA-256: 4822ca12b90cdd73e39caab8cdba777ac831451069f18f0be9b0340e9ad356e3
+ME MBP: Header: items: 9, size dw: 37
+ME: found version 9.5.13.1706
+ME: Wake Event to ME Reset:      0 ms
+ME: ME Reset to Platform Reset:  7 ms
+ME: Platform Reset to CPU Reset: 58 ms
+ME: ICC SET CLOCK ENABLES 0x01220000
+PCI: 00:16.0 init finished in 61 usecs
+PCI: 00:1b.0 init ...
+Azalia: base = e0714000
+Azalia: codec_mask = 01
+HDA: Initializing codec #0
+HDA: codec viddid: 10ec0283
+HDA: verb loaded.
+PCI: 00:1b.0 init finished in 3316 usecs
+PCI: 00:1c.0 init ...
+Initializing PCH PCIe bridge.
+PCI: 00:1c.0 init finished in 10 usecs
+PCI: 00:1c.1 init ...
+Initializing PCH PCIe bridge.
+PCI: 00:1c.1 init finished in 10 usecs
+PCI: 00:1c.2 init ...
+Initializing PCH PCIe bridge.
+PCI: 00:1c.2 init finished in 10 usecs
+PCI: 00:1d.0 init ...
+EHCI: Setting up controller.. IOBP: set 0xe5004001 to 0x000000ce
+done.
+PCI: 00:1d.0 init finished in 36 usecs
+PCI: 00:1f.0 init ...
+pch: lpc_init
+IOAPIC: Initializing IOAPIC at 0xfec00000
+IOAPIC: Bootstrap Processor Local APIC = 0x00
+IOAPIC: ID = 0x02
+Set power state keep after power failure.
+NMI sources disabled.
+LynxPoint LP PM init
+IOBP: set 0xed00015c to 0x1bc33700
+IOBP: set 0xed000118 to 0x00c00000
+IOBP: set 0xed000120 to 0x00245560
+IOBP: set 0xca000000 to 0x00000009
+IOBP: set 0xcf000000 to 0x00007007
+IOBP: set 0xce00c000 to 0x00000000
+rtc_failed = 0x0
+RTC Init
+Disabling ACPI via APMC:
+done.
+PCI: 00:1f.0 init finished in 366 usecs
+PCI: 00:1f.2 init ...
+SATA: Initializing...
+SATA: Controller in AHCI mode.
+ABAR: e0719000
+PCI: 00:1f.2 init finished in 30 usecs
+PCI: 00:1f.3 init ...
+PCI: 00:1f.3 init finished in 8 usecs
+PCI: 00:1f.6 init ...
+PCI: 00:1f.6 init finished in 3 usecs
+PCI: 01:00.0 init ...
+PCI: 01:00.0 init finished in 3 usecs
+PCI: 02:00.0 init ...
+PCI: 02:00.0 init finished in 3 usecs
+PNP: 002e.1 init ...
+PNP: 002e.1 init finished in 3 usecs
+PNP: 002e.4 init ...
+PNP: 002e.4 init finished in 1061 usecs
+PNP: 002e.7 init ...
+PNP: 002e.7 init finished in 3 usecs
+Devices initialized
+BS: BS_DEV_INIT times (us): entry 10 run 25020 exit 2
+Finalize devices...
+Devices finalized
+BS: BS_POST_DEVICE times (us): entry 2 run 5 exit 3
+BS: BS_OS_RESUME_CHECK times (us): entry 2 run 3 exit 3
+Updating MRC cache data.
+CBFS: 'Master Header Locator' located CBFS at [700100:7fffc0)
+CBFS: Locating 'mrc.cache'
+CBFS: Found @ offset fec0 size 10000
+find_current_mrc_cache_local: picked entry 0 from cache block
+MRC data in flash is up to date. No update.
+CBFS: 'Master Header Locator' located CBFS at [700100:7fffc0)
+CBFS: Locating 'fallback/dsdt.aml'
+CBFS: Found @ offset 9840 size 3d7c
+CBFS: 'Master Header Locator' located CBFS at [700100:7fffc0)
+CBFS: Locating 'fallback/slic'
+CBFS: 'fallback/slic' not found.
+ACPI: Writing ACPI tables at 7bf31000.
+ACPI:    * FACS
+ACPI:    * DSDT
+ACPI:    * FADT
+ACPI: added table 1/32, length now 40
+ACPI:     * SSDT
+Found 1 CPU(s) with 2 core(s) each.
+PSS: 1400MHz power 15000 control 0xe00 status 0xe00
+PSS: 1200MHz power 12559 control 0xc00 status 0xc00
+PSS: 1000MHz power 10217 control 0xa00 status 0xa00
+PSS: 800MHz power 7982 control 0x800 status 0x800
+PSS: 1400MHz power 15000 control 0xe00 status 0xe00
+PSS: 1200MHz power 12559 control 0xc00 status 0xc00
+PSS: 1000MHz power 10217 control 0xa00 status 0xa00
+PSS: 800MHz power 7982 control 0x800 status 0x800
+ACPI: added table 2/32, length now 44
+ACPI:    * MCFG
+ACPI: added table 3/32, length now 48
+ACPI:    * TCPA
+TCPA log created at 7bf21000
+ACPI: added table 4/32, length now 52
+ACPI:    * MADT
+ACPI: added table 5/32, length now 56
+current = 7bf35b10
+ACPI:    * HPET
+ACPI: added table 6/32, length now 60
+ACPI:     * SSDT2
+ACPI: added table 7/32, length now 64
+current = 7bf35bb0
+ACPI: done.
+ACPI tables: 19376 bytes.
+smbios_write_tables: 7bf20000
+Root Device (Google Panther)
+CPU_CLUSTER: 0 (Intel i7 (Haswell) integrated Northbridge)
+APIC: 00 (Intel Haswell CPU)
+APIC: acac (Intel Haswell CPU)
+DOMAIN: 0000 (Intel i7 (Haswell) integrated Northbridge)
+PCI: 00:00.0 (Intel i7 (Haswell) integrated Northbridge)
+PCI: 00:02.0 (Intel i7 (Haswell) integrated Northbridge)
+PCI: 00:03.0 (Intel i7 (Haswell) integrated Northbridge)
+PCI: 00:13.0 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:14.0 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:15.0 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:15.1 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:15.2 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:15.3 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:15.4 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:15.5 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:15.6 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:16.0 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:16.1 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:16.2 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:16.3 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:17.0 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:19.0 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:1b.0 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:1c.3 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:1c.4 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:1c.0 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:1c.1 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:1c.2 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:1c.5 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:1d.0 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:1e.0 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:1f.0 (Intel Series 8 (Lynx Point) Southbridge)
+PNP: 002e.0 (ITE IT8772F Super I/O)
+PNP: 002e.1 (ITE IT8772F Super I/O)
+PNP: 002e.4 (ITE IT8772F Super I/O)
+PNP: 002e.7 (ITE IT8772F Super I/O)
+PNP: 002e.5 (ITE IT8772F Super I/O)
+PNP: 002e.6 (ITE IT8772F Super I/O)
+PNP: 002e.a (ITE IT8772F Super I/O)
+PCI: 00:1f.2 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:1f.3 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 00:1f.6 (Intel Series 8 (Lynx Point) Southbridge)
+PCI: 01:00.0 (unknown)
+PCI: 02:00.0 (unknown)
+APIC: 02 (unknown)
+SMBIOS tables: 321 bytes.
+Writing table forward entry at 0x00000500
+Wrote coreboot table at: 00000500, 0x10 bytes, checksum 3ed
+Table forward entry ends at 0x00000528.
+... aligned to 0x00001000
+Writing coreboot table at 0x7bf18000
+rom_table_end = 0x7bf18000
+... aligned to 0x7bf20000
+ 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
+ 1. 0000000000001000-000000000009ffff: RAM
+ 2. 00000000000a0000-00000000000fffff: RESERVED
+ 3. 0000000000100000-000000007bf17fff: RAM
+ 4. 000000007bf18000-000000007bffffff: CONFIGURATION TABLES
+ 5. 000000007c000000-000000007e9fffff: RESERVED
+ 6. 00000000f0000000-00000000f3ffffff: RESERVED
+ 7. 00000000fed10000-00000000fed19fff: RESERVED
+ 8. 00000000fed84000-00000000fed84fff: RESERVED
+ 9. 0000000100000000-00000001005fffff: RAM
+CBFS: 'Master Header Locator' located CBFS at [700100:7fffc0)
+No FMAP found at 0 offset.
+Wrote coreboot table at: 7bf18000, 0x374 bytes, checksum afcd
+coreboot table: 908 bytes.
+IMD ROOT    0. 7bfff000 00001000
+IMD SMALL   1. 7bffe000 00001000
+CONSOLE     2. 7bfde000 00020000
+TIME STAMP  3. 7bfdd000 00000400
+MRC DATA    4. 7bfdc000 00000ff0
+ROMSTG STCK 5. 7bfd7000 00005000
+RAMSTAGE    6. 7bf9e000 00039000
+57a9e100    7. 7bf66000 000378b0
+ACPI GNVS   8. 7bf65000 00001000
+SMM BACKUP  9. 7bf55000 00010000
+ACPI       10. 7bf31000 00024000
+TCPA LOG   11. 7bf21000 00010000
+SMBIOS     12. 7bf20000 00000800
+COREBOOT   13. 7bf18000 00008000
+IMD small region:
+  IMD ROOT    0. 7bffec00 00000400
+  CAR GLOBALS 1. 7bffeac0 00000140
+  ROMSTAGE    2. 7bffeaa0 00000004
+  57a9e000    3. 7bffea80 00000010
+  GDT         4. 7bffe880 00000200
+  GNVS PTR    5. 7bffe860 00000004
+BS: BS_WRITE_TABLES times (us): entry 4970 run 3355 exit 3
+CBFS: 'Master Header Locator' located CBFS at [700100:7fffc0)
+CBFS: Locating 'fallback/payload'
+CBFS: Found @ offset 3c880 size ac46
+Loading segment from rom address 0xfff3c9b8
+  code (compression=1)
+  New segment dstaddr 0xebb08 memsize 0x144f8 srcaddr 0xfff3c9f0 filesize 0xac0e
+Loading segment from rom address 0xfff3c9d4
+  Entry Point 0x000ff06e
+Payload being loaded below 1MiB without region being marked as RAM usable.
+Loading Segment: addr: 0x00000000000ebb08 memsz: 0x00000000000144f8 filesz: 0x000000000000ac0e
+Post relocation: addr: 0x00000000000ebb08 memsz: 0x00000000000144f8 filesz: 0x000000000000ac0e
+using LZMA
+dest 000ebb08, end 00100000, bouncebuffer ffffffff
+BS: BS_PAYLOAD_LOAD times (us): entry 2 run 15535 exit 2
+PCH watchdog disabled
+Jumping to boot code at 000ff06e(7bf18000)
+SeaBIOS (version rel-1.9.0-115-g8276dcb-20160222-MattDevo)
+BUILD: gcc: (Ubuntu 5.2.1-22ubuntu2) 5.2.1 20151010 binutils: (GNU Binutils for Ubuntu) 2.25.1
+Found coreboot cbmem console @ 7bfde000
+Found mainboard Google Panther
+malloc preinit
+Relocating init from 0x000eccc0 to 0x7bed0aa0 (size 29888)
+malloc init
+Found CBFS header at 0xfff00138
+Add romfile: cbfs master header (size=32)
+Add romfile: fallback/romstage (size=35908)
+Add romfile: config (size=870)
+Add romfile: revision (size=578)
+Add romfile: cmos_layout.bin (size=1128)
+Add romfile: fallback/dsdt.aml (size=15740)
+Add romfile: etc/boot-menu-wait (size=8)
+Add romfile: bootorder (size=466)
+Add romfile: links (size=132)
+Add romfile:  (size=9432)
+Add romfile: mrc.cache (size=65536)
+Add romfile: cpu_microcode_blob.bin (size=41984)
+Add romfile: fallback/ramstage (size=74893)
+Add romfile: fallback/payload (size=44102)
+Add romfile: pci8086,0406.rom (size=65536)
+Add romfile: vpd.bin (size=16384)
+Add romfile:  (size=280792)
+Add romfile: mrc.bin (size=191236)
+Add romfile:  (size=199704)
+Add romfile: bootblock (size=2096)
+Copying romfile 'links' (len 132)
+Copying data 132@0xfff0da38 to 132@0x7becf940
+Add romfile: pci8086,0a06.rom (size=65536)
+Add romfile: pci8086,0a16.rom (size=65536)
+Add romfile: pci8086,0a26.rom (size=65536)
+init ivt
+init bda
+Copying romfile 'bootorder' (len 466)
+Copying data 466@0xfff0d7f8 to 466@0x7becf4c0
+boot order:
+1: /pci@i0cf8/*@1f,2/drive@0/disk@0
+2: /pci@i0cf8/usb@14/usb-*@0
+3: /pci@i0cf8/usb@14/usb-*@1
+4: /pci@i0cf8/usb@14/usb-*@2
+5: /pci@i0cf8/usb@14/usb-*@3
+6: /pci@i0cf8/usb@14/usb-*@4
+7: /pci@i0cf8/usb@14/usb-*@5
+8: /pci@i0cf8/usb@14/usb-*@6
+9: /pci@i0cf8/usb@14/usb-*@7
+10: /pci@i0cf8/usb@1d/hub@1/*@0
+11: /pci@i0cf8/usb@1d/hub@1/*@1
+12: /pci@i0cf8/usb@1d/hub@1/*@2
+13: /pci@i0cf8/usb@1d/hub@1/*@3
+14: /pci@i0cf8/usb@1d/hub@1/*@4
+15: /pci@i0cf8/usb@1d/hub@1/*@5
+16: /pci@i0cf8/usb@1d/hub@1/*@6
+17: /pci@i0cf8/usb@1d/hub@1/*@7
+18: 
+19: 
+init bios32
+init PMM
+init PNPBIOS table
+init keyboard
+init pic
+math cp init
+PCI probe
+PCI device 00:00.0 (vd=8086:0a04 c=0600)
+PCI device 00:02.0 (vd=8086:0a06 c=0300)
+PCI device 00:03.0 (vd=8086:0a0c c=0403)
+PCI device 00:14.0 (vd=8086:9c31 c=0c03)
+PCI device 00:16.0 (vd=8086:9c3a c=0780)
+PCI device 00:1b.0 (vd=8086:9c20 c=0403)
+PCI device 00:1c.0 (vd=8086:9c14 c=0604)
+PCI device 00:1c.1 (vd=8086:9c16 c=0604)
+PCI device 00:1c.2 (vd=8086:9c18 c=0604)
+PCI device 00:1f.0 (vd=8086:9c45 c=0601)
+PCI device 00:1f.2 (vd=8086:9c03 c=0106)
+PCI device 00:1f.3 (vd=8086:9c22 c=0c05)
+PCI device 00:1f.6 (vd=8086:9c24 c=1180)
+PCI device 01:00.0 (vd=10ec:8168 c=0200)
+PCI device 02:00.0 (vd=168c:0034 c=0280)
+Found 15 PCI devices (max PCI bus is 03)
+Relocating coreboot bios tables
+Copying SMBIOS entry point from 0x7bf20000 to 0x000f4160
+Copying ACPI RSDP from 0x7bf31000 to 0x000f4130
+rsdp=0x000f4130
+rsdt=0x7bf31030
+fadt=0x7bf35010
+pm_tmr_blk=1008
+Using pmtimer, ioport 0x1008
+init timer
+Scan for VGA option rom
+Attempting to init PCI bdf 00:02.0 (vd 8086:0a06)
+Copying data 65536@0xfff47648 to 65536@0x000c0000
+Checking rom 0x000c0000 (sig aa55 size 128)
+Running option rom at c000:0003
+Turning on vga text mode console
+SeaBIOS (version rel-1.9.0-115-g8276dcb-20160222-MattDevo)
+init usb
+XHCI init on dev 00:14.0: regs @ 0xe0700000, 13 ports, 32 slots, 32 byte contexts
+XHCI    protocol USB  2.00, 8 ports (offset 1), def 3018
+XHCI    protocol USB  3.00, 4 ports (offset 10), def 1000
+XHCI    extcap 0xc1 @ 0xe0708040
+XHCI    extcap 0xc0 @ 0xe0708070
+XHCI    extcap 0x1 @ 0xe0708460
+XHCI    extcap 0xa @ 0xe0708480
+configure_xhci: resetting
+configure_xhci: setup 16 scratch pad buffers
+xhci_hub_reset port #2: 0x000206e1, powered, pls 7, speed 1 [Full]
+XHCI port #2: 0x00200603, powered, enabled, pls 0, speed 1 [Full]
+set_address 0x7bf17fb0
+xhci_alloc_pipe: usbdev 0x7becee40, ring 0x7bf17900, slotid 0, epid 1
+xhci_cmd_enable_slot:
+xhci_trb_queue: ring 0x7bf17d00 [nidx 1, len 0]
+xhci_process_events port #2: 0x00200603, powered, enabled, pls 0, speed 1 [Full]
+xhci_process_events port #4: 0x000206e1, powered, pls 7, speed 1 [Full]
+xhci_process_events port #7: 0x000206e1, powered, pls 7, speed 1 [Full]
+xhci_process_events port #2: 0x00000603, powered, enabled, pls 0, speed 1 [Full]
+xhci_process_events: ring 0x7bf17d00 [trb 0x7bf17d00, evt 0x7bf17e00, type 33, eidx 1, cc 1]
+xhci_alloc_pipe: enable slot: got slotid 1
+xhci_cmd_address_device: slotid 1
+xhci_trb_queue: ring 0x7bf17d00 [nidx 2, len 0]
+xhci_process_events: ring 0x7bf17d00 [trb 0x7bf17d10, evt 0x7bf17e00, type 33, eidx 2, cc 1]
+xhci_realloc_pipe: usbdev 0x7becee40, ring 0x7bf17900, slotid 1, epid 1
+config_usb: 0x7bf17a20
+xhci_trb_queue: ring 0x7bf17900 [nidx 1, len 8]
+xhci_trb_queue: ring 0x7bf17900 [nidx 2, len 8]
+xhci_trb_queue: ring 0x7bf17900 [nidx 3, len 0]
+xhci_xfer_kick: ring 0x7bf17900, slotid 1, epid 1
+xhci_process_events: ring 0x7bf17900 [trb 0x7bf17920, evt 0x7bf17a00, type 32, eidx 3, cc 1]
+device rev=0200 cls=00 sub=00 proto=00 size=64
+xhci_realloc_pipe: usbdev 0x7becee40, ring 0x7bf17900, slotid 1, epid 1
+xhci_realloc_pipe: reconf ctl endpoint pkt size: 8 -> 64
+xhci_cmd_evaluate_context: slotid 1, add 0x2, del 0x0
+xhci_trb_queue: ring 0x7bf17d00 [nidx 3, len 0]
+xhci_process_events: ring 0x7bf17d00 [trb 0x7bf17d20, evt 0x7bf17e00, type 33, eidx 3, cc 1]
+xhci_trb_queue: ring 0x7bf17900 [nidx 4, len 8]
+xhci_trb_queue: ring 0x7bf17900 [nidx 5, len 9]
+xhci_trb_queue: ring 0x7bf17900 [nidx 6, len 0]
+xhci_xfer_kick: ring 0x7bf17900, slotid 1, epid 1
+xhci_process_events: ring 0x7bf17900 [trb 0x7bf17950, evt 0x7bf17a00, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x7bf17900 [nidx 7, len 8]
+xhci_trb_queue: ring 0x7bf17900 [nidx 8, len 84]
+xhci_trb_queue: ring 0x7bf17900 [nidx 9, len 0]
+xhci_xfer_kick: ring 0x7bf17900, slotid 1, epid 1
+xhci_process_events: ring 0x7bf17900 [trb 0x7bf17980, evt 0x7bf17a00, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x7bf17900 [nidx 10, len 8]
+xhci_trb_queue: ring 0x7bf17900 [nidx 11, len 0]
+xhci_xfer_kick: ring 0x7bf17900, slotid 1, epid 1
+xhci_process_events: ring 0x7bf17900 [trb 0x7bf179a0, evt 0x7bf17a00, type 32, eidx 11, cc 1]
+usb_hid_setup 0x7bf17a20
+xhci_trb_queue: ring 0x7bf17900 [nidx 12, len 8]
+xhci_trb_queue: ring 0x7bf17900 [nidx 13, len 0]
+xhci_xfer_kick: ring 0x7bf17900, slotid 1, epid 1
+xhci_process_events: ring 0x7bf17900 [trb 0x7bf179c0, evt 0x7bf17a00, type 32, eidx 13, cc 1]
+xhci_trb_queue: ring 0x7bf17900 [nidx 14, len 8]
+xhci_trb_queue: ring 0x7bf17900 [nidx 15, len 0]
+xhci_xfer_kick: ring 0x7bf17900, slotid 1, epid 1
+xhci_process_events: ring 0x7bf17900 [trb 0x7bf179e0, evt 0x7bf17a00, type 32, eidx 15, cc 1]
+xhci_alloc_pipe: usbdev 0x7becee40, ring 0x000ef600, slotid 0, epid 3
+xhci_cmd_configure_endpoint: slotid 1, add 0x9, del 0x0
+xhci_trb_queue: ring 0x7bf17d00 [nidx 4, len 0]
+xhci_process_events: ring 0x7bf17d00 [trb 0x7bf17d30, evt 0x7bf17e00, type 33, eidx 4, cc 1]
+USB keyboard initialized
+xhci_hub_reset port #4: 0x000006e1, powered, pls 7, speed 1 [Full]
+xhci_trb_queue: ring 0x000ef600 [nidx 1, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+XHCI port #4: 0x00200603, powered, enabled, pls 0, speed 1 [Full]
+set_address 0x7bf17fb0
+xhci_alloc_pipe: usbdev 0x7becee40, ring 0x7bf17200, slotid 0, epid 1
+xhci_cmd_enable_slot:
+xhci_trb_queue: ring 0x7bf17d00 [nidx 5, len 0]
+xhci_process_events: ring 0x000ef600 [trb 0x000ef600, evt 0x000ef700, type 32, eidx 1, cc 1]
+xhci_process_events port #4: 0x00200603, powered, enabled, pls 0, speed 1 [Full]
+xhci_process_events: ring 0x7bf17d00 [trb 0x7bf17d40, evt 0x7bf17e00, type 33, eidx 5, cc 1]
+xhci_alloc_pipe: enable slot: got slotid 2
+xhci_cmd_address_device: slotid 2
+xhci_trb_queue: ring 0x7bf17d00 [nidx 6, len 0]
+xhci_process_events: ring 0x7bf17d00 [trb 0x7bf17d50, evt 0x7bf17e00, type 33, eidx 6, cc 1]
+xhci_realloc_pipe: usbdev 0x7becee40, ring 0x7bf17200, slotid 2, epid 1
+config_usb: 0x7bf17320
+xhci_trb_queue: ring 0x7bf17200 [nidx 1, len 8]
+xhci_trb_queue: ring 0x7bf17200 [nidx 2, len 8]
+xhci_trb_queue: ring 0x7bf17200 [nidx 3, len 0]
+xhci_xfer_kick: ring 0x7bf17200, slotid 2, epid 1
+xhci_process_events: ring 0x7bf17200 [trb 0x7bf17220, evt 0x7bf17300, type 32, eidx 3, cc 1]
+device rev=0110 cls=e0 sub=01 proto=01 size=64
+xhci_realloc_pipe: usbdev 0x7becee40, ring 0x7bf17200, slotid 2, epid 1
+xhci_realloc_pipe: reconf ctl endpoint pkt size: 8 -> 64
+xhci_cmd_evaluate_context: slotid 2, add 0x2, del 0x0
+xhci_trb_queue: ring 0x7bf17d00 [nidx 7, len 0]
+xhci_process_events: ring 0x7bf17d00 [trb 0x7bf17d60, evt 0x7bf17e00, type 33, eidx 7, cc 1]
+xhci_trb_queue: ring 0x7bf17200 [nidx 4, len 8]
+xhci_trb_queue: ring 0x7bf17200 [nidx 5, len 9]
+xhci_trb_queue: ring 0x7bf17200 [nidx 6, len 0]
+xhci_xfer_kick: ring 0x7bf17200, slotid 2, epid 1
+xhci_process_events: ring 0x7bf17200 [trb 0x7bf17250, evt 0x7bf17300, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x7bf17200 [nidx 7, len 8]
+xhci_trb_queue: ring 0x7bf17200 [nidx 8, len 177]
+xhci_trb_queue: ring 0x7bf17200 [nidx 9, len 0]
+xhci_xfer_kick: ring 0x7bf17200, slotid 2, epid 1
+xhci_process_events: ring 0x7bf17200 [trb 0x7bf17280, evt 0x7bf17300, type 32, eidx 9, cc 1]
+xhci_hub_reset port #7: 0x000006e1, powered, pls 7, speed 1 [Full]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 2, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+XHCI port #7: 0x00200e03, powered, enabled, pls 0, speed 3 [High]
+set_address 0x7bf17fb0
+xhci_alloc_pipe: usbdev 0x7becee40, ring 0x7bf17000, slotid 0, epid 1
+xhci_cmd_enable_slot:
+xhci_trb_queue: ring 0x7bf17d00 [nidx 8, len 0]
+xhci_process_events: ring 0x000ef600 [trb 0x000ef610, evt 0x000ef700, type 32, eidx 2, cc 1]
+xhci_process_events port #7: 0x00200e03, powered, enabled, pls 0, speed 3 [High]
+xhci_process_events: ring 0x7bf17d00 [trb 0x7bf17d70, evt 0x7bf17e00, type 33, eidx 8, cc 1]
+xhci_alloc_pipe: enable slot: got slotid 3
+xhci_cmd_address_device: slotid 3
+xhci_trb_queue: ring 0x7bf17d00 [nidx 9, len 0]
+xhci_process_events: ring 0x7bf17d00 [trb 0x7bf17d80, evt 0x7bf17e00, type 33, eidx 9, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 3, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_realloc_pipe: usbdev 0x7becee40, ring 0x7bf17000, slotid 3, epid 1
+config_usb: 0x7bf17120
+xhci_trb_queue: ring 0x7bf17000 [nidx 1, len 8]
+xhci_trb_queue: ring 0x7bf17000 [nidx 2, len 8]
+xhci_trb_queue: ring 0x7bf17000 [nidx 3, len 0]
+xhci_xfer_kick: ring 0x7bf17000, slotid 3, epid 1
+xhci_process_events: ring 0x7bf17000 [trb 0x7bf17020, evt 0x7bf17100, type 32, eidx 3, cc 1]
+device rev=0200 cls=00 sub=00 proto=00 size=64
+xhci_realloc_pipe: usbdev 0x7becee40, ring 0x7bf17000, slotid 3, epid 1
+xhci_trb_queue: ring 0x7bf17000 [nidx 4, len 8]
+xhci_trb_queue: ring 0x7bf17000 [nidx 5, len 9]
+xhci_trb_queue: ring 0x7bf17000 [nidx 6, len 0]
+xhci_xfer_kick: ring 0x7bf17000, slotid 3, epid 1
+xhci_process_events: ring 0x7bf17000 [trb 0x7bf17050, evt 0x7bf17100, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x7bf17000 [nidx 7, len 8]
+xhci_trb_queue: ring 0x7bf17000 [nidx 8, len 32]
+xhci_trb_queue: ring 0x7bf17000 [nidx 9, len 0]
+xhci_xfer_kick: ring 0x7bf17000, slotid 3, epid 1
+xhci_process_events: ring 0x7bf17000 [trb 0x7bf17080, evt 0x7bf17100, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x7bf17000 [nidx 10, len 8]
+xhci_trb_queue: ring 0x7bf17000 [nidx 11, len 0]
+xhci_xfer_kick: ring 0x7bf17000, slotid 3, epid 1
+xhci_process_events: ring 0x7bf17000 [trb 0x7bf170a0, evt 0x7bf17100, type 32, eidx 11, cc 1]
+xhci_alloc_pipe: usbdev 0x7becee40, ring 0x000ef400, slotid 0, epid 3
+xhci_cmd_configure_endpoint: slotid 3, add 0x9, del 0x0
+xhci_trb_queue: ring 0x7bf17d00 [nidx 10, len 0]
+xhci_process_events: ring 0x7bf17d00 [trb 0x7bf17d90, evt 0x7bf17e00, type 33, eidx 10, cc 1]
+xhci_alloc_pipe: usbdev 0x7becee40, ring 0x000ef200, slotid 0, epid 4
+xhci_cmd_configure_endpoint: slotid 3, add 0x11, del 0x0
+xhci_trb_queue: ring 0x7bf17d00 [nidx 11, len 0]
+xhci_process_events: ring 0x7bf17d00 [trb 0x7bf17da0, evt 0x7bf17e00, type 33, eidx 11, cc 1]
+xhci_trb_queue: ring 0x7bf17000 [nidx 12, len 8]
+xhci_trb_queue: ring 0x7bf17000 [nidx 13, len 1]
+xhci_trb_queue: ring 0x7bf17000 [nidx 14, len 0]
+xhci_xfer_kick: ring 0x7bf17000, slotid 3, epid 1
+xhci_process_events: ring 0x000ef600 [trb 0x000ef620, evt 0x000ef700, type 32, eidx 3, cc 1]
+xhci_process_events: ring 0x7bf17000 [trb 0x7bf170d0, evt 0x7bf17100, type 32, eidx 14, cc 1]
+Searching bootorder for: /pci@i0cf8/usb@14/storage@7/*@0/*@0,0
+Searching bootorder for: /pci@i0cf8/usb@14/usb-*@7
+xhci_trb_queue: ring 0x000ef200 [nidx 1, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef200, evt 0x000ef300, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 1, len 36]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef400, evt 0x000ef500, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 2, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef410, evt 0x000ef500, type 32, eidx 2, cc 1]
+USB MSC vendor='Generic' product='Power Saving USB' rev='0260' type=0 removable=1
+scsi_is_ready (drive=0x000f4100)
+xhci_trb_queue: ring 0x000ef200 [nidx 2, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef210, evt 0x000ef300, type 32, eidx 2, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 3, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 4, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef630, evt 0x000ef700, type 32, eidx 4, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 5, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef640, evt 0x000ef700, type 32, eidx 5, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 6, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef650, evt 0x000ef700, type 32, eidx 6, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 7, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef660, evt 0x000ef700, type 32, eidx 7, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 8, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef670, evt 0x000ef700, type 32, eidx 8, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 9, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef680, evt 0x000ef700, type 32, eidx 9, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 10, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef690, evt 0x000ef700, type 32, eidx 10, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 11, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6a0, evt 0x000ef700, type 32, eidx 11, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 12, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6b0, evt 0x000ef700, type 32, eidx 12, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 13, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6c0, evt 0x000ef700, type 32, eidx 13, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 14, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6d0, evt 0x000ef700, type 32, eidx 14, cc 1]
+xhci_process_events: ring 0x000ef400 [trb 0x000ef420, evt 0x000ef500, type 32, eidx 3, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 3, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef220, evt 0x000ef300, type 32, eidx 3, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 4, len 18]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef430, evt 0x000ef500, type 32, eidx 4, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 5, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef440, evt 0x000ef500, type 32, eidx 5, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 4, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef230, evt 0x000ef300, type 32, eidx 4, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 6, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef450, evt 0x000ef500, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 5, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef240, evt 0x000ef300, type 32, eidx 5, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 7, len 8]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef460, evt 0x000ef500, type 32, eidx 7, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 8, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef470, evt 0x000ef500, type 32, eidx 8, cc 1]
+USB MSC blksize=512 sectors=31260672
+Registering bootable: USB MSC Drive Generic Power Saving USB 0260 (type:4 prio:9 data:f4100)
+init ps2port
+i8042_flush
+i8042 flushed ff (status=ff)
+i8042 flushed ff (status=ff)
+i8042 flushed ff (status=ff)
+i8042 flushed ff (status=ff)
+i8042 flushed ff (status=ff)
+i8042 flushed ff (status=ff)
+i8042 flushed ff (status=ff)
+i8042 flushed ff (status=ff)
+i8042 flushed ff (status=ff)
+i8042 flushed ff (status=ff)
+i8042 flushed ff (status=ff)
+i8042 flushed ff (status=ff)
+i8042 flushed ff (status=ff)
+i8042 flushed ff (status=ff)
+i8042 flushed ff (status=ff)
+i8042 flushed ff (status=ff)
+WARNING - Timeout at i8042_flush:71!
+init ahci
+AHCI controller at 00:1f.2, iobase 0xe0719000, irq 10
+AHCI: cap 0xdf34ff01, ports_impl 0x1
+AHCI/0: probing
+AHCI/0: link up
+AHCI/0: ... finished, status 0x51, ERROR 0x4
+Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0
+AHCI/0: registering: "AHCI/0: KINGSTON SNS4151S316GD ATA-10 Hard-Disk (15272 MiBytes)"
+Registering bootable: AHCI/0: KINGSTON SNS4151S316GD ATA-10 Hard-Disk (15272 MiBytes) (type:2 prio:1 data:f4090)
+Scan for option roms
+Attempting to init PCI bdf 00:00.0 (vd 8086:0a04)
+Attempting to map option rom on dev 00:00.0
+Option rom sizing returned 0 0
+Attempting to init PCI bdf 00:03.0 (vd 8086:0a0c)
+Attempting to map option rom on dev 00:03.0
+Option rom sizing returned 0 0
+Attempting to init PCI bdf 00:16.0 (vd 8086:9c3a)
+Attempting to map option rom on dev 00:16.0
+Option rom sizing returned 0 0
+Attempting to init PCI bdf 00:1b.0 (vd 8086:9c20)
+Attempting to map option rom on dev 00:1b.0
+Option rom sizing returned 0 0
+Attempting to init PCI bdf 00:1c.0 (vd 8086:9c14)
+Attempting to map option rom on dev 00:1c.0
+Skipping non-normal pci device (type=81)
+Attempting to init PCI bdf 00:1c.1 (vd 8086:9c16)
+Attempting to map option rom on dev 00:1c.1
+Skipping non-normal pci device (type=81)
+Attempting to init PCI bdf 00:1c.2 (vd 8086:9c18)
+Attempting to map option rom on dev 00:1c.2
+Skipping non-normal pci device (type=81)
+Attempting to init PCI bdf 00:1f.0 (vd 8086:9c45)
+Attempting to map option rom on dev 00:1f.0
+Option rom sizing returned 0 0
+Attempting to init PCI bdf 00:1f.3 (vd 8086:9c22)
+Attempting to map option rom on dev 00:1f.3
+Option rom sizing returned 0 0
+Attempting to init PCI bdf 00:1f.6 (vd 8086:9c24)
+Attempting to map option rom on dev 00:1f.6
+Option rom sizing returned 0 0
+Attempting to init PCI bdf 01:00.0 (vd 10ec:8168)
+Attempting to map option rom on dev 01:00.0
+Option rom sizing returned 0 0
+Attempting to init PCI bdf 02:00.0 (vd 168c:0034)
+Attempting to map option rom on dev 02:00.0
+Option rom sizing returned e0680000 ffff0000
+Inspecting possible rom at 0xe0680000 (vd=168c:0034 bdf=02:00.0)
+No option rom signature (got beef)
+
+Press ESC for boot menu.
+
+Copying data 8@0xfff0d788 to 8@0x00006e70
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 15, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6e0, evt 0x000ef700, type 32, eidx 15, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [linked]
+xhci_trb_queue: ring 0x000ef600 [nidx 1, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef600, evt 0x000ef700, type 32, eidx 1, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 2, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef610, evt 0x000ef700, type 32, eidx 2, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 3, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef620, evt 0x000ef700, type 32, eidx 3, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 4, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef630, evt 0x000ef700, type 32, eidx 4, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 5, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef640, evt 0x000ef700, type 32, eidx 5, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 6, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef650, evt 0x000ef700, type 32, eidx 6, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 7, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef660, evt 0x000ef700, type 32, eidx 7, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 8, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef670, evt 0x000ef700, type 32, eidx 8, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 9, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef680, evt 0x000ef700, type 32, eidx 9, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 10, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef690, evt 0x000ef700, type 32, eidx 10, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 11, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6a0, evt 0x000ef700, type 32, eidx 11, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 12, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6b0, evt 0x000ef700, type 32, eidx 12, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 13, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6c0, evt 0x000ef700, type 32, eidx 13, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 14, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6d0, evt 0x000ef700, type 32, eidx 14, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 15, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6e0, evt 0x000ef700, type 32, eidx 15, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [linked]
+xhci_trb_queue: ring 0x000ef600 [nidx 1, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef600, evt 0x000ef700, type 32, eidx 1, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 2, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef610, evt 0x000ef700, type 32, eidx 2, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 3, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef620, evt 0x000ef700, type 32, eidx 3, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 4, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef630, evt 0x000ef700, type 32, eidx 4, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 5, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef640, evt 0x000ef700, type 32, eidx 5, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 6, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef650, evt 0x000ef700, type 32, eidx 6, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 7, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef660, evt 0x000ef700, type 32, eidx 7, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 8, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef670, evt 0x000ef700, type 32, eidx 8, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 9, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+Select boot device:
+
+1. AHCI/0: KINGSTON SNS4151S316GD ATA-10 Hard-Disk (15272 MiBy
+2. USB MSC Drive Generic Power Saving USB 0260
+xhci_process_events: ring 0x000ef600 [trb 0x000ef680, evt 0x000ef700, type 32, eidx 9, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 10, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef690, evt 0x000ef700, type 32, eidx 10, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 11, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6a0, evt 0x000ef700, type 32, eidx 11, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 12, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6b0, evt 0x000ef700, type 32, eidx 12, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 13, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6c0, evt 0x000ef700, type 32, eidx 13, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 14, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6d0, evt 0x000ef700, type 32, eidx 14, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 15, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6e0, evt 0x000ef700, type 32, eidx 15, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [linked]
+xhci_trb_queue: ring 0x000ef600 [nidx 1, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef600, evt 0x000ef700, type 32, eidx 1, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 2, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef610, evt 0x000ef700, type 32, eidx 2, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 3, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef620, evt 0x000ef700, type 32, eidx 3, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 4, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef630, evt 0x000ef700, type 32, eidx 4, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 5, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef640, evt 0x000ef700, type 32, eidx 5, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 6, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef650, evt 0x000ef700, type 32, eidx 6, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 7, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef660, evt 0x000ef700, type 32, eidx 7, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 8, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef670, evt 0x000ef700, type 32, eidx 8, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 9, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef680, evt 0x000ef700, type 32, eidx 9, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 10, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+
+Searching bootorder for: HALT
+Mapping hd drive 0x000f4100 to 0
+drive 0x000f4100: PCHS=0/0/0 translation=lba LCHS=1024/255/63 s=31260672
+Mapping hd drive 0x000f4090 to 1
+drive 0x000f4090: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=31277232
+finalize PMM
+malloc finalize
+Space available for UMB: d0000-ee800, f0000-f4090
+Returned 188416 bytes of ZoneHigh
+e820 map has 9 items:
+  0: 0000000000000000 - 000000000009fc00 = 1 RAM
+  1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
+  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
+  3: 0000000000100000 - 000000007bf06000 = 1 RAM
+  4: 000000007bf06000 - 000000007ea00000 = 2 RESERVED
+  5: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
+  6: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED
+  7: 00000000fed84000 - 00000000fed85000 = 2 RESERVED
+  8: 0000000100000000 - 0000000100600000 = 1 RAM
+Jump to int19
+enter handle_19:
+  NULL
+Booting from USB Device...
+xhci_trb_queue: ring 0x000ef200 [nidx 6, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef250, evt 0x000ef300, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 9, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef690, evt 0x000ef700, type 32, eidx 10, cc 1]
+xhci_process_events: ring 0x000ef400 [trb 0x000ef480, evt 0x000ef500, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 10, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef490, evt 0x000ef500, type 32, eidx 10, cc 1]
+Booting from 0000:7c00
+xhci_trb_queue: ring 0x000ef200 [nidx 7, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef260, evt 0x000ef300, type 32, eidx 7, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 11, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4a0, evt 0x000ef500, type 32, eidx 11, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 12, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4b0, evt 0x000ef500, type 32, eidx 12, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 8, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef270, evt 0x000ef300, type 32, eidx 8, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 13, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4c0, evt 0x000ef500, type 32, eidx 13, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 14, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4d0, evt 0x000ef500, type 32, eidx 14, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 9, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef280, evt 0x000ef300, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 15, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4e0, evt 0x000ef500, type 32, eidx 15, cc 1]
+xhci_trb_queue: ring 0x000ef400 [linked]
+xhci_trb_queue: ring 0x000ef400 [nidx 1, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef400, evt 0x000ef500, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 10, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef290, evt 0x000ef300, type 32, eidx 10, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 2, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef410, evt 0x000ef500, type 32, eidx 2, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 3, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef420, evt 0x000ef500, type 32, eidx 3, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 11, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2a0, evt 0x000ef300, type 32, eidx 11, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 4, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef430, evt 0x000ef500, type 32, eidx 4, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 5, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef440, evt 0x000ef500, type 32, eidx 5, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 12, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2b0, evt 0x000ef300, type 32, eidx 12, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 6, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef450, evt 0x000ef500, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 7, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef460, evt 0x000ef500, type 32, eidx 7, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 13, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2c0, evt 0x000ef300, type 32, eidx 13, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 8, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef470, evt 0x000ef500, type 32, eidx 8, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 9, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef480, evt 0x000ef500, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 14, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2d0, evt 0x000ef300, type 32, eidx 14, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 10, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef490, evt 0x000ef500, type 32, eidx 10, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 11, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4a0, evt 0x000ef500, type 32, eidx 11, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 15, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2e0, evt 0x000ef300, type 32, eidx 15, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 12, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4b0, evt 0x000ef500, type 32, eidx 12, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 13, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4c0, evt 0x000ef500, type 32, eidx 13, cc 1]
+xhci_trb_queue: ring 0x000ef200 [linked]
+xhci_trb_queue: ring 0x000ef200 [nidx 1, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef200, evt 0x000ef300, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 14, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4d0, evt 0x000ef500, type 32, eidx 14, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 15, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4e0, evt 0x000ef500, type 32, eidx 15, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 2, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef210, evt 0x000ef300, type 32, eidx 2, cc 1]
+xhci_trb_queue: ring 0x000ef400 [linked]
+xhci_trb_queue: ring 0x000ef400 [nidx 1, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef400, evt 0x000ef500, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 2, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef410, evt 0x000ef500, type 32, eidx 2, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 3, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef220, evt 0x000ef300, type 32, eidx 3, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 3, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef420, evt 0x000ef500, type 32, eidx 3, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 4, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef430, evt 0x000ef500, type 32, eidx 4, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 4, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef230, evt 0x000ef300, type 32, eidx 4, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 5, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef440, evt 0x000ef500, type 32, eidx 5, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 6, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef450, evt 0x000ef500, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 5, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef240, evt 0x000ef300, type 32, eidx 5, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 7, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef460, evt 0x000ef500, type 32, eidx 7, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 8, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef470, evt 0x000ef500, type 32, eidx 8, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 6, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef250, evt 0x000ef300, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 9, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef480, evt 0x000ef500, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 10, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef490, evt 0x000ef500, type 32, eidx 10, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 7, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef260, evt 0x000ef300, type 32, eidx 7, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 11, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4a0, evt 0x000ef500, type 32, eidx 11, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 12, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4b0, evt 0x000ef500, type 32, eidx 12, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 8, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef270, evt 0x000ef300, type 32, eidx 8, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 13, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4c0, evt 0x000ef500, type 32, eidx 13, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 14, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4d0, evt 0x000ef500, type 32, eidx 14, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 9, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef280, evt 0x000ef300, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 15, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4e0, evt 0x000ef500, type 32, eidx 15, cc 1]
+xhci_trb_queue: ring 0x000ef400 [linked]
+xhci_trb_queue: ring 0x000ef400 [nidx 1, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef400, evt 0x000ef500, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 10, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef290, evt 0x000ef300, type 32, eidx 10, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 2, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef410, evt 0x000ef500, type 32, eidx 2, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 3, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef420, evt 0x000ef500, type 32, eidx 3, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 11, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2a0, evt 0x000ef300, type 32, eidx 11, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 4, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef430, evt 0x000ef500, type 32, eidx 4, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 5, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef440, evt 0x000ef500, type 32, eidx 5, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 12, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2b0, evt 0x000ef300, type 32, eidx 12, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 6, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef450, evt 0x000ef500, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 7, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef460, evt 0x000ef500, type 32, eidx 7, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 13, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2c0, evt 0x000ef300, type 32, eidx 13, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 8, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef470, evt 0x000ef500, type 32, eidx 8, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 9, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef480, evt 0x000ef500, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 14, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2d0, evt 0x000ef300, type 32, eidx 14, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 10, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef490, evt 0x000ef500, type 32, eidx 10, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 11, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4a0, evt 0x000ef500, type 32, eidx 11, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 15, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2e0, evt 0x000ef300, type 32, eidx 15, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 12, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4b0, evt 0x000ef500, type 32, eidx 12, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 13, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4c0, evt 0x000ef500, type 32, eidx 13, cc 1]
+xhci_trb_queue: ring 0x000ef200 [linked]
+xhci_trb_queue: ring 0x000ef200 [nidx 1, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef200, evt 0x000ef300, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 14, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4d0, evt 0x000ef500, type 32, eidx 14, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 15, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4e0, evt 0x000ef500, type 32, eidx 15, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 2, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef210, evt 0x000ef300, type 32, eidx 2, cc 1]
+xhci_trb_queue: ring 0x000ef400 [linked]
+xhci_trb_queue: ring 0x000ef400 [nidx 1, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef400, evt 0x000ef500, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 2, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef410, evt 0x000ef500, type 32, eidx 2, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 3, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef220, evt 0x000ef300, type 32, eidx 3, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 3, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef420, evt 0x000ef500, type 32, eidx 3, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 4, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef430, evt 0x000ef500, type 32, eidx 4, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 4, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef230, evt 0x000ef300, type 32, eidx 4, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 5, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000efe20 <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 11, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6a0, evt 0x000ef700, type 32, eidx 11, cc 1]
+xhci_process_events: ring 0x000ef400 [trb 0x000ef440, evt 0x000ef500, type 32, eidx 5, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 6, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef450, evt 0x000ef500, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 5, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef240, evt 0x000ef300, type 32, eidx 5, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 7, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef460, evt 0x000ef500, type 32, eidx 7, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 8, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef470, evt 0x000ef500, type 32, eidx 8, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 6, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef250, evt 0x000ef300, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 9, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef480, evt 0x000ef500, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 10, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef490, evt 0x000ef500, type 32, eidx 10, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 7, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef260, evt 0x000ef300, type 32, eidx 7, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 11, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4a0, evt 0x000ef500, type 32, eidx 11, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 12, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4b0, evt 0x000ef500, type 32, eidx 12, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 8, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef270, evt 0x000ef300, type 32, eidx 8, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 13, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4c0, evt 0x000ef500, type 32, eidx 13, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 14, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4d0, evt 0x000ef500, type 32, eidx 14, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 9, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef280, evt 0x000ef300, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 15, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4e0, evt 0x000ef500, type 32, eidx 15, cc 1]
+xhci_trb_queue: ring 0x000ef400 [linked]
+xhci_trb_queue: ring 0x000ef400 [nidx 1, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef400, evt 0x000ef500, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 10, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef290, evt 0x000ef300, type 32, eidx 10, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 2, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef410, evt 0x000ef500, type 32, eidx 2, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 3, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef420, evt 0x000ef500, type 32, eidx 3, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 11, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2a0, evt 0x000ef300, type 32, eidx 11, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 4, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef430, evt 0x000ef500, type 32, eidx 4, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 5, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef440, evt 0x000ef500, type 32, eidx 5, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 12, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2b0, evt 0x000ef300, type 32, eidx 12, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 6, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef450, evt 0x000ef500, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 7, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef460, evt 0x000ef500, type 32, eidx 7, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 13, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2c0, evt 0x000ef300, type 32, eidx 13, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 8, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef470, evt 0x000ef500, type 32, eidx 8, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 9, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef480, evt 0x000ef500, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 14, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2d0, evt 0x000ef300, type 32, eidx 14, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 10, len 3072]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef490, evt 0x000ef500, type 32, eidx 10, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 11, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4a0, evt 0x000ef500, type 32, eidx 11, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 15, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2e0, evt 0x000ef300, type 32, eidx 15, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 12, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4b0, evt 0x000ef500, type 32, eidx 12, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 13, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4c0, evt 0x000ef500, type 32, eidx 13, cc 1]
+xhci_trb_queue: ring 0x000ef200 [linked]
+xhci_trb_queue: ring 0x000ef200 [nidx 1, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef200, evt 0x000ef300, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 14, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4d0, evt 0x000ef500, type 32, eidx 14, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 15, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4e0, evt 0x000ef500, type 32, eidx 15, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 2, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef210, evt 0x000ef300, type 32, eidx 2, cc 1]
+xhci_trb_queue: ring 0x000ef400 [linked]
+xhci_trb_queue: ring 0x000ef400 [nidx 1, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef400, evt 0x000ef500, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 2, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef410, evt 0x000ef500, type 32, eidx 2, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 3, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef220, evt 0x000ef300, type 32, eidx 3, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 3, len 16384]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef420, evt 0x000ef500, type 32, eidx 3, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 4, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef430, evt 0x000ef500, type 32, eidx 4, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 4, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef230, evt 0x000ef300, type 32, eidx 4, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 5, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef440, evt 0x000ef500, type 32, eidx 5, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 6, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef450, evt 0x000ef500, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 5, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef240, evt 0x000ef300, type 32, eidx 5, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 7, len 39936]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef460, evt 0x000ef500, type 32, eidx 7, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 8, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef470, evt 0x000ef500, type 32, eidx 8, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 6, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef250, evt 0x000ef300, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 9, len 1024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef480, evt 0x000ef500, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 10, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef490, evt 0x000ef500, type 32, eidx 10, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 7, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef260, evt 0x000ef300, type 32, eidx 7, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 11, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4a0, evt 0x000ef500, type 32, eidx 11, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 12, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4b0, evt 0x000ef500, type 32, eidx 12, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 8, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef270, evt 0x000ef300, type 32, eidx 8, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 13, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4c0, evt 0x000ef500, type 32, eidx 13, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 14, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4d0, evt 0x000ef500, type 32, eidx 14, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 12, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_trb_queue: ring 0x000ef200 [nidx 9, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6b0, evt 0x000ef700, type 32, eidx 12, cc 1]
+xhci_process_events: ring 0x000ef200 [trb 0x000ef280, evt 0x000ef300, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 15, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4e0, evt 0x000ef500, type 32, eidx 15, cc 1]
+xhci_trb_queue: ring 0x000ef400 [linked]
+xhci_trb_queue: ring 0x000ef400 [nidx 1, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef400, evt 0x000ef500, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 10, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef290, evt 0x000ef300, type 32, eidx 10, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 2, len 1536]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef410, evt 0x000ef500, type 32, eidx 2, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 3, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef420, evt 0x000ef500, type 32, eidx 3, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 11, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2a0, evt 0x000ef300, type 32, eidx 11, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 4, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef430, evt 0x000ef500, type 32, eidx 4, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 5, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef440, evt 0x000ef500, type 32, eidx 5, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 12, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2b0, evt 0x000ef300, type 32, eidx 12, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 6, len 16384]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef450, evt 0x000ef500, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 7, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef460, evt 0x000ef500, type 32, eidx 7, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 13, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2c0, evt 0x000ef300, type 32, eidx 13, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 8, len 10752]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef470, evt 0x000ef500, type 32, eidx 8, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 9, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef480, evt 0x000ef500, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 14, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2d0, evt 0x000ef300, type 32, eidx 14, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 10, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef490, evt 0x000ef500, type 32, eidx 10, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 11, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4a0, evt 0x000ef500, type 32, eidx 11, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 15, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2e0, evt 0x000ef300, type 32, eidx 15, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 12, len 16384]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4b0, evt 0x000ef500, type 32, eidx 12, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 13, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4c0, evt 0x000ef500, type 32, eidx 13, cc 1]
+xhci_trb_queue: ring 0x000ef200 [linked]
+xhci_trb_queue: ring 0x000ef200 [nidx 1, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef200, evt 0x000ef300, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 14, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4d0, evt 0x000ef500, type 32, eidx 14, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 15, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4e0, evt 0x000ef500, type 32, eidx 15, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 2, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef210, evt 0x000ef300, type 32, eidx 2, cc 1]
+xhci_trb_queue: ring 0x000ef400 [linked]
+xhci_trb_queue: ring 0x000ef400 [nidx 1, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef400, evt 0x000ef500, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 2, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef410, evt 0x000ef500, type 32, eidx 2, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 3, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef220, evt 0x000ef300, type 32, eidx 3, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 3, len 38912]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef420, evt 0x000ef500, type 32, eidx 3, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 4, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef430, evt 0x000ef500, type 32, eidx 4, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 4, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef230, evt 0x000ef300, type 32, eidx 4, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 5, len 1536]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef440, evt 0x000ef500, type 32, eidx 5, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 6, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef450, evt 0x000ef500, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 5, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef240, evt 0x000ef300, type 32, eidx 5, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 7, len 16384]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef460, evt 0x000ef500, type 32, eidx 7, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 8, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef470, evt 0x000ef500, type 32, eidx 8, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 6, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef250, evt 0x000ef300, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 9, len 8192]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef480, evt 0x000ef500, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 10, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef490, evt 0x000ef500, type 32, eidx 10, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 13, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_trb_queue: ring 0x000ef200 [nidx 7, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6c0, evt 0x000ef700, type 32, eidx 13, cc 1]
+xhci_process_events: ring 0x000ef200 [trb 0x000ef260, evt 0x000ef300, type 32, eidx 7, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 11, len 1536]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4a0, evt 0x000ef500, type 32, eidx 11, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 12, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4b0, evt 0x000ef500, type 32, eidx 12, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 14, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_trb_queue: ring 0x000ef200 [nidx 8, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef270, evt 0x000ef300, type 32, eidx 8, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 13, len 16384]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6d0, evt 0x000ef700, type 32, eidx 14, cc 1]
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4c0, evt 0x000ef500, type 32, eidx 13, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 14, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4d0, evt 0x000ef500, type 32, eidx 14, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 9, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef280, evt 0x000ef300, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 15, len 16384]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4e0, evt 0x000ef500, type 32, eidx 15, cc 1]
+xhci_trb_queue: ring 0x000ef400 [linked]
+xhci_trb_queue: ring 0x000ef400 [nidx 1, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef400, evt 0x000ef500, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 10, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef290, evt 0x000ef300, type 32, eidx 10, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 2, len 16384]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef410, evt 0x000ef500, type 32, eidx 2, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 3, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef420, evt 0x000ef500, type 32, eidx 3, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 15, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_trb_queue: ring 0x000ef200 [nidx 11, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2a0, evt 0x000ef300, type 32, eidx 11, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 4, len 16384]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6e0, evt 0x000ef700, type 32, eidx 15, cc 1]
+xhci_process_events: ring 0x000ef400 [trb 0x000ef430, evt 0x000ef500, type 32, eidx 4, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 5, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef440, evt 0x000ef500, type 32, eidx 5, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 12, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2b0, evt 0x000ef300, type 32, eidx 12, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 6, len 8192]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef450, evt 0x000ef500, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 7, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef460, evt 0x000ef500, type 32, eidx 7, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [linked]
+xhci_trb_queue: ring 0x000ef600 [nidx 1, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef600, evt 0x000ef700, type 32, eidx 1, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 2, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef610, evt 0x000ef700, type 32, eidx 2, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 3, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef620, evt 0x000ef700, type 32, eidx 3, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 4, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef630, evt 0x000ef700, type 32, eidx 4, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 5, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef640, evt 0x000ef700, type 32, eidx 5, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 6, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef650, evt 0x000ef700, type 32, eidx 6, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 7, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef660, evt 0x000ef700, type 32, eidx 7, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 8, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef670, evt 0x000ef700, type 32, eidx 8, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 9, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef680, evt 0x000ef700, type 32, eidx 9, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 10, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef690, evt 0x000ef700, type 32, eidx 10, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 11, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6a0, evt 0x000ef700, type 32, eidx 11, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 12, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6b0, evt 0x000ef700, type 32, eidx 12, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 13, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6c0, evt 0x000ef700, type 32, eidx 13, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 14, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6d0, evt 0x000ef700, type 32, eidx 14, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 15, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6e0, evt 0x000ef700, type 32, eidx 15, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [linked]
+xhci_trb_queue: ring 0x000ef600 [nidx 1, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef600, evt 0x000ef700, type 32, eidx 1, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 2, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef610, evt 0x000ef700, type 32, eidx 2, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 3, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef620, evt 0x000ef700, type 32, eidx 3, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 4, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef630, evt 0x000ef700, type 32, eidx 4, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 5, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef640, evt 0x000ef700, type 32, eidx 5, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff10 <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 6, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef650, evt 0x000ef700, type 32, eidx 6, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 7, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef660, evt 0x000ef700, type 32, eidx 7, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff10 <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 8, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef670, evt 0x000ef700, type 32, eidx 8, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 9, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef680, evt 0x000ef700, type 32, eidx 9, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 10, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef690, evt 0x000ef700, type 32, eidx 10, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 11, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6a0, evt 0x000ef700, type 32, eidx 11, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 12, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6b0, evt 0x000ef700, type 32, eidx 12, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 13, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6c0, evt 0x000ef700, type 32, eidx 13, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 14, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6d0, evt 0x000ef700, type 32, eidx 14, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 15, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6e0, evt 0x000ef700, type 32, eidx 15, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [linked]
+xhci_trb_queue: ring 0x000ef600 [nidx 1, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef600, evt 0x000ef700, type 32, eidx 1, cc 1]
+xhci_poll_intr: st 1000000 ct 1038001 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 2, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef610, evt 0x000ef700, type 32, eidx 2, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 3, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef620, evt 0x000ef700, type 32, eidx 3, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 4, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef630, evt 0x000ef700, type 32, eidx 4, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 5, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef640, evt 0x000ef700, type 32, eidx 5, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 6, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef650, evt 0x000ef700, type 32, eidx 6, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 7, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef660, evt 0x000ef700, type 32, eidx 7, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 8, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef670, evt 0x000ef700, type 32, eidx 8, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 9, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef680, evt 0x000ef700, type 32, eidx 9, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 10, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef690, evt 0x000ef700, type 32, eidx 10, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 11, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6a0, evt 0x000ef700, type 32, eidx 11, cc 1]
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000eff6c <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 12, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_trb_queue: ring 0x000ef200 [nidx 13, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6b0, evt 0x000ef700, type 32, eidx 12, cc 1]
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2c0, evt 0x000ef300, type 32, eidx 13, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 8, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef470, evt 0x000ef500, type 32, eidx 8, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 9, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef480, evt 0x000ef500, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 14, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2d0, evt 0x000ef300, type 32, eidx 14, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 10, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef490, evt 0x000ef500, type 32, eidx 10, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 11, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4a0, evt 0x000ef500, type 32, eidx 11, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 15, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2e0, evt 0x000ef300, type 32, eidx 15, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 12, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4b0, evt 0x000ef500, type 32, eidx 12, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 13, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4c0, evt 0x000ef500, type 32, eidx 13, cc 1]
+xhci_trb_queue: ring 0x000ef200 [linked]
+xhci_trb_queue: ring 0x000ef200 [nidx 1, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef200, evt 0x000ef300, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 14, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4d0, evt 0x000ef500, type 32, eidx 14, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 15, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4e0, evt 0x000ef500, type 32, eidx 15, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 2, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef210, evt 0x000ef300, type 32, eidx 2, cc 1]
+xhci_trb_queue: ring 0x000ef400 [linked]
+xhci_trb_queue: ring 0x000ef400 [nidx 1, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef400, evt 0x000ef500, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 2, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef410, evt 0x000ef500, type 32, eidx 2, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 3, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef220, evt 0x000ef300, type 32, eidx 3, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 3, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef420, evt 0x000ef500, type 32, eidx 3, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 4, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef430, evt 0x000ef500, type 32, eidx 4, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 4, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef230, evt 0x000ef300, type 32, eidx 4, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 5, len 512]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef440, evt 0x000ef500, type 32, eidx 5, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 6, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef450, evt 0x000ef500, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 5, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef240, evt 0x000ef300, type 32, eidx 5, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 7, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef460, evt 0x000ef500, type 32, eidx 7, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 8, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef470, evt 0x000ef500, type 32, eidx 8, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 6, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef250, evt 0x000ef300, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 9, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef480, evt 0x000ef500, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 10, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef490, evt 0x000ef500, type 32, eidx 10, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 7, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef260, evt 0x000ef300, type 32, eidx 7, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 11, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4a0, evt 0x000ef500, type 32, eidx 11, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 12, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4b0, evt 0x000ef500, type 32, eidx 12, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 8, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef270, evt 0x000ef300, type 32, eidx 8, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 13, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4c0, evt 0x000ef500, type 32, eidx 13, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 14, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4d0, evt 0x000ef500, type 32, eidx 14, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 9, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef280, evt 0x000ef300, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 15, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000efe20 <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 13, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6c0, evt 0x000ef700, type 32, eidx 13, cc 1]
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4e0, evt 0x000ef500, type 32, eidx 15, cc 1]
+xhci_trb_queue: ring 0x000ef400 [linked]
+xhci_trb_queue: ring 0x000ef400 [nidx 1, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef400, evt 0x000ef500, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 10, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef290, evt 0x000ef300, type 32, eidx 10, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 2, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef410, evt 0x000ef500, type 32, eidx 2, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 3, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef420, evt 0x000ef500, type 32, eidx 3, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 11, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2a0, evt 0x000ef300, type 32, eidx 11, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 4, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef430, evt 0x000ef500, type 32, eidx 4, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 5, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef440, evt 0x000ef500, type 32, eidx 5, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 12, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2b0, evt 0x000ef300, type 32, eidx 12, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 6, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef450, evt 0x000ef500, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 7, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef460, evt 0x000ef500, type 32, eidx 7, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 13, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2c0, evt 0x000ef300, type 32, eidx 13, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 8, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef470, evt 0x000ef500, type 32, eidx 8, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 9, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef480, evt 0x000ef500, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 14, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2d0, evt 0x000ef300, type 32, eidx 14, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 10, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef490, evt 0x000ef500, type 32, eidx 10, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 11, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4a0, evt 0x000ef500, type 32, eidx 11, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 15, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2e0, evt 0x000ef300, type 32, eidx 15, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 12, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4b0, evt 0x000ef500, type 32, eidx 12, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 13, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4c0, evt 0x000ef500, type 32, eidx 13, cc 1]
+xhci_trb_queue: ring 0x000ef200 [linked]
+xhci_trb_queue: ring 0x000ef200 [nidx 1, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef200, evt 0x000ef300, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 14, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4d0, evt 0x000ef500, type 32, eidx 14, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 15, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4e0, evt 0x000ef500, type 32, eidx 15, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 2, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef210, evt 0x000ef300, type 32, eidx 2, cc 1]
+xhci_trb_queue: ring 0x000ef400 [linked]
+xhci_trb_queue: ring 0x000ef400 [nidx 1, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000efe20 <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 14, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6d0, evt 0x000ef700, type 32, eidx 14, cc 1]
+xhci_process_events: ring 0x000ef400 [trb 0x000ef400, evt 0x000ef500, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 2, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef410, evt 0x000ef500, type 32, eidx 2, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 3, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef220, evt 0x000ef300, type 32, eidx 3, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 3, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef420, evt 0x000ef500, type 32, eidx 3, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 4, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef430, evt 0x000ef500, type 32, eidx 4, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 4, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef230, evt 0x000ef300, type 32, eidx 4, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 5, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef440, evt 0x000ef500, type 32, eidx 5, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 6, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef450, evt 0x000ef500, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 5, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef240, evt 0x000ef300, type 32, eidx 5, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 7, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef460, evt 0x000ef500, type 32, eidx 7, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 8, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef470, evt 0x000ef500, type 32, eidx 8, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 6, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef250, evt 0x000ef300, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 9, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef480, evt 0x000ef500, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 10, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef490, evt 0x000ef500, type 32, eidx 10, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 7, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef260, evt 0x000ef300, type 32, eidx 7, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 11, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4a0, evt 0x000ef500, type 32, eidx 11, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 12, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4b0, evt 0x000ef500, type 32, eidx 12, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 8, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef270, evt 0x000ef300, type 32, eidx 8, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 13, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4c0, evt 0x000ef500, type 32, eidx 13, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 14, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4d0, evt 0x000ef500, type 32, eidx 14, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 9, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef280, evt 0x000ef300, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 15, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4e0, evt 0x000ef500, type 32, eidx 15, cc 1]
+xhci_trb_queue: ring 0x000ef400 [linked]
+xhci_trb_queue: ring 0x000ef400 [nidx 1, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef400, evt 0x000ef500, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 10, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef290, evt 0x000ef300, type 32, eidx 10, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 2, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef410, evt 0x000ef500, type 32, eidx 2, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 3, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef420, evt 0x000ef500, type 32, eidx 3, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 11, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2a0, evt 0x000ef300, type 32, eidx 11, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 4, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef430, evt 0x000ef500, type 32, eidx 4, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 5, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef440, evt 0x000ef500, type 32, eidx 5, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 12, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2b0, evt 0x000ef300, type 32, eidx 12, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 6, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef450, evt 0x000ef500, type 32, eidx 6, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 7, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef460, evt 0x000ef500, type 32, eidx 7, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 13, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2c0, evt 0x000ef300, type 32, eidx 13, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 8, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_poll_intr: st 1000000 ct 1038000 [ 0x000efe20 <= 0x7bf17fa0 / 8 ]
+xhci_trb_queue: ring 0x000ef600 [nidx 15, len 8]
+xhci_xfer_kick: ring 0x000ef600, slotid 1, epid 3
+xhci_process_events: ring 0x000ef600 [trb 0x000ef6e0, evt 0x000ef700, type 32, eidx 15, cc 1]
+xhci_process_events: ring 0x000ef400 [trb 0x000ef470, evt 0x000ef500, type 32, eidx 8, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 9, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef480, evt 0x000ef500, type 32, eidx 9, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 14, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2d0, evt 0x000ef300, type 32, eidx 14, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 10, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef490, evt 0x000ef500, type 32, eidx 10, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 11, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4a0, evt 0x000ef500, type 32, eidx 11, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 15, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef2e0, evt 0x000ef300, type 32, eidx 15, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 12, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4b0, evt 0x000ef500, type 32, eidx 12, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 13, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4c0, evt 0x000ef500, type 32, eidx 13, cc 1]
+xhci_trb_queue: ring 0x000ef200 [linked]
+xhci_trb_queue: ring 0x000ef200 [nidx 1, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef200, evt 0x000ef300, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 14, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4d0, evt 0x000ef500, type 32, eidx 14, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 15, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef4e0, evt 0x000ef500, type 32, eidx 15, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 2, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef210, evt 0x000ef300, type 32, eidx 2, cc 1]
+xhci_trb_queue: ring 0x000ef400 [linked]
+xhci_trb_queue: ring 0x000ef400 [nidx 1, len 65024]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef400, evt 0x000ef500, type 32, eidx 1, cc 1]
+xhci_trb_queue: ring 0x000ef400 [nidx 2, len 13]
+xhci_xfer_kick: ring 0x000ef400, slotid 3, epid 3
+xhci_process_events: ring 0x000ef400 [trb 0x000ef410, evt 0x000ef500, type 32, eidx 2, cc 1]
+xhci_trb_queue: ring 0x000ef200 [nidx 3, len 31]
+xhci_xfer_kick: ring 0x000ef200, slotid 3, epid 4
+xhci_process_events: ring 0x000ef200 [trb 0x000ef220, evt 0x000ef300, type 32, eidx
+57449 bytes lost