sapphire/pureplatinumh61/4.5-1575-ge0f30920f0/2017-04-18T20_17_30Z
diff --git a/sapphire/pureplatinumh61/4.5-1575-ge0f30920f0/2017-04-18T20_17_30Z/coreboot_console.txt b/sapphire/pureplatinumh61/4.5-1575-ge0f30920f0/2017-04-18T20_17_30Z/coreboot_console.txt
new file mode 100644
index 0000000..5cbcba8
--- /dev/null
+++ b/sapphire/pureplatinumh61/4.5-1575-ge0f30920f0/2017-04-18T20_17_30Z/coreboot_console.txt
@@ -0,0 +1,1865 @@
+
+
+coreboot-4.5-1575-ge0f30920f0 Tue Apr 18 20:17:30 UTC 2017 romstage starting...
+Setting up static southbridge registers... done.
+Disabling Watchdog reboot... done.
+Setting up static northbridge registers... done.
+Initializing Graphics...
+CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 1b440 size 5b0
+Back from sandybridge_early_initialization()
+SMBus controller enabled.
+CPU id(306a9): Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz
+AES supported, TXT supported, VT supported
+PCH type: H61, device id: 1c5c, rev id 5
+Intel ME early init
+Intel ME firmware is ready
+ME: Requested 16MB UMA
+Starting native Platform init
+CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
+CBFS: Locating 'mrc.cache'
+CBFS: Found @ offset 1e980 size 10000
+find_current_mrc_cache_local: picked entry 0 from cache block
+Trying stored timings.
+Starting Ivybridge RAM training (1).
+100MHz reference clock support: yes
+PLL busy... done in 10 us
+MCU frequency is set at : 800 MHz
+XOVER CLK [c14] = 3000000
+XOVER CMD [320c] = 24000
+XOVER CLK [d14] = 3000000
+XOVER CMD [330c] = 24000
+DBP [4000] = 188999
+RAP [4004] = cc186465
+OTHP [400c] = a08b4
+OTHP [400c] = 8b4
+REFI [4298] = 6cd01860
+SRFTP [42a4] = 41f88200
+DBP [4400] = 188999
+RAP [4404] = cc186465
+OTHP [440c] = a08b4
+OTHP [440c] = 8b4
+REFI [4698] = 6cd01860
+SRFTP [46a4] = 41f88200
+Done dimm mapping
+Update PCI-E configuration space:
+PCI(0, 0, 0)[a0] = 0
+PCI(0, 0, 0)[a4] = 4
+PCI(0, 0, 0)[bc] = 82a00000
+PCI(0, 0, 0)[a8] = 7c600000
+PCI(0, 0, 0)[ac] = 4
+PCI(0, 0, 0)[b8] = 80000000
+PCI(0, 0, 0)[b0] = 80a00000
+PCI(0, 0, 0)[b4] = 80800000
+PCI(0, 0, 0)[7c] = 7f
+PCI(0, 0, 0)[70] = ff000000
+PCI(0, 0, 0)[74] = 3
+PCI(0, 0, 0)[78] = ff000c00
+Done memory map
+RCOMP...done
+COMP2 done
+COMP1 done
+FORCE RCOMP and wait 20us...done
+Done io registers
+CPE
+CP5b
+CP5c
+OTHP [400c] = 8b4
+OTHP [440c] = 8b4
+t123: 1767, 6000, 7620
+ME: FW Partition Table : OK
+ME: Bringup Loader Failure : NO
+ME: Firmware Init Complete : NO
+ME: Manufacturing Mode : NO
+ME: Boot Options Present : NO
+ME: Update In Progress : NO
+ME: Current Working State : Recovery
+ME: Current Operation State : Bring up
+ME: Current Operation Mode : Security Override via Jumper
+ME: Error Code : No Error
+ME: Progress Phase : BUP Phase
+ME: Power Management Event : Clean Moff->Mx wake
+ME: Progress Phase State : Waiting for DID BIOS message
+ME: Wrong mode : 4
+ME: FWS2: 0x101f0172
+ME: Bist in progress: 0x0
+ME: ICC Status : 0x1
+ME: Invoke MEBx : 0x0
+ME: CPU replaced : 0x1
+ME: MBP ready : 0x1
+ME: MFS failure : 0x1
+ME: Warm reset req : 0x0
+ME: CPU repl valid : 0x1
+ME: (Reserved) : 0x0
+ME: FW update req : 0x0
+ME: (Reserved) : 0x0
+ME: Current state : 0x1f
+ME: Current PM event: 0x0
+ME: Progress code : 0x1
+Full training required
+PASSED! Tell ME that DRAM is ready
+ME: FWS2: 0x10520172
+ME: Bist in progress: 0x0
+ME: ICC Status : 0x1
+
+
+*** Log truncated, 1388 characters dropped. ***
+
+CBMEM entry for DIMM info: 0x7fffe880
+MTRR Range: Start=ffc00000 End=0 (Size 400000)
+MTRR Range: Start=0 End=1000000 (Size 1000000)
+MTRR Range: Start=7f800000 End=80000000 (Size 800000)
+MTRR Range: Start=80000000 End=80800000 (Size 800000)
+CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
+CBFS: Locating 'fallback/ramstage'
+CBFS: Found @ offset 2ff00 size 129e6
+Decompressing stage fallback/ramstage @ 0x7ff9ffc0 (227600 bytes)
+Loading module at 7ffa0000 with entry 7ffa0000. filesize: 0x26c50 memsize: 0x378d0
+Processing 2481 relocs. Offset value of 0x7fea0000
+Capability: type 0x01 @ 0x50
+Capability: type 0x0a @ 0x58
+
+
+coreboot-4.5-1575-ge0f30920f0 Tue Apr 18 20:17:30 UTC 2017 ramstage starting...
+Normal boot.
+BS: BS_PRE_DEVICE times (us): entry 0 run 2 exit 0
+BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 2 exit 0
+Enumerating buses...
+Show all devs... Before device enumeration.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+APIC: 00: enabled 1
+APIC: acac: enabled 0
+DOMAIN: 0000: enabled 1
+PCI: 00:16.0: enabled 1
+PCI: 00:16.1: enabled 0
+PCI: 00:16.2: enabled 0
+PCI: 00:16.3: enabled 0
+PCI: 00:19.0: enabled 0
+PCI: 00:1a.0: enabled 1
+PCI: 00:1b.0: enabled 1
+PCI: 00:1c.0: enabled 1
+PCI: 00:1c.1: enabled 0
+PCI: 00:1c.2: enabled 0
+PCI: 00:1c.3: enabled 0
+PCI: 00:1c.4: enabled 1
+PCI: 00:1c.5: enabled 1
+PCI: 00:1c.6: enabled 0
+PCI: 00:1c.7: enabled 0
+PCI: 00:1d.0: enabled 1
+PCI: 00:1e.0: enabled 0
+PCI: 00:1f.0: enabled 1
+PNP: 004e.1: enabled 0
+PNP: 004e.4: enabled 1
+PNP: 004e.5: enabled 0
+PNP: 004e.6: enabled 1
+PNP: 004e.7: enabled 1
+PNP: 004e.8: enabled 0
+PNP: 004e.a: enabled 1
+PCI: 00:1f.2: enabled 1
+PCI: 00:1f.3: enabled 1
+PCI: 00:1f.5: enabled 0
+PCI: 00:1f.6: enabled 0
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 1
+PCI: 00:02.0: enabled 1
+Compare with tree...
+Root Device: enabled 1
+ CPU_CLUSTER: 0: enabled 1
+ APIC: 00: enabled 1
+ APIC: acac: enabled 0
+ DOMAIN: 0000: enabled 1
+ PCI: 00:16.0: enabled 1
+ PCI: 00:16.1: enabled 0
+ PCI: 00:16.2: enabled 0
+ PCI: 00:16.3: enabled 0
+ PCI: 00:19.0: enabled 0
+ PCI: 00:1a.0: enabled 1
+ PCI: 00:1b.0: enabled 1
+ PCI: 00:1c.0: enabled 1
+ PCI: 00:1c.1: enabled 0
+ PCI: 00:1c.2: enabled 0
+ PCI: 00:1c.3: enabled 0
+ PCI: 00:1c.4: enabled 1
+ PCI: 00:1c.5: enabled 1
+ PCI: 00:1c.6: enabled 0
+ PCI: 00:1c.7: enabled 0
+ PCI: 00:1d.0: enabled 1
+ PCI: 00:1e.0: enabled 0
+ PCI: 00:1f.0: enabled 1
+ PNP: 004e.1: enabled 0
+ PNP: 004e.4: enabled 1
+ PNP: 004e.5: enabled 0
+ PNP: 004e.6: enabled 1
+ PNP: 004e.7: enabled 1
+ PNP: 004e.8: enabled 0
+ PNP: 004e.a: enabled 1
+ PCI: 00:1f.2: enabled 1
+ PCI: 00:1f.3: enabled 1
+ PCI: 00:1f.5: enabled 0
+ PCI: 00:1f.6: enabled 0
+ PCI: 00:00.0: enabled 1
+ PCI: 00:01.0: enabled 1
+ PCI: 00:02.0: enabled 1
+Root Device scanning...
+root_dev_scan_bus for Root Device
+CPU_CLUSTER: 0 enabled
+DOMAIN: 0000 enabled
+DOMAIN: 0000 scanning...
+PCI: pci_scan_bus for bus 00
+PCI: 00:00.0 [8086/0150] ops
+PCI: 00:00.0 [8086/0150] enabled
+Capability: type 0x0d @ 0x88
+Capability: type 0x01 @ 0x80
+Capability: type 0x05 @ 0x90
+Capability: type 0x10 @ 0xa0
+Capability: type 0x0d @ 0x88
+Capability: type 0x01 @ 0x80
+Capability: type 0x05 @ 0x90
+Capability: type 0x10 @ 0xa0
+PCI: 00:01.0 subordinate bus PCI Express
+PCI: 00:01.0 [8086/0151] enabled
+PCI: 00:02.0 [8086/0000] ops
+PCI: 00:02.0 [8086/0162] enabled
+PCI: 00:16.0 [8086/1c3a] ops
+PCI: 00:16.0 [8086/1c3a] enabled
+PCI: 00:16.1: Disabling device
+PCI: 00:16.2: Disabling device
+PCI: 00:16.3: Disabling device
+PCI: 00:19.0: Disabling device
+PCI: 00:1a.0 [8086/0000] ops
+PCI: 00:1a.0 [8086/1c2d] enabled
+PCI: 00:1b.0 [8086/0000] ops
+PCI: 00:1b.0 [8086/1c20] enabled
+PCH: PCIe Root Port coalescing is enabled
+PCI: 00:1c.0 [8086/0000] bus ops
+PCI: 00:1c.0 [8086/1c10] enabled
+PCI: 00:1c.1: Disabling device
+PCI: 00:1c.2: Disabling device
+PCI: 00:1c.3: Disabling device
+PCH: Remap PCIe function 4 to 1
+PCI: 00:1c.4 [8086/0000] bus ops
+PCI: 00:1c.4 [8086/1c18] enabled
+PCH: Remap PCIe function 5 to 1
+PCI: 00:1c.5 [8086/0000] bus ops
+PCI: 00:1c.5 [8086/1c1a] enabled
+PCI: 00:1c.6: Disabling device
+PCI: 00:1c.7: Disabling device
+PCH: RPFN 0x76543210 -> 0xfe41bad0
+PCH: PCIe map 1c.1 -> 1c.5
+PCH: PCIe map 1c.4 -> 1c.1
+PCH: PCIe map 1c.5 -> 1c.4
+PCI: 00:1d.0 [8086/0000] ops
+PCI: 00:1d.0 [8086/1c26] enabled
+PCI: 00:1e.0: Disabling device
+PCI: 00:1f.0 [8086/0000] bus ops
+PCI: 00:1f.0 [8086/1c5c] enabled
+PCI: 00:1f.2 [8086/0000] ops
+CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 1b440 size 5b0
+PCI: 00:1f.2 [8086/1c00] enabled
+PCI: 00:1f.3 [8086/0000] bus ops
+PCI: 00:1f.3 [8086/1c22] enabled
+PCI: 00:1f.5: Disabling device
+PCI: 00:1f.6: Disabling device
+PCI: 00:01.0 scanning...
+do_pci_scan_bridge for PCI: 00:01.0
+PCI: pci_scan_bus for bus 01
+PCI: 01:00.0 [10de/1401] enabled
+PCI: 01:00.1 [10de/0fba] enabled
+Capability: type 0x01 @ 0x60
+Capability: type 0x05 @ 0x68
+Capability: type 0x10 @ 0x78
+Capability: type 0x0d @ 0x88
+Capability: type 0x01 @ 0x80
+Capability: type 0x05 @ 0x90
+Capability: type 0x10 @ 0xa0
+Enabling Common Clock Configuration
+ASPM: Enabled None
+Capability: type 0x01 @ 0x60
+Capability: type 0x05 @ 0x68
+Capability: type 0x10 @ 0x78
+Capability: type 0x0d @ 0x88
+Capability: type 0x01 @ 0x80
+Capability: type 0x05 @ 0x90
+Capability: type 0x10 @ 0xa0
+Enabling Common Clock Configuration
+ASPM: Enabled None
+scan_bus: scanning of bus PCI: 00:01.0 took 264 usecs
+PCI: 00:1c.0 scanning...
+do_pci_scan_bridge for PCI: 00:1c.0
+PCI: pci_scan_bus for bus 02
+scan_bus: scanning of bus PCI: 00:1c.0 took 52 usecs
+PCI: 00:1c.1 scanning...
+do_pci_scan_bridge for PCI: 00:1c.1
+PCI: pci_scan_bus for bus 03
+PCI: 03:00.0 [1b21/1042] enabled
+Capability: type 0x05 @ 0x50
+Capability: type 0x11 @ 0x68
+Capability: type 0x01 @ 0x78
+Capability: type 0x10 @ 0x80
+Capability: type 0x10 @ 0x40
+Enabling Common Clock Configuration
+PCIE CLK PM is not supported by endpointASPM: Enabled None
+scan_bus: scanning of bus PCI: 00:1c.1 took 211 usecs
+PCI: 00:1c.4 scanning...
+do_pci_scan_bridge for PCI: 00:1c.4
+PCI: pci_scan_bus for bus 04
+PCI: 04:00.0 [11ab/4380] enabled
+Capability: type 0x01 @ 0x48
+Capability: type 0x05 @ 0x5c
+Capability: type 0x10 @ 0xc0
+Capability: type 0x10 @ 0x40
+Enabling Common Clock Configuration
+ASPM: Enabled L0s and L1
+scan_bus: scanning of bus PCI: 00:1c.4 took 231 usecs
+PCI: 00:1f.0 scanning...
+scan_lpc_bus for PCI: 00:1f.0
+PNP: 004e.1 disabled
+PNP: 004e.4 enabled
+PNP: 004e.5 disabled
+PNP: 004e.6 enabled
+PNP: 004e.7 enabled
+PNP: 004e.8 disabled
+PNP: 004e.a enabled
+scan_lpc_bus for PCI: 00:1f.0 done
+scan_bus: scanning of bus PCI: 00:1f.0 took 120 usecs
+PCI: 00:1f.3 scanning...
+scan_generic_bus for PCI: 00:1f.3
+scan_generic_bus for PCI: 00:1f.3 done
+scan_bus: scanning of bus PCI: 00:1f.3 took 5 usecs
+scan_bus: scanning of bus DOMAIN: 0000 took 1353 usecs
+root_dev_scan_bus for Root Device done
+scan_bus: scanning of bus Root Device took 1362 usecs
+done
+BS: BS_DEV_ENUMERATE times (us): entry 0 run 1478 exit 0
+found VGA at PCI: 00:02.0
+found VGA at PCI: 01:00.0
+Setting up VGA for PCI: 00:02.0
+Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
+Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
+Allocating resources...
+Reading resources...
+Root Device read_resources bus 0 link: 0
+CPU_CLUSTER: 0 read_resources bus 0 link: 0
+CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
+DOMAIN: 0000 read_resources bus 0 link: 0
+Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
+PCI: 00:01.0 read_resources bus 1 link: 0
+PCI: 00:01.0 read_resources bus 1 link: 0 done
+More than one caller of pci_ehci_read_resources from PCI: 00:1a.0
+PCI: 00:1c.0 read_resources bus 2 link: 0
+PCI: 00:1c.0 read_resources bus 2 link: 0 done
+PCI: 00:1c.1 read_resources bus 3 link: 0
+PCI: 00:1c.1 read_resources bus 3 link: 0 done
+PCI: 00:1c.4 read_resources bus 4 link: 0
+PCI: 00:1c.4 read_resources bus 4 link: 0 done
+PCI: 00:1d.0 EHCI BAR hook registered
+PCI: 00:1f.0 read_resources bus 0 link: 0
+PCI: 00:1f.0 read_resources bus 0 link: 0 done
+DOMAIN: 0000 read_resources bus 0 link: 0 done
+Root Device read_resources bus 0 link: 0 done
+Done reading resources.
+Show resources in subtree (Root Device)...After reading.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 00
+ APIC: 00
+ APIC: acac
+ DOMAIN: 0000 child on link 0 PCI: 00:00.0
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
+ PCI: 00:00.0
+ PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60
+ PCI: 00:01.0 child on link 0 PCI: 01:00.0
+ PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 01:00.0
+ PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10
+ PCI: 01:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 14
+ PCI: 01:00.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffffffffffff flags 1201 index 1c
+ PCI: 01:00.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 24
+ PCI: 01:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30
+ PCI: 01:00.1
+ PCI: 01:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
+ PCI: 00:02.0
+ PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
+ PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
+ PCI: 00:16.0
+ PCI: 00:16.0 resource base 0 size 10 align 12 gran 4 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:16.1
+ PCI: 00:16.2
+ PCI: 00:16.3
+ PCI: 00:19.0
+ PCI: 00:1a.0
+ PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
+ PCI: 00:1b.0
+ PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:1c.0
+ PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 00:1c.5
+ PCI: 00:1c.2
+ PCI: 00:1c.3
+ PCI: 00:1c.1 child on link 0 PCI: 03:00.0
+ PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 03:00.0
+ PCI: 03:00.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:1c.4 child on link 0 PCI: 04:00.0
+ PCI: 00:1c.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 04:00.0
+ PCI: 04:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
+ PCI: 04:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 18
+ PCI: 04:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
+ PCI: 00:1c.6
+ PCI: 00:1c.7
+ PCI: 00:1d.0
+ PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
+ PCI: 00:1e.0
+ PCI: 00:1f.0 child on link 0 PNP: 004e.1
+ PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PNP: 004e.1
+ PNP: 004e.1 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
+ PNP: 004e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 004e.4
+ PNP: 004e.4 resource base 295 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
+ PNP: 004e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 004e.5
+ PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
+ PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 72
+ PNP: 004e.6
+ PNP: 004e.6 resource base 1f size 0 align 0 gran 0 limit 0 flags c0000400 index c5
+ PNP: 004e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 004e.7
+ PNP: 004e.7 resource base a00 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
+ PNP: 004e.8
+ PNP: 004e.8 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
+ PNP: 004e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 004e.a
+ PNP: 004e.a resource base 90 size 0 align 0 gran 0 limit 0 flags c0000400 index e0
+ PNP: 004e.a resource base 0 size 0 align 0 gran 0 limit 0 flags c0000400 index f8
+ PNP: 004e.a resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 index f9
+ PNP: 004e.a resource base 0 size 0 align 0 gran 0 limit 0 flags c0000400 index fa
+ PCI: 00:1f.2
+ PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
+ PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
+ PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
+ PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
+ PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
+ PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
+ PCI: 00:1f.3
+ PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
+ PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:1f.5
+ PCI: 00:1f.6
+DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
+PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 01:00.0 24 * [0x0 - 0x7f] io
+PCI: 00:01.0 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done
+PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
+PCI: 00:1c.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:1c.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
+PCI: 00:1c.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 04:00.0 18 * [0x0 - 0xff] io
+PCI: 00:1c.4 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
+PCI: 00:01.0 1c * [0x0 - 0xfff] io
+PCI: 00:1c.4 1c * [0x1000 - 0x1fff] io
+PCI: 00:02.0 20 * [0x2000 - 0x203f] io
+PCI: 00:1f.2 20 * [0x2040 - 0x205f] io
+PCI: 00:1f.2 10 * [0x2060 - 0x2067] io
+PCI: 00:1f.2 18 * [0x2068 - 0x206f] io
+PCI: 00:1f.2 14 * [0x2070 - 0x2073] io
+PCI: 00:1f.2 1c * [0x2074 - 0x2077] io
+DOMAIN: 0000 io: base: 2078 size: 2078 align: 12 gran: 0 limit: ffff done
+DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
+PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 01:00.0 14 * [0x0 - 0xfffffff] prefmem
+PCI: 01:00.0 1c * [0x10000000 - 0x11ffffff] prefmem
+PCI: 00:01.0 prefmem: base: 12000000 size: 12000000 align: 28 gran: 20 limit: ffffffffffffffff done
+PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 01:00.0 10 * [0x0 - 0xffffff] mem
+PCI: 01:00.0 30 * [0x1000000 - 0x107ffff] mem
+PCI: 01:00.1 10 * [0x1080000 - 0x1083fff] mem
+PCI: 00:01.0 mem: base: 1084000 size: 1100000 align: 24 gran: 20 limit: ffffffff done
+PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:1c.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:1c.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:1c.1 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 03:00.0 10 * [0x0 - 0x7fff] mem
+PCI: 00:1c.1 mem: base: 8000 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:1c.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:1c.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:1c.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 04:00.0 30 * [0x0 - 0x1ffff] mem
+PCI: 04:00.0 10 * [0x20000 - 0x23fff] mem
+PCI: 00:1c.4 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:01.0 24 * [0x0 - 0x11ffffff] prefmem
+PCI: 00:02.0 18 * [0x20000000 - 0x2fffffff] prefmem
+PCI: 00:01.0 20 * [0x30000000 - 0x310fffff] mem
+PCI: 00:02.0 10 * [0x31400000 - 0x317fffff] mem
+PCI: 00:1c.1 20 * [0x31800000 - 0x318fffff] mem
+PCI: 00:1c.4 20 * [0x31900000 - 0x319fffff] mem
+PCI: 00:1b.0 10 * [0x31a00000 - 0x31a03fff] mem
+PCI: 00:1f.2 24 * [0x31a04000 - 0x31a047ff] mem
+PCI: 00:1a.0 10 * [0x31a05000 - 0x31a053ff] mem
+PCI: 00:1d.0 10 * [0x31a06000 - 0x31a063ff] mem
+PCI: 00:1f.3 10 * [0x31a07000 - 0x31a070ff] mem
+PCI: 00:16.0 10 * [0x31a08000 - 0x31a0800f] mem
+DOMAIN: 0000 mem: base: 31a08010 size: 31a08010 align: 28 gran: 0 limit: ffffffff done
+avoid_fixed_resources: DOMAIN: 0000
+avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
+avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
+constrain_resources: PCI: 00:00.0 60 base f0000000 limit f3ffffff mem (fixed)
+constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
+skipping PNP: 004e.6@c5 fixed resource, size=0!
+skipping PNP: 004e.a@e0 fixed resource, size=0!
+skipping PNP: 004e.a@f8 fixed resource, size=0!
+skipping PNP: 004e.a@f9 fixed resource, size=0!
+skipping PNP: 004e.a@fa fixed resource, size=0!
+avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff
+avoid_fixed_resources:@DOMAIN: 0000 10000100 base b0000000 limit efffffff
+Setting resources...
+DOMAIN: 0000 io: base:1000 size:2078 align:12 gran:0 limit:ffff
+PCI: 00:01.0 1c * [0x1000 - 0x1fff] io
+PCI: 00:1c.4 1c * [0x2000 - 0x2fff] io
+PCI: 00:02.0 20 * [0x3000 - 0x303f] io
+PCI: 00:1f.2 20 * [0x3040 - 0x305f] io
+PCI: 00:1f.2 10 * [0x3060 - 0x3067] io
+PCI: 00:1f.2 18 * [0x3068 - 0x306f] io
+PCI: 00:1f.2 14 * [0x3070 - 0x3073] io
+PCI: 00:1f.2 1c * [0x3074 - 0x3077] io
+DOMAIN: 0000 io: next_base: 3078 size: 2078 align: 12 gran: 0 done
+PCI: 00:01.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff
+PCI: 01:00.0 24 * [0x1000 - 0x107f] io
+PCI: 00:01.0 io: next_base: 1080 size: 1000 align: 12 gran: 12 done
+PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff
+PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done
+PCI: 00:1c.1 io: base:ffff size:0 align:12 gran:12 limit:ffff
+PCI: 00:1c.1 io: next_base: ffff size: 0 align: 12 gran: 12 done
+PCI: 00:1c.4 io: base:2000 size:1000 align:12 gran:12 limit:2fff
+PCI: 04:00.0 18 * [0x2000 - 0x20ff] io
+PCI: 00:1c.4 io: next_base: 2100 size: 1000 align: 12 gran: 12 done
+DOMAIN: 0000 mem: base:b0000000 size:31a08010 align:28 gran:0 limit:efffffff
+PCI: 00:01.0 24 * [0xb0000000 - 0xc1ffffff] prefmem
+PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem
+PCI: 00:01.0 20 * [0xe0000000 - 0xe10fffff] mem
+PCI: 00:02.0 10 * [0xe1400000 - 0xe17fffff] mem
+PCI: 00:1c.1 20 * [0xe1800000 - 0xe18fffff] mem
+PCI: 00:1c.4 20 * [0xe1900000 - 0xe19fffff] mem
+PCI: 00:1b.0 10 * [0xe1a00000 - 0xe1a03fff] mem
+PCI: 00:1f.2 24 * [0xe1a04000 - 0xe1a047ff] mem
+PCI: 00:1a.0 10 * [0xe1a05000 - 0xe1a053ff] mem
+PCI: 00:1d.0 10 * [0xe1a06000 - 0xe1a063ff] mem
+PCI: 00:1f.3 10 * [0xe1a07000 - 0xe1a070ff] mem
+PCI: 00:16.0 10 * [0xe1a08000 - 0xe1a0800f] mem
+DOMAIN: 0000 mem: next_base: e1a08010 size: 31a08010 align: 28 gran: 0 done
+PCI: 00:01.0 prefmem: base:b0000000 size:12000000 align:28 gran:20 limit:c1ffffff
+PCI: 01:00.0 14 * [0xb0000000 - 0xbfffffff] prefmem
+PCI: 01:00.0 1c * [0xc0000000 - 0xc1ffffff] prefmem
+PCI: 00:01.0 prefmem: next_base: c2000000 size: 12000000 align: 28 gran: 20 done
+PCI: 00:01.0 mem: base:e0000000 size:1100000 align:24 gran:20 limit:e10fffff
+PCI: 01:00.0 10 * [0xe0000000 - 0xe0ffffff] mem
+PCI: 01:00.0 30 * [0xe1000000 - 0xe107ffff] mem
+PCI: 01:00.1 10 * [0xe1080000 - 0xe1083fff] mem
+PCI: 00:01.0 mem: next_base: e1084000 size: 1100000 align: 24 gran: 20 done
+PCI: 00:1c.0 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:1c.0 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1c.0 mem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:1c.0 mem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1c.1 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:1c.1 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1c.1 mem: base:e1800000 size:100000 align:20 gran:20 limit:e18fffff
+PCI: 03:00.0 10 * [0xe1800000 - 0xe1807fff] mem
+PCI: 00:1c.1 mem: next_base: e1808000 size: 100000 align: 20 gran: 20 done
+PCI: 00:1c.4 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:1c.4 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1c.4 mem: base:e1900000 size:100000 align:20 gran:20 limit:e19fffff
+PCI: 04:00.0 30 * [0xe1900000 - 0xe191ffff] mem
+PCI: 04:00.0 10 * [0xe1920000 - 0xe1923fff] mem
+PCI: 00:1c.4 mem: next_base: e1924000 size: 100000 align: 20 gran: 20 done
+Root Device assign_resources, bus 0 link: 0
+TOUUD 0x47c600000 TOLUD 0x82a00000 TOM 0x400000000
+MEBASE 0x3ff000000
+IGD decoded, subtracting 32M UMA and 2M GTT
+TSEG base 0x80000000 size 8M
+Available memory below 4GB: 2048M
+Available memory above 4GB: 14278M
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+PCI: 00:01.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
+PCI: 00:01.0 24 <- [0x00b0000000 - 0x00c1ffffff] size 0x12000000 gran 0x14 bus 01 prefmem
+PCI: 00:01.0 20 <- [0x00e0000000 - 0x00e10fffff] size 0x01100000 gran 0x14 bus 01 mem
+PCI: 00:01.0 assign_resources, bus 1 link: 0
+PCI: 01:00.0 10 <- [0x00e0000000 - 0x00e0ffffff] size 0x01000000 gran 0x18 mem
+PCI: 01:00.0 14 <- [0x00b0000000 - 0x00bfffffff] size 0x10000000 gran 0x1c prefmem64
+PCI: 01:00.0 1c <- [0x00c0000000 - 0x00c1ffffff] size 0x02000000 gran 0x19 prefmem64
+PCI: 01:00.0 24 <- [0x0000001000 - 0x000000107f] size 0x00000080 gran 0x07 io
+PCI: 01:00.0 30 <- [0x00e1000000 - 0x00e107ffff] size 0x00080000 gran 0x13 romem
+PCI: 01:00.1 10 <- [0x00e1080000 - 0x00e1083fff] size 0x00004000 gran 0x0e mem
+PCI: 00:01.0 assign_resources, bus 1 link: 0
+PCI: 00:02.0 10 <- [0x00e1400000 - 0x00e17fffff] size 0x00400000 gran 0x16 mem64
+PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64
+PCI: 00:02.0 20 <- [0x0000003000 - 0x000000303f] size 0x00000040 gran 0x06 io
+PCI: 00:16.0 10 <- [0x00e1a08000 - 0x00e1a0800f] size 0x00000010 gran 0x04 mem64
+PCI: 00:1a.0 10 <- [0x00e1a05000 - 0x00e1a053ff] size 0x00000400 gran 0x0a mem
+PCI: 00:1b.0 10 <- [0x00e1a00000 - 0x00e1a03fff] size 0x00004000 gran 0x0e mem64
+PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
+PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem
+PCI: 00:1c.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 mem
+PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io
+PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem
+PCI: 00:1c.1 20 <- [0x00e1800000 - 0x00e18fffff] size 0x00100000 gran 0x14 bus 03 mem
+PCI: 00:1c.1 assign_resources, bus 3 link: 0
+PCI: 03:00.0 10 <- [0x00e1800000 - 0x00e1807fff] size 0x00008000 gran 0x0f mem64
+PCI: 00:1c.1 assign_resources, bus 3 link: 0
+PCI: 00:1c.4 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 04 io
+PCI: 00:1c.4 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 prefmem
+PCI: 00:1c.4 20 <- [0x00e1900000 - 0x00e19fffff] size 0x00100000 gran 0x14 bus 04 mem
+PCI: 00:1c.4 assign_resources, bus 4 link: 0
+PCI: 04:00.0 10 <- [0x00e1920000 - 0x00e1923fff] size 0x00004000 gran 0x0e mem64
+PCI: 04:00.0 18 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
+PCI: 04:00.0 30 <- [0x00e1900000 - 0x00e191ffff] size 0x00020000 gran 0x11 romem
+PCI: 00:1c.4 assign_resources, bus 4 link: 0
+PCI: 00:1d.0 EHCI Debug Port hook triggered
+PCI: 00:1d.0 10 <- [0x00e1a06000 - 0x00e1a063ff] size 0x00000400 gran 0x0a mem
+PCI: 00:1d.0 10 <- [0x00e1a06000 - 0x00e1a063ff] size 0x00000400 gran 0x0a mem
+PCI: 00:1d.0 EHCI Debug Port relocated
+PCI: 00:1f.0 assign_resources, bus 0 link: 0
+PNP: 004e.4 60 <- [0x0000000295 - 0x000000029c] size 0x00000008 gran 0x03 io
+PNP: 004e.4 70 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 irq
+PNP: 004e.6 c5 <- [0x000000001f - 0x000000001e] size 0x00000000 gran 0x00 irq
+ERROR: PNP: 004e.6 70 irq size: 0x0000000001 not assigned
+PNP: 004e.7 60 <- [0x0000000a00 - 0x0000000a07] size 0x00000008 gran 0x03 io
+PNP: 004e.a e0 <- [0x0000000090 - 0x000000008f] size 0x00000000 gran 0x00 irq
+PNP: 004e.a f8 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq
+PNP: 004e.a f9 <- [0x0000000009 - 0x0000000008] size 0x00000000 gran 0x00 irq
+PNP: 004e.a fa <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq
+PCI: 00:1f.0 assign_resources, bus 0 link: 0
+PCI: 00:1f.2 10 <- [0x0000003060 - 0x0000003067] size 0x00000008 gran 0x03 io
+PCI: 00:1f.2 14 <- [0x0000003070 - 0x0000003073] size 0x00000004 gran 0x02 io
+PCI: 00:1f.2 18 <- [0x0000003068 - 0x000000306f] size 0x00000008 gran 0x03 io
+PCI: 00:1f.2 1c <- [0x0000003074 - 0x0000003077] size 0x00000004 gran 0x02 io
+PCI: 00:1f.2 20 <- [0x0000003040 - 0x000000305f] size 0x00000020 gran 0x05 io
+PCI: 00:1f.2 24 <- [0x00e1a04000 - 0x00e1a047ff] size 0x00000800 gran 0x0b mem
+PCI: 00:1f.3 10 <- [0x00e1a07000 - 0x00e1a070ff] size 0x00000100 gran 0x08 mem64
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+Root Device assign_resources, bus 0 link: 0
+Done setting resources.
+Show resources in subtree (Root Device)...After assigning values.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 00
+ APIC: 00
+ APIC: acac
+ DOMAIN: 0000 child on link 0 PCI: 00:00.0
+ DOMAIN: 0000 resource base 1000 size 2078 align 12 gran 0 limit ffff flags 40040100 index 10000000
+ DOMAIN: 0000 resource base b0000000 size 31a08010 align 28 gran 0 limit efffffff flags 40040200 index 10000100
+ DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
+ DOMAIN: 0000 resource base 100000 size 7ff00000 align 0 gran 0 limit 0 flags e0004200 index 4
+ DOMAIN: 0000 resource base 100000000 size 37c600000 align 0 gran 0 limit 0 flags e0004200 index 5
+ DOMAIN: 0000 resource base 80000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6
+ DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7
+ DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 8
+ DOMAIN: 0000 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
+ DOMAIN: 0000 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
+ PCI: 00:00.0
+ PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60
+ PCI: 00:01.0 child on link 0 PCI: 01:00.0
+ PCI: 00:01.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c
+ PCI: 00:01.0 resource base b0000000 size 12000000 align 28 gran 20 limit c1ffffff flags 60081202 index 24
+ PCI: 00:01.0 resource base e0000000 size 1100000 align 24 gran 20 limit e10fffff flags 60080202 index 20
+ PCI: 01:00.0
+ PCI: 01:00.0 resource base e0000000 size 1000000 align 24 gran 24 limit e0ffffff flags 60000200 index 10
+ PCI: 01:00.0 resource base b0000000 size 10000000 align 28 gran 28 limit bfffffff flags 60001201 index 14
+ PCI: 01:00.0 resource base c0000000 size 2000000 align 25 gran 25 limit c1ffffff flags 60001201 index 1c
+ PCI: 01:00.0 resource base 1000 size 80 align 7 gran 7 limit 107f flags 60000100 index 24
+ PCI: 01:00.0 resource base e1000000 size 80000 align 19 gran 19 limit e107ffff flags 60002200 index 30
+ PCI: 01:00.1
+ PCI: 01:00.1 resource base e1080000 size 4000 align 14 gran 14 limit e1083fff flags 60000200 index 10
+ PCI: 00:02.0
+ PCI: 00:02.0 resource base e1400000 size 400000 align 22 gran 22 limit e17fffff flags 60000201 index 10
+ PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60001201 index 18
+ PCI: 00:02.0 resource base 3000 size 40 align 6 gran 6 limit 303f flags 60000100 index 20
+ PCI: 00:16.0
+ PCI: 00:16.0 resource base e1a08000 size 10 align 12 gran 4 limit e1a0800f flags 60000201 index 10
+ PCI: 00:16.1
+ PCI: 00:16.2
+ PCI: 00:16.3
+ PCI: 00:19.0
+ PCI: 00:1a.0
+ PCI: 00:1a.0 resource base e1a05000 size 400 align 12 gran 10 limit e1a053ff flags 60000200 index 10
+ PCI: 00:1b.0
+ PCI: 00:1b.0 resource base e1a00000 size 4000 align 14 gran 14 limit e1a03fff flags 60000201 index 10
+ PCI: 00:1c.0
+ PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
+ PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20
+ PCI: 00:1c.5
+ PCI: 00:1c.2
+ PCI: 00:1c.3
+ PCI: 00:1c.1 child on link 0 PCI: 03:00.0
+ PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
+ PCI: 00:1c.1 resource base e1800000 size 100000 align 20 gran 20 limit e18fffff flags 60080202 index 20
+ PCI: 03:00.0
+ PCI: 03:00.0 resource base e1800000 size 8000 align 15 gran 15 limit e1807fff flags 60000201 index 10
+ PCI: 00:1c.4 child on link 0 PCI: 04:00.0
+ PCI: 00:1c.4 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c
+ PCI: 00:1c.4 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
+ PCI: 00:1c.4 resource base e1900000 size 100000 align 20 gran 20 limit e19fffff flags 60080202 index 20
+ PCI: 04:00.0
+ PCI: 04:00.0 resource base e1920000 size 4000 align 14 gran 14 limit e1923fff flags 60000201 index 10
+ PCI: 04:00.0 resource base 2000 size 100 align 8 gran 8 limit 20ff flags 60000100 index 18
+ PCI: 04:00.0 resource base e1900000 size 20000 align 17 gran 17 limit e191ffff flags 60002200 index 30
+ PCI: 00:1c.6
+ PCI: 00:1c.7
+ PCI: 00:1d.0
+ PCI: 00:1d.0 resource base e1a06000 size 400 align 12 gran 10 limit e1a063ff flags 60000200 index 10
+ PCI: 00:1e.0
+ PCI: 00:1f.0 child on link 0 PNP: 004e.1
+ PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PNP: 004e.1
+ PNP: 004e.1 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
+ PNP: 004e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 004e.4
+ PNP: 004e.4 resource base 295 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
+ PNP: 004e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 004e.5
+ PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
+ PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 72
+ PNP: 004e.6
+ PNP: 004e.6 resource base 1f size 0 align 0 gran 0 limit 0 flags e0000400 index c5
+ PNP: 004e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 004e.7
+ PNP: 004e.7 resource base a00 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
+ PNP: 004e.8
+ PNP: 004e.8 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
+ PNP: 004e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 004e.a
+ PNP: 004e.a resource base 90 size 0 align 0 gran 0 limit 0 flags e0000400 index e0
+ PNP: 004e.a resource base 0 size 0 align 0 gran 0 limit 0 flags e0000400 index f8
+ PNP: 004e.a resource base 9 size 0 align 0 gran 0 limit 0 flags e0000400 index f9
+ PNP: 004e.a resource base 0 size 0 align 0 gran 0 limit 0 flags e0000400 index fa
+ PCI: 00:1f.2
+ PCI: 00:1f.2 resource base 3060 size 8 align 3 gran 3 limit 3067 flags 60000100 index 10
+ PCI: 00:1f.2 resource base 3070 size 4 align 2 gran 2 limit 3073 flags 60000100 index 14
+ PCI: 00:1f.2 resource base 3068 size 8 align 3 gran 3 limit 306f flags 60000100 index 18
+ PCI: 00:1f.2 resource base 3074 size 4 align 2 gran 2 limit 3077 flags 60000100 index 1c
+ PCI: 00:1f.2 resource base 3040 size 20 align 5 gran 5 limit 305f flags 60000100 index 20
+ PCI: 00:1f.2 resource base e1a04000 size 800 align 12 gran 11 limit e1a047ff flags 60000200 index 24
+ PCI: 00:1f.3
+ PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
+ PCI: 00:1f.3 resource base e1a07000 size 100 align 12 gran 8 limit e1a070ff flags 60000201 index 10
+ PCI: 00:1f.5
+ PCI: 00:1f.6
+Done allocating resources.
+BS: BS_DEV_RESOURCES times (us): entry 0 run 3079 exit 0
+Enabling resources...
+PCI: 00:00.0 subsystem <- 174b/1007
+PCI: 00:00.0 cmd <- 06
+PCI: 00:01.0 bridge ctrl <- 0003
+PCI: 00:01.0 cmd <- 07
+PCI: 00:02.0 subsystem <- 8086/2010
+PCI: 00:02.0 cmd <- 03
+PCI: 00:16.0 subsystem <- 174b/1007
+PCI: 00:16.0 cmd <- 02
+PCI: 00:1a.0 subsystem <- 174b/1007
+PCI: 00:1a.0 cmd <- 102
+PCI: 00:1b.0 subsystem <- 8086/1c20
+PCI: 00:1b.0 cmd <- 102
+PCI: 00:1c.0 bridge ctrl <- 0003
+PCI: 00:1c.0 subsystem <- 174b/1007
+PCI: 00:1c.0 cmd <- 100
+PCI: 00:1c.1 bridge ctrl <- 0003
+PCI: 00:1c.1 subsystem <- 174b/1007
+PCI: 00:1c.1 cmd <- 106
+PCI: 00:1c.4 bridge ctrl <- 0003
+PCI: 00:1c.4 subsystem <- 174b/1007
+PCI: 00:1c.4 cmd <- 107
+PCI: 00:1d.0 subsystem <- 174b/1007
+PCI: 00:1d.0 cmd <- 102
+pch_decode_init
+PCI: 00:1f.0 subsystem <- 174b/1007
+PCI: 00:1f.0 cmd <- 107
+PCI: 00:1f.2 subsystem <- 174b/1007
+PCI: 00:1f.2 cmd <- 03
+PCI: 00:1f.3 subsystem <- 174b/1007
+PCI: 00:1f.3 cmd <- 103
+PCI: 01:00.0 cmd <- 03
+PCI: 01:00.1 cmd <- 02
+PCI: 03:00.0 cmd <- 02
+PCI: 04:00.0 cmd <- 03
+done.
+BS: BS_DEV_ENABLE times (us): entry 0 run 200 exit 0
+Initializing devices...
+Root Device init ...
+Root Device init finished in 1 usecs
+CPU_CLUSTER: 0 init ...
+start_eip=0x00001000, code_size=0x00000031
+Setting up SMI for CPU
+Loading module at 00038000 with entry 00038000. filesize: 0x160 memsize: 0x160
+Processing 10 relocs. Offset value of 0x00038000
+Adjusting 00038002: 0x00000024 -> 0x00038024
+Adjusting 0003801d: 0x0000003c -> 0x0003803c
+Adjusting 00038026: 0x00000024 -> 0x00038024
+Adjusting 00038054: 0x000000d8 -> 0x000380d8
+Adjusting 00038066: 0x00000160 -> 0x00038160
+Adjusting 0003806d: 0x000000c0 -> 0x000380c0
+Adjusting 00038075: 0x000000c4 -> 0x000380c4
+Adjusting 0003807e: 0x000000d0 -> 0x000380d0
+Adjusting 00038085: 0x000000cc -> 0x000380cc
+Adjusting 0003808b: 0x000000c8 -> 0x000380c8
+SMM Module: stub loaded at 00038000. Will call 7ffb560d(7ffd3860)
+Installing SMM handler to 0x80000000
+Loading module at 80010000 with entry 80010541. filesize: 0x1590 memsize: 0x55b0
+Processing 65 relocs. Offset value of 0x80010000
+Adjusting 80010036: 0x0000148c -> 0x8001148c
+Adjusting 80010055: 0x0000148c -> 0x8001148c
+Adjusting 80010108: 0x0000148c -> 0x8001148c
+Adjusting 80010198: 0x0000149c -> 0x8001149c
+Adjusting 800104b8: 0x00001590 -> 0x80011590
+Adjusting 8001050e: 0x00001588 -> 0x80011588
+Adjusting 80010524: 0x00001500 -> 0x80011500
+Adjusting 8001054a: 0x00001590 -> 0x80011590
+Adjusting 80010558: 0x00001590 -> 0x80011590
+Adjusting 80010565: 0x00001580 -> 0x80011580
+Adjusting 80010570: 0x00001580 -> 0x80011580
+Adjusting 80010584: 0x00001584 -> 0x80011584
+Adjusting 8001058a: 0x00001594 -> 0x80011594
+Adjusting 80010592: 0x00001584 -> 0x80011584
+Adjusting 800105af: 0x00001594 -> 0x80011594
+Adjusting 800105b8: 0x00001580 -> 0x80011580
+Adjusting 8001060f: 0x000014bc -> 0x800114bc
+Adjusting 80010721: 0x00001478 -> 0x80011478
+Adjusting 80010a71: 0x00001598 -> 0x80011598
+Adjusting 80010aa0: 0x0000159c -> 0x8001159c
+Adjusting 80010ab3: 0x00001598 -> 0x80011598
+Adjusting 80010ad6: 0x0000159c -> 0x8001159c
+Adjusting 80010b99: 0x00001598 -> 0x80011598
+Adjusting 80010dd1: 0x0000159c -> 0x8001159c
+Adjusting 80010fd8: 0x0000159c -> 0x8001159c
+Adjusting 800110b7: 0x00001588 -> 0x80011588
+Adjusting 800110c7: 0x00001588 -> 0x80011588
+Adjusting 800110dc: 0x00001588 -> 0x80011588
+Adjusting 800110fd: 0x00001588 -> 0x80011588
+Adjusting 80011126: 0x00001588 -> 0x80011588
+Adjusting 80011143: 0x00001588 -> 0x80011588
+Adjusting 80011156: 0x000015a8 -> 0x800115a8
+Adjusting 8001119a: 0x000015a0 -> 0x800115a0
+Adjusting 800111b7: 0x000015a0 -> 0x800115a0
+Adjusting 800111d5: 0x000015a8 -> 0x800115a8
+Adjusting 800111db: 0x000015a4 -> 0x800115a4
+Adjusting 800111e8: 0x00001588 -> 0x80011588
+Adjusting 8001123e: 0x000015a4 -> 0x800115a4
+Adjusting 80011294: 0x000014cc -> 0x800114cc
+Adjusting 800112b1: 0x00001588 -> 0x80011588
+Adjusting 800112d0: 0x000014e0 -> 0x800114e0
+Adjusting 800112d5: 0x000015a4 -> 0x800115a4
+Adjusting 800113a6: 0x00001588 -> 0x80011588
+Adjusting 800113d4: 0x00001588 -> 0x80011588
+Adjusting 80011402: 0x00001588 -> 0x80011588
+Adjusting 80011428: 0x00001588 -> 0x80011588
+Adjusting 80011435: 0x000015a4 -> 0x800115a4
+Adjusting 80011449: 0x00001588 -> 0x80011588
+Adjusting 80011470: 0x00001458 -> 0x80011458
+Adjusting 80011478: 0x00000021 -> 0x80010021
+Adjusting 8001147c: 0x00001458 -> 0x80011458
+Adjusting 80011484: 0x00000092 -> 0x80010092
+Adjusting 80011490: 0x000014a8 -> 0x800114a8
+Adjusting 800114a8: 0x000002d0 -> 0x800102d0
+Adjusting 800114ac: 0x000002dc -> 0x800102dc
+Adjusting 800114b0: 0x000002df -> 0x800102df
+Adjusting 80011510: 0x0000127b -> 0x8001127b
+Adjusting 80011514: 0x0000110d -> 0x8001110d
+Adjusting 80011520: 0x000013ff -> 0x800113ff
+Adjusting 80011524: 0x000010b4 -> 0x800110b4
+Adjusting 80011528: 0x000010d5 -> 0x800110d5
+Adjusting 8001152c: 0x000010d0 -> 0x800110d0
+Adjusting 80011534: 0x000011e5 -> 0x800111e5
+Adjusting 80011538: 0x000010c4 -> 0x800110c4
+Adjusting 80011554: 0x00001229 -> 0x80011229
+Loading module at 80008000 with entry 80008000. filesize: 0x160 memsize: 0x160
+Processing 10 relocs. Offset value of 0x80008000
+Adjusting 80008002: 0x00000024 -> 0x80008024
+Adjusting 8000801d: 0x0000003c -> 0x8000803c
+Adjusting 80008026: 0x00000024 -> 0x80008024
+Adjusting 80008054: 0x000000d8 -> 0x800080d8
+Adjusting 80008066: 0x00000160 -> 0x80008160
+Adjusting 8000806d: 0x000000c0 -> 0x800080c0
+Adjusting 80008075: 0x000000c4 -> 0x800080c4
+Adjusting 8000807e: 0x000000d0 -> 0x800080d0
+Adjusting 80008085: 0x000000cc -> 0x800080cc
+Adjusting 8000808b: 0x000000c8 -> 0x800080c8
+SMM Module: placing jmp sequence at 80007c00 rel16 0x03fd
+SMM Module: placing jmp sequence at 80007800 rel16 0x07fd
+SMM Module: placing jmp sequence at 80007400 rel16 0x0bfd
+SMM Module: placing jmp sequence at 80007000 rel16 0x0ffd
+SMM Module: placing jmp sequence at 80006c00 rel16 0x13fd
+SMM Module: placing jmp sequence at 80006800 rel16 0x17fd
+SMM Module: placing jmp sequence at 80006400 rel16 0x1bfd
+SMM Module: stub loaded at 80008000. Will call 80010541(00000000)
+Initializing southbridge SMI... ... pmbase = 0x0500
+
+SMI_STS: PM1
+PM1_STS: WAK PWRBTN TMROF
+GPE0_STS: GPIO14 GPIO11 GPIO10 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 TCO_SCI
+ALT_GP_SMI_STS: GPI14 GPI11 GPI10 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0
+TCO_STS:
+ ... raise SMI#
+In relocation handler: cpu 0
+New SMBASE=0x80000000 IEDBASE=0x80400000 @ 0003fc00
+Writing SMRR. base = 0x80000006, mask=0xff800800
+Relocation complete.
+Locking SMM.
+Initializing CPU #0
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 15440 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x1b
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Physical address space:
+0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
+0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
+0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
+0x0000000080000000 - 0x00000000b0000000 size 0x30000000 type 0
+0x00000000b0000000 - 0x00000000c2000000 size 0x12000000 type 1
+0x00000000c2000000 - 0x00000000d0000000 size 0x0e000000 type 0
+0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
+0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
+0x0000000100000000 - 0x000000047c600000 size 0x37c600000 type 6
+MTRR addr 0x0-0x10 set to 6 type @ 0
+MTRR addr 0x10-0x20 set to 6 type @ 1
+MTRR addr 0x20-0x30 set to 6 type @ 2
+MTRR addr 0x30-0x40 set to 6 type @ 3
+MTRR addr 0x40-0x50 set to 6 type @ 4
+MTRR addr 0x50-0x60 set to 6 type @ 5
+MTRR addr 0x60-0x70 set to 6 type @ 6
+MTRR addr 0x70-0x80 set to 6 type @ 7
+MTRR addr 0x80-0x84 set to 6 type @ 8
+MTRR addr 0x84-0x88 set to 6 type @ 9
+MTRR addr 0x88-0x8c set to 6 type @ 10
+MTRR addr 0x8c-0x90 set to 6 type @ 11
+MTRR addr 0x90-0x94 set to 6 type @ 12
+MTRR addr 0x94-0x98 set to 6 type @ 13
+MTRR addr 0x98-0x9c set to 6 type @ 14
+MTRR addr 0x9c-0xa0 set to 6 type @ 15
+MTRR addr 0xa0-0xa4 set to 0 type @ 16
+MTRR addr 0xa4-0xa8 set to 0 type @ 17
+MTRR addr 0xa8-0xac set to 0 type @ 18
+MTRR addr 0xac-0xb0 set to 0 type @ 19
+MTRR addr 0xb0-0xb4 set to 0 type @ 20
+MTRR addr 0xb4-0xb8 set to 0 type @ 21
+MTRR addr 0xb8-0xbc set to 0 type @ 22
+MTRR addr 0xbc-0xc0 set to 0 type @ 23
+MTRR addr 0xc0-0xc1 set to 6 type @ 24
+MTRR addr 0xc1-0xc2 set to 6 type @ 25
+MTRR addr 0xc2-0xc3 set to 6 type @ 26
+MTRR addr 0xc3-0xc4 set to 6 type @ 27
+MTRR addr 0xc4-0xc5 set to 6 type @ 28
+MTRR addr 0xc5-0xc6 set to 6 type @ 29
+MTRR addr 0xc6-0xc7 set to 6 type @ 30
+MTRR addr 0xc7-0xc8 set to 6 type @ 31
+MTRR addr 0xc8-0xc9 set to 6 type @ 32
+MTRR addr 0xc9-0xca set to 6 type @ 33
+MTRR addr 0xca-0xcb set to 6 type @ 34
+MTRR addr 0xcb-0xcc set to 6 type @ 35
+MTRR addr 0xcc-0xcd set to 6 type @ 36
+MTRR addr 0xcd-0xce set to 6 type @ 37
+MTRR addr 0xce-0xcf set to 6 type @ 38
+MTRR addr 0xcf-0xd0 set to 6 type @ 39
+MTRR addr 0xd0-0xd1 set to 6 type @ 40
+MTRR addr 0xd1-0xd2 set to 6 type @ 41
+MTRR addr 0xd2-0xd3 set to 6 type @ 42
+MTRR addr 0xd3-0xd4 set to 6 type @ 43
+MTRR addr 0xd4-0xd5 set to 6 type @ 44
+MTRR addr 0xd5-0xd6 set to 6 type @ 45
+MTRR addr 0xd6-0xd7 set to 6 type @ 46
+MTRR addr 0xd7-0xd8 set to 6 type @ 47
+MTRR addr 0xd8-0xd9 set to 6 type @ 48
+MTRR addr 0xd9-0xda set to 6 type @ 49
+MTRR addr 0xda-0xdb set to 6 type @ 50
+MTRR addr 0xdb-0xdc set to 6 type @ 51
+MTRR addr 0xdc-0xdd set to 6 type @ 52
+MTRR addr 0xdd-0xde set to 6 type @ 53
+MTRR addr 0xde-0xdf set to 6 type @ 54
+MTRR addr 0xdf-0xe0 set to 6 type @ 55
+MTRR addr 0xe0-0xe1 set to 6 type @ 56
+MTRR addr 0xe1-0xe2 set to 6 type @ 57
+MTRR addr 0xe2-0xe3 set to 6 type @ 58
+MTRR addr 0xe3-0xe4 set to 6 type @ 59
+MTRR addr 0xe4-0xe5 set to 6 type @ 60
+MTRR addr 0xe5-0xe6 set to 6 type @ 61
+MTRR addr 0xe6-0xe7 set to 6 type @ 62
+MTRR addr 0xe7-0xe8 set to 6 type @ 63
+MTRR addr 0xe8-0xe9 set to 6 type @ 64
+MTRR addr 0xe9-0xea set to 6 type @ 65
+MTRR addr 0xea-0xeb set to 6 type @ 66
+MTRR addr 0xeb-0xec set to 6 type @ 67
+MTRR addr 0xec-0xed set to 6 type @ 68
+MTRR addr 0xed-0xee set to 6 type @ 69
+MTRR addr 0xee-0xef set to 6 type @ 70
+MTRR addr 0xef-0xf0 set to 6 type @ 71
+MTRR addr 0xf0-0xf1 set to 6 type @ 72
+MTRR addr 0xf1-0xf2 set to 6 type @ 73
+MTRR addr 0xf2-0xf3 set to 6 type @ 74
+MTRR addr 0xf3-0xf4 set to 6 type @ 75
+MTRR addr 0xf4-0xf5 set to 6 type @ 76
+MTRR addr 0xf5-0xf6 set to 6 type @ 77
+MTRR addr 0xf6-0xf7 set to 6 type @ 78
+MTRR addr 0xf7-0xf8 set to 6 type @ 79
+MTRR addr 0xf8-0xf9 set to 6 type @ 80
+MTRR addr 0xf9-0xfa set to 6 type @ 81
+MTRR addr 0xfa-0xfb set to 6 type @ 82
+MTRR addr 0xfb-0xfc set to 6 type @ 83
+MTRR addr 0xfc-0xfd set to 6 type @ 84
+MTRR addr 0xfd-0xfe set to 6 type @ 85
+MTRR addr 0xfe-0xff set to 6 type @ 86
+MTRR addr 0xff-0x100 set to 6 type @ 87
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+CPU physical address size: 36 bits
+MTRR: Removing WRCOMB type. WB/UC MTRR counts: 9/11 > 8.
+MTRR: default type WB/UC MTRR counts: 1/8.
+MTRR: WB selected as default type.
+MTRR: 0 base 0x0000000080000000 mask 0x0000000f80000000 type 0
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local APIC... apic_id: 0x00 done.
+VMX status: enabled, locked
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+Turbo is available but hidden
+Turbo has been enabled
+CPU: 0 has 4 cores, 2 threads per core
+CPU: 0 has core 1
+CPU1: stack_base 7ffcd000, stack_end 7ffcdff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 1.
+After apic_write.
+In relocation handler: cpu 1
+New SMBASE=0x7ffffc00 IEDBASE=0x80400000 @ 0003fc00
+Writing SMRR. base = 0x80000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 1.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+Initializing CPU #1
+CPU: 0 has core 2
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 15440 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x1b
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+CPU physical address size: 36 bits
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local APIC... apic_id: 0x01 done.
+VMX status: enabled, locked
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+CPU #1 initialized
+CPU2: stack_base 7ffcc000, stack_end 7ffccff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 2.
+After apic_write.
+In relocation handler: cpu 2
+Startup point 1.
+Waiting for send to finish...
++New SMBASE=0x7ffff800 IEDBASE=0x80400000 @ 0003fc00
+Sending STARTUP #2 to 2.
+After apic_write.
+Writing SMRR. base = 0x80000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU: 0 has core 3
+Initializing CPU #2
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 15440 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x0
+microcode: updated to revision 0x1b date=2014-05-29
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+CPU physical address size: 36 bits
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local APIC... apic_id: 0x02 done.
+VMX status: enabled, locked
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+CPU #2 initialized
+CPU3: stack_base 7ffcb000, stack_end 7ffcbff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 3.
+After apic_write.
+In relocation handler: cpu 3
+New SMBASE=0x7ffff400 IEDBASE=0x80400000 @ 0003fc00
+Writing SMRR. base = 0x80000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 3.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU: 0 has core 4
+CPU4: stack_base 7ffca000, stack_end 7ffcaff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 4.
+After apic_write.
+In relocation handler: cpu 4
+Startup point 1.
+Waiting for send to finish...
++New SMBASE=0x7ffff000 IEDBASE=0x80400000 @ 0003fc00
+Sending STARTUP #2 to 4.
+After apic_write.
+Writing SMRR. base = 0x80000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU: 0 has core 5
+Initializing CPU #4
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 15440 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x0
+microcode: updated to revision 0x1b date=2014-05-29
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+CPU physical address size: 36 bits
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local APIC... apic_id: 0x04 done.
+VMX status: enabled, locked
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+CPU #4 initialized
+CPU5: stack_base 7ffc9000, stack_end 7ffc9ff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 5.
+After apic_write.
+In relocation handler: cpu 5
+New SMBASE=0x7fffec00 IEDBASE=0x80400000 @ 0003fc00
+Writing SMRR. base = 0x80000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 5.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU: 0 has core 6
+Initializing CPU #5
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 15440 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x1b
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+CPU physical address size: 36 bits
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local APIC... apic_id: 0x05 done.
+VMX status: enabled, locked
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+CPU #5 initialized
+CPU6: stack_base 7ffc8000, stack_end 7ffc8ff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 6.
+After apic_write.
+In relocation handler: cpu 6
+Startup point 1.
+Waiting for send to finish...
++New SMBASE=0x7fffe800 IEDBASE=0x80400000 @ 0003fc00
+Sending STARTUP #2 to 6.
+After apic_write.
+Writing SMRR. base = 0x80000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU: 0 has core 7
+Initializing CPU #6
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 15440 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x0
+microcode: updated to revision 0x1b date=2014-05-29
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+CPU physical address size: 36 bits
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local APIC... apic_id: 0x06 done.
+VMX status: enabled, locked
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+CPU #6 initialized
+CPU7: stack_base 7ffc7000, stack_end 7ffc7ff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 7.
+After apic_write.
+In relocation handler: cpu 7
+New SMBASE=0x7fffe400 IEDBASE=0x80400000 @ 0003fc00
+Writing SMRR. base = 0x80000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 7.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU #0 initialized
+Waiting for 2 CPUS to stop
+Initializing CPU #3
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 15440 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x1b
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+CPU physical address size: 36 bits
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local APIC... apic_id: 0x03 done.
+VMX status: enabled, locked
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+CPU #3 initialized
+Waiting for 1 CPUS to stop
+Initializing CPU #7
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 15440 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x1b
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+CPU physical address size: 36 bits
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local APIC... apic_id: 0x07 done.
+VMX status: enabled, locked
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+CPU #7 initialized
+All AP CPUs stopped (990 loops)
+CPU0: stack: 7ffce000 - 7ffcf000, lowest used address 7ffcea80, stack used: 1408 bytes
+CPU1: stack: 7ffcd000 - 7ffce000, lowest used address 7ffcdc54, stack used: 940 bytes
+CPU2: stack: 7ffcc000 - 7ffcd000, lowest used address 7ffccc54, stack used: 940 bytes
+CPU3: stack: 7ffcb000 - 7ffcc000, lowest used address 7ffcbc54, stack used: 940 bytes
+CPU4: stack: 7ffca000 - 7ffcb000, lowest used address 7ffcac54, stack used: 940 bytes
+CPU5: stack: 7ffc9000 - 7ffca000, lowest used address 7ffc9c54, stack used: 940 bytes
+CPU6: stack: 7ffc8000 - 7ffc9000, lowest used address 7ffc8c54, stack used: 940 bytes
+CPU7: stack: 7ffc7000 - 7ffc8000, lowest used address 7ffc7c54, stack used: 940 bytes
+CPU_CLUSTER: 0 init finished in 212497 usecs
+PCI: 00:00.0 init ...
+Disabling PEG12.
+Disabling PEG11.
+Disabling PEG60.
+Set BIOS_RESET_CPL
+CPU TDP: 77 Watts
+PCI: 00:00.0 init finished in 1011 usecs
+PCI: 00:02.0 init ...
+GT Power Management Init
+IVB GT2 35W Power Meter Weights
+GT Power Management Init (post VBIOS)
+PCI: 00:02.0 init finished in 468 usecs
+PCI: 00:16.0 init ...
+ME: FW Partition Table : OK
+ME: Bringup Loader Failure : NO
+ME: Firmware Init Complete : NO
+ME: Manufacturing Mode : YES
+ME: Boot Options Present : NO
+ME: Update In Progress : NO
+ME: Current Working State : Recovery
+ME: Current Operation State : Bring up
+ME: Current Operation Mode : Security Override via Jumper
+ME: Error Code : No Error
+ME: Progress Phase : BUP Phase
+ME: Power Management Event : Clean Moff->Mx wake
+ME: Progress Phase State : 0x52
+ME: BIOS path: Disable
+PCI: 00:16.0 init finished in 20 usecs
+PCI: 00:1a.0 init ...
+EHCI: Setting up controller.. done.
+PCI: 00:1a.0 init finished in 13 usecs
+PCI: 00:1b.0 init ...
+Azalia: base = e1a00000
+Azalia: codec_mask = 0c
+Azalia: Initializing codec #3
+Azalia: codec viddid: 80862805
+Azalia: verb_size: 16
+Azalia: verb loaded.
+Azalia: Initializing codec #2
+Azalia: codec viddid: 10ec0892
+Azalia: verb_size: 60
+Azalia: verb loaded.
+PCI: 00:1b.0 init finished in 5265 usecs
+PCI: 00:1c.0 init ...
+Initializing PCH PCIe bridge.
+PCI: 00:1c.0 init finished in 11 usecs
+PCI: 00:1c.1 init ...
+Initializing PCH PCIe bridge.
+PCI: 00:1c.1 init finished in 8 usecs
+PCI: 00:1c.4 init ...
+Initializing PCH PCIe bridge.
+PCI: 00:1c.4 init finished in 8 usecs
+PCI: 00:1d.0 init ...
+EHCI: Setting up controller.. done.
+PCI: 00:1d.0 init finished in 13 usecs
+PCI: 00:1f.0 init ...
+pch: lpc_init
+IOAPIC: Initializing IOAPIC at 0xfec00000
+IOAPIC: Bootstrap Processor Local APIC = 0x00
+IOAPIC: ID = 0x02
+IOAPIC: Dumping registers
+ reg 0x0000: 0x02000000
+ reg 0x0001: 0x00170020
+ reg 0x0002: 0x00170020
+CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 1b440 size 5b0
+Set power on after power failure.
+CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 1b440 size 5b0
+NMI sources enabled.
+CougarPoint PM init
+rtc_failed = 0x0
+RTC Init
+Enabling BIOS updates outside of SMM... Disabling ACPI via APMC:
+done.
+pch_spi_init
+PCI: 00:1f.0 init finished in 1007 usecs
+PCI: 00:1f.2 init ...
+SATA: Initializing...
+CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 1b440 size 5b0
+SATA: Controller in AHCI mode.
+ABAR: e1a04000
+PCI: 00:1f.2 init finished in 361 usecs
+PCI: 00:1f.3 init ...
+PCI: 00:1f.3 init finished in 6 usecs
+PCI: 01:00.0 init ...
+PCI: 01:00.0 init finished in 0 usecs
+PCI: 01:00.1 init ...
+PCI: 01:00.1 init finished in 0 usecs
+PCI: 03:00.0 init ...
+PCI: 03:00.0 init finished in 0 usecs
+PCI: 04:00.0 init ...
+PCI: 04:00.0 init finished in 0 usecs
+PNP: 004e.4 init ...
+PNP: 004e.4 init finished in 69 usecs
+PNP: 004e.6 init ...
+PNP: 004e.6 init finished in 0 usecs
+PNP: 004e.7 init ...
+PNP: 004e.7 init finished in 0 usecs
+PNP: 004e.a init ...
+PNP: 004e.a init finished in 0 usecs
+Devices initialized
+Show all devs... After init.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+APIC: 00: enabled 1
+APIC: acac: enabled 0
+DOMAIN: 0000: enabled 1
+PCI: 00:16.0: enabled 1
+PCI: 00:16.1: enabled 0
+PCI: 00:16.2: enabled 0
+PCI: 00:16.3: enabled 0
+PCI: 00:19.0: enabled 0
+PCI: 00:1a.0: enabled 1
+PCI: 00:1b.0: enabled 1
+PCI: 00:1c.0: enabled 1
+PCI: 00:1c.5: enabled 0
+PCI: 00:1c.2: enabled 0
+PCI: 00:1c.3: enabled 0
+PCI: 00:1c.1: enabled 1
+PCI: 00:1c.4: enabled 1
+PCI: 00:1c.6: enabled 0
+PCI: 00:1c.7: enabled 0
+PCI: 00:1d.0: enabled 1
+PCI: 00:1e.0: enabled 0
+PCI: 00:1f.0: enabled 1
+PNP: 004e.1: enabled 0
+PNP: 004e.4: enabled 1
+PNP: 004e.5: enabled 0
+PNP: 004e.6: enabled 1
+PNP: 004e.7: enabled 1
+PNP: 004e.8: enabled 0
+PNP: 004e.a: enabled 1
+PCI: 00:1f.2: enabled 1
+PCI: 00:1f.3: enabled 1
+PCI: 00:1f.5: enabled 0
+PCI: 00:1f.6: enabled 0
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 1
+PCI: 00:02.0: enabled 1
+PCI: 01:00.0: enabled 1
+PCI: 01:00.1: enabled 1
+PCI: 03:00.0: enabled 1
+PCI: 04:00.0: enabled 1
+APIC: 01: enabled 1
+APIC: 02: enabled 1
+APIC: 03: enabled 1
+APIC: 04: enabled 1
+APIC: 05: enabled 1
+APIC: 06: enabled 1
+APIC: 07: enabled 1
+BS: BS_DEV_INIT times (us): entry 5 run 220910 exit 0
+Finalize devices...
+PCI: 00:1f.0 final
+Devices finalized
+BS: BS_POST_DEVICE times (us): entry 0 run 4 exit 0
+BS: BS_OS_RESUME_CHECK times (us): entry 0 run 2 exit 0
+Updating MRC cache data.
+No MRC cache in cbmem. Can't update flash.
+CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
+CBFS: Locating 'fallback/dsdt.aml'
+CBFS: Found @ offset 1ba40 size 2752
+CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
+CBFS: Locating 'fallback/slic'
+CBFS: 'fallback/slic' not found.
+ACPI: Writing ACPI tables at 7ff3b000.
+ACPI: * FACS
+ACPI: * DSDT
+ACPI: * IGD OpRegion
+GET_VBIOS: 86b1 4724 a5 1f c5
+VBIOS not found.
+ACPI: * FADT
+ACPI: added table 1/32, length now 40
+ACPI: * SSDT
+Found 1 CPU(s) with 8 core(s) each.
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+ACPI: added table 2/32, length now 44
+ACPI: * MCFG
+ACPI: * TCPA
+TCPA log created at 7ff28000
+ACPI: added table 3/32, length now 48
+ACPI: * MADT
+ACPI: added table 4/32, length now 52
+current = 7ff40360
+ACPI: * DMAR
+ACPI: added table 5/32, length now 56
+current = 7ff40410
+ACPI: * HPET
+ACPI: added table 6/32, length now 60
+CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
+CBFS: Locating 'pci10de,1401.rom'
+CBFS: 'pci10de,1401.rom' not found.
+PCI Option ROM loading disabled for PCI: 01:00.0
+ACPI: done.
+ACPI tables: 21584 bytes.
+smbios_write_tables: 7ff27000
+Create SMBIOS type 17
+Root Device (Sapphire Pure Platinum H61)
+CPU_CLUSTER: 0 (Intel SandyBridge/IvyBridge integrated Northbridge)
+APIC: 00 (unknown)
+APIC: acac (Intel SandyBridge/IvyBridge CPU)
+DOMAIN: 0000 (Intel SandyBridge/IvyBridge integrated Northbridge)
+PCI: 00:16.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:16.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:16.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:16.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:19.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1a.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1b.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.7 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1d.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1e.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1f.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PNP: 004e.1 (Fintek F71808A Super I/O)
+PNP: 004e.4 (Fintek F71808A Super I/O)
+PNP: 004e.5 (Fintek F71808A Super I/O)
+PNP: 004e.6 (Fintek F71808A Super I/O)
+PNP: 004e.7 (Fintek F71808A Super I/O)
+PNP: 004e.8 (Fintek F71808A Super I/O)
+PNP: 004e.a (Fintek F71808A Super I/O)
+PCI: 00:1f.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1f.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1f.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1f.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:00.0 (Intel SandyBridge/IvyBridge integrated Northbridge)
+PCI: 00:01.0 (Intel SandyBridge/IvyBridge integrated Northbridge)
+PCI: 00:02.0 (Intel SandyBridge/IvyBridge integrated Northbridge)
+PCI: 01:00.0 (unknown)
+PCI: 01:00.1 (unknown)
+PCI: 03:00.0 (unknown)
+PCI: 04:00.0 (unknown)
+APIC: 01 (unknown)
+APIC: 02 (unknown)
+APIC: 03 (unknown)
+APIC: 04 (unknown)
+APIC: 05 (unknown)
+APIC: 06 (unknown)
+APIC: 07 (unknown)
+SMBIOS tables: 562 bytes.
+Writing table forward entry at 0x00000500
+Wrote coreboot table at: 00000500, 0x10 bytes, checksum 8fe8
+Writing coreboot table at 0x7ff5f000
+CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 1b440 size 5b0
+ 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
+ 1. 0000000000001000-000000000009ffff: RAM
+ 2. 00000000000a0000-00000000000fffff: RESERVED
+ 3. 0000000000100000-000000007ff26fff: RAM
+ 4. 000000007ff27000-000000007fffffff: CONFIGURATION TABLES
+ 5. 0000000080000000-00000000829fffff: RESERVED
+ 6. 00000000f0000000-00000000f3ffffff: RESERVED
+ 7. 00000000fed90000-00000000fed91fff: RESERVED
+ 8. 0000000100000000-000000047c5fffff: RAM
+CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
+FMAP: Found "FLASH" version 1.1 at 20000.
+FMAP: base = ffc00000 size = 400000 #areas = 3
+Wrote coreboot table at: 7ff5f000, 0x920 bytes, checksum 7284
+coreboot table: 2360 bytes.
+IMD ROOT 0. 7ffff000 00001000
+IMD SMALL 1. 7fffe000 00001000
+CONSOLE 2. 7ffde000 00020000
+TIME STAMP 3. 7ffdd000 00000400
+ROMSTG STCK 4. 7ffd8000 00005000
+RAMSTAGE 5. 7ff9f000 00039000
+57a9e100 6. 7ff67000 000378d0
+COREBOOT 7. 7ff5f000 00008000
+ACPI 8. 7ff3b000 00024000
+ACPI GNVS 9. 7ff3a000 00001000
+4f444749 10. 7ff38000 00002000
+TCPA LOG 11. 7ff28000 00010000
+SMBIOS 12. 7ff27000 00000800
+IMD small region:
+ IMD ROOT 0. 7fffec00 00000400
+ CAR GLOBALS 1. 7fffea40 000001c0
+ USBDEBUG 2. 7fffe9e0 00000058
+ MEM INFO 3. 7fffe880 00000141
+ ROMSTAGE 4. 7fffe860 00000004
+ 57a9e000 5. 7fffe840 00000010
+BS: BS_WRITE_TABLES times (us): entry 1 run 4808 exit 0
+CBFS: 'Master Header Locator' located CBFS at [20100:3fffc0)
+CBFS: Locating 'fallback/payload'
+CBFS: Found @ offset 8dc80 size f65f
+Loading segment from ROM address 0xffcaddb8
+ code (compression=1)
+ New segment dstaddr 0xe31c0 memsize 0x1ce40 srcaddr 0xffcaddf0 filesize 0xf627
+Loading segment from ROM address 0xffcaddd4
+ Entry Point 0x000ff06e
+Payload being loaded at below 1MiB without region being marked as RAM usable.
+Loading Segment: addr: 0x00000000000e31c0 memsz: 0x000000000001ce40 filesz: 0x000000000000f627
+lb: [0x000000007ffa0000, 0x000000007ffd78d0)
+Post relocation: addr: 0x00000000000e31c0 memsz: 0x000000000001ce40 filesz: 0x000000000000f627
+using LZMA
+[ 0x000e31c0, 00100000, 0x00100000) <- ffcaddf0
+dest 000e31c0, end 00100000, bouncebuffer ffffffff
+Loaded segments
+BS: BS_PAYLOAD_LOAD times (us): entry 0 run 19460 exit 0
+PCH watchdog disabled
+Jumping to boot code at 000ff06e(7ff5f000)
+CPU0: stack: 7ffce000 - 7ffcf000, lowest used address 7ffcea80, stack used: 1408 bytes
+SeaBIOS (version rel-1.10.2-0-g5f4c7b1)
+BUILD: gcc: (coreboot toolchain v1.44 March 3rd, 2017) 6.3.0 binutils: (GNU Binutils) 2.28
+Found coreboot cbmem console @ 7ffde000
+Found mainboard Sapphire Pure Platinum H61
+Relocating init from 0x000e4740 to 0x7fedada0 (size 49600)
+Found CBFS header at 0xffc20138
+multiboot: eax=7ffc65e0, ebx=7ffc6594
+Found 17 PCI devices (max PCI bus is 04)
+Copying SMBIOS entry point from 0x7ff27000 to 0x000f08e0
+Copying ACPI RSDP from 0x7ff3b000 to 0x000f08b0
+Using pmtimer, ioport 0x508
+Scan for VGA option rom
+Running option rom at c000:0003
+Turning on vga text mode console
+SeaBIOS (version rel-1.10.2-0-g5f4c7b1)
+XHCI init on dev 03:00.0: regs @ 0xe1800000, 4 ports, 32 slots, 32 byte contexts
+XHCI extcap 0x1 @ 0xe1800800
+XHCI protocol USB 3.00, 2 ports (offset 1), def 0
+XHCI protocol USB 2.00, 2 ports (offset 3), def 1
+EHCI init on dev 00:1a.0 (regs=0xe1a05020)
+EHCI init on dev 00:1d.0 (regs=0xe1a06020)
+WARNING - Timeout at i8042_flush:71!
+AHCI controller at 00:1f.2, iobase 0xe1a04000, irq 10
+Found 0 lpt ports
+Found 0 serial ports
+Searching bootorder for: /rom@img/memtest
+Searching bootorder for: /rom@img/tint
+Searching bootorder for: /rom@img/nvramcui
+Searching bootorder for: /rom@img/coreinfo
+Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0
+AHCI/0: Set transfer mode to UDMA-6
+AHCI/0: registering: "AHCI/0: KINGSTON SH103S3120G ATA-8 Hard-Disk (111 GiBytes)"
+Searching bootorder for: /pci@i0cf8/*@1f,2/drive@1/disk@0
+AHCI/1: Set transfer mode to UDMA-6
+AHCI/1: registering: "AHCI/1: KINGSTON SH103S3120G ATA-8 Hard-Disk (111 GiBytes)"
+XHCI no devices found
+Initialized USB HUB (0 ports used)
+USB keyboard initialized
+USB mouse initialized
+Initialized USB HUB (2 ports used)
+Initialized USB HUB (1 ports used)
+Searching bootorder for: /pci@i0cf8/*@1f,2/drive@4/disk@0
+AHCI/4: Set transfer mode to UDMA-6
+AHCI/4: registering: "AHCI/4: SAMSUNG HD502HI ATA-7 Hard-Disk (465 GiBytes)"
+All threads complete.
+Scan for option roms
+
+Press ESC for boot menu.
+
+Searching bootorder for: HALT
+drive 0x000f0840: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=234441648
+drive 0x000f07f0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=234441648
+drive 0x000f07a0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=976773168
+Space available for UMB: ce800-ec800, f0000-f07a0
+Returned 245760 bytes of ZoneHigh
+e820 map has 8 items:
+ 0: 0000000000000000 - 000000000009fc00 = 1 RAM
+ 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
+ 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
+ 3: 0000000000100000 - 000000007ff23000 = 1 RAM
+ 4: 000000007ff23000 - 0000000082a00000 = 2 RESERVED
+ 5: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
+ 6: 00000000fed90000 - 00000000fed92000 = 2 RESERVED
+ 7: 0000000100000000 - 000000047c600000 = 1 RAM
+enter handle_19:
+ NULL
+Booting from Hard Disk...
+Booting from 0000:7c00
+