amd/thatcher/4.3-102-g380e167/2016-02-04T18_30_40Z
diff --git a/amd/thatcher/4.3-102-g380e167/2016-02-04T18_30_40Z/coreboot_console.txt b/amd/thatcher/4.3-102-g380e167/2016-02-04T18_30_40Z/coreboot_console.txt
new file mode 100644
index 0000000..e023339
--- /dev/null
+++ b/amd/thatcher/4.3-102-g380e167/2016-02-04T18_30_40Z/coreboot_console.txt
@@ -0,0 +1,1146 @@
+
+
+coreboot-4.3-102-g380e167 Thu Feb 4 18:30:40 UTC 2016 ramstage starting...
+BS: BS_PRE_DEVICE times (us): entry 0 run 1 exit 0
+BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 6 exit 0
+Enumerating buses...
+Show all devs... Before device enumeration.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+APIC: 10: enabled 1
+DOMAIN: 0000: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 1
+PCI: 00:01.1: enabled 1
+PCI: 00:02.0: enabled 1
+PCI: 00:03.0: enabled 0
+PCI: 00:04.0: enabled 1
+PCI: 00:05.0: enabled 1
+PCI: 00:06.0: enabled 1
+PCI: 00:07.0: enabled 0
+PCI: 00:08.0: enabled 0
+PCI: 00:10.0: enabled 1
+PCI: 00:10.1: enabled 1
+PCI: 00:11.0: enabled 1
+PCI: 00:12.0: enabled 1
+PCI: 00:12.2: enabled 1
+PCI: 00:13.0: enabled 1
+PCI: 00:13.2: enabled 1
+PCI: 00:14.0: enabled 1
+I2C: 00:50: enabled 1
+I2C: 00:51: enabled 1
+PCI: 00:14.1: enabled 1
+PCI: 00:14.2: enabled 1
+PCI: 00:14.3: enabled 1
+PNP: 002e.3: enabled 0
+PNP: 002e.4: enabled 1
+PNP: 002e.5: enabled 0
+PCI: 00:14.4: enabled 1
+PCI: 00:14.5: enabled 1
+PCI: 00:14.6: enabled 0
+PCI: 00:14.7: enabled 1
+PCI: 00:15.0: enabled 0
+PCI: 00:15.1: enabled 0
+PCI: 00:15.2: enabled 0
+PCI: 00:15.3: enabled 0
+PCI: 00:18.0: enabled 1
+PCI: 00:18.1: enabled 1
+PCI: 00:18.2: enabled 1
+PCI: 00:18.3: enabled 1
+PCI: 00:18.4: enabled 1
+PCI: 00:18.5: enabled 1
+Compare with tree...
+Root Device: enabled 1
+ CPU_CLUSTER: 0: enabled 1
+ APIC: 10: enabled 1
+ DOMAIN: 0000: enabled 1
+ PCI: 00:00.0: enabled 1
+ PCI: 00:01.0: enabled 1
+ PCI: 00:01.1: enabled 1
+ PCI: 00:02.0: enabled 1
+ PCI: 00:03.0: enabled 0
+ PCI: 00:04.0: enabled 1
+ PCI: 00:05.0: enabled 1
+ PCI: 00:06.0: enabled 1
+ PCI: 00:07.0: enabled 0
+ PCI: 00:08.0: enabled 0
+ PCI: 00:10.0: enabled 1
+ PCI: 00:10.1: enabled 1
+ PCI: 00:11.0: enabled 1
+ PCI: 00:12.0: enabled 1
+ PCI: 00:12.2: enabled 1
+ PCI: 00:13.0: enabled 1
+ PCI: 00:13.2: enabled 1
+ PCI: 00:14.0: enabled 1
+ I2C: 00:50: enabled 1
+ I2C: 00:51: enabled 1
+ PCI: 00:14.1: enabled 1
+ PCI: 00:14.2: enabled 1
+ PCI: 00:14.3: enabled 1
+ PNP: 002e.3: enabled 0
+ PNP: 002e.4: enabled 1
+ PNP: 002e.5: enabled 0
+ PCI: 00:14.4: enabled 1
+ PCI: 00:14.5: enabled 1
+ PCI: 00:14.6: enabled 0
+ PCI: 00:14.7: enabled 1
+ PCI: 00:15.0: enabled 0
+ PCI: 00:15.1: enabled 0
+ PCI: 00:15.2: enabled 0
+ PCI: 00:15.3: enabled 0
+ PCI: 00:18.0: enabled 1
+ PCI: 00:18.1: enabled 1
+ PCI: 00:18.2: enabled 1
+ PCI: 00:18.3: enabled 1
+ PCI: 00:18.4: enabled 1
+ PCI: 00:18.5: enabled 1
+Mainboard Thatcher Enable.
+Root Device scanning...
+root_dev_scan_bus for Root Device
+setup_bsp_ramtop, TOP MEM: msr.lo = 0xe0000000, msr.hi = 0x00000000
+setup_bsp_ramtop, TOP MEM2: msr.lo = 0x1f000000, msr.hi = 0x00000001
+setup_uma_memory: uma size 0x20000000, memory start 0xc0000000
+CPU_CLUSTER: 0 enabled
+DOMAIN: 0000 enabled
+CPU_CLUSTER: 0 scanning...
+PCI: 00:18.5 family15h, core_max=0x10, core_nums=0xf, siblings=0x3
+lpaicid_start=0x10 node 0x0 core 0x0 apicid=0x10
+CPU: APIC: 10 enabled
+lpaicid_start=0x10 node 0x0 core 0x1 apicid=0x11
+CPU: APIC: 11 enabled
+lpaicid_start=0x10 node 0x0 core 0x2 apicid=0x12
+CPU: APIC: 12 enabled
+lpaicid_start=0x10 node 0x0 core 0x3 apicid=0x13
+CPU: APIC: 13 enabled
+scan_bus: scanning of bus CPU_CLUSTER: 0 took 16825 usecs
+DOMAIN: 0000 scanning...
+PCI: pci_scan_bus for bus 00
+PCI: 00:00.0 [1022/1410] enabled
+PCI: 00:01.0 [1002/9917] enabled
+PCI: 00:01.1 [1002/9902] enabled
+PCI: Static device PCI: 00:02.0 not found, disabling it.
+PCI: Static device PCI: 00:04.0 not found, disabling it.
+PCI: Static device PCI: 00:05.0 not found, disabling it.
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Capability: type 0x05 @ 0xa0
+Capability: type 0x0d @ 0xb0
+Capability: type 0x08 @ 0xb8
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+PCI: 00:06.0 subordinate bus PCI Express
+PCI: 00:06.0 [1022/1416] enabled
+hudson_enable()
+PCI: Static device PCI: 00:10.0 not found, disabling it.
+hudson_enable()
+PCI: Static device PCI: 00:10.1 not found, disabling it.
+hudson_enable()
+PCI: 00:11.0 [1022/7801] ops
+PCI: 00:11.0 [1022/7801] enabled
+hudson_enable()
+PCI: 00:12.0 [1022/7807] ops
+PCI: 00:12.0 [1022/7807] enabled
+hudson_enable()
+PCI: 00:12.2 [1022/7808] ops
+PCI: 00:12.2 [1022/7808] enabled
+hudson_enable()
+PCI: 00:13.0 [1022/7807] ops
+PCI: 00:13.0 [1022/7807] enabled
+hudson_enable()
+PCI: 00:13.2 [1022/7808] ops
+PCI: 00:13.2 [1022/7808] enabled
+hudson_enable()
+PCI: 00:14.0 [1022/780b] bus ops
+PCI: 00:14.0 [1022/780b] enabled
+hudson_enable()
+PCI: Static device PCI: 00:14.1 not found, disabling it.
+hudson_enable()
+PCI: 00:14.2 [1022/780d] ops
+PCI: 00:14.2 [1022/780d] enabled
+hudson_enable()
+PCI: 00:14.3 [1022/780e] bus ops
+PCI: 00:14.3 [1022/780e] enabled
+hudson_enable()
+PCI: 00:14.4 [1022/780f] bus ops
+PCI: 00:14.4 [1022/780f] enabled
+hudson_enable()
+PCI: 00:14.5 [1022/7809] ops
+PCI: 00:14.5 [1022/7809] enabled
+hudson_enable()
+hudson_enable()
+PCI: 00:14.7 [1022/7806] enabled
+hudson_enable()
+hudson_enable()
+hudson_enable()
+hudson_enable()
+PCI: 00:18.0 [1022/1400] ops
+PCI: 00:18.0 [1022/1400] enabled
+PCI: 00:18.1 [1022/1401] enabled
+PCI: 00:18.2 [1022/1402] enabled
+PCI: 00:18.3 [1022/1403] enabled
+PCI: 00:18.4 [1022/1404] enabled
+PCI: 00:18.5 [1022/1405] enabled
+PCI: 00:06.0 scanning...
+do_pci_scan_bridge for PCI: 00:06.0
+PCI: pci_scan_bus for bus 01
+PCI: 01:00.0 [10ec/8168] enabled
+PCI: 01:00.1 [10ec/816a] enabled
+PCI: 01:00.2 [10ec/816b] enabled
+PCI: 01:00.3 [10ec/816c] enabled
+Capability: type 0x01 @ 0x40
+Capability: type 0x05 @ 0x50
+Capability: type 0x10 @ 0x70
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Capability: type 0x01 @ 0x40
+Capability: type 0x05 @ 0x50
+Capability: type 0x10 @ 0x70
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Capability: type 0x01 @ 0x40
+Capability: type 0x05 @ 0x50
+Capability: type 0x10 @ 0x70
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Capability: type 0x01 @ 0x40
+Capability: type 0x05 @ 0x50
+Capability: type 0x10 @ 0x70
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+scan_bus: scanning of bus PCI: 00:06.0 took 35967 usecs
+PCI: 00:14.0 scanning...
+scan_smbus for PCI: 00:14.0
+smbus: PCI: 00:14.0[0]->I2C: 01:50 enabled
+smbus: PCI: 00:14.0[0]->I2C: 01:51 enabled
+scan_smbus for PCI: 00:14.0 done
+scan_bus: scanning of bus PCI: 00:14.0 took 7664 usecs
+PCI: 00:14.3 scanning...
+scan_lpc_bus for PCI: 00:14.3
+PNP: 002e.3 disabled
+PNP: 002e.4 enabled
+PNP: 002e.5 disabled
+scan_lpc_bus for PCI: 00:14.3 done
+scan_bus: scanning of bus PCI: 00:14.3 took 6937 usecs
+PCI: 00:14.4 scanning...
+do_pci_scan_bridge for PCI: 00:14.4
+PCI: pci_scan_bus for bus 02
+scan_bus: scanning of bus PCI: 00:14.4 took 4063 usecs
+scan_bus: scanning of bus DOMAIN: 0000 took 152641 usecs
+root_dev_scan_bus for Root Device done
+scan_bus: scanning of bus Root Device took 189708 usecs
+done
+BS: BS_DEV_ENUMERATE times (us): entry 9 run 295848 exit 0
+found VGA at PCI: 00:01.0
+Setting up VGA for PCI: 00:01.0
+Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
+Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
+Allocating resources...
+Reading resources...
+Root Device read_resources bus 0 link: 0
+CPU_CLUSTER: 0 read_resources bus 0 link: 0
+CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
+fx_devs=0x1
+DOMAIN: 0000 read_resources bus 0 link: 0
+PCI: 00:06.0 read_resources bus 1 link: 0
+PCI: 00:06.0 read_resources bus 1 link: 0 done
+PCI: 00:14.0 read_resources bus 1 link: 0
+I2C: 01:50 missing read_resources
+I2C: 01:51 missing read_resources
+PCI: 00:14.0 read_resources bus 1 link: 0 done
+PCI: 00:14.3 read_resources bus 0 link: 0
+PCI: 00:14.3 read_resources bus 0 link: 0 done
+PCI: 00:14.4 read_resources bus 2 link: 0
+PCI: 00:14.4 read_resources bus 2 link: 0 done
+PCI: 00:18.0 read_resources bus 0 link: 0
+PCI: 00:18.0 read_resources bus 0 link: 0 done
+PCI: 00:18.0 read_resources bus 0 link: 1
+PCI: 00:18.0 read_resources bus 0 link: 1 done
+PCI: 00:18.0 read_resources bus 0 link: 2
+PCI: 00:18.0 read_resources bus 0 link: 2 done
+PCI: 00:18.0 read_resources bus 0 link: 3
+PCI: 00:18.0 read_resources bus 0 link: 3 done
+DOMAIN: 0000 read_resources bus 0 link: 0 done
+Root Device read_resources bus 0 link: 0 done
+Done reading resources.
+Show resources in subtree (Root Device)...After reading.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 10
+ APIC: 10
+ APIC: 11
+ APIC: 12
+ APIC: 13
+ DOMAIN: 0000 child on link 0 PCI: 00:00.0
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
+ PCI: 00:00.0
+ PCI: 00:01.0
+ PCI: 00:01.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10
+ PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
+ PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 18
+ PCI: 00:01.1
+ PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
+ PCI: 00:02.0
+ PCI: 00:03.0
+ PCI: 00:04.0
+ PCI: 00:05.0
+ PCI: 00:06.0 child on link 0 PCI: 01:00.0
+ PCI: 00:06.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
+ PCI: 00:06.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:06.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 01:00.0
+ PCI: 01:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
+ PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 1201 index 18
+ PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
+ PCI: 01:00.1
+ PCI: 01:00.1 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
+ PCI: 01:00.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
+ PCI: 01:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 20
+ PCI: 01:00.2
+ PCI: 01:00.2 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
+ PCI: 01:00.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
+ PCI: 01:00.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 20
+ PCI: 01:00.3
+ PCI: 01:00.3 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
+ PCI: 01:00.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 18
+ PCI: 01:00.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 20
+ PCI: 00:07.0
+ PCI: 00:08.0
+ PCI: 00:10.0
+ PCI: 00:10.1
+ PCI: 00:11.0
+ PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
+ PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
+ PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
+ PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
+ PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
+ PCI: 00:11.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
+ PCI: 00:12.0
+ PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
+ PCI: 00:12.2
+ PCI: 00:12.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
+ PCI: 00:13.0
+ PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
+ PCI: 00:13.2
+ PCI: 00:13.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
+ PCI: 00:14.0 child on link 0 I2C: 01:50
+ I2C: 01:50
+ I2C: 01:51
+ PCI: 00:14.1
+ PCI: 00:14.2
+ PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:14.3 child on link 0 PNP: 002e.3
+ PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2
+ PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PNP: 002e.3
+ PNP: 002e.3 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
+ PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
+ PNP: 002e.4
+ PNP: 002e.4 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
+ PNP: 002e.4 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.5
+ PNP: 002e.5 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
+ PNP: 002e.5 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PCI: 00:14.4
+ PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
+ PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 00:14.5
+ PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
+ PCI: 00:14.6
+ PCI: 00:14.7
+ PCI: 00:14.7 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:15.0
+ PCI: 00:15.1
+ PCI: 00:15.2
+ PCI: 00:15.3
+ PCI: 00:18.0
+ PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
+ PCI: 00:18.1
+ PCI: 00:18.2
+ PCI: 00:18.3
+ PCI: 00:18.4
+ PCI: 00:18.5
+DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
+PCI: 00:06.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
+PCI: 01:00.0 10 * [0x0 - 0xff] io
+PCI: 01:00.1 10 * [0x400 - 0x4ff] io
+PCI: 01:00.2 10 * [0x800 - 0x8ff] io
+PCI: 01:00.3 10 * [0xc00 - 0xcff] io
+PCI: 00:06.0 io: base: d00 size: 1000 align: 12 gran: 12 limit: ffff done
+PCI: 00:14.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:14.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
+PCI: 00:06.0 1c * [0x0 - 0xfff] io
+PCI: 00:01.0 14 * [0x1000 - 0x10ff] io
+PCI: 00:11.0 20 * [0x1400 - 0x140f] io
+PCI: 00:11.0 10 * [0x1410 - 0x1417] io
+PCI: 00:11.0 18 * [0x1418 - 0x141f] io
+PCI: 00:11.0 14 * [0x1420 - 0x1423] io
+PCI: 00:11.0 1c * [0x1424 - 0x1427] io
+DOMAIN: 0000 io: base: 1428 size: 1428 align: 12 gran: 0 limit: ffff done
+DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
+PCI: 00:06.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 01:00.0 20 * [0x0 - 0x3fff] prefmem
+PCI: 01:00.0 18 * [0x4000 - 0x4fff] prefmem
+PCI: 00:06.0 prefmem: base: 5000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:06.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 01:00.1 20 * [0x0 - 0x3fff] mem
+PCI: 01:00.2 20 * [0x4000 - 0x7fff] mem
+PCI: 01:00.3 20 * [0x8000 - 0xbfff] mem
+PCI: 01:00.1 18 * [0xc000 - 0xcfff] mem
+PCI: 01:00.2 18 * [0xd000 - 0xdfff] mem
+PCI: 01:00.3 18 * [0xe000 - 0xe0ff] mem
+PCI: 00:06.0 mem: base: e100 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:01.0 10 * [0x0 - 0xfffffff] prefmem
+PCI: 00:06.0 24 * [0x10000000 - 0x100fffff] prefmem
+PCI: 00:06.0 20 * [0x10100000 - 0x101fffff] mem
+PCI: 00:01.0 18 * [0x10200000 - 0x1023ffff] mem
+PCI: 00:01.1 10 * [0x10240000 - 0x10243fff] mem
+PCI: 00:14.2 10 * [0x10244000 - 0x10247fff] mem
+PCI: 00:12.0 10 * [0x10248000 - 0x10248fff] mem
+PCI: 00:13.0 10 * [0x10249000 - 0x10249fff] mem
+PCI: 00:14.5 10 * [0x1024a000 - 0x1024afff] mem
+PCI: 00:11.0 24 * [0x1024b000 - 0x1024b7ff] mem
+PCI: 00:12.2 10 * [0x1024c000 - 0x1024c0ff] mem
+PCI: 00:13.2 10 * [0x1024d000 - 0x1024d0ff] mem
+PCI: 00:14.7 10 * [0x1024e000 - 0x1024e0ff] mem
+DOMAIN: 0000 mem: base: 1024e100 size: 1024e100 align: 28 gran: 0 limit: ffffffff done
+avoid_fixed_resources: DOMAIN: 0000
+avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
+avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
+constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed)
+constrain_resources: PCI: 00:14.3 10000100 base ff800000 limit ffffffff mem (fixed)
+constrain_resources: PCI: 00:14.3 02 base fec10000 limit fec103ff mem (fixed)
+constrain_resources: PCI: 00:14.3 03 base fec00000 limit fec00fff mem (fixed)
+constrain_resources: PCI: 00:18.0 c0010058 base f8000000 limit fbffffff mem (fixed)
+avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff
+avoid_fixed_resources:@DOMAIN: 0000 10000100 base e0000000 limit f7ffffff
+Setting resources...
+DOMAIN: 0000 io: base:1000 size:1428 align:12 gran:0 limit:ffff
+PCI: 00:06.0 1c * [0x1000 - 0x1fff] io
+PCI: 00:01.0 14 * [0x2000 - 0x20ff] io
+PCI: 00:11.0 20 * [0x2400 - 0x240f] io
+PCI: 00:11.0 10 * [0x2410 - 0x2417] io
+PCI: 00:11.0 18 * [0x2418 - 0x241f] io
+PCI: 00:11.0 14 * [0x2420 - 0x2423] io
+PCI: 00:11.0 1c * [0x2424 - 0x2427] io
+DOMAIN: 0000 io: next_base: 2428 size: 1428 align: 12 gran: 0 done
+PCI: 00:06.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff
+PCI: 01:00.0 10 * [0x1000 - 0x10ff] io
+PCI: 01:00.1 10 * [0x1400 - 0x14ff] io
+PCI: 01:00.2 10 * [0x1800 - 0x18ff] io
+PCI: 01:00.3 10 * [0x1c00 - 0x1cff] io
+PCI: 00:06.0 io: next_base: 1d00 size: 1000 align: 12 gran: 12 done
+PCI: 00:14.4 io: base:ffff size:0 align:12 gran:12 limit:ffff
+PCI: 00:14.4 io: next_base: ffff size: 0 align: 12 gran: 12 done
+DOMAIN: 0000 mem: base:e0000000 size:1024e100 align:28 gran:0 limit:f7ffffff
+PCI: 00:01.0 10 * [0xe0000000 - 0xefffffff] prefmem
+PCI: 00:06.0 24 * [0xf0000000 - 0xf00fffff] prefmem
+PCI: 00:06.0 20 * [0xf0100000 - 0xf01fffff] mem
+PCI: 00:01.0 18 * [0xf0200000 - 0xf023ffff] mem
+PCI: 00:01.1 10 * [0xf0240000 - 0xf0243fff] mem
+PCI: 00:14.2 10 * [0xf0244000 - 0xf0247fff] mem
+PCI: 00:12.0 10 * [0xf0248000 - 0xf0248fff] mem
+PCI: 00:13.0 10 * [0xf0249000 - 0xf0249fff] mem
+PCI: 00:14.5 10 * [0xf024a000 - 0xf024afff] mem
+PCI: 00:11.0 24 * [0xf024b000 - 0xf024b7ff] mem
+PCI: 00:12.2 10 * [0xf024c000 - 0xf024c0ff] mem
+PCI: 00:13.2 10 * [0xf024d000 - 0xf024d0ff] mem
+PCI: 00:14.7 10 * [0xf024e000 - 0xf024e0ff] mem
+DOMAIN: 0000 mem: next_base: f024e100 size: 1024e100 align: 28 gran: 0 done
+PCI: 00:06.0 prefmem: base:f0000000 size:100000 align:20 gran:20 limit:f00fffff
+PCI: 01:00.0 20 * [0xf0000000 - 0xf0003fff] prefmem
+PCI: 01:00.0 18 * [0xf0004000 - 0xf0004fff] prefmem
+PCI: 00:06.0 prefmem: next_base: f0005000 size: 100000 align: 20 gran: 20 done
+PCI: 00:06.0 mem: base:f0100000 size:100000 align:20 gran:20 limit:f01fffff
+PCI: 01:00.1 20 * [0xf0100000 - 0xf0103fff] mem
+PCI: 01:00.2 20 * [0xf0104000 - 0xf0107fff] mem
+PCI: 01:00.3 20 * [0xf0108000 - 0xf010bfff] mem
+PCI: 01:00.1 18 * [0xf010c000 - 0xf010cfff] mem
+PCI: 01:00.2 18 * [0xf010d000 - 0xf010dfff] mem
+PCI: 01:00.3 18 * [0xf010e000 - 0xf010e0ff] mem
+PCI: 00:06.0 mem: next_base: f010e100 size: 100000 align: 20 gran: 20 done
+PCI: 00:14.4 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
+PCI: 00:14.4 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
+PCI: 00:14.4 mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
+PCI: 00:14.4 mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
+Root Device assign_resources, bus 0 link: 0
+node 0: mmio_basek=00380000, basek=00400000, limitk=00460000
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+PCI: 00:01.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem
+PCI: 00:01.0 14 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
+PCI: 00:01.0 18 <- [0x00f0200000 - 0x00f023ffff] size 0x00040000 gran 0x12 mem
+PCI: 00:01.1 10 <- [0x00f0240000 - 0x00f0243fff] size 0x00004000 gran 0x0e mem
+PCI: 00:06.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
+PCI: 00:06.0 24 <- [0x00f0000000 - 0x00f00fffff] size 0x00100000 gran 0x14 bus 01 prefmem
+PCI: 00:06.0 20 <- [0x00f0100000 - 0x00f01fffff] size 0x00100000 gran 0x14 bus 01 mem
+PCI: 00:06.0 assign_resources, bus 1 link: 0
+PCI: 01:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
+PCI: 01:00.0 18 <- [0x00f0004000 - 0x00f0004fff] size 0x00001000 gran 0x0c prefmem64
+PCI: 01:00.0 20 <- [0x00f0000000 - 0x00f0003fff] size 0x00004000 gran 0x0e prefmem64
+PCI: 01:00.1 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io
+PCI: 01:00.1 18 <- [0x00f010c000 - 0x00f010cfff] size 0x00001000 gran 0x0c mem64
+PCI: 01:00.1 20 <- [0x00f0100000 - 0x00f0103fff] size 0x00004000 gran 0x0e mem64
+PCI: 01:00.2 10 <- [0x0000001800 - 0x00000018ff] size 0x00000100 gran 0x08 io
+PCI: 01:00.2 18 <- [0x00f010d000 - 0x00f010dfff] size 0x00001000 gran 0x0c mem64
+PCI: 01:00.2 20 <- [0x00f0104000 - 0x00f0107fff] size 0x00004000 gran 0x0e mem64
+PCI: 01:00.3 10 <- [0x0000001c00 - 0x0000001cff] size 0x00000100 gran 0x08 io
+PCI: 01:00.3 18 <- [0x00f010e000 - 0x00f010e0ff] size 0x00000100 gran 0x08 mem64
+PCI: 01:00.3 20 <- [0x00f0108000 - 0x00f010bfff] size 0x00004000 gran 0x0e mem64
+PCI: 00:06.0 assign_resources, bus 1 link: 0
+PCI: 00:11.0 10 <- [0x0000002410 - 0x0000002417] size 0x00000008 gran 0x03 io
+PCI: 00:11.0 14 <- [0x0000002420 - 0x0000002423] size 0x00000004 gran 0x02 io
+PCI: 00:11.0 18 <- [0x0000002418 - 0x000000241f] size 0x00000008 gran 0x03 io
+PCI: 00:11.0 1c <- [0x0000002424 - 0x0000002427] size 0x00000004 gran 0x02 io
+PCI: 00:11.0 20 <- [0x0000002400 - 0x000000240f] size 0x00000010 gran 0x04 io
+PCI: 00:11.0 24 <- [0x00f024b000 - 0x00f024b7ff] size 0x00000800 gran 0x0b mem
+PCI: 00:12.0 10 <- [0x00f0248000 - 0x00f0248fff] size 0x00001000 gran 0x0c mem
+PCI: 00:12.2 10 <- [0x00f024c000 - 0x00f024c0ff] size 0x00000100 gran 0x08 mem
+PCI: 00:13.0 10 <- [0x00f0249000 - 0x00f0249fff] size 0x00001000 gran 0x0c mem
+PCI: 00:13.2 10 <- [0x00f024d000 - 0x00f024d0ff] size 0x00000100 gran 0x08 mem
+PCI: 00:14.2 10 <- [0x00f0244000 - 0x00f0247fff] size 0x00004000 gran 0x0e mem64
+PCI: 00:14.3 assign_resources, bus 0 link: 0
+PNP: 002e.4 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
+PNP: 002e.4 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
+PCI: 00:14.3 assign_resources, bus 0 link: 0
+PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
+PCI: 00:14.4 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem
+PCI: 00:14.4 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 mem
+PCI: 00:14.5 10 <- [0x00f024a000 - 0x00f024afff] size 0x00001000 gran 0x0c mem
+PCI: 00:14.7 10 <- [0x00f024e000 - 0x00f024e0ff] size 0x00000100 gran 0x08 mem64
+PCI: 00:18.0 c0010058 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x00 mem <mmconfig>
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+Root Device assign_resources, bus 0 link: 0
+Done setting resources.
+Show resources in subtree (Root Device)...After assigning values.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 10
+ APIC: 10
+ APIC: 11
+ APIC: 12
+ APIC: 13
+ DOMAIN: 0000 child on link 0 PCI: 00:00.0
+ DOMAIN: 0000 resource base 1000 size 1428 align 12 gran 0 limit ffff flags 40040100 index 10000000
+ DOMAIN: 0000 resource base e0000000 size 1024e100 align 28 gran 0 limit f7ffffff flags 40040200 index 10000100
+ DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
+ DOMAIN: 0000 resource base c0000 size dff40000 align 0 gran 0 limit 0 flags e0004200 index 20
+ DOMAIN: 0000 resource base 100000000 size 1f000000 align 0 gran 0 limit 0 flags e0004200 index 30
+ DOMAIN: 0000 resource base c0000000 size 20000000 align 0 gran 0 limit 0 flags f0000200 index 7
+ PCI: 00:00.0
+ PCI: 00:01.0
+ PCI: 00:01.0 resource base e0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001200 index 10
+ PCI: 00:01.0 resource base 2000 size 100 align 8 gran 8 limit 20ff flags 60000100 index 14
+ PCI: 00:01.0 resource base f0200000 size 40000 align 18 gran 18 limit f023ffff flags 60000200 index 18
+ PCI: 00:01.1
+ PCI: 00:01.1 resource base f0240000 size 4000 align 14 gran 14 limit f0243fff flags 60000200 index 10
+ PCI: 00:02.0
+ PCI: 00:03.0
+ PCI: 00:04.0
+ PCI: 00:05.0
+ PCI: 00:06.0 child on link 0 PCI: 01:00.0
+ PCI: 00:06.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c
+ PCI: 00:06.0 resource base f0000000 size 100000 align 20 gran 20 limit f00fffff flags 60081202 index 24
+ PCI: 00:06.0 resource base f0100000 size 100000 align 20 gran 20 limit f01fffff flags 60080202 index 20
+ PCI: 01:00.0
+ PCI: 01:00.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 10
+ PCI: 01:00.0 resource base f0004000 size 1000 align 12 gran 12 limit f0004fff flags 60001201 index 18
+ PCI: 01:00.0 resource base f0000000 size 4000 align 14 gran 14 limit f0003fff flags 60001201 index 20
+ PCI: 01:00.1
+ PCI: 01:00.1 resource base 1400 size 100 align 8 gran 8 limit 14ff flags 60000100 index 10
+ PCI: 01:00.1 resource base f010c000 size 1000 align 12 gran 12 limit f010cfff flags 60000201 index 18
+ PCI: 01:00.1 resource base f0100000 size 4000 align 14 gran 14 limit f0103fff flags 60000201 index 20
+ PCI: 01:00.2
+ PCI: 01:00.2 resource base 1800 size 100 align 8 gran 8 limit 18ff flags 60000100 index 10
+ PCI: 01:00.2 resource base f010d000 size 1000 align 12 gran 12 limit f010dfff flags 60000201 index 18
+ PCI: 01:00.2 resource base f0104000 size 4000 align 14 gran 14 limit f0107fff flags 60000201 index 20
+ PCI: 01:00.3
+ PCI: 01:00.3 resource base 1c00 size 100 align 8 gran 8 limit 1cff flags 60000100 index 10
+ PCI: 01:00.3 resource base f010e000 size 100 align 12 gran 8 limit f010e0ff flags 60000201 index 18
+ PCI: 01:00.3 resource base f0108000 size 4000 align 14 gran 14 limit f010bfff flags 60000201 index 20
+ PCI: 00:07.0
+ PCI: 00:08.0
+ PCI: 00:10.0
+ PCI: 00:10.1
+ PCI: 00:11.0
+ PCI: 00:11.0 resource base 2410 size 8 align 3 gran 3 limit 2417 flags 60000100 index 10
+ PCI: 00:11.0 resource base 2420 size 4 align 2 gran 2 limit 2423 flags 60000100 index 14
+ PCI: 00:11.0 resource base 2418 size 8 align 3 gran 3 limit 241f flags 60000100 index 18
+ PCI: 00:11.0 resource base 2424 size 4 align 2 gran 2 limit 2427 flags 60000100 index 1c
+ PCI: 00:11.0 resource base 2400 size 10 align 4 gran 4 limit 240f flags 60000100 index 20
+ PCI: 00:11.0 resource base f024b000 size 800 align 12 gran 11 limit f024b7ff flags 60000200 index 24
+ PCI: 00:12.0
+ PCI: 00:12.0 resource base f0248000 size 1000 align 12 gran 12 limit f0248fff flags 60000200 index 10
+ PCI: 00:12.2
+ PCI: 00:12.2 resource base f024c000 size 100 align 12 gran 8 limit f024c0ff flags 60000200 index 10
+ PCI: 00:13.0
+ PCI: 00:13.0 resource base f0249000 size 1000 align 12 gran 12 limit f0249fff flags 60000200 index 10
+ PCI: 00:13.2
+ PCI: 00:13.2 resource base f024d000 size 100 align 12 gran 8 limit f024d0ff flags 60000200 index 10
+ PCI: 00:14.0 child on link 0 I2C: 01:50
+ I2C: 01:50
+ I2C: 01:51
+ PCI: 00:14.1
+ PCI: 00:14.2
+ PCI: 00:14.2 resource base f0244000 size 4000 align 14 gran 14 limit f0247fff flags 60000201 index 10
+ PCI: 00:14.3 child on link 0 PNP: 002e.3
+ PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2
+ PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PNP: 002e.3
+ PNP: 002e.3 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
+ PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
+ PNP: 002e.4
+ PNP: 002e.4 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
+ PNP: 002e.4 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.5
+ PNP: 002e.5 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
+ PNP: 002e.5 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PCI: 00:14.4
+ PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:14.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24
+ PCI: 00:14.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20
+ PCI: 00:14.5
+ PCI: 00:14.5 resource base f024a000 size 1000 align 12 gran 12 limit f024afff flags 60000200 index 10
+ PCI: 00:14.6
+ PCI: 00:14.7
+ PCI: 00:14.7 resource base f024e000 size 100 align 12 gran 8 limit f024e0ff flags 60000201 index 10
+ PCI: 00:15.0
+ PCI: 00:15.1
+ PCI: 00:15.2
+ PCI: 00:15.3
+ PCI: 00:18.0
+ PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
+ PCI: 00:18.1
+ PCI: 00:18.2
+ PCI: 00:18.3
+ PCI: 00:18.4
+ PCI: 00:18.5
+Done allocating resources.
+BS: BS_DEV_RESOURCES times (us): entry 0 run 998019 exit 0
+Warning: Can't write PCI_INTR 0xC00/0xC01 registers because
+'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL
+Warning: Can't write PCI IRQ assignments because 'mainboard_pirq_data' structure does not exist
+Enabling resources...
+agesawrapper_amdinitmid() returned AGESA_SUCCESS
+ ader - leaving domain_enable_resources.
+PCI: 00:00.0 subsystem <- 1022/1410
+PCI: 00:00.0 cmd <- 06
+PCI: 00:01.0 subsystem <- 1022/1410
+PCI: 00:01.0 cmd <- 07
+PCI: 00:01.1 subsystem <- 1022/1410
+PCI: 00:01.1 cmd <- 02
+PCI: 00:06.0 bridge ctrl <- 0003
+PCI: 00:06.0 cmd <- 07
+PCI: 00:11.0 cmd <- 03
+PCI: 00:12.0 subsystem <- 1022/1410
+PCI: 00:12.0 cmd <- 02
+PCI: 00:12.2 subsystem <- 1022/1410
+PCI: 00:12.2 cmd <- 02
+PCI: 00:13.0 subsystem <- 1022/1410
+PCI: 00:13.0 cmd <- 02
+PCI: 00:13.2 subsystem <- 1022/1410
+PCI: 00:13.2 cmd <- 02
+PCI: 00:14.0 subsystem <- 1022/1410
+PCI: 00:14.0 cmd <- 403
+PCI: 00:14.2 subsystem <- 1022/1410
+PCI: 00:14.2 cmd <- 02
+PCI: 00:14.3 subsystem <- 1022/1410
+PCI: 00:14.3 cmd <- 0f
+hudson lpc decode:PNP: 002e.4, base=0x000003f8, end=0x000003ff
+PCI: 00:14.4 bridge ctrl <- 0003
+PCI: 00:14.4 cmd <- 00
+PCI: 00:14.5 subsystem <- 1022/1410
+PCI: 00:14.5 cmd <- 02
+PCI: 00:14.7 subsystem <- 1022/1410
+PCI: 00:14.7 cmd <- 06
+PCI: 00:18.0 cmd <- 00
+PCI: 00:18.1 subsystem <- 1022/1410
+PCI: 00:18.1 cmd <- 00
+PCI: 00:18.2 subsystem <- 1022/1410
+PCI: 00:18.2 cmd <- 00
+PCI: 00:18.3 subsystem <- 1022/1410
+PCI: 00:18.3 cmd <- 00
+PCI: 00:18.4 subsystem <- 1022/1410
+PCI: 00:18.4 cmd <- 00
+PCI: 00:18.5 subsystem <- 1022/1410
+PCI: 00:18.5 cmd <- 00
+PCI: 01:00.0 cmd <- 03
+PCI: 01:00.1 cmd <- 03
+PCI: 01:00.2 cmd <- 03
+PCI: 01:00.3 cmd <- 03
+done.
+BS: BS_DEV_ENABLE times (us): entry 9593 run 73505 exit 0
+Initializing devices...
+Root Device init ...
+Root Device init finished in 952 usecs
+CPU_CLUSTER: 0 init ...
+start_eip=0x00001000, code_size=0x00000031
+Initializing CPU #0
+CPU: vendor AMD device 610f01
+CPU: family 15, model 10, stepping 01
+Using generic cpu ops (good)
+Model 15 Init.
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Enabling cache
+Setting up local apic... apic_id: 0x10 done.
+siblings = 03, CPU #0 initialized
+CPU1: stack_base 00151000, stack_end 00151ff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 17.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 17.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+Initializing CPU #1
+CPU: vendor AMD device 610f01
+CPU: family 15, model 10, stepping 01
+Using generic cpu ops (good)
+Model 15 Init.
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Enabling cache
+Setting up local apic... apic_id: 0x11 done.
+siblings = 03, CPU #1 initialized
+CPU2: stack_base 00150000, stack_end 00150ff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 18.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 18.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+Initializing CPU #2
+CPU: vendor AMD device 610f01
+CPU: family 15, model 10, stepping 01
+Using generic cpu ops (good)
+Model 15 Init.
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Enabling cache
+Setting up local apic... apic_id: 0x12 done.
+siblings = 03, CPU #2 initialized
+CPU3: stack_base 0014f000, stack_end 0014fff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 19.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 19.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+Initializing CPU #3
+Waiting for 1 CPUS to stop
+CPU: vendor AMD device 610f01
+CPU: family 15, model 10, stepping 01
+Using generic cpu ops (good)
+Model 15 Init.
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Enabling cache
+Setting up local apic... apic_id: 0x13 done.
+siblings = 03, CPU #3 initialized
+All AP CPUs stopped (1209 loops)
+CPU0: stack: 00152000 - 00153000, lowest used address 00152654, stack used: 2476 bytes
+CPU1: stack: 00151000 - 00152000, lowest used address 00151e08, stack used: 504 bytes
+CPU2: stack: 00150000 - 00151000, lowest used address 00150e08, stack used: 504 bytes
+CPU3: stack: 0014f000 - 00150000, lowest used address 0014fe08, stack used: 504 bytes
+CPU_CLUSTER: 0 init finished in 156220 usecs
+DOMAIN: 0000 init ...
+DOMAIN: 0000 init finished in 995 usecs
+PCI: 00:00.0 init ...
+PCI: 00:00.0 init finished in 995 usecs
+PCI: 00:01.0 init ...
+PCI: 00:01.0 init finished in 995 usecs
+PCI: 00:01.1 init ...
+PCI: 00:01.1 init finished in 995 usecs
+PCI: 00:11.0 init ...
+PCI: 00:11.0 init finished in 995 usecs
+PCI: 00:12.0 init ...
+PCI: 00:12.0 init finished in 995 usecs
+PCI: 00:12.2 init ...
+PCI: 00:12.2 init finished in 995 usecs
+PCI: 00:13.0 init ...
+PCI: 00:13.0 init finished in 995 usecs
+PCI: 00:13.2 init ...
+PCI: 00:13.2 init finished in 995 usecs
+PCI: 00:14.0 init ...
+IOAPIC: Initializing IOAPIC at 0xfec00000
+IOAPIC: Bootstrap Processor Local APIC = 0x10
+IOAPIC: ID = 0x04
+IOAPIC: Dumping registers
+ reg 0x0000: 0x04000000
+ reg 0x0001: 0x00178021
+ reg 0x0002: 0x04000000
+IOAPIC: 24 interrupts
+IOAPIC: Enabling interrupts on FSB
+IOAPIC: reg 0x00000000 value 0x10000000 0x00000700
+IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
+IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
+PCI: 00:14.0 init finished in 66763 usecs
+PCI: 00:14.2 init ...
+PCI: 00:14.2 init finished in 995 usecs
+PCI: 00:14.3 init ...
+RTC Init
+PCI: 00:14.3 init finished in 1459 usecs
+PCI: 00:14.4 init ...
+PCI: 00:14.4 init finished in 995 usecs
+PCI: 00:14.5 init ...
+PCI: 00:14.5 init finished in 995 usecs
+PCI: 00:14.7 init ...
+PCI: 00:14.7 init finished in 995 usecs
+PCI: 00:18.0 init ...
+PCI: 00:18.0 init finished in 995 usecs
+PCI: 00:18.1 init ...
+PCI: 00:18.1 init finished in 995 usecs
+PCI: 00:18.2 init ...
+PCI: 00:18.2 init finished in 995 usecs
+PCI: 00:18.3 init ...
+PCI: 00:18.3 init finished in 995 usecs
+PCI: 00:18.4 init ...
+PCI: 00:18.4 init finished in 995 usecs
+PCI: 00:18.5 init ...
+PCI: 00:18.5 init finished in 995 usecs
+PCI: 01:00.0 init ...
+PCI: 01:00.0 init finished in 995 usecs
+PCI: 01:00.1 init ...
+PCI: 01:00.1 init finished in 995 usecs
+PCI: 01:00.2 init ...
+PCI: 01:00.2 init finished in 995 usecs
+PCI: 01:00.3 init ...
+PCI: 01:00.3 init finished in 995 usecs
+PNP: 002e.4 init ...
+PNP: 002e.4 init finished in 952 usecs
+Devices initialized
+Show all devs... After init.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+APIC: 10: enabled 1
+DOMAIN: 0000: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 1
+PCI: 00:01.1: enabled 1
+PCI: 00:02.0: enabled 0
+PCI: 00:03.0: enabled 0
+PCI: 00:04.0: enabled 0
+PCI: 00:05.0: enabled 0
+PCI: 00:06.0: enabled 1
+PCI: 00:07.0: enabled 0
+PCI: 00:08.0: enabled 0
+PCI: 00:10.0: enabled 0
+PCI: 00:10.1: enabled 0
+PCI: 00:11.0: enabled 1
+PCI: 00:12.0: enabled 1
+PCI: 00:12.2: enabled 1
+PCI: 00:13.0: enabled 1
+PCI: 00:13.2: enabled 1
+PCI: 00:14.0: enabled 1
+I2C: 01:50: enabled 1
+I2C: 01:51: enabled 1
+PCI: 00:14.1: enabled 0
+PCI: 00:14.2: enabled 1
+PCI: 00:14.3: enabled 1
+PNP: 002e.3: enabled 0
+PNP: 002e.4: enabled 1
+PNP: 002e.5: enabled 0
+PCI: 00:14.4: enabled 1
+PCI: 00:14.5: enabled 1
+PCI: 00:14.6: enabled 0
+PCI: 00:14.7: enabled 1
+PCI: 00:15.0: enabled 0
+PCI: 00:15.1: enabled 0
+PCI: 00:15.2: enabled 0
+PCI: 00:15.3: enabled 0
+PCI: 00:18.0: enabled 1
+PCI: 00:18.1: enabled 1
+PCI: 00:18.2: enabled 1
+PCI: 00:18.3: enabled 1
+PCI: 00:18.4: enabled 1
+PCI: 00:18.5: enabled 1
+APIC: 11: enabled 1
+APIC: 12: enabled 1
+APIC: 13: enabled 1
+PCI: 01:00.0: enabled 1
+PCI: 01:00.1: enabled 1
+PCI: 01:00.2: enabled 1
+PCI: 01:00.3: enabled 1
+BS: BS_DEV_INIT times (us): entry 0 run 356689 exit 0
+CBMEM:
+IMD: root @ bffff000 254 entries.
+IMD: root @ bfffec00 62 entries.
+Moving GDT to bfffe720...ok
+Finalize devices...
+Devices finalized
+agesawrapper_amdinitlate() returned AGESA_SUCCESS
+BS: BS_POST_DEVICE times (us): entry 4595 run 1733 exit 2305
+BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1 exit 0
+Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.
+Writing IRQ routing tables to 0xbffdd000...write_pirq_routing_table done.
+PIRQ table: 48 bytes.
+Wrote the mp table end at: 000f0410 - 000f0624
+Wrote the mp table end at: bffdc010 - bffdc224
+MP table: 548 bytes.
+CBFS: 'Master Header Locator' located CBFS at [100:3fffc0)
+CBFS: Locating 'fallback/dsdt.aml'
+CBFS: Found @ offset b4300 size 1c72
+CBFS: 'Master Header Locator' located CBFS at [100:3fffc0)
+CBFS: Locating 'fallback/slic'
+CBFS: 'fallback/slic' not found.
+ACPI: Writing ACPI tables at bffb8000.
+ACPI: * FACS
+ACPI: * DSDT
+ACPI: * FADT
+pm_base: 0x0800
+ACPI: added table 1/32, length now 40
+ACPI: * SSDT
+ACPI: added table 2/32, length now 44
+ACPI: * MCFG
+ACPI: * TCPA
+TCPA log created at bffa8000
+ACPI: added table 3/32, length now 48
+ACPI: * MADT
+ACPI: added table 4/32, length now 52
+current = bffba110
+ACPI: * HPET
+ACPI: added table 5/32, length now 56
+ACPI: added table 6/32, length now 60
+ACPI: * IVRS at bffba320
+ AGESA IVRS table NULL. Skipping.
+ACPI: * SRAT at bffba320
+ AGESA SRAT table NULL. Skipping.
+ACPI: * SLIT at bffba320
+ AGESA SLIT table NULL. Skipping.
+ACPI: * AGESA ALIB SSDT at bffba320
+ACPI: added table 7/32, length now 64
+ACPI: * SSDT at bffbc200
+ACPI: added table 8/32, length now 68
+ACPI: * SSDT for PState at bffbcbf8
+ACPI: done.
+ACPI tables: 19456 bytes.
+smbios_write_tables: bffa7000
+Root Device (AMD Thatcher)
+CPU_CLUSTER: 0 (AMD FAM15tn Root Complex)
+APIC: 10 (AMD CPU Family 15h)
+DOMAIN: 0000 (AMD FAM15tn Root Complex)
+PCI: 00:00.0 (AMD FAM15 Northbridge)
+PCI: 00:01.0 (AMD FAM15 Northbridge)
+PCI: 00:01.1 (AMD FAM15 Northbridge)
+PCI: 00:02.0 (AMD FAM15 Northbridge)
+PCI: 00:03.0 (AMD FAM15 Northbridge)
+PCI: 00:04.0 (AMD FAM15 Northbridge)
+PCI: 00:05.0 (AMD FAM15 Northbridge)
+PCI: 00:06.0 (AMD FAM15 Northbridge)
+PCI: 00:07.0 (AMD FAM15 Northbridge)
+PCI: 00:08.0 (AMD FAM15 Northbridge)
+PCI: 00:10.0 (ATI HUDSON)
+PCI: 00:10.1 (ATI HUDSON)
+PCI: 00:11.0 (ATI HUDSON)
+PCI: 00:12.0 (ATI HUDSON)
+PCI: 00:12.2 (ATI HUDSON)
+PCI: 00:13.0 (ATI HUDSON)
+PCI: 00:13.2 (ATI HUDSON)
+PCI: 00:14.0 (ATI HUDSON)
+I2C: 01:50 (unknown)
+I2C: 01:51 (unknown)
+PCI: 00:14.1 (ATI HUDSON)
+PCI: 00:14.2 (ATI HUDSON)
+PCI: 00:14.3 (ATI HUDSON)
+PNP: 002e.3 (SMSC LPC47N217 Super I/O)
+PNP: 002e.4 (SMSC LPC47N217 Super I/O)
+PNP: 002e.5 (SMSC LPC47N217 Super I/O)
+PCI: 00:14.4 (ATI HUDSON)
+PCI: 00:14.5 (ATI HUDSON)
+PCI: 00:14.6 (ATI HUDSON)
+PCI: 00:14.7 (ATI HUDSON)
+PCI: 00:15.0 (ATI HUDSON)
+PCI: 00:15.1 (ATI HUDSON)
+PCI: 00:15.2 (ATI HUDSON)
+PCI: 00:15.3 (ATI HUDSON)
+PCI: 00:18.0 (AMD FAM15 Northbridge)
+PCI: 00:18.1 (AMD FAM15 Northbridge)
+PCI: 00:18.2 (AMD FAM15 Northbridge)
+PCI: 00:18.3 (AMD FAM15 Northbridge)
+PCI: 00:18.4 (AMD FAM15 Northbridge)
+PCI: 00:18.5 (AMD FAM15 Northbridge)
+APIC: 11 (unknown)
+APIC: 12 (unknown)
+APIC: 13 (unknown)
+PCI: 01:00.0 (unknown)
+PCI: 01:00.1 (unknown)
+PCI: 01:00.2 (unknown)
+PCI: 01:00.3 (unknown)
+SMBIOS tables: 334 bytes.
+Writing table forward entry at 0x00000500
+Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4fe4
+Table forward entry ends at 0x00000528.
+... aligned to 0x00001000
+Writing coreboot table at 0xbff9f000
+rom_table_end = 0xbff9f000
+... aligned to 0xbffa0000
+ 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
+ 1. 0000000000001000-000000000009ffff: RAM
+ 2. 00000000000c0000-00000000bff9efff: RAM
+ 3. 00000000bff9f000-00000000bfffffff: CONFIGURATION TABLES
+ 4. 00000000c0000000-00000000dfffffff: RESERVED
+ 5. 00000000f8000000-00000000fbffffff: RESERVED
+ 6. 0000000100000000-000000011effffff: RAM
+CBFS: 'Master Header Locator' located CBFS at [100:3fffc0)
+FMAP: Found "FLASH" version 1.1 at 0.
+FMAP: base = ffc00000 size = 400000 #areas = 3
+Wrote coreboot table at: bff9f000, 0x264 bytes, checksum 5d5e
+coreboot table: 636 bytes.
+IMD ROOT 0. bffff000 00001000
+IMD SMALL 1. bfffe000 00001000
+CONSOLE 2. bffde000 00020000
+IRQ TABLE 3. bffdd000 00001000
+SMP TABLE 4. bffdc000 00001000
+ACPI 5. bffb8000 00024000
+TCPA LOG 6. bffa8000 00010000
+SMBIOS 7. bffa7000 00000800
+COREBOOT 8. bff9f000 00008000
+IMD small region:
+ IMD ROOT 0. bfffec00 00000400
+ TIME STAMP 1. bfffe920 000002e0
+ GDT 2. bfffe720 00000200
+BS: BS_WRITE_TABLES times (us): entry 0 run 191005 exit 0
+CBFS: 'Master Header Locator' located CBFS at [100:3fffc0)
+CBFS: Locating 'fallback/payload'
+CBFS: Found @ offset 80 size ed70
+Loading segment from rom address 0xffc001b8
+ code (compression=1)
+ New segment dstaddr 0xe44a4 memsize 0x1bb5c srcaddr 0xffc001f0 filesize 0xed38
+Loading segment from rom address 0xffc001d4
+ Entry Point 0x000ff06e
+Bounce Buffer at bfd30000, 2548416 bytes
+Loading Segment: addr: 0x00000000000e44a4 memsz: 0x000000000001bb5c filesz: 0x000000000000ed38
+lb: [0x0000000000100000, 0x0000000000237160)
+Post relocation: addr: 0x00000000000e44a4 memsz: 0x000000000001bb5c filesz: 0x000000000000ed38
+using LZMA
+[ 0x000e44a4, 00100000, 0x00100000) <- ffc001f0
+dest 000e44a4, end 00100000, bouncebuffer bfd30000
+Loaded segments
+BS: BS_PAYLOAD_LOAD times (us): entry 0 run 47042 exit 0
+Jumping to boot code at 000ff06e(bff9f000)
+CPU0: stack: 00152000 - 00153000, lowest used address 00152654, stack used: 2476 bytes
+entry = 0x000ff06e
+lb_start = 0x00100000
+lb_size = 0x00137160
+buffer = 0xbfd30000
+SeaBIOS (version rel-1.9.0-0-g01a84be)
+BUILD: gcc: (coreboot toolchain v1.31 June 17th, 2015) 4.9.2 binutils: (GNU Binutils) 2.25
+Found coreboot cbmem console @ bffde000
+Found mainboard AMD Thatcher
+Relocating init from 0x000e58b0 to 0xbff53ed0 (size 45216)
+Found CBFS header at 0xffc00138
+multiboot: eax=0, ebx=0
+Found 25 PCI devices (max PCI bus is 02)
+Copying SMBIOS entry point from 0xbffa7000 to 0x000f0930
+Copying ACPI RSDP from 0xbffb8000 to 0x000f0900
+Copying MPTABLE from 0xbffdc000/bffdc010 to 0x000f06d0
+Copying PIR from 0xbffdd000 to 0x000f06a0
+Using pmtimer, ioport 0x818
+Scan for VGA option rom
+Running option rom at c000:0003
+Turning on vga text mode console
+SeaBIOS (version rel-1.9.0-0-g01a84be)
+EHCI init on dev 00:12.2 (regs=0xf024c020)
+WARNING - Timeout at i8042_flush:71!
+EHCI init on dev 00:13.2 (regs=0xf024d020)
+Found 0 lpt ports
+Found 1 serial ports
+AHCI controller at 11.0, iobase f024b000, irq 0
+OHCI init on dev 00:12.0 (regs=0xf0248000)
+OHCI init on dev 00:13.0 (regs=0xf0249000)
+OHCI init on dev 00:14.5 (regs=0xf024a000)
+Searching bootorder for: /pci@i0cf8/*@14,7
+Searching bootorder for: /pci@i0cf8/usb@12,2/storage@3/*@0/*@0,0
+Searching bootorder for: /pci@i0cf8/usb@12,2/usb-*@3
+USB keyboard initialized
+USB mouse initialized
+Initialized USB HUB (2 ports used)
+USB MSC vendor='PNY' product='USB 2.0 FD' rev='1100' type=0 removable=1
+USB MSC blksize=512 sectors=15814656
+All threads complete.
+Scan for option roms
+
+Press ESC for boot menu.
+
+Searching bootorder for: HALT
+drive 0x000f0650: PCHS=0/0/0 translation=lba LCHS=984/255/63 s=15814656
+Space available for UMB: d0000-ee800, f0000-f0650
+Returned 253952 bytes of ZoneHigh
+e820 map has 7 items:
+ 0: 0000000000000000 - 000000000009fc00 = 1 RAM
+ 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
+ 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
+ 3: 0000000000100000 - 00000000bff9d000 = 1 RAM
+ 4: 00000000bff9d000 - 00000000e0000000 = 2 RESERVED
+ 5: 00000000f8000000 - 00000000fc000000 = 2 RESERVED
+ 6: 0000000100000000 - 000000011f000000 = 1 RAM
+enter handle_19:
+ NULL
+Booting from Hard Disk...
+Booting from 0000:7c00
+