diff --git a/asus/kfsn4-dre_k8/4.2-266-g7dcf9d5/2015-11-17T20:31:20Z/coreboot_console.txt b/asus/kfsn4-dre_k8/4.2-266-g7dcf9d5/2015-11-17T20:31:20Z/coreboot_console.txt
new file mode 100644
index 0000000..481445b
--- /dev/null
+++ b/asus/kfsn4-dre_k8/4.2-266-g7dcf9d5/2015-11-17T20:31:20Z/coreboot_console.txt
@@ -0,0 +1,2209 @@
+
+
+coreboot-4.2-266-g7dcf9d5-dirty-RAPTOR-NORMAL Tue Nov 17 20:31:20 UTC 2015 ramstage starting...
+POST: 0x39
+POST: 0x80
+POST: 0x70
+POST: 0x71
+POST: 0x72
+Enumerating buses...
+Show all devs... Before device enumeration.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+APIC: 00: enabled 1
+DOMAIN: 0000: enabled 1
+PCI: 00:18.0: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 1
+PNP: 002e.0: enabled 1
+PNP: 002e.1: enabled 0
+PNP: 002e.2: enabled 1
+PNP: 002e.3: enabled 1
+PNP: 002e.5: enabled 1
+PNP: 002e.7: enabled 0
+PNP: 002e.8: enabled 0
+PNP: 002e.9: enabled 1
+PNP: 002e.a: enabled 0
+PNP: 002e.b: enabled 1
+PCI: 00:01.1: enabled 1
+I2C: 00:50: enabled 1
+I2C: 00:51: enabled 1
+I2C: 00:52: enabled 1
+I2C: 00:53: enabled 1
+I2C: 00:54: enabled 1
+I2C: 00:55: enabled 1
+I2C: 00:56: enabled 1
+I2C: 00:57: enabled 1
+I2C: 00:2f: enabled 1
+PCI: 00:02.0: enabled 1
+PCI: 00:02.1: enabled 1
+PCI: 00:04.0: enabled 0
+PCI: 00:04.1: enabled 0
+PCI: 00:06.0: enabled 1
+PCI: 00:07.0: enabled 1
+PCI: 00:08.0: enabled 1
+PCI: 00:09.0: enabled 1
+PCI: 00:04.0: enabled 1
+PCI: 00:0a.0: enabled 0
+PCI: 00:0b.0: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:0c.0: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:0d.0: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:0e.0: enabled 1
+PCI: 00:0f.0: enabled 0
+PCI: 00:18.1: enabled 1
+PCI: 00:18.2: enabled 1
+PCI: 00:18.3: enabled 1
+PCI: 00:18.4: enabled 1
+PCI: 00:19.0: enabled 1
+PCI: 00:19.1: enabled 1
+PCI: 00:19.2: enabled 1
+PCI: 00:19.3: enabled 1
+PCI: 00:19.4: enabled 1
+Compare with tree...
+Root Device: enabled 1
+ CPU_CLUSTER: 0: enabled 1
+  APIC: 00: enabled 1
+ DOMAIN: 0000: enabled 1
+  PCI: 00:18.0: enabled 1
+   PCI: 00:00.0: enabled 1
+   PCI: 00:01.0: enabled 1
+    PNP: 002e.0: enabled 1
+    PNP: 002e.1: enabled 0
+    PNP: 002e.2: enabled 1
+    PNP: 002e.3: enabled 1
+    PNP: 002e.5: enabled 1
+    PNP: 002e.7: enabled 0
+    PNP: 002e.8: enabled 0
+    PNP: 002e.9: enabled 1
+    PNP: 002e.a: enabled 0
+    PNP: 002e.b: enabled 1
+   PCI: 00:01.1: enabled 1
+    I2C: 00:50: enabled 1
+    I2C: 00:51: enabled 1
+    I2C: 00:52: enabled 1
+    I2C: 00:53: enabled 1
+    I2C: 00:54: enabled 1
+    I2C: 00:55: enabled 1
+    I2C: 00:56: enabled 1
+    I2C: 00:57: enabled 1
+    I2C: 00:2f: enabled 1
+   PCI: 00:02.0: enabled 1
+   PCI: 00:02.1: enabled 1
+   PCI: 00:04.0: enabled 0
+   PCI: 00:04.1: enabled 0
+   PCI: 00:06.0: enabled 1
+   PCI: 00:07.0: enabled 1
+   PCI: 00:08.0: enabled 1
+   PCI: 00:09.0: enabled 1
+    PCI: 00:04.0: enabled 1
+   PCI: 00:0a.0: enabled 0
+   PCI: 00:0b.0: enabled 1
+    PCI: 00:00.0: enabled 1
+   PCI: 00:0c.0: enabled 1
+    PCI: 00:00.0: enabled 1
+   PCI: 00:0d.0: enabled 1
+    PCI: 00:00.0: enabled 1
+   PCI: 00:0e.0: enabled 1
+   PCI: 00:0f.0: enabled 0
+  PCI: 00:18.1: enabled 1
+  PCI: 00:18.2: enabled 1
+  PCI: 00:18.3: enabled 1
+  PCI: 00:18.4: enabled 1
+  PCI: 00:19.0: enabled 1
+  PCI: 00:19.1: enabled 1
+  PCI: 00:19.2: enabled 1
+  PCI: 00:19.3: enabled 1
+  PCI: 00:19.4: enabled 1
+Root Device scanning...
+root_dev_scan_bus for Root Device
+setup_bsp_ramtop, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000
+setup_bsp_ramtop, TOP MEM2: msr.lo = 0x40000000, msr.hi = 0x00000001
+CPU_CLUSTER: 0 enabled
+DOMAIN: 0000 enabled
+CPU_CLUSTER: 0 scanning...
+CBFS @ 0 size ff480
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Checking offset 0
+CBFS:  Unmatched 'cmos.default' at 0
+CBFS: Checking offset 140
+CBFS:  Unmatched 'cpu_microcode_blob.bin' at 140
+CBFS: Checking offset 19c0
+CBFS: Found @ offset 19c0 size a64
+  PCI: 00:18.3 siblings=1
+CPU: APIC: 10 enabled
+CPU: APIC: 11 enabled
+  PCI: 00:19.3 siblings=1
+CPU: APIC: 12 enabled
+CPU: APIC: 13 enabled
+scan_bus: scanning of bus CPU_CLUSTER: 0 took 0 usecs
+DOMAIN: 0000 scanning...
+PCI: pci_scan_bus for bus 00
+POST: 0x24
+PCI: 00:18.0 [1022/1100] bus ops
+PCI: 00:18.0 [1022/1100] enabled
+PCI: 00:18.1 [1022/1101] enabled
+PCI: 00:18.2 [1022/1102] enabled
+PCI: 00:18.3 [1022/1103] ops
+PCI: 00:18.3 [1022/1103] enabled
+PCI: Static device PCI: 00:18.4 not found, disabling it.
+PCI: 00:19.0 [1022/1100] bus ops
+PCI: 00:19.0 [1022/1100] enabled
+PCI: 00:19.1 [1022/1101] enabled
+PCI: 00:19.2 [1022/1102] enabled
+PCI: 00:19.3 [1022/1103] ops
+PCI: 00:19.3 [1022/1103] enabled
+PCI: Static device PCI: 00:19.4 not found, disabling it.
+POST: 0x25
+PCI: 00:18.0 scanning...
+do_hypertransport_scan_chain for bus 00
+PCI: 00:00.0 [10de/005e] ops
+PCI: 00:00.0 [10de/005e] enabled
+Capability: type 0x08 @ 0x44
+flags: 0x01e0
+PCI: 00:00.0 count: 000f static_count: 0010
+PCI: 00:00.0 [10de/005e] enabled next_unitid: 0010
+PCI: pci_scan_bus for bus 00
+POST: 0x24
+PCI: 00:00.0 [10de/005e] enabled
+PCI: 00:01.0 [10de/0051] bus ops
+PCI: 00:01.0 [10de/0051] enabled
+PCI: 00:01.1 [10de/0052] bus ops
+PCI: 00:01.1 [10de/0052] enabled
+PCI: 00:02.0 [10de/005a] ops
+PCI: 00:02.0 [10de/005a] enabled
+PCI: 00:02.1 [10de/005b] ops
+PCI: 00:02.1 [10de/005b] enabled
+PCI: 00:04.0 [10de/0059] ops
+PCI: 00:04.0 [10de/0059] disabled
+PCI: 00:04.1 [10de/0058] ops
+PCI: 00:04.1 [10de/0058] disabled
+PCI: 00:06.0 [10de/0053] ops
+PCI: 00:06.0 [10de/0053] enabled
+PCI: 00:07.0 [10de/0054] ops
+PCI: 00:07.0 [10de/0054] enabled
+PCI: 00:08.0 [10de/0055] ops
+PCI: 00:08.0 [10de/0055] enabled
+PCI: 00:09.0 [10de/005c] bus ops
+PCI: 00:09.0 [10de/005c] enabled
+PCI: 00:0b.0 [10de/005d] bus ops
+PCI: 00:0b.0 [10de/005d] enabled
+PCI: 00:0c.0 [10de/005d] bus ops
+PCI: 00:0c.0 [10de/005d] enabled
+PCI: 00:0d.0 [10de/005d] bus ops
+PCI: 00:0d.0 [10de/005d] enabled
+PCI: 00:0e.0 [10de/005d] bus ops
+PCI: 00:0e.0 [10de/005d] enabled
+POST: 0x25
+PCI: 00:01.0 scanning...
+scan_lpc_bus for PCI: 00:01.0
+PNP: 002e.0 enabled
+PNP: 002e.1 disabled
+PNP: 002e.2 enabled
+PNP: 002e.3 enabled
+PNP: 002e.5 enabled
+PNP: 002e.7 disabled
+PNP: 002e.8 disabled
+PNP: 002e.9 enabled
+PNP: 002e.a disabled
+PNP: 002e.b enabled
+scan_lpc_bus for PCI: 00:01.0 done
+scan_bus: scanning of bus PCI: 00:01.0 took 0 usecs
+PCI: 00:01.1 scanning...
+scan_smbus for PCI: 00:01.1
+smbus: PCI: 00:01.1[0]->I2C: 01:50 enabled
+smbus: PCI: 00:01.1[0]->I2C: 01:51 enabled
+smbus: PCI: 00:01.1[0]->I2C: 01:52 enabled
+smbus: PCI: 00:01.1[0]->I2C: 01:53 enabled
+smbus: PCI: 00:01.1[0]->I2C: 01:54 enabled
+smbus: PCI: 00:01.1[0]->I2C: 01:55 enabled
+smbus: PCI: 00:01.1[0]->I2C: 01:56 enabled
+smbus: PCI: 00:01.1[0]->I2C: 01:57 enabled
+smbus: PCI: 00:01.1[0]->I2C: 01:2f enabled
+scan_smbus for PCI: 00:01.1 done
+scan_bus: scanning of bus PCI: 00:01.1 took 0 usecs
+PCI: 00:09.0 scanning...
+do_pci_scan_bridge for PCI: 00:09.0
+PCI: pci_scan_bus for bus 01
+POST: 0x24
+PCI: 01:04.0 [18ca/0020] ops
+PCI: 01:04.0 [18ca/0020] enabled
+POST: 0x25
+POST: 0x55
+scan_bus: scanning of bus PCI: 00:09.0 took 0 usecs
+PCI: 00:0b.0 scanning...
+do_pci_scan_bridge for PCI: 00:0b.0
+PCI: pci_scan_bus for bus 02
+POST: 0x24
+PCI: 02:00.0 [14e4/1659] enabled
+POST: 0x25
+POST: 0x55
+scan_bus: scanning of bus PCI: 00:0b.0 took 0 usecs
+PCI: 00:0c.0 scanning...
+do_pci_scan_bridge for PCI: 00:0c.0
+PCI: pci_scan_bus for bus 03
+POST: 0x24
+PCI: 03:00.0 [14e4/1659] enabled
+POST: 0x25
+POST: 0x55
+scan_bus: scanning of bus PCI: 00:0c.0 took 0 usecs
+PCI: 00:0d.0 scanning...
+do_pci_scan_bridge for PCI: 00:0d.0
+PCI: pci_scan_bus for bus 04
+POST: 0x24
+PCI: Static device PCI: 04:00.0 not found, disabling it.
+POST: 0x25
+POST: 0x55
+scan_bus: scanning of bus PCI: 00:0d.0 took 0 usecs
+PCI: 00:0e.0 scanning...
+do_pci_scan_bridge for PCI: 00:0e.0
+PCI: pci_scan_bus for bus 05
+POST: 0x24
+Capability: type 0x10 @ 0x40
+Capability: type 0x01 @ 0x70
+Capability: type 0x10 @ 0x40
+Capability: type 0x01 @ 0x70
+Capability: type 0x10 @ 0x40
+PCI: 05:00.0 subordinate bus PCI Express
+PCI: 05:00.0 [111d/8018] enabled
+POST: 0x25
+PCI: 05:00.0 scanning...
+do_pci_scan_bridge for PCI: 05:00.0
+PCI: pci_scan_bus for bus 06
+POST: 0x24
+Capability: type 0x10 @ 0x40
+Capability: type 0x01 @ 0x70
+Capability: type 0x05 @ 0x7c
+Capability: type 0x10 @ 0x40
+Capability: type 0x01 @ 0x70
+Capability: type 0x05 @ 0x7c
+Capability: type 0x10 @ 0x40
+PCI: 06:00.0 subordinate bus PCI Express
+PCI: 06:00.0 [111d/8018] enabled
+Capability: type 0x10 @ 0x40
+Capability: type 0x01 @ 0x70
+Capability: type 0x05 @ 0x7c
+Capability: type 0x10 @ 0x40
+Capability: type 0x01 @ 0x70
+Capability: type 0x05 @ 0x7c
+Capability: type 0x10 @ 0x40
+PCI: 06:01.0 subordinate bus PCI Express
+PCI: 06:01.0 [111d/8018] enabled
+POST: 0x25
+PCI: 06:00.0 scanning...
+do_pci_scan_bridge for PCI: 06:00.0
+PCI: pci_scan_bus for bus 07
+POST: 0x24
+PCI: 07:00.0 [8086/10bc] enabled
+PCI: 07:00.1 [8086/10bc] enabled
+POST: 0x25
+POST: 0x55
+Capability: type 0x01 @ 0xc8
+Capability: type 0x05 @ 0xd0
+Capability: type 0x10 @ 0xe0
+Capability: type 0x10 @ 0x40
+Capability: type 0x01 @ 0xc8
+Capability: type 0x05 @ 0xd0
+Capability: type 0x10 @ 0xe0
+Capability: type 0x10 @ 0x40
+scan_bus: scanning of bus PCI: 06:00.0 took 0 usecs
+PCI: 06:01.0 scanning...
+do_pci_scan_bridge for PCI: 06:01.0
+PCI: pci_scan_bus for bus 08
+POST: 0x24
+PCI: 08:00.0 [8086/10bc] enabled
+PCI: 08:00.1 [8086/10bc] enabled
+POST: 0x25
+POST: 0x55
+Capability: type 0x01 @ 0xc8
+Capability: type 0x05 @ 0xd0
+Capability: type 0x10 @ 0xe0
+Capability: type 0x10 @ 0x40
+Capability: type 0x01 @ 0xc8
+Capability: type 0x05 @ 0xd0
+Capability: type 0x10 @ 0xe0
+Capability: type 0x10 @ 0x40
+scan_bus: scanning of bus PCI: 06:01.0 took 0 usecs
+POST: 0x55
+Capability: type 0x10 @ 0x40
+Capability: type 0x10 @ 0x40
+Capability: type 0x10 @ 0x40
+Capability: type 0x10 @ 0x40
+scan_bus: scanning of bus PCI: 05:00.0 took 0 usecs
+POST: 0x55
+scan_bus: scanning of bus PCI: 00:0e.0 took 0 usecs
+POST: 0x55
+scan_bus: scanning of bus PCI: 00:18.0 took 0 usecs
+PCI: 00:19.0 scanning...
+scan_bus: scanning of bus PCI: 00:19.0 took 0 usecs
+POST: 0x55
+DOMAIN: 0000 passpw: enabled
+DOMAIN: 0000 passpw: enabled
+scan_bus: scanning of bus DOMAIN: 0000 took 0 usecs
+root_dev_scan_bus for Root Device done
+scan_bus: scanning of bus Root Device took 0 usecs
+done
+POST: 0x73
+found VGA at PCI: 01:04.0
+Setting up VGA for PCI: 01:04.0
+Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:09.0
+Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
+Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
+Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
+Allocating resources...
+Reading resources...
+Root Device read_resources bus 0 link: 0
+CPU_CLUSTER: 0 read_resources bus 0 link: 0
+APIC: 10 missing read_resources
+APIC: 11 missing read_resources
+APIC: 12 missing read_resources
+APIC: 13 missing read_resources
+CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
+DOMAIN: 0000 read_resources bus 0 link: 0
+VGA: PCI: 00:18.0 (aka node 0) link 1 has VGA device
+PCI: 00:18.0 read_resources bus 0 link: 1
+PCI: 00:01.0 read_resources bus 0 link: 0
+PCI: 00:01.0 read_resources bus 0 link: 0 done
+PCI: 00:01.1 read_resources bus 1 link: 0
+I2C: 01:50 missing read_resources
+I2C: 01:51 missing read_resources
+I2C: 01:52 missing read_resources
+I2C: 01:53 missing read_resources
+I2C: 01:54 missing read_resources
+I2C: 01:55 missing read_resources
+I2C: 01:56 missing read_resources
+I2C: 01:57 missing read_resources
+PCI: 00:01.1 read_resources bus 1 link: 0 done
+PCI: 00:01.1 read_resources bus 2 link: 1
+PCI: 00:01.1 read_resources bus 2 link: 1 done
+PCI: 00:09.0 read_resources bus 1 link: 0
+PCI: 00:09.0 read_resources bus 1 link: 0 done
+PCI: 00:0b.0 read_resources bus 2 link: 0
+PCI: 00:0b.0 read_resources bus 2 link: 0 done
+PCI: 00:0c.0 read_resources bus 3 link: 0
+PCI: 00:0c.0 read_resources bus 3 link: 0 done
+PCI: 00:0d.0 read_resources bus 4 link: 0
+PCI: 00:0d.0 read_resources bus 4 link: 0 done
+PCI: 00:0e.0 read_resources bus 5 link: 0
+PCI: 05:00.0 read_resources bus 6 link: 0
+PCI: 06:00.0 read_resources bus 7 link: 0
+PCI: 06:00.0 read_resources bus 7 link: 0 done
+PCI: 06:01.0 read_resources bus 8 link: 0
+PCI: 06:01.0 read_resources bus 8 link: 0 done
+PCI: 05:00.0 read_resources bus 6 link: 0 done
+PCI: 00:0e.0 read_resources bus 5 link: 0 done
+PCI: 00:18.0 read_resources bus 0 link: 1 done
+PCI: 00:18.0 read_resources bus 0 link: 0
+PCI: 00:18.0 read_resources bus 0 link: 0 done
+PCI: 00:18.0 read_resources bus 0 link: 2
+PCI: 00:18.0 read_resources bus 0 link: 2 done
+CBFS @ 0 size ff480
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Checking offset 0
+CBFS:  Unmatched 'cmos.default' at 0
+CBFS: Checking offset 140
+CBFS:  Unmatched 'cpu_microcode_blob.bin' at 140
+CBFS: Checking offset 19c0
+CBFS: Found @ offset 19c0 size a64
+PCI: 00:19.0 read_resources bus 0 link: 0
+PCI: 00:19.0 read_resources bus 0 link: 0 done
+PCI: 00:19.0 read_resources bus 0 link: 1
+PCI: 00:19.0 read_resources bus 0 link: 1 done
+PCI: 00:19.0 read_resources bus 0 link: 2
+PCI: 00:19.0 read_resources bus 0 link: 2 done
+DOMAIN: 0000 read_resources bus 0 link: 0 done
+Root Device read_resources bus 0 link: 0 done
+Done reading resources.
+Show resources in subtree (Root Device)...After reading.
+ Root Device child on link 0 CPU_CLUSTER: 0
+  CPU_CLUSTER: 0 child on link 0 APIC: 10
+   APIC: 10
+   APIC: 11
+   APIC: 12
+   APIC: 13
+  DOMAIN: 0000 child on link 0 PCI: 00:18.0
+  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
+  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
+   PCI: 00:18.0 child on link 0 PCI: 00:00.0
+   PCI: 00:18.0 resource base 33 size 0 align 0 gran 0 limit 3010 flags 1 index 101c0
+   PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 10000
+   PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 10002
+   PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80200 index 10001
+   PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags c0000200 index 10004
+    PCI: 00:00.0
+    PCI: 00:01.0 child on link 0 PNP: 002e.0
+    PCI: 00:01.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 10
+    PCI: 00:01.0 resource base fec00000 size 1000 align 12 gran 12 limit ffffffff flags c0000200 index 14
+    PCI: 00:01.0 resource base fed00000 size 1000 align 12 gran 12 limit ffffffff flags c0000200 index 44
+    PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 60
+    PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 64
+    PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 68
+    PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+    PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+     PNP: 002e.0
+     PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
+     PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+     PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
+     PNP: 002e.1
+     PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
+     PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+     PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
+     PNP: 002e.2
+     PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
+     PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+     PNP: 002e.3
+     PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
+     PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+     PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000500 index f1
+     PNP: 002e.5
+     PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
+     PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
+     PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+     PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72
+     PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f0
+     PNP: 002e.7
+     PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
+     PNP: 002e.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62
+     PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+     PNP: 002e.8
+     PNP: 002e.9
+     PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 30
+     PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f0
+     PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f1
+     PNP: 002e.a
+     PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+     PNP: 002e.b
+     PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags c0000100 index 60
+     PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+    PCI: 00:01.1 child on link 0 I2C: 01:50
+    PCI: 00:01.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 10
+    PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
+    PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 24
+     I2C: 01:50
+     I2C: 01:51
+     I2C: 01:52
+     I2C: 01:53
+     I2C: 01:54
+     I2C: 01:55
+     I2C: 01:56
+     I2C: 01:57
+     I2C: 01:2f
+    PCI: 00:02.0
+    PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
+    PCI: 00:02.1
+    PCI: 00:02.1 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
+    PCI: 00:04.0
+    PCI: 00:04.1
+    PCI: 00:06.0
+    PCI: 00:06.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
+    PCI: 00:07.0
+    PCI: 00:07.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
+    PCI: 00:07.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
+    PCI: 00:07.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
+    PCI: 00:07.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
+    PCI: 00:07.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
+    PCI: 00:07.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 24
+    PCI: 00:08.0
+    PCI: 00:08.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
+    PCI: 00:08.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
+    PCI: 00:08.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
+    PCI: 00:08.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
+    PCI: 00:08.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
+    PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 24
+    PCI: 00:09.0 child on link 0 PCI: 01:04.0
+    PCI: 00:09.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+    PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
+    PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+     PCI: 01:04.0
+     PCI: 01:04.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 1200 index 10
+     PCI: 01:04.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 14
+     PCI: 01:04.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 18
+    PCI: 00:0a.0
+    PCI: 00:0b.0 child on link 0 PCI: 02:00.0
+    PCI: 00:0b.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
+    PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+    PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+     PCI: 02:00.0
+     PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
+    PCI: 00:0c.0 child on link 0 PCI: 03:00.0
+    PCI: 00:0c.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
+    PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+    PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+     PCI: 03:00.0
+     PCI: 03:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
+    PCI: 00:0d.0 child on link 0 PCI: 04:00.0
+    PCI: 00:0d.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
+    PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+    PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+     PCI: 04:00.0
+    PCI: 00:0e.0 child on link 0 PCI: 05:00.0
+    PCI: 00:0e.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
+    PCI: 00:0e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+    PCI: 00:0e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+     PCI: 05:00.0 child on link 0 PCI: 06:00.0
+     PCI: 05:00.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
+     PCI: 05:00.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+     PCI: 05:00.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+      PCI: 06:00.0 child on link 0 PCI: 07:00.0
+      PCI: 06:00.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
+      PCI: 06:00.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+      PCI: 06:00.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+       PCI: 07:00.0
+       PCI: 07:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
+       PCI: 07:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 14
+       PCI: 07:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
+       PCI: 07:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
+       PCI: 07:00.1
+       PCI: 07:00.1 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
+       PCI: 07:00.1 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 14
+       PCI: 07:00.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
+       PCI: 07:00.1 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
+      PCI: 06:01.0 child on link 0 PCI: 08:00.0
+      PCI: 06:01.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
+      PCI: 06:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+      PCI: 06:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+       PCI: 08:00.0
+       PCI: 08:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
+       PCI: 08:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 14
+       PCI: 08:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
+       PCI: 08:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
+       PCI: 08:00.1
+       PCI: 08:00.1 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
+       PCI: 08:00.1 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 14
+       PCI: 08:00.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
+       PCI: 08:00.1 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
+    PCI: 00:0f.0
+   PCI: 00:18.1
+   PCI: 00:18.2
+   PCI: 00:18.3
+   PCI: 00:18.4
+   PCI: 00:19.0
+   PCI: 00:19.1
+   PCI: 00:19.2
+   PCI: 00:19.3
+   PCI: 00:19.4
+DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
+PCI: 00:18.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:09.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 01:04.0 18 *  [0x0 - 0x7f] io
+PCI: 00:09.0 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done
+PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
+PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
+PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
+PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
+PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
+PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
+PCI: 00:0e.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
+PCI: 05:00.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
+PCI: 06:00.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
+PCI: 07:00.0 18 *  [0x0 - 0x1f] io
+PCI: 07:00.1 18 *  [0x20 - 0x3f] io
+PCI: 06:00.0 io: base: 40 size: 1000 align: 12 gran: 12 limit: ffff done
+PCI: 06:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
+PCI: 08:00.0 18 *  [0x0 - 0x1f] io
+PCI: 08:00.1 18 *  [0x20 - 0x3f] io
+PCI: 06:01.0 io: base: 40 size: 1000 align: 12 gran: 12 limit: ffff done
+PCI: 06:00.0 1c *  [0x0 - 0xfff] io
+PCI: 06:01.0 1c *  [0x1000 - 0x1fff] io
+PCI: 05:00.0 io: base: 2000 size: 2000 align: 12 gran: 12 limit: ffff done
+PCI: 05:00.0 1c *  [0x0 - 0x1fff] io
+PCI: 00:0e.0 io: base: 2000 size: 2000 align: 12 gran: 12 limit: ffff done
+PCI: 00:0e.0 1c *  [0x0 - 0x1fff] io
+PCI: 00:09.0 1c *  [0x2000 - 0x2fff] io
+PCI: 00:01.0 60 *  [0x3000 - 0x30ff] io
+PCI: 00:01.0 64 *  [0x3400 - 0x34ff] io
+PCI: 00:01.0 68 *  [0x3800 - 0x38ff] io
+PCI: 00:01.0 10 *  [0x3c00 - 0x3c7f] io
+PCI: 00:01.1 20 *  [0x3c80 - 0x3cbf] io
+PCI: 00:01.1 24 *  [0x3cc0 - 0x3cff] io
+PCI: 00:01.1 10 *  [0x4000 - 0x401f] io
+PCI: 00:06.0 20 *  [0x4020 - 0x402f] io
+PCI: 00:07.0 20 *  [0x4030 - 0x403f] io
+PCI: 00:08.0 20 *  [0x4040 - 0x404f] io
+PCI: 00:07.0 10 *  [0x4050 - 0x4057] io
+PCI: 00:07.0 18 *  [0x4058 - 0x405f] io
+PCI: 00:08.0 10 *  [0x4060 - 0x4067] io
+PCI: 00:08.0 18 *  [0x4068 - 0x406f] io
+PCI: 00:07.0 14 *  [0x4070 - 0x4073] io
+PCI: 00:07.0 1c *  [0x4074 - 0x4077] io
+PCI: 00:08.0 14 *  [0x4078 - 0x407b] io
+PCI: 00:08.0 1c *  [0x407c - 0x407f] io
+PCI: 00:18.0 io: base: 4080 size: 5000 align: 12 gran: 12 limit: ffff done
+PCI: 00:18.0 10000 *  [0x0 - 0x4fff] io
+DOMAIN: 0000 io: base: 5000 size: 5000 align: 12 gran: 0 limit: ffff done
+DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
+PCI: 00:18.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
+PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 01:04.0 10 *  [0x0 - 0x3ffffff] prefmem
+PCI: 00:09.0 prefmem: base: 4000000 size: 4000000 align: 26 gran: 20 limit: ffffffff done
+PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:0e.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 05:00.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 06:00.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 06:00.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 06:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 06:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 05:00.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:0e.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:09.0 24 *  [0x0 - 0x3ffffff] prefmem
+PCI: 00:18.0 prefmem: base: 4000000 size: 4000000 align: 26 gran: 20 limit: ffffffff done
+PCI: 00:18.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 00:09.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 01:04.0 14 *  [0x0 - 0x3ffff] mem
+PCI: 00:09.0 mem: base: 40000 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 02:00.0 10 *  [0x0 - 0xffff] mem
+PCI: 00:0b.0 mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 03:00.0 10 *  [0x0 - 0xffff] mem
+PCI: 00:0c.0 mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:0e.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 05:00.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 06:00.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 07:00.0 10 *  [0x0 - 0x1ffff] mem
+PCI: 07:00.0 14 *  [0x20000 - 0x3ffff] mem
+PCI: 07:00.0 30 *  [0x40000 - 0x5ffff] mem
+PCI: 07:00.1 10 *  [0x60000 - 0x7ffff] mem
+PCI: 07:00.1 14 *  [0x80000 - 0x9ffff] mem
+PCI: 07:00.1 30 *  [0xa0000 - 0xbffff] mem
+PCI: 06:00.0 mem: base: c0000 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 06:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 08:00.0 10 *  [0x0 - 0x1ffff] mem
+PCI: 08:00.0 14 *  [0x20000 - 0x3ffff] mem
+PCI: 08:00.0 30 *  [0x40000 - 0x5ffff] mem
+PCI: 08:00.1 10 *  [0x60000 - 0x7ffff] mem
+PCI: 08:00.1 14 *  [0x80000 - 0x9ffff] mem
+PCI: 08:00.1 30 *  [0xa0000 - 0xbffff] mem
+PCI: 06:01.0 mem: base: c0000 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 06:00.0 20 *  [0x0 - 0xfffff] mem
+PCI: 06:01.0 20 *  [0x100000 - 0x1fffff] mem
+PCI: 05:00.0 mem: base: 200000 size: 200000 align: 20 gran: 20 limit: ffffffff done
+PCI: 05:00.0 20 *  [0x0 - 0x1fffff] mem
+PCI: 00:0e.0 mem: base: 200000 size: 200000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:0e.0 20 *  [0x0 - 0x1fffff] mem
+PCI: 00:09.0 20 *  [0x200000 - 0x2fffff] mem
+PCI: 00:0b.0 20 *  [0x300000 - 0x3fffff] mem
+PCI: 00:0c.0 20 *  [0x400000 - 0x4fffff] mem
+PCI: 00:02.0 10 *  [0x500000 - 0x500fff] mem
+PCI: 00:07.0 24 *  [0x501000 - 0x501fff] mem
+PCI: 00:08.0 24 *  [0x502000 - 0x502fff] mem
+PCI: 00:02.1 10 *  [0x503000 - 0x5030ff] mem
+PCI: 00:18.0 mem: base: 503100 size: 600000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:18.0 10002 *  [0x0 - 0x3ffffff] prefmem
+PCI: 00:18.0 10001 *  [0x4000000 - 0x45fffff] mem
+DOMAIN: 0000 mem: base: 4600000 size: 4600000 align: 26 gran: 0 limit: ffffffff done
+avoid_fixed_resources: DOMAIN: 0000
+avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
+avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
+constrain_resources: PCI: 00:18.0 10004 base 000a0000 limit 000bffff mem (fixed)
+constrain_resources: PCI: 00:01.0 14 base fec00000 limit fec00fff mem (fixed)
+constrain_resources: PCI: 00:01.0 10000000 base 00000000 limit 00000fff io (fixed)
+avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff
+avoid_fixed_resources:@DOMAIN: 0000 10000100 base f8000000 limit febfffff
+Setting resources...
+DOMAIN: 0000 io: base:1000 size:5000 align:12 gran:0 limit:ffff
+PCI: 00:18.0 10000 *  [0x1000 - 0x5fff] io
+DOMAIN: 0000 io: next_base: 6000 size: 5000 align: 12 gran: 0 done
+PCI: 00:18.0 io: base:1000 size:5000 align:12 gran:12 limit:5fff
+PCI: 00:0e.0 1c *  [0x1000 - 0x2fff] io
+PCI: 00:09.0 1c *  [0x3000 - 0x3fff] io
+PCI: 00:01.0 60 *  [0x4000 - 0x40ff] io
+PCI: 00:01.0 64 *  [0x4400 - 0x44ff] io
+PCI: 00:01.0 68 *  [0x4800 - 0x48ff] io
+PCI: 00:01.0 10 *  [0x4c00 - 0x4c7f] io
+PCI: 00:01.1 20 *  [0x4c80 - 0x4cbf] io
+PCI: 00:01.1 24 *  [0x4cc0 - 0x4cff] io
+PCI: 00:01.1 10 *  [0x5000 - 0x501f] io
+PCI: 00:06.0 20 *  [0x5020 - 0x502f] io
+PCI: 00:07.0 20 *  [0x5030 - 0x503f] io
+PCI: 00:08.0 20 *  [0x5040 - 0x504f] io
+PCI: 00:07.0 10 *  [0x5050 - 0x5057] io
+PCI: 00:07.0 18 *  [0x5058 - 0x505f] io
+PCI: 00:08.0 10 *  [0x5060 - 0x5067] io
+PCI: 00:08.0 18 *  [0x5068 - 0x506f] io
+PCI: 00:07.0 14 *  [0x5070 - 0x5073] io
+PCI: 00:07.0 1c *  [0x5074 - 0x5077] io
+PCI: 00:08.0 14 *  [0x5078 - 0x507b] io
+PCI: 00:08.0 1c *  [0x507c - 0x507f] io
+PCI: 00:18.0 io: next_base: 5080 size: 5000 align: 12 gran: 12 done
+PCI: 00:09.0 io: base:3000 size:1000 align:12 gran:12 limit:3fff
+PCI: 01:04.0 18 *  [0x3000 - 0x307f] io
+PCI: 00:09.0 io: next_base: 3080 size: 1000 align: 12 gran: 12 done
+PCI: 00:0b.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
+PCI: 00:0b.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
+PCI: 00:0c.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
+PCI: 00:0c.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
+PCI: 00:0d.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
+PCI: 00:0d.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
+PCI: 00:0e.0 io: base:1000 size:2000 align:12 gran:12 limit:2fff
+PCI: 05:00.0 1c *  [0x1000 - 0x2fff] io
+PCI: 00:0e.0 io: next_base: 3000 size: 2000 align: 12 gran: 12 done
+PCI: 05:00.0 io: base:1000 size:2000 align:12 gran:12 limit:2fff
+PCI: 06:00.0 1c *  [0x1000 - 0x1fff] io
+PCI: 06:01.0 1c *  [0x2000 - 0x2fff] io
+PCI: 05:00.0 io: next_base: 3000 size: 2000 align: 12 gran: 12 done
+PCI: 06:00.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff
+PCI: 07:00.0 18 *  [0x1000 - 0x101f] io
+PCI: 07:00.1 18 *  [0x1020 - 0x103f] io
+PCI: 06:00.0 io: next_base: 1040 size: 1000 align: 12 gran: 12 done
+PCI: 06:01.0 io: base:2000 size:1000 align:12 gran:12 limit:2fff
+PCI: 08:00.0 18 *  [0x2000 - 0x201f] io
+PCI: 08:00.1 18 *  [0x2020 - 0x203f] io
+PCI: 06:01.0 io: next_base: 2040 size: 1000 align: 12 gran: 12 done
+DOMAIN: 0000 mem: base:f8000000 size:4600000 align:26 gran:0 limit:febfffff
+PCI: 00:18.0 10002 *  [0xf8000000 - 0xfbffffff] prefmem
+PCI: 00:18.0 10001 *  [0xfc000000 - 0xfc5fffff] mem
+DOMAIN: 0000 mem: next_base: fc600000 size: 4600000 align: 26 gran: 0 done
+PCI: 00:18.0 prefmem: base:f8000000 size:4000000 align:26 gran:20 limit:fbffffff
+PCI: 00:09.0 24 *  [0xf8000000 - 0xfbffffff] prefmem
+PCI: 00:18.0 prefmem: next_base: fc000000 size: 4000000 align: 26 gran: 20 done
+PCI: 00:09.0 prefmem: base:f8000000 size:4000000 align:26 gran:20 limit:fbffffff
+PCI: 01:04.0 10 *  [0xf8000000 - 0xfbffffff] prefmem
+PCI: 00:09.0 prefmem: next_base: fc000000 size: 4000000 align: 26 gran: 20 done
+PCI: 00:0b.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff
+PCI: 00:0b.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done
+PCI: 00:0c.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff
+PCI: 00:0c.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done
+PCI: 00:0d.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff
+PCI: 00:0d.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done
+PCI: 00:0e.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff
+PCI: 00:0e.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done
+PCI: 05:00.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff
+PCI: 05:00.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done
+PCI: 06:00.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff
+PCI: 06:00.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done
+PCI: 06:01.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff
+PCI: 06:01.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done
+PCI: 00:18.0 mem: base:fc000000 size:600000 align:20 gran:20 limit:fc5fffff
+PCI: 00:0e.0 20 *  [0xfc000000 - 0xfc1fffff] mem
+PCI: 00:09.0 20 *  [0xfc200000 - 0xfc2fffff] mem
+PCI: 00:0b.0 20 *  [0xfc300000 - 0xfc3fffff] mem
+PCI: 00:0c.0 20 *  [0xfc400000 - 0xfc4fffff] mem
+PCI: 00:02.0 10 *  [0xfc500000 - 0xfc500fff] mem
+PCI: 00:07.0 24 *  [0xfc501000 - 0xfc501fff] mem
+PCI: 00:08.0 24 *  [0xfc502000 - 0xfc502fff] mem
+PCI: 00:02.1 10 *  [0xfc503000 - 0xfc5030ff] mem
+PCI: 00:18.0 mem: next_base: fc503100 size: 600000 align: 20 gran: 20 done
+PCI: 00:09.0 mem: base:fc200000 size:100000 align:20 gran:20 limit:fc2fffff
+PCI: 01:04.0 14 *  [0xfc200000 - 0xfc23ffff] mem
+PCI: 00:09.0 mem: next_base: fc240000 size: 100000 align: 20 gran: 20 done
+PCI: 00:0b.0 mem: base:fc300000 size:100000 align:20 gran:20 limit:fc3fffff
+PCI: 02:00.0 10 *  [0xfc300000 - 0xfc30ffff] mem
+PCI: 00:0b.0 mem: next_base: fc310000 size: 100000 align: 20 gran: 20 done
+PCI: 00:0c.0 mem: base:fc400000 size:100000 align:20 gran:20 limit:fc4fffff
+PCI: 03:00.0 10 *  [0xfc400000 - 0xfc40ffff] mem
+PCI: 00:0c.0 mem: next_base: fc410000 size: 100000 align: 20 gran: 20 done
+PCI: 00:0d.0 mem: base:fc5fffff size:0 align:20 gran:20 limit:fc5fffff
+PCI: 00:0d.0 mem: next_base: fc5fffff size: 0 align: 20 gran: 20 done
+PCI: 00:0e.0 mem: base:fc000000 size:200000 align:20 gran:20 limit:fc1fffff
+PCI: 05:00.0 20 *  [0xfc000000 - 0xfc1fffff] mem
+PCI: 00:0e.0 mem: next_base: fc200000 size: 200000 align: 20 gran: 20 done
+PCI: 05:00.0 mem: base:fc000000 size:200000 align:20 gran:20 limit:fc1fffff
+PCI: 06:00.0 20 *  [0xfc000000 - 0xfc0fffff] mem
+PCI: 06:01.0 20 *  [0xfc100000 - 0xfc1fffff] mem
+PCI: 05:00.0 mem: next_base: fc200000 size: 200000 align: 20 gran: 20 done
+PCI: 06:00.0 mem: base:fc000000 size:100000 align:20 gran:20 limit:fc0fffff
+PCI: 07:00.0 10 *  [0xfc000000 - 0xfc01ffff] mem
+PCI: 07:00.0 14 *  [0xfc020000 - 0xfc03ffff] mem
+PCI: 07:00.0 30 *  [0xfc040000 - 0xfc05ffff] mem
+PCI: 07:00.1 10 *  [0xfc060000 - 0xfc07ffff] mem
+PCI: 07:00.1 14 *  [0xfc080000 - 0xfc09ffff] mem
+PCI: 07:00.1 30 *  [0xfc0a0000 - 0xfc0bffff] mem
+PCI: 06:00.0 mem: next_base: fc0c0000 size: 100000 align: 20 gran: 20 done
+PCI: 06:01.0 mem: base:fc100000 size:100000 align:20 gran:20 limit:fc1fffff
+PCI: 08:00.0 10 *  [0xfc100000 - 0xfc11ffff] mem
+PCI: 08:00.0 14 *  [0xfc120000 - 0xfc13ffff] mem
+PCI: 08:00.0 30 *  [0xfc140000 - 0xfc15ffff] mem
+PCI: 08:00.1 10 *  [0xfc160000 - 0xfc17ffff] mem
+PCI: 08:00.1 14 *  [0xfc180000 - 0xfc19ffff] mem
+PCI: 08:00.1 30 *  [0xfc1a0000 - 0xfc1bffff] mem
+PCI: 06:01.0 mem: next_base: fc1c0000 size: 100000 align: 20 gran: 20 done
+Root Device assign_resources, bus 0 link: 0
+0: mmio_basek=00300000, basek=00400000, limitk=00500000
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0 link 0x1
+PCI: 00:18.0 101c0 <- [0x0000001000 - 0x0000005fff] size 0x00005000 gran 0x0c io <node 0 link 1>
+PCI: 00:18.0 101b8 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x14 prefmem <node 0 link 1>
+PCI: 00:18.0 101b0 <- [0x00fc000000 - 0x00fc5fffff] size 0x00600000 gran 0x14 mem <node 0 link 1>
+PCI: 00:18.0 101a8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem <node 0 link 1>
+PCI: 00:18.0 assign_resources, bus 0 link: 1
+PCI: 00:01.0 10 <- [0x0000004c00 - 0x0000004c7f] size 0x00000080 gran 0x07 io
+PCI: 00:01.0 60 <- [0x0000004000 - 0x00000040ff] size 0x00000100 gran 0x08 io
+PCI: 00:01.0 64 <- [0x0000004400 - 0x00000044ff] size 0x00000100 gran 0x08 io
+PCI: 00:01.0 68 <- [0x0000004800 - 0x00000048ff] size 0x00000100 gran 0x08 io
+PCI: 00:01.0 assign_resources, bus 0 link: 0
+PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io
+PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq
+PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq
+PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
+PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
+PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
+PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
+PNP: 002e.3 f1 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 io
+PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
+PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
+PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
+PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
+ERROR: PNP: 002e.5 f0 irq size: 0x0000000001 not assigned
+ERROR: PNP: 002e.9 30 irq size: 0x0000000001 not assigned
+ERROR: PNP: 002e.9 f0 irq size: 0x0000000001 not assigned
+ERROR: PNP: 002e.9 f1 irq size: 0x0000000001 not assigned
+PNP: 002e.b 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io
+PNP: 002e.b 70 <- [0x0000000005 - 0x0000000005] size 0x00000001 gran 0x00 irq
+PCI: 00:01.0 assign_resources, bus 0 link: 0
+PCI: 00:01.0 14 <- [0x00fec00000 - 0x00fec00fff] size 0x00001000 gran 0x0c mem
+PCI: 00:01.0 44 <- [0x00fed00000 - 0x00fed00fff] size 0x00001000 gran 0x0c mem
+PCI: 00:01.1 10 <- [0x0000005000 - 0x000000501f] size 0x00000020 gran 0x05 io
+PCI: 00:01.1 20 <- [0x0000004c80 - 0x0000004cbf] size 0x00000040 gran 0x06 io
+PCI: 00:01.1 24 <- [0x0000004cc0 - 0x0000004cff] size 0x00000040 gran 0x06 io
+PCI: 00:01.1 assign_resources, bus 1 link: 0
+PCI: 00:01.1 assign_resources, bus 1 link: 0
+PCI: 00:02.0 10 <- [0x00fc500000 - 0x00fc500fff] size 0x00001000 gran 0x0c mem
+PCI: 00:02.1 10 <- [0x00fc503000 - 0x00fc5030ff] size 0x00000100 gran 0x08 mem
+PCI: 00:06.0 20 <- [0x0000005020 - 0x000000502f] size 0x00000010 gran 0x04 io
+PCI: 00:07.0 10 <- [0x0000005050 - 0x0000005057] size 0x00000008 gran 0x03 io
+PCI: 00:07.0 14 <- [0x0000005070 - 0x0000005073] size 0x00000004 gran 0x02 io
+PCI: 00:07.0 18 <- [0x0000005058 - 0x000000505f] size 0x00000008 gran 0x03 io
+PCI: 00:07.0 1c <- [0x0000005074 - 0x0000005077] size 0x00000004 gran 0x02 io
+PCI: 00:07.0 20 <- [0x0000005030 - 0x000000503f] size 0x00000010 gran 0x04 io
+PCI: 00:07.0 24 <- [0x00fc501000 - 0x00fc501fff] size 0x00001000 gran 0x0c mem
+PCI: 00:08.0 10 <- [0x0000005060 - 0x0000005067] size 0x00000008 gran 0x03 io
+PCI: 00:08.0 14 <- [0x0000005078 - 0x000000507b] size 0x00000004 gran 0x02 io
+PCI: 00:08.0 18 <- [0x0000005068 - 0x000000506f] size 0x00000008 gran 0x03 io
+PCI: 00:08.0 1c <- [0x000000507c - 0x000000507f] size 0x00000004 gran 0x02 io
+PCI: 00:08.0 20 <- [0x0000005040 - 0x000000504f] size 0x00000010 gran 0x04 io
+PCI: 00:08.0 24 <- [0x00fc502000 - 0x00fc502fff] size 0x00001000 gran 0x0c mem
+PCI: 00:09.0 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 01 io
+PCI: 00:09.0 24 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x14 bus 01 prefmem
+PCI: 00:09.0 20 <- [0x00fc200000 - 0x00fc2fffff] size 0x00100000 gran 0x14 bus 01 mem
+PCI: 00:09.0 assign_resources, bus 1 link: 0
+PCI: 01:04.0 10 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a prefmem
+PCI: 01:04.0 14 <- [0x00fc200000 - 0x00fc23ffff] size 0x00040000 gran 0x12 mem
+PCI: 01:04.0 18 <- [0x0000003000 - 0x000000307f] size 0x00000080 gran 0x07 io
+PCI: 00:09.0 assign_resources, bus 1 link: 0
+PCI: 00:0b.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 02 io
+PCI: 00:0b.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 02 prefmem
+PCI: 00:0b.0 20 <- [0x00fc300000 - 0x00fc3fffff] size 0x00100000 gran 0x14 bus 02 mem
+PCI: 00:0b.0 assign_resources, bus 2 link: 0
+PCI: 02:00.0 10 <- [0x00fc300000 - 0x00fc30ffff] size 0x00010000 gran 0x10 mem64
+PCI: 00:0b.0 assign_resources, bus 2 link: 0
+PCI: 00:0c.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 03 io
+PCI: 00:0c.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 03 prefmem
+PCI: 00:0c.0 20 <- [0x00fc400000 - 0x00fc4fffff] size 0x00100000 gran 0x14 bus 03 mem
+PCI: 00:0c.0 assign_resources, bus 3 link: 0
+PCI: 03:00.0 10 <- [0x00fc400000 - 0x00fc40ffff] size 0x00010000 gran 0x10 mem64
+PCI: 00:0c.0 assign_resources, bus 3 link: 0
+PCI: 00:0d.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 04 io
+PCI: 00:0d.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 04 prefmem
+PCI: 00:0d.0 20 <- [0x00fc5fffff - 0x00fc5ffffe] size 0x00000000 gran 0x14 bus 04 mem
+PCI: 00:0d.0 assign_resources, bus 4 link: 0
+PCI: 00:0d.0 assign_resources, bus 4 link: 0
+PCI: 00:0e.0 1c <- [0x0000001000 - 0x0000002fff] size 0x00002000 gran 0x0c bus 05 io
+PCI: 00:0e.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 05 prefmem
+PCI: 00:0e.0 20 <- [0x00fc000000 - 0x00fc1fffff] size 0x00200000 gran 0x14 bus 05 mem
+PCI: 00:0e.0 assign_resources, bus 5 link: 0
+PCI: 05:00.0 1c <- [0x0000001000 - 0x0000002fff] size 0x00002000 gran 0x0c bus 06 io
+PCI: 05:00.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 06 prefmem
+PCI: 05:00.0 20 <- [0x00fc000000 - 0x00fc1fffff] size 0x00200000 gran 0x14 bus 06 mem
+PCI: 05:00.0 assign_resources, bus 6 link: 0
+PCI: 06:00.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 07 io
+PCI: 06:00.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 07 prefmem
+PCI: 06:00.0 20 <- [0x00fc000000 - 0x00fc0fffff] size 0x00100000 gran 0x14 bus 07 mem
+PCI: 06:00.0 assign_resources, bus 7 link: 0
+PCI: 07:00.0 10 <- [0x00fc000000 - 0x00fc01ffff] size 0x00020000 gran 0x11 mem
+PCI: 07:00.0 14 <- [0x00fc020000 - 0x00fc03ffff] size 0x00020000 gran 0x11 mem
+PCI: 07:00.0 18 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io
+PCI: 07:00.0 30 <- [0x00fc040000 - 0x00fc05ffff] size 0x00020000 gran 0x11 romem
+PCI: 07:00.1 10 <- [0x00fc060000 - 0x00fc07ffff] size 0x00020000 gran 0x11 mem
+PCI: 07:00.1 14 <- [0x00fc080000 - 0x00fc09ffff] size 0x00020000 gran 0x11 mem
+PCI: 07:00.1 18 <- [0x0000001020 - 0x000000103f] size 0x00000020 gran 0x05 io
+PCI: 07:00.1 30 <- [0x00fc0a0000 - 0x00fc0bffff] size 0x00020000 gran 0x11 romem
+PCI: 06:00.0 assign_resources, bus 7 link: 0
+PCI: 06:01.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 08 io
+PCI: 06:01.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 08 prefmem
+PCI: 06:01.0 20 <- [0x00fc100000 - 0x00fc1fffff] size 0x00100000 gran 0x14 bus 08 mem
+PCI: 06:01.0 assign_resources, bus 8 link: 0
+PCI: 08:00.0 10 <- [0x00fc100000 - 0x00fc11ffff] size 0x00020000 gran 0x11 mem
+PCI: 08:00.0 14 <- [0x00fc120000 - 0x00fc13ffff] size 0x00020000 gran 0x11 mem
+PCI: 08:00.0 18 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io
+PCI: 08:00.0 30 <- [0x00fc140000 - 0x00fc15ffff] size 0x00020000 gran 0x11 romem
+PCI: 08:00.1 10 <- [0x00fc160000 - 0x00fc17ffff] size 0x00020000 gran 0x11 mem
+PCI: 08:00.1 14 <- [0x00fc180000 - 0x00fc19ffff] size 0x00020000 gran 0x11 mem
+PCI: 08:00.1 18 <- [0x0000002020 - 0x000000203f] size 0x00000020 gran 0x05 io
+PCI: 08:00.1 30 <- [0x00fc1a0000 - 0x00fc1bffff] size 0x00020000 gran 0x11 romem
+PCI: 06:01.0 assign_resources, bus 8 link: 0
+PCI: 05:00.0 assign_resources, bus 6 link: 0
+PCI: 00:0e.0 assign_resources, bus 5 link: 0
+PCI: 00:18.0 assign_resources, bus 0 link: 1
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+Root Device assign_resources, bus 0 link: 0
+Done setting resources.
+Show resources in subtree (Root Device)...After assigning values.
+ Root Device child on link 0 CPU_CLUSTER: 0
+  CPU_CLUSTER: 0 child on link 0 APIC: 10
+   APIC: 10
+   APIC: 11
+   APIC: 12
+   APIC: 13
+  DOMAIN: 0000 child on link 0 PCI: 00:18.0
+  DOMAIN: 0000 resource base 1000 size 5000 align 12 gran 0 limit ffff flags 40040100 index 10000000
+  DOMAIN: 0000 resource base f8000000 size 4600000 align 26 gran 0 limit febfffff flags 40040200 index 10000100
+  DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
+  DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20
+  DOMAIN: 0000 resource base 100000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 30
+   PCI: 00:18.0 child on link 0 PCI: 00:00.0
+   PCI: 00:18.0 resource base 1000 size 5000 align 12 gran 12 limit 5fff flags 60080100 index 101c0
+   PCI: 00:18.0 resource base f8000000 size 4000000 align 26 gran 20 limit fbffffff flags 60081200 index 101b8
+   PCI: 00:18.0 resource base fc000000 size 600000 align 20 gran 20 limit fc5fffff flags 60080200 index 101b0
+   PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags e0000200 index 101a8
+    PCI: 00:00.0
+    PCI: 00:01.0 child on link 0 PNP: 002e.0
+    PCI: 00:01.0 resource base 4c00 size 80 align 7 gran 7 limit 4c7f flags 60000100 index 10
+    PCI: 00:01.0 resource base fec00000 size 1000 align 12 gran 12 limit ffffffff flags e0000200 index 14
+    PCI: 00:01.0 resource base fed00000 size 1000 align 12 gran 12 limit ffffffff flags e0000200 index 44
+    PCI: 00:01.0 resource base 4000 size 100 align 8 gran 8 limit 40ff flags 60000100 index 60
+    PCI: 00:01.0 resource base 4400 size 100 align 8 gran 8 limit 44ff flags 60000100 index 64
+    PCI: 00:01.0 resource base 4800 size 100 align 8 gran 8 limit 48ff flags 60000100 index 68
+    PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+    PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+     PNP: 002e.0
+     PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
+     PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+     PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74
+     PNP: 002e.1
+     PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
+     PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+     PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
+     PNP: 002e.2
+     PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
+     PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+     PNP: 002e.3
+     PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
+     PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+     PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000500 index f1
+     PNP: 002e.5
+     PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
+     PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
+     PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+     PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72
+     PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f0
+     PNP: 002e.7
+     PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
+     PNP: 002e.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62
+     PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+     PNP: 002e.8
+     PNP: 002e.9
+     PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 30
+     PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f0
+     PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f1
+     PNP: 002e.a
+     PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+     PNP: 002e.b
+     PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags e0000100 index 60
+     PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+    PCI: 00:01.1 child on link 0 I2C: 01:50
+    PCI: 00:01.1 resource base 5000 size 20 align 5 gran 5 limit 501f flags 60000100 index 10
+    PCI: 00:01.1 resource base 4c80 size 40 align 6 gran 6 limit 4cbf flags 60000100 index 20
+    PCI: 00:01.1 resource base 4cc0 size 40 align 6 gran 6 limit 4cff flags 60000100 index 24
+     I2C: 01:50
+     I2C: 01:51
+     I2C: 01:52
+     I2C: 01:53
+     I2C: 01:54
+     I2C: 01:55
+     I2C: 01:56
+     I2C: 01:57
+     I2C: 01:2f
+    PCI: 00:02.0
+    PCI: 00:02.0 resource base fc500000 size 1000 align 12 gran 12 limit fc500fff flags 60000200 index 10
+    PCI: 00:02.1
+    PCI: 00:02.1 resource base fc503000 size 100 align 12 gran 8 limit fc5030ff flags 60000200 index 10
+    PCI: 00:04.0
+    PCI: 00:04.1
+    PCI: 00:06.0
+    PCI: 00:06.0 resource base 5020 size 10 align 4 gran 4 limit 502f flags 60000100 index 20
+    PCI: 00:07.0
+    PCI: 00:07.0 resource base 5050 size 8 align 3 gran 3 limit 5057 flags 60000100 index 10
+    PCI: 00:07.0 resource base 5070 size 4 align 2 gran 2 limit 5073 flags 60000100 index 14
+    PCI: 00:07.0 resource base 5058 size 8 align 3 gran 3 limit 505f flags 60000100 index 18
+    PCI: 00:07.0 resource base 5074 size 4 align 2 gran 2 limit 5077 flags 60000100 index 1c
+    PCI: 00:07.0 resource base 5030 size 10 align 4 gran 4 limit 503f flags 60000100 index 20
+    PCI: 00:07.0 resource base fc501000 size 1000 align 12 gran 12 limit fc501fff flags 60000200 index 24
+    PCI: 00:08.0
+    PCI: 00:08.0 resource base 5060 size 8 align 3 gran 3 limit 5067 flags 60000100 index 10
+    PCI: 00:08.0 resource base 5078 size 4 align 2 gran 2 limit 507b flags 60000100 index 14
+    PCI: 00:08.0 resource base 5068 size 8 align 3 gran 3 limit 506f flags 60000100 index 18
+    PCI: 00:08.0 resource base 507c size 4 align 2 gran 2 limit 507f flags 60000100 index 1c
+    PCI: 00:08.0 resource base 5040 size 10 align 4 gran 4 limit 504f flags 60000100 index 20
+    PCI: 00:08.0 resource base fc502000 size 1000 align 12 gran 12 limit fc502fff flags 60000200 index 24
+    PCI: 00:09.0 child on link 0 PCI: 01:04.0
+    PCI: 00:09.0 resource base 3000 size 1000 align 12 gran 12 limit 3fff flags 60080102 index 1c
+    PCI: 00:09.0 resource base f8000000 size 4000000 align 26 gran 20 limit fbffffff flags 60081202 index 24
+    PCI: 00:09.0 resource base fc200000 size 100000 align 20 gran 20 limit fc2fffff flags 60080202 index 20
+     PCI: 01:04.0
+     PCI: 01:04.0 resource base f8000000 size 4000000 align 26 gran 26 limit fbffffff flags 60001200 index 10
+     PCI: 01:04.0 resource base fc200000 size 40000 align 18 gran 18 limit fc23ffff flags 60000200 index 14
+     PCI: 01:04.0 resource base 3000 size 80 align 7 gran 7 limit 307f flags 60000100 index 18
+     PCI: 01:04.0 resource base a0000 size 1fc00 align 0 gran 0 limit 0 flags f0000200 index 3
+    PCI: 00:0a.0
+    PCI: 00:0b.0 child on link 0 PCI: 02:00.0
+    PCI: 00:0b.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
+    PCI: 00:0b.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24
+    PCI: 00:0b.0 resource base fc300000 size 100000 align 20 gran 20 limit fc3fffff flags 60080202 index 20
+     PCI: 02:00.0
+     PCI: 02:00.0 resource base fc300000 size 10000 align 16 gran 16 limit fc30ffff flags 60000201 index 10
+    PCI: 00:0c.0 child on link 0 PCI: 03:00.0
+    PCI: 00:0c.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
+    PCI: 00:0c.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24
+    PCI: 00:0c.0 resource base fc400000 size 100000 align 20 gran 20 limit fc4fffff flags 60080202 index 20
+     PCI: 03:00.0
+     PCI: 03:00.0 resource base fc400000 size 10000 align 16 gran 16 limit fc40ffff flags 60000201 index 10
+    PCI: 00:0d.0 child on link 0 PCI: 04:00.0
+    PCI: 00:0d.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
+    PCI: 00:0d.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24
+    PCI: 00:0d.0 resource base fc5fffff size 0 align 20 gran 20 limit fc5fffff flags 60080202 index 20
+     PCI: 04:00.0
+    PCI: 00:0e.0 child on link 0 PCI: 05:00.0
+    PCI: 00:0e.0 resource base 1000 size 2000 align 12 gran 12 limit 2fff flags 60080102 index 1c
+    PCI: 00:0e.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24
+    PCI: 00:0e.0 resource base fc000000 size 200000 align 20 gran 20 limit fc1fffff flags 60080202 index 20
+     PCI: 05:00.0 child on link 0 PCI: 06:00.0
+     PCI: 05:00.0 resource base 1000 size 2000 align 12 gran 12 limit 2fff flags 60080102 index 1c
+     PCI: 05:00.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24
+     PCI: 05:00.0 resource base fc000000 size 200000 align 20 gran 20 limit fc1fffff flags 60080202 index 20
+      PCI: 06:00.0 child on link 0 PCI: 07:00.0
+      PCI: 06:00.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c
+      PCI: 06:00.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24
+      PCI: 06:00.0 resource base fc000000 size 100000 align 20 gran 20 limit fc0fffff flags 60080202 index 20
+       PCI: 07:00.0
+       PCI: 07:00.0 resource base fc000000 size 20000 align 17 gran 17 limit fc01ffff flags 60000200 index 10
+       PCI: 07:00.0 resource base fc020000 size 20000 align 17 gran 17 limit fc03ffff flags 60000200 index 14
+       PCI: 07:00.0 resource base 1000 size 20 align 5 gran 5 limit 101f flags 60000100 index 18
+       PCI: 07:00.0 resource base fc040000 size 20000 align 17 gran 17 limit fc05ffff flags 60002200 index 30
+       PCI: 07:00.1
+       PCI: 07:00.1 resource base fc060000 size 20000 align 17 gran 17 limit fc07ffff flags 60000200 index 10
+       PCI: 07:00.1 resource base fc080000 size 20000 align 17 gran 17 limit fc09ffff flags 60000200 index 14
+       PCI: 07:00.1 resource base 1020 size 20 align 5 gran 5 limit 103f flags 60000100 index 18
+       PCI: 07:00.1 resource base fc0a0000 size 20000 align 17 gran 17 limit fc0bffff flags 60002200 index 30
+      PCI: 06:01.0 child on link 0 PCI: 08:00.0
+      PCI: 06:01.0 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c
+      PCI: 06:01.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24
+      PCI: 06:01.0 resource base fc100000 size 100000 align 20 gran 20 limit fc1fffff flags 60080202 index 20
+       PCI: 08:00.0
+       PCI: 08:00.0 resource base fc100000 size 20000 align 17 gran 17 limit fc11ffff flags 60000200 index 10
+       PCI: 08:00.0 resource base fc120000 size 20000 align 17 gran 17 limit fc13ffff flags 60000200 index 14
+       PCI: 08:00.0 resource base 2000 size 20 align 5 gran 5 limit 201f flags 60000100 index 18
+       PCI: 08:00.0 resource base fc140000 size 20000 align 17 gran 17 limit fc15ffff flags 60002200 index 30
+       PCI: 08:00.1
+       PCI: 08:00.1 resource base fc160000 size 20000 align 17 gran 17 limit fc17ffff flags 60000200 index 10
+       PCI: 08:00.1 resource base fc180000 size 20000 align 17 gran 17 limit fc19ffff flags 60000200 index 14
+       PCI: 08:00.1 resource base 2020 size 20 align 5 gran 5 limit 203f flags 60000100 index 18
+       PCI: 08:00.1 resource base fc1a0000 size 20000 align 17 gran 17 limit fc1bffff flags 60002200 index 30
+    PCI: 00:0f.0
+   PCI: 00:18.1
+   PCI: 00:18.2
+   PCI: 00:18.3
+   PCI: 00:18.4
+   PCI: 00:19.0
+   PCI: 00:19.1
+   PCI: 00:19.2
+   PCI: 00:19.3
+   PCI: 00:19.4
+Done allocating resources.
+POST: 0x74
+Enabling resources...
+PCI: 00:18.0 cmd <- 00
+PCI: 00:18.1 subsystem <- 1043/8162
+PCI: 00:18.1 cmd <- 00
+PCI: 00:18.2 subsystem <- 1043/8162
+PCI: 00:18.2 cmd <- 00
+PCI: 00:18.3 cmd <- 00
+PCI: 00:19.0 cmd <- 00
+PCI: 00:19.1 subsystem <- 1043/8162
+PCI: 00:19.1 cmd <- 00
+PCI: 00:19.2 subsystem <- 1043/8162
+PCI: 00:19.2 cmd <- 00
+PCI: 00:19.3 cmd <- 00
+PCI: 00:00.0 subsystem <- 1043/8162
+PCI: 00:00.0 cmd <- 06
+PCI: 00:01.0 subsystem <- 1043/8162
+PCI: 00:01.0 cmd <- 0f
+ck804 lpc decode:PNP: 002e.0, base=0x000003f0, end=0x000003f7
+ck804 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff
+ck804 lpc decode:PNP: 002e.3, base=0x000002f8, end=0x000002ff
+ck804 lpc decode:PNP: 002e.3, base=0x00000004, end=0x00000004
+ck804 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060
+ck804 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064
+ck804 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000297
+PCI: 00:01.1 subsystem <- 1043/8162
+PCI: 00:01.1 cmd <- 01
+PCI: 00:02.0 subsystem <- 1043/8162
+PCI: 00:02.0 cmd <- 02
+PCI: 00:02.1 subsystem <- 1043/8162
+PCI: 00:02.1 cmd <- 02
+PCI: 00:06.0 subsystem <- 1043/8162
+PCI: 00:06.0 cmd <- 01
+PCI: 00:07.0 subsystem <- 1043/8162
+PCI: 00:07.0 cmd <- 03
+PCI: 00:08.0 subsystem <- 1043/8162
+PCI: 00:08.0 cmd <- 03
+PCI: 00:09.0 bridge ctrl <- 000b
+PCI: 00:09.0 cmd <- 07
+PCI: 00:0b.0 bridge ctrl <- 0003
+PCI: 00:0b.0 cmd <- 06
+PCI: 00:0c.0 bridge ctrl <- 0003
+PCI: 00:0c.0 cmd <- 06
+PCI: 00:0d.0 bridge ctrl <- 0003
+PCI: 00:0d.0 cmd <- 00
+PCI: 00:0e.0 bridge ctrl <- 0003
+PCI: 00:0e.0 cmd <- 07
+PCI: 01:04.0 cmd <- 03
+PCI: 02:00.0 subsystem <- 1043/8162
+PCI: 02:00.0 cmd <- 02
+PCI: 03:00.0 subsystem <- 1043/8162
+PCI: 03:00.0 cmd <- 02
+PCI: 05:00.0 bridge ctrl <- 0003
+PCI: 05:00.0 cmd <- 07
+PCI: 06:00.0 bridge ctrl <- 0003
+PCI: 06:00.0 cmd <- 07
+PCI: 06:01.0 bridge ctrl <- 0003
+PCI: 06:01.0 cmd <- 07
+PCI: 07:00.0 cmd <- 03
+PCI: 07:00.1 cmd <- 03
+PCI: 08:00.0 cmd <- 03
+PCI: 08:00.1 cmd <- 03
+done.
+POST: 0x75
+Initializing devices...
+Root Device init ...
+POST: 0x75
+CPU_CLUSTER: 0 init ...
+start_eip=0x00001000, code_size=0x00000031
+CPU1: stack_base 00125000, stack_end 00125ff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 17.
+After apic_write.
+Initializing CPU #1
+CPU: vendor AMD device 40f13
+CPU: family 0f, model 41, stepping 03
+Startup point 1.
+Waiting for send to finish...
++POST: 0x60
+Enabling cache
+CPU ID 0x80000001: 40f13
+CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
+Sending STARTUP #2 to 17.
+After apic_write.
+MTRR: Physical address space:
+0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
+0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
+0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6
+0x00000000c0000000 - 0x00000000f8000000 size 0x38000000 type 0
+0x00000000f8000000 - 0x00000000fc000000 size 0x04000000 type 1
+0x00000000fc000000 - 0x0000000100000000 size 0x04000000 type 0
+0x0000000100000000 - 0x0000000140000000 size 0x40000000 type 6
+MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
+MTRR: default type WB/UC MTRR counts: 5/3.
+MTRR: UC selected as default type.
+MTRR: 0 base 0x0000000000000000 mask 0x000000ff80000000 type 6
+MTRR: 1 base 0x0000000080000000 mask 0x000000ffc0000000 type 6
+MTRR: 2 base 0x00000000f8000000 mask 0x000000fffc000000 type 1
+Startup point 1.
+Waiting for send to finish...
++
+MTRR check
+Fixed MTRRs   : Enabled
+Variable MTRRs: Enabled
+
+POST: 0x93
+CBFS @ 0 size ff480
+CBFS: Locating 'microcode_amd.bin'
+CBFS: Checking offset 0
+CBFS:  Unmatched 'cmos.default' at 0
+CBFS: Checking offset 140
+CBFS:  Unmatched 'cpu_microcode_blob.bin' at 140
+CBFS: Checking offset 19c0
+CBFS:  Unmatched 'cmos_layout.bin' at 19c0
+CBFS: Checking offset 2480
+After Startup.
+CPU2: stack_base 00124000, stack_end 00124ff8
+Asserting INIT.
+Waiting for send to finish...
++CBFS:  Unmatched 'fallback/dsdt.aml' at 2480
+CBFS: Checking offset 4b40
+CBFS:  Unmatched 'normal/dsdt.aml' at 4b40
+CBFS: Checking offset 71c0
+CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 71c0
+CBFS: Checking offset e240
+CBFS:  Unmatched 'config' at e240
+CBFS: Checking offset e540
+CBFS:  Unmatched 'revision' at e540
+CBFS: Checking offset e800
+CBFS:  Unmatched 'payload_config' at e800
+CBFS: Checking offset ee40
+CBFS:  Unmatched 'payload_revision' at ee40
+CBFS: Checking offset ef00
+CBFS:  Unmatched 'etc/pci-optionrom-exec' at ef00
+CBFS: Checking offset ef80
+CBFS:  Unmatched '' at ef80
+CBFS: Checking offset ff80
+CBFS:  Unmatched 'fallback/romstage' at ff80
+CBFS: Checking offset 1d080
+CBFS:  Unmatched 'fallback/ramstage' at 1d080
+CBFS: Checking offset 2ca80
+CBFS:  Unmatched 'fallback/payload' at 2ca80
+CBFS: Checking offset 3a540
+CBFS:  Unmatched 'pci14e4,1659.rom' at 3a540
+CBFS: Checking offset 4b5c0
+CBFS:  Unmatched '' at 4b5c0
+CBFS: Checking offset 4ff80
+CBFS:  Unmatched 'normal/romstage' at 4ff80
+CBFS: Checking offset 5cf40
+CBFS:  Unmatched 'normal/ramstage' at 5cf40
+CBFS: Checking offset 6c7c0
+CBFS:  Unmatched 'normal/payload' at 6c7c0
+CBFS: Checking offset 79f80
+CBFS:  Unmatched 'bootsplash.jpg' at 79f80
+CBFS: Checking offset 810c0
+CBFS:  Unmatched '' at 810c0
+CBFS: Checking offset ff480
+CBFS: 'microcode_amd.bin' not found.
+[microcode] microcode file not found. Skipping updates.
+CPU model Dual-Core AMD Opteron(tm) Processor 8222
+Setting up local apic... apic_id: 0x11 done.
+POST: 0x9b
+siblings = 01, CPU #1 initialized
+Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 18.
+After apic_write.
+Initializing CPU #2
+CPU: vendor AMD device 40f13
+CPU: family 0f, model 41, stepping 03
+Startup point 1.
+Waiting for send to finish...
++POST: 0x60
+Enabling cache
+CPU ID 0x80000001: 40f13
+CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
+Sending STARTUP #2 to 18.
+After apic_write.
+MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
+Startup point 1.
+Waiting for send to finish...
++
+MTRR check
+Fixed MTRRs   : Enabled
+Variable MTRRs: Enabled
+
+POST: 0x93
+CBFS @ 0 size ff480
+CBFS: Locating 'microcode_amd.bin'
+CBFS: Checking offset 0
+CBFS:  Unmatched 'cmos.default' at 0
+CBFS: Checking offset 140
+CBFS:  Unmatched 'cpu_microcode_blob.bin' at 140
+CBFS: Checking offset 19c0
+CBFS:  Unmatched 'cmos_layout.bin' at 19c0
+CBFS: Checking offset 2480
+After Startup.
+CPU3: stack_base 00123000, stack_end 00123ff8
+Asserting INIT.
+Waiting for send to finish...
++CBFS:  Unmatched 'fallback/dsdt.aml' at 2480
+CBFS: Checking offset 4b40
+CBFS:  Unmatched 'normal/dsdt.aml' at 4b40
+CBFS: Checking offset 71c0
+CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 71c0
+CBFS: Checking offset e240
+CBFS:  Unmatched 'config' at e240
+CBFS: Checking offset e540
+CBFS:  Unmatched 'revision' at e540
+CBFS: Checking offset e800
+CBFS:  Unmatched 'payload_config' at e800
+CBFS: Checking offset ee40
+CBFS:  Unmatched 'payload_revision' at ee40
+CBFS: Checking offset ef00
+CBFS:  Unmatched 'etc/pci-optionrom-exec' at ef00
+CBFS: Checking offset ef80
+CBFS:  Unmatched '' at ef80
+CBFS: Checking offset ff80
+CBFS:  Unmatched 'fallback/romstage' at ff80
+CBFS: Checking offset 1d080
+CBFS:  Unmatched 'fallback/ramstage' at 1d080
+CBFS: Checking offset 2ca80
+CBFS:  Unmatched 'fallback/payload' at 2ca80
+CBFS: Checking offset 3a540
+CBFS:  Unmatched 'pci14e4,1659.rom' at 3a540
+CBFS: Checking offset 4b5c0
+CBFS:  Unmatched '' at 4b5c0
+CBFS: Checking offset 4ff80
+CBFS:  Unmatched 'normal/romstage' at 4ff80
+CBFS: Checking offset 5cf40
+CBFS:  Unmatched 'normal/ramstage' at 5cf40
+CBFS: Checking offset 6c7c0
+CBFS:  Unmatched 'normal/payload' at 6c7c0
+CBFS: Checking offset 79f80
+CBFS:  Unmatched 'bootsplash.jpg' at 79f80
+CBFS: Checking offset 810c0
+CBFS:  Unmatched '' at 810c0
+CBFS: Checking offset ff480
+CBFS: 'microcode_amd.bin' not found.
+[microcode] microcode file not found. Skipping updates.
+CPU model Dual-Core AMD Opteron(tm) Processor 8222
+Setting up local apic... apic_id: 0x12 done.
+POST: 0x9b
+siblings = 01, CBFS @ 0 size ff480
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Checking offset 0
+CBFS:  Unmatched 'cmos.default' at 0
+CBFS: Checking offset 140
+CBFS:  Unmatched 'cpu_microcode_blob.bin' at 140
+CBFS: Checking offset 19c0
+CBFS: Found @ offset 19c0 size a64
+ECC Disabled
+CPU #2 initialized
+Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 19.
+After apic_write.
+Initializing CPU #3
+CPU: vendor AMD device 40f13
+CPU: family 0f, model 41, stepping 03
+Startup point 1.
+Waiting for send to finish...
++POST: 0x60
+Enabling cache
+CPU ID 0x80000001: 40f13
+CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
+Sending STARTUP #2 to 19.
+After apic_write.
+MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
+Startup point 1.
+Waiting for send to finish...
++
+MTRR check
+Fixed MTRRs   : Enabled
+Variable MTRRs: Enabled
+
+POST: 0x93
+CBFS @ 0 size ff480
+CBFS: Locating 'microcode_amd.bin'
+CBFS: Checking offset 0
+CBFS:  Unmatched 'cmos.default' at 0
+CBFS: Checking offset 140
+CBFS:  Unmatched 'cpu_microcode_blob.bin' at 140
+CBFS: Checking offset 19c0
+CBFS:  Unmatched 'cmos_layout.bin' at 19c0
+CBFS: Checking offset 2480
+After Startup.
+Initializing CPU #0
+CPU: vendor AMD device 40f13
+CPU: family 0f, model 41, stepping 03
+POST: 0x60
+Enabling cache
+CBFS:  Unmatched 'fallback/dsdt.aml' at 2480
+CBFS: Checking offset 4b40
+CBFS:  Unmatched 'normal/dsdt.aml' at 4b40
+CBFS: Checking offset 71c0
+CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 71c0
+CBFS: Checking offset e240
+CBFS:  Unmatched 'config' at e240
+CBFS: Checking offset e540
+CPU ID 0x80000001: 40f13
+CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
+CBFS:  Unmatched 'revision' at e540
+CBFS: Checking offset e800
+CBFS:  Unmatched 'payload_config' at e800
+CBFS: Checking offset ee40
+CBFS:  Unmatched 'payload_revision' at ee40
+CBFS: Checking offset ef00
+MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
+MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
+CBFS:  Unmatched 'etc/pci-optionrom-exec' at ef00
+CBFS: Checking offset ef80
+CBFS:  Unmatched '' at ef80
+CBFS: Checking offset ff80
+CBFS:  Unmatched 'fallback/romstage' at ff80
+CBFS: Checking offset 1d080
+CBFS:  Unmatched 'fallback/ramstage' at 1d080
+CBFS: Checking offset 2ca80
+CBFS:  Unmatched 'fallback/payload' at 2ca80
+CBFS: Checking offset 3a540
+CBFS:  Unmatched 'pci14e4,1659.rom' at 3a540
+CBFS: Checking offset 4b5c0
+
+MTRR check
+Fixed MTRRs   : Enabled
+Variable MTRRs: Enabled
+
+POST: 0x93
+CBFS:  Unmatched '' at 4b5c0
+CBFS: Checking offset 4ff80
+CBFS @ 0 size ff480
+CBFS: Locating 'microcode_amd.bin'
+CBFS: Checking offset 0
+CBFS:  Unmatched 'normal/romstage' at 4ff80
+CBFS: Checking offset 5cf40
+CBFS:  Unmatched 'cmos.default' at 0
+CBFS: Checking offset 140
+CBFS:  Unmatched 'normal/ramstage' at 5cf40
+CBFS: Checking offset 6c7c0
+CBFS:  Unmatched 'cpu_microcode_blob.bin' at 140
+CBFS: Checking offset 19c0
+CBFS:  Unmatched 'normal/payload' at 6c7c0
+CBFS: Checking offset 79f80
+CBFS:  Unmatched 'cmos_layout.bin' at 19c0
+CBFS: Checking offset 2480
+CBFS:  Unmatched 'bootsplash.jpg' at 79f80
+CBFS: Checking offset 810c0
+CBFS:  Unmatched 'fallback/dsdt.aml' at 2480
+CBFS: Checking offset 4b40
+CBFS:  Unmatched '' at 810c0
+CBFS: Checking offset ff480
+CBFS: 'microcode_amd.bin' not found.
+[microcode] microcode file not found. Skipping updates.
+CBFS:  Unmatched 'normal/dsdt.aml' at 4b40
+CBFS: Checking offset 71c0
+CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 71c0
+CBFS: Checking offset e240
+CPU model Dual-Core AMD Opteron(tm) Processor 8222
+Setting up local apic... apic_id: 0x13 done.
+POST: 0x9b
+siblings = 01, CPU #3 initialized
+CBFS:  Unmatched 'config' at e240
+CBFS: Checking offset e540
+CBFS:  Unmatched 'revision' at e540
+CBFS: Checking offset e800
+CBFS:  Unmatched 'payload_config' at e800
+CBFS: Checking offset ee40
+CBFS:  Unmatched 'payload_revision' at ee40
+CBFS: Checking offset ef00
+CBFS:  Unmatched 'etc/pci-optionrom-exec' at ef00
+CBFS: Checking offset ef80
+CBFS:  Unmatched '' at ef80
+CBFS: Checking offset ff80
+CBFS:  Unmatched 'fallback/romstage' at ff80
+CBFS: Checking offset 1d080
+CBFS:  Unmatched 'fallback/ramstage' at 1d080
+CBFS: Checking offset 2ca80
+CBFS:  Unmatched 'fallback/payload' at 2ca80
+CBFS: Checking offset 3a540
+CBFS:  Unmatched 'pci14e4,1659.rom' at 3a540
+CBFS: Checking offset 4b5c0
+CBFS:  Unmatched '' at 4b5c0
+CBFS: Checking offset 4ff80
+CBFS:  Unmatched 'normal/romstage' at 4ff80
+CBFS: Checking offset 5cf40
+CBFS:  Unmatched 'normal/ramstage' at 5cf40
+CBFS: Checking offset 6c7c0
+CBFS:  Unmatched 'normal/payload' at 6c7c0
+CBFS: Checking offset 79f80
+CBFS:  Unmatched 'bootsplash.jpg' at 79f80
+CBFS: Checking offset 810c0
+CBFS:  Unmatched '' at 810c0
+CBFS: Checking offset ff480
+CBFS: 'microcode_amd.bin' not found.
+[microcode] microcode file not found. Skipping updates.
+CPU model Dual-Core AMD Opteron(tm) Processor 8222
+Setting up local apic... apic_id: 0x10 done.
+POST: 0x9b
+siblings = 01, CBFS @ 0 size ff480
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Checking offset 0
+CBFS:  Unmatched 'cmos.default' at 0
+CBFS: Checking offset 140
+CBFS:  Unmatched 'cpu_microcode_blob.bin' at 140
+CBFS: Checking offset 19c0
+CBFS: Found @ offset 19c0 size a64
+Clearing memory 2048K - 5242880K: -----------------------------------------------++++++++++++++++ done
+CPU #0 initialized
+All AP CPUs stopped (0 loops)
+CPU0: stack: 00126000 - 00127000, lowest used address 0012690c, stack used: 1780 bytes
+CPU1: stack: 00125000 - 00126000, lowest used address 00125bdc, stack used: 1060 bytes
+CPU2: stack: 00124000 - 00125000, lowest used address 00124c40, stack used: 960 bytes
+CPU3: stack: 00123000 - 00124000, lowest used address 00123c40, stack used: 960 bytes
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+PCI: 00:18.0 init ...
+POST: 0x75
+PCI: 00:18.1 init ...
+POST: 0x75
+PCI: 00:18.2 init ...
+POST: 0x75
+PCI: 00:18.3 init ...
+NB: Function 3 Misc Control.. done.
+POST: 0x75
+POST: 0x75
+PCI: 00:19.0 init ...
+POST: 0x75
+PCI: 00:19.1 init ...
+POST: 0x75
+PCI: 00:19.2 init ...
+POST: 0x75
+PCI: 00:19.3 init ...
+NB: Function 3 Misc Control.. done.
+POST: 0x75
+POST: 0x75
+PCI: 00:00.0 init ...
+POST: 0x75
+PCI: 00:01.0 init ...
+IOAPIC: Initializing IOAPIC at 0xfec00000
+IOAPIC: Bootstrap Processor Local APIC = 0x10
+IOAPIC: Dumping registers
+  reg 0x0000: 0x00000000
+  reg 0x0001: 0x00170011
+  reg 0x0002: 0x00000000
+IOAPIC: 24 interrupts
+IOAPIC: Enabling interrupts on FSB
+IOAPIC: reg 0x00000000 value 0x10000000 0x00000700
+IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
+IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
+lpc_init: pm_base = 4000 
+CBFS @ 0 size ff480
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Checking offset 0
+CBFS:  Unmatched 'cmos.default' at 0
+CBFS: Checking offset 140
+CBFS:  Unmatched 'cpu_microcode_blob.bin' at 140
+CBFS: Checking offset 19c0
+CBFS: Found @ offset 19c0 size a64
+set power on after power fail
+CBFS @ 0 size ff480
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Checking offset 0
+CBFS:  Unmatched 'cmos.default' at 0
+CBFS: Checking offset 140
+CBFS:  Unmatched 'cpu_microcode_blob.bin' at 140
+CBFS: Checking offset 19c0
+CBFS: Found @ offset 19c0 size a64
+CBFS @ 0 size ff480
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Checking offset 0
+CBFS:  Unmatched 'cmos.default' at 0
+CBFS: Checking offset 140
+CBFS:  Unmatched 'cpu_microcode_blob.bin' at 140
+CBFS: Checking offset 19c0
+CBFS: Found @ offset 19c0 size a64
+RTC Init
+POST: 0x75
+POST: 0x75
+PCI: 00:02.0 init ...
+POST: 0x75
+PCI: 00:02.1 init ...
+POST: 0x75
+POST: 0x75
+POST: 0x75
+PCI: 00:06.0 init ...
+IDE1 	IDE0
+POST: 0x75
+PCI: 00:07.0 init ...
+SATA S 	SATA P 
+POST: 0x75
+PCI: 00:08.0 init ...
+SATA S 	SATA P 
+POST: 0x75
+PCI: 00:09.0 init ...
+PCI DOMAIN mem base = 0x00f8000000
+[0x50] <-- 0xf8000000
+POST: 0x75
+POST: 0x75
+PCI: 00:0b.0 init ...
+POST: 0x75
+PCI: 00:0c.0 init ...
+POST: 0x75
+PCI: 00:0d.0 init ...
+POST: 0x75
+PCI: 00:0e.0 init ...
+POST: 0x75
+POST: 0x75
+PNP: 002e.0 init ...
+POST: 0x75
+POST: 0x75
+PNP: 002e.2 init ...
+POST: 0x75
+PNP: 002e.3 init ...
+POST: 0x75
+PNP: 002e.5 init ...
+Keyboard init...
+No PS/2 keyboard detected.
+POST: 0x75
+POST: 0x75
+POST: 0x75
+PNP: 002e.9 init ...
+POST: 0x75
+POST: 0x75
+PNP: 002e.b init ...
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+smbus: PCI: 00:01.1[0]->I2C: 01:2f init ...
+ID: 5ca3
+POST: 0x75
+PCI: 01:04.0 init ...
+XGI Z9s: initializing video device
+XGI VGA: Relocate IO address: 3000 [00003030]
+XGI VGA: chipid = 31
+XGI VGA: Framebuffer at 0xf8000000, mapped to 0xf8000000, size 16384k
+XGI VGA: MMIO at 0xfc200000, mapped to 0xfc200000, size 256k
+XGI VGA: No or unknown bridge type detected
+XGI VGA: Default mode is 800x600x8 (60Hz)
+XGI VGA text mode initialized
+POST: 0x75
+PCI: 02:00.0 init ...
+POST: 0x75
+PCI: 03:00.0 init ...
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+PCI: 07:00.0 init ...
+POST: 0x75
+PCI: 07:00.1 init ...
+POST: 0x75
+PCI: 08:00.0 init ...
+POST: 0x75
+PCI: 08:00.1 init ...
+Devices initialized
+Show all devs... After init.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+APIC: 10: enabled 1
+DOMAIN: 0000: enabled 1
+PCI: 00:18.0: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 1
+PNP: 002e.0: enabled 1
+PNP: 002e.1: enabled 0
+PNP: 002e.2: enabled 1
+PNP: 002e.3: enabled 1
+PNP: 002e.5: enabled 1
+PNP: 002e.7: enabled 0
+PNP: 002e.8: enabled 0
+PNP: 002e.9: enabled 1
+PNP: 002e.a: enabled 0
+PNP: 002e.b: enabled 1
+PCI: 00:01.1: enabled 1
+I2C: 01:50: enabled 1
+I2C: 01:51: enabled 1
+I2C: 01:52: enabled 1
+I2C: 01:53: enabled 1
+I2C: 01:54: enabled 1
+I2C: 01:55: enabled 1
+I2C: 01:56: enabled 1
+I2C: 01:57: enabled 1
+I2C: 01:2f: enabled 1
+PCI: 00:02.0: enabled 1
+PCI: 00:02.1: enabled 1
+PCI: 00:04.0: enabled 0
+PCI: 00:04.1: enabled 0
+PCI: 00:06.0: enabled 1
+PCI: 00:07.0: enabled 1
+PCI: 00:08.0: enabled 1
+PCI: 00:09.0: enabled 1
+PCI: 01:04.0: enabled 1
+PCI: 00:0a.0: enabled 0
+PCI: 00:0b.0: enabled 1
+PCI: 02:00.0: enabled 1
+PCI: 00:0c.0: enabled 1
+PCI: 03:00.0: enabled 1
+PCI: 00:0d.0: enabled 1
+PCI: 04:00.0: enabled 0
+PCI: 00:0e.0: enabled 1
+PCI: 00:0f.0: enabled 0
+PCI: 00:18.1: enabled 1
+PCI: 00:18.2: enabled 1
+PCI: 00:18.3: enabled 1
+PCI: 00:18.4: enabled 0
+PCI: 00:19.0: enabled 1
+PCI: 00:19.1: enabled 1
+PCI: 00:19.2: enabled 1
+PCI: 00:19.3: enabled 1
+PCI: 00:19.4: enabled 0
+APIC: 11: enabled 1
+APIC: 12: enabled 1
+APIC: 13: enabled 1
+PCI: 05:00.0: enabled 1
+PCI: 06:00.0: enabled 1
+PCI: 06:01.0: enabled 1
+PCI: 07:00.0: enabled 1
+PCI: 07:00.1: enabled 1
+PCI: 08:00.0: enabled 1
+PCI: 08:00.1: enabled 1
+CBMEM:
+IMD: root @ bffff000 254 entries.
+IMD: root @ bfffec00 62 entries.
+Moving GDT to bfffe720...ok
+POST: 0x76
+Finalize devices...
+Devices finalized
+POST: 0x77
+POST: 0x79
+POST: 0x9b
+CBFS @ 0 size ff480
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Checking offset 0
+CBFS:  Unmatched 'cmos.default' at 0
+CBFS: Checking offset 140
+CBFS:  Unmatched 'cpu_microcode_blob.bin' at 140
+CBFS: Checking offset 19c0
+CBFS: Found @ offset 19c0 size a64
+CONFIG_LOGICAL_CPUS==1: apicid_base: 00000000
+Wrote the mp table end at: 000f0010 - 000f0194
+Wrote the mp table end at: bffdd010 - bffdd194
+MP table: 404 bytes.
+POST: 0x9c
+CBFS @ 0 size ff480
+CBFS: Locating 'normal/dsdt.aml'
+CBFS: Checking offset 0
+CBFS:  Unmatched 'cmos.default' at 0
+CBFS: Checking offset 140
+CBFS:  Unmatched 'cpu_microcode_blob.bin' at 140
+CBFS: Checking offset 19c0
+CBFS:  Unmatched 'cmos_layout.bin' at 19c0
+CBFS: Checking offset 2480
+CBFS:  Unmatched 'fallback/dsdt.aml' at 2480
+CBFS: Checking offset 4b40
+CBFS: Found @ offset 4b40 size 2648
+CBFS @ 0 size ff480
+CBFS: Locating 'normal/slic'
+CBFS: Checking offset 0
+CBFS:  Unmatched 'cmos.default' at 0
+CBFS: Checking offset 140
+CBFS:  Unmatched 'cpu_microcode_blob.bin' at 140
+CBFS: Checking offset 19c0
+CBFS:  Unmatched 'cmos_layout.bin' at 19c0
+CBFS: Checking offset 2480
+CBFS:  Unmatched 'fallback/dsdt.aml' at 2480
+CBFS: Checking offset 4b40
+CBFS:  Unmatched 'normal/dsdt.aml' at 4b40
+CBFS: Checking offset 71c0
+CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 71c0
+CBFS: Checking offset e240
+CBFS:  Unmatched 'config' at e240
+CBFS: Checking offset e540
+CBFS:  Unmatched 'revision' at e540
+CBFS: Checking offset e800
+CBFS:  Unmatched 'payload_config' at e800
+CBFS: Checking offset ee40
+CBFS:  Unmatched 'payload_revision' at ee40
+CBFS: Checking offset ef00
+CBFS:  Unmatched 'etc/pci-optionrom-exec' at ef00
+CBFS: Checking offset ef80
+CBFS:  Unmatched '' at ef80
+CBFS: Checking offset ff80
+CBFS:  Unmatched 'fallback/romstage' at ff80
+CBFS: Checking offset 1d080
+CBFS:  Unmatched 'fallback/ramstage' at 1d080
+CBFS: Checking offset 2ca80
+CBFS:  Unmatched 'fallback/payload' at 2ca80
+CBFS: Checking offset 3a540
+CBFS:  Unmatched 'pci14e4,1659.rom' at 3a540
+CBFS: Checking offset 4b5c0
+CBFS:  Unmatched '' at 4b5c0
+CBFS: Checking offset 4ff80
+CBFS:  Unmatched 'normal/romstage' at 4ff80
+CBFS: Checking offset 5cf40
+CBFS:  Unmatched 'normal/ramstage' at 5cf40
+CBFS: Checking offset 6c7c0
+CBFS:  Unmatched 'normal/payload' at 6c7c0
+CBFS: Checking offset 79f80
+CBFS:  Unmatched 'bootsplash.jpg' at 79f80
+CBFS: Checking offset 810c0
+CBFS:  Unmatched '' at 810c0
+CBFS: Checking offset ff480
+CBFS: 'normal/slic' not found.
+ACPI: Writing ACPI tables at bffb9000.
+ACPI:    * FACS
+ACPI:    * DSDT
+ACPI:    * FADT
+pm_base: 0x4000
+ACPI: added table 1/32, length now 40
+ACPI:     * SSDT
+processor_brand=Dual-Core AMD Opteron(tm) Processor 8222
+Pstates Algorithm ...
+Pstate_freq[0] = 3000MHz	Pstate_vid[0] = 10	Pstate_volt[0] = 1300mv	Pstate_power[0] = 95000mw
+Pstate_freq[1] = 2800MHz	Pstate_vid[1] = 12	Pstate_volt[1] = 1250mv	Pstate_power[1] = 81977mw
+Pstate_freq[2] = 2600MHz	Pstate_vid[2] = 14	Pstate_volt[2] = 1200mv	Pstate_power[2] = 70153mw
+Pstate_freq[3] = 2400MHz	Pstate_vid[3] = 16	Pstate_volt[3] = 1150mv	Pstate_power[3] = 59473mw
+Pstate_freq[4] = 2200MHz	Pstate_vid[4] = 18	Pstate_volt[4] = 1100mv	Pstate_power[4] = 49879mw
+Pstate_freq[5] = 2000MHz	Pstate_vid[5] = 18	Pstate_volt[5] = 1100mv	Pstate_power[5] = 49879mw
+Pstate_freq[6] = 1000MHz	Pstate_vid[6] = 18	Pstate_volt[6] = 1100mv	Pstate_power[6] = 22672mw
+PSS: 3000MHz power 95000 control 0xe8202a96 status 0x296
+PSS: 2800MHz power 81977 control 0xe8202b14 status 0x314
+PSS: 2600MHz power 70153 control 0xe8202b92 status 0x392
+PSS: 2400MHz power 59473 control 0xe8202c10 status 0x410
+PSS: 2200MHz power 49879 control 0xe8202c8e status 0x48e
+PSS: 2000MHz power 49879 control 0xe8202c8c status 0x48c
+PSS: 1000MHz power 22672 control 0xe8202c82 status 0x482
+PSS: 3000MHz power 95000 control 0xe8202a96 status 0x296
+PSS: 2800MHz power 81977 control 0xe8202b14 status 0x314
+PSS: 2600MHz power 70153 control 0xe8202b92 status 0x392
+PSS: 2400MHz power 59473 control 0xe8202c10 status 0x410
+PSS: 2200MHz power 49879 control 0xe8202c8e status 0x48e
+PSS: 2000MHz power 49879 control 0xe8202c8c status 0x48c
+PSS: 1000MHz power 22672 control 0xe8202c82 status 0x482
+PSS: 3000MHz power 95000 control 0xe8202a96 status 0x296
+PSS: 2800MHz power 81977 control 0xe8202b14 status 0x314
+PSS: 2600MHz power 70153 control 0xe8202b92 status 0x392
+PSS: 2400MHz power 59473 control 0xe8202c10 status 0x410
+PSS: 2200MHz power 49879 control 0xe8202c8e status 0x48e
+PSS: 2000MHz power 49879 control 0xe8202c8c status 0x48c
+PSS: 1000MHz power 22672 control 0xe8202c82 status 0x482
+PSS: 3000MHz power 95000 control 0xe8202a96 status 0x296
+PSS: 2800MHz power 81977 control 0xe8202b14 status 0x314
+PSS: 2600MHz power 70153 control 0xe8202b92 status 0x392
+PSS: 2400MHz power 59473 control 0xe8202c10 status 0x410
+PSS: 2200MHz power 49879 control 0xe8202c8e status 0x48e
+PSS: 2000MHz power 49879 control 0xe8202c8c status 0x48c
+PSS: 1000MHz power 22672 control 0xe8202c82 status 0x482
+ACPI: added table 2/32, length now 44
+ACPI:    * MCFG
+ACPI:    * TCPA
+TCPA log created at bffa9000
+ACPI: added table 3/32, length now 48
+ACPI:    * MADT
+ACPI: added table 4/32, length now 52
+current = bffbc160
+ACPI:    * SRAT @ bffbc160
+SRAT: lapic cpu_index=00, node_id=00, apic_id=10
+SRAT: lapic cpu_index=01, node_id=00, apic_id=11
+SRAT: lapic cpu_index=02, node_id=01, apic_id=12
+SRAT: lapic cpu_index=03, node_id=01, apic_id=13
+set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
+set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
+set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00100000
+ACPI: added table 5/32, length now 56
+ACPI:    * SLIT @ bffbc250
+ACPI: added table 6/32, length now 60
+ACPI:    * HPET
+ACPI: added table 7/32, length now 64
+ACPI:    * SRAT @ bffbc2c0
+SRAT: lapic cpu_index=00, node_id=00, apic_id=10
+SRAT: lapic cpu_index=01, node_id=00, apic_id=11
+SRAT: lapic cpu_index=02, node_id=01, apic_id=12
+SRAT: lapic cpu_index=03, node_id=01, apic_id=13
+set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
+set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
+set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00100000
+ACPI: added table 8/32, length now 68
+ACPI:    * SLIT @ bffbc3b0
+ACPI: added table 9/32, length now 72
+ACPI: done.
+ACPI tables: 13280 bytes.
+smbios_write_tables: bffa8000
+Root Device (ASUS KFSN4-DRE_K8)
+CPU_CLUSTER: 0 (AMD K8 Root Complex)
+APIC: 10 (unknown)
+DOMAIN: 0000 (AMD K8 Root Complex)
+PCI: 00:18.0 (AMD K8 Northbridge)
+PCI: 00:00.0 (NVIDIA CK804 Southbridge)
+PCI: 00:01.0 (NVIDIA CK804 Southbridge)
+PNP: 002e.0 (Winbond W83627THG Super I/O)
+PNP: 002e.1 (Winbond W83627THG Super I/O)
+PNP: 002e.2 (Winbond W83627THG Super I/O)
+PNP: 002e.3 (Winbond W83627THG Super I/O)
+PNP: 002e.5 (Winbond W83627THG Super I/O)
+PNP: 002e.7 (Winbond W83627THG Super I/O)
+PNP: 002e.8 (Winbond W83627THG Super I/O)
+PNP: 002e.9 (Winbond W83627THG Super I/O)
+PNP: 002e.a (Winbond W83627THG Super I/O)
+PNP: 002e.b (Winbond W83627THG Super I/O)
+PCI: 00:01.1 (NVIDIA CK804 Southbridge)
+I2C: 01:50 (unknown)
+I2C: 01:51 (unknown)
+I2C: 01:52 (unknown)
+I2C: 01:53 (unknown)
+I2C: 01:54 (unknown)
+I2C: 01:55 (unknown)
+I2C: 01:56 (unknown)
+I2C: 01:57 (unknown)
+I2C: 01:2f (Nuvoton W83793 Hardware Monitor)
+PCI: 00:02.0 (NVIDIA CK804 Southbridge)
+PCI: 00:02.1 (NVIDIA CK804 Southbridge)
+PCI: 00:04.0 (NVIDIA CK804 Southbridge)
+PCI: 00:04.1 (NVIDIA CK804 Southbridge)
+PCI: 00:06.0 (NVIDIA CK804 Southbridge)
+PCI: 00:07.0 (NVIDIA CK804 Southbridge)
+PCI: 00:08.0 (NVIDIA CK804 Southbridge)
+PCI: 00:09.0 (NVIDIA CK804 Southbridge)
+PCI: 01:04.0 (NVIDIA CK804 Southbridge)
+PCI: 00:0a.0 (NVIDIA CK804 Southbridge)
+PCI: 00:0b.0 (NVIDIA CK804 Southbridge)
+PCI: 02:00.0 (NVIDIA CK804 Southbridge)
+PCI: 00:0c.0 (NVIDIA CK804 Southbridge)
+PCI: 03:00.0 (NVIDIA CK804 Southbridge)
+PCI: 00:0d.0 (NVIDIA CK804 Southbridge)
+PCI: 04:00.0 (NVIDIA CK804 Southbridge)
+PCI: 00:0e.0 (NVIDIA CK804 Southbridge)
+PCI: 00:0f.0 (NVIDIA CK804 Southbridge)
+PCI: 00:18.1 (AMD K8 Northbridge)
+PCI: 00:18.2 (AMD K8 Northbridge)
+PCI: 00:18.3 (AMD K8 Northbridge)
+PCI: 00:18.4 (AMD K8 Northbridge)
+PCI: 00:19.0 (AMD K8 Northbridge)
+PCI: 00:19.1 (AMD K8 Northbridge)
+PCI: 00:19.2 (AMD K8 Northbridge)
+PCI: 00:19.3 (AMD K8 Northbridge)
+PCI: 00:19.4 (AMD K8 Northbridge)
+APIC: 11 (unknown)
+APIC: 12 (unknown)
+APIC: 13 (unknown)
+PCI: 05:00.0 (unknown)
+PCI: 06:00.0 (unknown)
+PCI: 06:01.0 (unknown)
+PCI: 07:00.0 (unknown)
+PCI: 07:00.1 (unknown)
+PCI: 08:00.0 (unknown)
+PCI: 08:00.1 (unknown)
+SMBIOS tables: 329 bytes.
+POST: 0x9e
+POST: 0x9d
+Writing table forward entry at 0x00000500
+Wrote coreboot table at: 00000500, 0x10 bytes, checksum 3fe4
+Table forward entry ends at 0x00000528.
+... aligned to 0x00001000
+Writing coreboot table at 0xbffa0000
+rom_table_end = 0xbffa0000
+... aligned to 0xbffa0000
+CBFS @ 0 size ff480
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Checking offset 0
+CBFS:  Unmatched 'cmos.default' at 0
+CBFS: Checking offset 140
+CBFS:  Unmatched 'cpu_microcode_blob.bin' at 140
+CBFS: Checking offset 19c0
+CBFS: Found @ offset 19c0 size a64
+ 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
+ 1. 0000000000001000-000000000009ffff: RAM
+ 2. 00000000000a0000-00000000000bffff: RESERVED
+ 3. 00000000000c0000-00000000bff9ffff: RAM
+ 4. 00000000bffa0000-00000000bfffffff: CONFIGURATION TABLES
+ 5. 0000000100000000-000000013fffffff: RAM
+CBFS @ 0 size ff480
+No FMAP found at 0 offset.
+Wrote coreboot table at: bffa0000, 0xca4 bytes, checksum a687
+coreboot table: 3260 bytes.
+IMD ROOT    0. bffff000 00001000
+IMD SMALL   1. bfffe000 00001000
+CONSOLE     2. bffde000 00020000
+SMP TABLE   3. bffdd000 00001000
+ACPI        4. bffb9000 00024000
+TCPA LOG    5. bffa9000 00010000
+SMBIOS      6. bffa8000 00000800
+COREBOOT    7. bffa0000 00008000
+IMD small region:
+  IMD ROOT    0. bfffec00 00000400
+  TIME STAMP  1. bfffe920 000002e0
+  GDT         2. bfffe720 00000200
+POST: 0x7a
+CBFS provider active.
+CBFS @ 0 size ff480
+CBFS: Locating 'normal/payload'
+CBFS: Checking offset 0
+CBFS:  Unmatched 'cmos.default' at 0
+CBFS: Checking offset 140
+CBFS:  Unmatched 'cpu_microcode_blob.bin' at 140
+CBFS: Checking offset 19c0
+CBFS:  Unmatched 'cmos_layout.bin' at 19c0
+CBFS: Checking offset 2480
+CBFS:  Unmatched 'fallback/dsdt.aml' at 2480
+CBFS: Checking offset 4b40
+CBFS:  Unmatched 'normal/dsdt.aml' at 4b40
+CBFS: Checking offset 71c0
+CBFS:  Unmatched 'vgaroms/seavgabios.bin' at 71c0
+CBFS: Checking offset e240
+CBFS:  Unmatched 'config' at e240
+CBFS: Checking offset e540
+CBFS:  Unmatched 'revision' at e540
+CBFS: Checking offset e800
+CBFS:  Unmatched 'payload_config' at e800
+CBFS: Checking offset ee40
+CBFS:  Unmatched 'payload_revision' at ee40
+CBFS: Checking offset ef00
+CBFS:  Unmatched 'etc/pci-optionrom-exec' at ef00
+CBFS: Checking offset ef80
+CBFS:  Unmatched '' at ef80
+CBFS: Checking offset ff80
+CBFS:  Unmatched 'fallback/romstage' at ff80
+CBFS: Checking offset 1d080
+CBFS:  Unmatched 'fallback/ramstage' at 1d080
+CBFS: Checking offset 2ca80
+CBFS:  Unmatched 'fallback/payload' at 2ca80
+CBFS: Checking offset 3a540
+CBFS:  Unmatched 'pci14e4,1659.rom' at 3a540
+CBFS: Checking offset 4b5c0
+CBFS:  Unmatched '' at 4b5c0
+CBFS: Checking offset 4ff80
+CBFS:  Unmatched 'normal/romstage' at 4ff80
+CBFS: Checking offset 5cf40
+CBFS:  Unmatched 'normal/ramstage' at 5cf40
+CBFS: Checking offset 6c7c0
+CBFS: Found @ offset 6c7c0 size d784
+'normal/payload' located at offset: 6c7e8 size: d784
+Loading segment from rom address 0xfff6c7e8
+  code (compression=1)
+  New segment dstaddr 0xe6a0c memsize 0x195f4 srcaddr 0xfff6c820 filesize 0xd74c
+Loading segment from rom address 0xfff6c804
+  Entry Point 0x000fd55a
+Bounce Buffer at bfe5f000, 1311776 bytes
+Loading Segment: addr: 0x00000000000e6a0c memsz: 0x00000000000195f4 filesz: 0x000000000000d74c
+lb: [0x0000000000100000, 0x00000000001a0210)
+Post relocation: addr: 0x00000000000e6a0c memsz: 0x00000000000195f4 filesz: 0x000000000000d74c
+using LZMA
+[ 0x000e6a0c, 00100000, 0x00100000) <- fff6c820
+dest 000e6a0c, end 00100000, bouncebuffer bfe5f000
+Loaded segments
+POST: 0x7b
+Jumping to boot code at 000fd55a(bffa0000)
+POST: 0xf8
+CPU0: stack: 00126000 - 00127000, lowest used address 0012690c, stack used: 1780 bytes
+entry    = 0x000fd55a
+lb_start = 0x00100000
+lb_size  = 0x000a0210
+buffer   = 0xbfe5f000
+SeaBIOS (version rel-1.8.0-10-g5ae3dd6-20151117_210636-cb-test-tgt)
+Found coreboot cbmem console @ bffde000
+Found mainboard ASUS KFSN4-DRE_K8
+Relocating init from 0x000e7c30 to 0xbff55c60 (size 41696)
+Found CBFS header at 0xfffff498
+CPU Mhz=3017
+Found 31 PCI devices (max PCI bus is 08)
+Copying SMBIOS entry point from 0xbffa8000 to 0x000f1ef0
+Copying ACPI RSDP from 0xbffb9000 to 0x000f1ec0
+Copying MPTABLE from 0xbffdd000/bffdd010 to 0x000f1d20
+Using pmtimer, ioport 0x4008
+Scan for VGA option rom
+Running option rom at c000:0003
+pmm call arg1=0
+Turning on vga text mode console
+SeaBIOS (version rel-1.8.0-10-g5ae3dd6-20151117_210636-cb-test-tgt)
+EHCI init on dev 00:02.1 (regs=0xfc503020)
+OHCI init on dev 00:02.0 (regs=0xfc500000)
+Found 1 lpt ports
+Found 2 serial ports
+ATA controller 1 at 1f0/3f4/0 (irq 14 dev 30)
+ATA controller 2 at 170/374/0 (irq 15 dev 30)
+ATA controller 3 at 5050/5070/0 (irq 0 dev 38)
+ATA controller 4 at 5058/5074/0 (irq 0 dev 38)
+ATA controller 5 at 5060/5078/0 (irq 0 dev 40)
+ATA controller 6 at 5068/507c/0 (irq 0 dev 40)
+Got ps2 nak (status=51)
+All threads complete.
+Scan for option roms
+Running option rom at c700:0003
+pmm call arg1=1
+pmm call arg1=0
+pmm call arg1=1
+pmm call arg1=0
+Running option rom at c800:0003
+pmm call arg1=1
+pmm call arg1=1
+Searching bootorder for: /pci@i0cf8/pci-bridge@b/*@0
+Searching bootorder for: /pci@i0cf8/pci-bridge@c/*@0
+
+Press F12 for boot menu.
+
+Unable to find vesa video mode dimensions 640/480
+failed to find a videomode with 640x480 0bpp (0=any).
+Searching bootorder for: HALT
+Space available for UMB: c9000-ed000, f0000-f1cc0
+Returned 262144 bytes of ZoneHigh
+e820 map has 6 items:
+  0: 0000000000000000 - 000000000009fc00 = 1 RAM
+  1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
+  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
+  3: 0000000000100000 - 00000000bffa0000 = 1 RAM
+  4: 00000000bffa0000 - 00000000c0000000 = 2 RESERVED
+  5: 0000000100000000 - 0000000140000000 = 1 RAM
+enter handle_19:
+  NULL
+Booting from ROM...
+Booting from c700:0373
+