

======= Fri Mar 10 15:32:19 2017 (adjust=86.8us)
00.000: <00>
00.190: 
00.190: 
00.190: coreboot-4.5-1206-g589fc34 Fri Mar 10 10:20:39 UTC 2017 romstage starting...
00.190: Initial stack pointer: 000dffb8
00.191: CPU APICID 00 start flag set
00.193: BSP Family_Model: 00600f12
00.193: *sysinfo range: [000c2d20,000cd28c]
00.193: bsp_apicid = 00
00.193: cpu_init_detectedx = 00000000
00.193: sb700 reset flags: 0020
00.193: WARNING: MC4 Machine Check Exception detected on node 0!
00.193: Signature: e300000400190127
00.194: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
00.194: CBFS: Locating 'microcode_amd.bin'
00.195: CBFS: Found @ offset d0000 size 318c
00.196: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
00.196: CBFS: Locating 'microcode_amd_fam15h.bin'
00.196: CBFS: Found @ offset d3200 size 1ec4
00.217: [microcode] patch id to apply = 0x0600063d
00.218: [microcode] updated to patch id = 0x0600063d success
00.218: cpuSetAMDMSR CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
00.220: CBFS: Locating 'cmos_layout.bin'
00.221: CBFS: Found @ offset 2b0c0 size e88
00.222: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
00.222: CBFS: Locating 'cmos_layout.bin'
00.222: CBFS: Found @ offset 2b0c0 size e88
00.223:  done
00.223: Enter amd_ht_init
00.226: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1
00.227: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2
00.227: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3
00.230: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
00.230: CBFS: Locating 'cmos_layout.bin'
00.231: CBFS: Found @ offset 2b0c0 size e88
00.231: Forcing HT links to isochronous mode due to enabled IOMMU
00.231: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
00.232: CBFS: Locating 'cmos_layout.bin'
00.232: CBFS: Found @ offset 2b0c0 size e88
00.233: Exit amd_ht_init
00.233: amd_ht_fixup
00.233: amd_ht_fixup: node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1)
00.234: amd_ht_fixup: node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1)
00.234: amd_ht_fixup: node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1)
00.234: amd_ht_fixup: node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1)
00.235: cpuSetAMDPCI 00 done
00.237: cpuSetAMDPCI 01 done
00.238: cpuSetAMDPCI 02 done
00.238: cpuSetAMDPCI 03 done
00.239: Prep FID/VID Node:00
00.239:   F3x80: e20be281
00.239:   F3x84: 01e200e2
00.239:   F3xD4: c3312f18
00.239:   F3xD8: 03000016
00.240:   F3xDC: 05475632
00.240: Prep FID/VID Node:01
00.240:   F3x80: e20be281
00.240:   F3x84: 01e200e2
00.240:   F3xD4: c3312f18
00.240:   F3xD8: 03000016
00.240:   F3xDC: 05475632
00.240: Prep FID/VID Node:02
00.240:   F3x80: e20be281
00.240:   F3x84: 01e200e2
00.240:   F3xD4: c3312f18
00.240:   F3xD8: 03000016
00.240:   F3xDC: 05475632
00.240: Prep FID/VID Node:03
00.241:   F3x80: e20be281
00.241:   F3x84: 01e200e2
00.241:   F3xD4: c3312f18
00.241:   F3xD8: 03000016
00.241:   F3xDC: 05475632
00.241: setup_remote_node: 01 done
00.241: Start node 01 done.
00.241: setup_remote_node: 02 done
00.242: Start node 02 done.
00.242: setup_remote_node: 03 done
00.243: Start node 03 done.
00.245: WARNING: MC4 Machine Check Exception detected on node 1!
00.251: Signature: f627f7fe561fd7bf
00.252: WARNING: MC4 Machine Check Exception detected on node 2!
00.255: Signature: fa1008e3ca054c0f
00.257: WARNING: MC4 Machine Check Exception detected on node 3!
00.258: Signature: f20512f100010e0f
00.259: core0 started:  01 02 03
00.259: sr5650_early_setup()
00.259: get_cpu_rev EAX=0x600f12.
00.259: CPU Rev is Fam 15.
00.259: NB Revision is A12.
00.259: fam10_optimization()
00.260: sr5650_por_init
00.265: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
00.266: CBFS: Locating 'cmos_layout.bin'
00.266: CBFS: Found @ offset 2b0c0 size e88
00.266: Enabling IOMMU
00.268: sb700_early_setup()
00.268: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
00.268: CBFS: Locating 'cmos_layout.bin'
00.270: CBFS: Found @ offset 2b0c0 size e88
00.272: sb700_devices_por_init()
00.273: sb700_devices_por_init(): SMBus Device, BDF:0-20-0
00.275: SMBus controller enabled, sb revision is A15
00.275: sb700_devices_por_init: Disabling ISA DMA support
00.275: sb700_devices_por_init(): IDE Device, BDF:0-20-1
00.278: sb700_devices_por_init(): LPC Device, BDF:0-20-3
00.279: sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
00.280: sb700_devices_por_init(): SATA Device, BDF:0-17-0
00.280: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
00.280: CBFS: Locating 'cmos_layout.bin'
00.281: CBFS: Found @ offset 2b0c0 size e88
00.281: sb700_pmio_por_init()
00.281: start_other_cores()
00.282: init node: 00  cores: 07 pass 1
00.282: Start other core - nodeid: 00  cores: 07
00.282: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
00.336: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
00.363: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
00.386: init node: 01  cores: 07 pass 1
00.389: Start other core - nodeid: 01  cores: 07
00.394: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
00.494: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
00.520: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
00.545: init node: 02  cores: 07 pass 1
00.547: Start other core - nodeid: 02  cores: 07
00.549: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
00.758: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
00.782: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
00.833: init node: 03  cores: 07 pass 1
00.837: Start other core - nodeid: 03  cores: 07
00.842: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
01.105: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
01.105: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
01.106: started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
01.109: * AP 01started
01.110: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
01.114: * AP 02started
01.117: get_boot_apic_id: using 3 as APIC ID for node 0, core 3
01.117: * AP 03started
01.118: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
01.118: * AP 04started
01.118: get_boot_apic_id: using 5 as APIC ID for node 0, core 5
01.118: * AP 05started
01.118: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
01.118: * AP 06started
01.120: get_boot_apic_id: using 7 as APIC ID for node 0, core 7
01.123: * AP 07started
01.123: get_boot_apic_id: using 9 as APIC ID for node 1, core 1
01.123: * AP 09started
01.123: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
01.124: * AP 0astarted
01.124: get_boot_apic_id: using 11 as APIC ID for node 1, core 3
01.124: * AP 0bstarted
01.124: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
01.127: * AP 0cstarted
01.127: get_boot_apic_id: using 13 as APIC ID for node 1, core 5
01.128: * AP 0dstarted
01.128: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
01.129: * AP 0estarted
01.129: get_boot_apic_id: using 15 as APIC ID for node 1, core 7
01.129: * AP 0fstarted
01.129: get_boot_apic_id: using 33 as APIC ID for node 2, core 1
01.131: * AP 21started
01.132: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
01.133: * AP 22started
01.133: get_boot_apic_id: using 35 as APIC ID for node 2, core 3
01.134: * AP 23started
01.134: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
01.134: * AP 24started
01.134: get_boot_apic_id: using 37 as APIC ID for node 2, core 5
01.135: * AP 25started
01.136: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
01.137: * AP 26started
01.137: get_boot_apic_id: using 39 as APIC ID for node 2, core 7
01.137: * AP 27started
01.137: get_boot_apic_id: using 41 as APIC ID for node 3, core 1
01.137: * AP 29started
01.137: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
01.137: * AP 2astarted
01.137: get_boot_apic_id: using 43 as APIC ID for node 3, core 3
01.138: * AP 2bstarted
01.138: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
01.138: * AP 2cstarted
01.138: get_boot_apic_id: using 45 as APIC ID for node 3, core 5
01.138: * AP 2dstarted
01.138: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
01.138: * AP 2estarted
01.138: get_boot_apic_id: using 47 as APIC ID for node 3, core 7
01.139: * AP 2fstarted
01.139: 
01.139: 
01.139: Begin FIDVID MSR 0xc0010071 0x52c2009e 0x3c06644c
01.139: FIDVID on BSP, APIC_id: 00
01.140: BSP fid = 0
01.140: get_boot_apic_id: using 0 as APIC ID for node 0, core 0
01.140: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
01.140: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
01.140: get_boot_apic_id: using 3 as APIC ID for node 0, core 3
01.140: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
01.140: get_boot_apic_id: using 5 as APIC ID for node 0, core 5
01.141: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
01.141: get_boot_apic_id: using 7 as APIC ID for node 0, core 7
01.141: get_boot_apic_id: using 8 as APIC ID for node 1, core 0
01.141: get_boot_apic_id: using 9 as APIC ID for node 1, core 1
01.141: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
01.141: get_boot_apic_id: using 11 as APIC ID for node 1, core 3
01.142: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
01.142: get_boot_apic_id: using 13 as APIC ID for node 1, core 5
01.142: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
01.142: get_boot_apic_id: using 15 as APIC ID for node 1, core 7
01.142: get_boot_apic_id: using 32 as APIC ID for node 2, core 0
01.142: get_boot_apic_id: using 33 as APIC ID for node 2, core 1
01.143: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
01.143: get_boot_apic_id: using 35 as APIC ID for node 2, core 3
01.143: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
01.143: get_boot_apic_id: using 37 as APIC ID for node 2, core 5
01.143: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
01.143: get_boot_apic_id: using 39 as APIC ID for node 2, core 7
01.144: get_boot_apic_id: using 40 as APIC ID for node 3, core 0
01.144: get_boot_apic_id: using 41 as APIC ID for node 3, core 1
01.144: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
01.144: get_boot_apic_id: using 43 as APIC ID for node 3, core 3
01.144: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
01.144: get_boot_apic_id: using 45 as APIC ID for node 3, core 5
01.145: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
01.145: get_boot_apic_id: using 47 as APIC ID for node 3, core 7
01.145: Wait for AP stage 1: ap_apicid = 1
01.145: <09>readback = 1000014
01.145: <09>common_fid(packed) = 0
01.145: Wait for AP stage 1: ap_apicid = 2
01.145: <09>readback = 2000014
01.146: <09>common_fid(packed) = 0
01.146: Wait for AP stage 1: ap_apicid = 3
01.146: <09>readback = 3000014
01.146: <09>common_fid(packed) = 0
01.146: Wait for AP stage 1: ap_apicid = 4
01.146: <09>readback = 4000014
01.146: <09>common_fid(packed) = 0
01.146: Wait for AP stage 1: ap_apicid = 5
01.146: <09>readback = 5000014
01.146: <09>common_fid(packed) = 0
01.146: Wait for AP stage 1: ap_apicid = 6
01.146: <09>readback = 6000014
01.147: <09>common_fid(packed) = 0
01.147: Wait for AP stage 1: ap_apicid = 7
01.147: <09>readback = 7000014
01.147: <09>common_fid(packed) = 0
01.147: Wait for AP stage 1: ap_apicid = 8
01.147: <09>readback = 8000014
01.147: <09>common_fid(packed) = 0
01.147: Wait for AP stage 1: ap_apicid = 9
01.147: <09>readback = 9000014
01.147: <09>common_fid(packed) = 0
01.147: Wait for AP stage 1: ap_apicid = a
01.148: <09>readback = a000014
01.148: <09>common_fid(packed) = 0
01.148: Wait for AP stage 1: ap_apicid = b
01.148: <09>readback = b000014
01.148: <09>common_fid(packed) = 0
01.148: Wait for AP stage 1: ap_apicid = c
01.148: <09>readback = c000014
01.148: <09>common_fid(packed) = 0
01.148: Wait for AP stage 1: ap_apicid = d
01.148: <09>readback = d000014
01.148: <09>common_fid(packed) = 0
01.148: Wait for AP stage 1: ap_apicid = e
01.149: <09>readback = e000014
01.149: <09>common_fid(packed) = 0
01.149: Wait for AP stage 1: ap_apicid = f
01.149: <09>readback = f000014
01.149: <09>common_fid(packed) = 0
01.149: Wait for AP stage 1: ap_apicid = 20
01.149: <09>readback = 20000014
01.149: <09>common_fid(packed) = 0
01.150: Wait for AP stage 1: ap_apicid = 21
01.149: <09>readback = 21000014
01.149: <09>common_fid(packed) = 0
01.150: Wait for AP stage 1: ap_apicid = 22
01.150: <09>readback = 22000014
01.150: <09>common_fid(packed) = 0
01.150: Wait for AP stage 1: ap_apicid = 23
01.150: <09>readback = 23000014
01.150: <09>common_fid(packed) = 0
01.150: Wait for AP stage 1: ap_apicid = 24
01.150: <09>readback = 24000014
01.150: <09>common_fid(packed) = 0
01.150: Wait for AP stage 1: ap_apicid = 25
01.150: <09>readback = 25000014
01.150: <09>common_fid(packed) = 0
01.151: Wait for AP stage 1: ap_apicid = 26
01.151: <09>readback = 26000014
01.151: <09>common_fid(packed) = 0
01.151: Wait for AP stage 1: ap_apicid = 27
01.151: <09>readback = 27000014
01.151: <09>common_fid(packed) = 0
01.151: Wait for AP stage 1: ap_apicid = 28
01.151: <09>readback = 28000014
01.151: <09>common_fid(packed) = 0
01.151: Wait for AP stage 1: ap_apicid = 29
01.151: <09>readback = 29000014
01.152: <09>common_fid(packed) = 0
01.152: Wait for AP stage 1: ap_apicid = 2a
01.152: <09>readback = 2a000014
01.152: <09>common_fid(packed) = 0
01.152: Wait for AP stage 1: ap_apicid = 2b
01.152: <09>readback = 2b000014
01.152: <09>common_fid(packed) = 0
01.152: Wait for AP stage 1: ap_apicid = 2c
01.152: <09>readback = 2c000014
01.152: <09>common_fid(packed) = 0
01.152: Wait for AP stage 1: ap_apicid = 2d
01.153: <09>readback = 2d000014
01.153: <09>common_fid(packed) = 0
01.153: Wait for AP stage 1: ap_apicid = 2e
01.153: <09>readback = 2e000014
01.153: <09>common_fid(packed) = 0
01.153: Wait for AP stage 1: ap_apicid = 2f
01.153: <09>readback = 2f000014
01.153: <09>common_fid(packed) = 0
01.153: common_fid = 0
01.153: End FIDVIDMSR 0xc0010071 0x52c2009e 0x3c06644c
01.154: sr5650_htinit: Node 0 Link 1, HT freq=e.
01.154: sr5650_htinit: HT3 mode
01.154: ...WARM RESET...
01.154: 
01.154: 
01.154: <00>
01.266: 
01.266: 
01.266: coreboot-4.5-1206-g589fc34 Fri Mar 10 10:20:39 UTC 2017 romstage starting...
01.266: Initial stack pointer: 000dffb8
01.267: CPU APICID 00 start flag set
01.268: BSP Family_Model: 00600f12
01.268: *sysinfo range: [000c2d20,000cd28c]
01.268: bsp_apicid = 00
01.268: cpu_init_detectedx = 00000000
01.268: sb700 reset flags: 0004
01.269: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
01.269: CBFS: Locating 'microcode_amd.bin'
01.269: CBFS: Found @ offset d0000 size 318c
01.270: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
01.270: CBFS: Locating 'microcode_amd_fam15h.bin'
01.270: CBFS: Found @ offset d3200 size 1ec4
01.292: [microcode] patch id to apply = 0x0600063d
01.293: [microcode] updated to patch id = 0x0600063d success
01.293: cpuSetAMDMSR CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
01.295: CBFS: Locating 'cmos_layout.bin'
01.295: CBFS: Found @ offset 2b0c0 size e88
01.296: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
01.296: CBFS: Locating 'cmos_layout.bin'
01.296: CBFS: Found @ offset 2b0c0 size e88
01.296:  done
01.296: Enter amd_ht_init
01.299: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1
01.300: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2
01.300: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3
01.302: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
01.303: CBFS: Locating 'cmos_layout.bin'
01.303: CBFS: Found @ offset 2b0c0 size e88
01.303: Forcing HT links to isochronous mode due to enabled IOMMU
01.303: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
01.303: CBFS: Locating 'cmos_layout.bin'
01.303: CBFS: Found @ offset 2b0c0 size e88
01.304: Exit amd_ht_init
01.304: amd_ht_fixup
01.304: amd_ht_fixup: node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1)
01.305: amd_ht_fixup: node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1)
01.305: amd_ht_fixup: node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1)
01.305: amd_ht_fixup: node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1)
01.305: cpuSetAMDPCI 00 done
01.307: cpuSetAMDPCI 01 done
01.308: cpuSetAMDPCI 02 done
01.308: cpuSetAMDPCI 03 done
01.308: Prep FID/VID Node:00
01.308:   F3x80: e20be281
01.308:   F3x84: 01e200e2
01.308:   F3xD4: c3312f18
01.308:   F3xD8: 03000016
01.308:   F3xDC: 05475632
01.308: Prep FID/VID Node:01
01.308:   F3x80: e20be281
01.309:   F3x84: 01e200e2
01.309:   F3xD4: c3312f18
01.309:   F3xD8: 03000016
01.309:   F3xDC: 05475632
01.309: Prep FID/VID Node:02
01.309:   F3x80: e20be281
01.309:   F3x84: 01e200e2
01.309:   F3xD4: c3312f18
01.309:   F3xD8: 03000016
01.309:   F3xDC: 05475632
01.309: Prep FID/VID Node:03
01.309:   F3x80: e20be281
01.309:   F3x84: 01e200e2
01.309:   F3xD4: c3312f18
01.309:   F3xD8: 03000016
01.309:   F3xDC: 05475632
01.309: setup_remote_node: 01 done
01.309: Start node 01 done.
01.309: setup_remote_node: 02 done
01.310: Start node 02 done.
01.310: setup_remote_node: 03 done
01.311: Start node 03 done.
01.315: core0 started:  01 02 03
01.317: sr5650_early_setup()
01.318: get_cpu_rev EAX=0x600f12.
01.319: CPU Rev is Fam 15.
01.320: NB Revision is A12.
01.321: fam10_optimization()
01.323: sr5650_por_init
01.324: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
01.325: CBFS: Locating 'cmos_layout.bin'
01.325: CBFS: Found @ offset 2b0c0 size e88
01.326: Enabling IOMMU
01.326: sb700_early_setup()
01.326: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
01.329: CBFS: Locating 'cmos_layout.bin'
01.329: CBFS: Found @ offset 2b0c0 size e88
01.330: sb700_devices_por_init()
01.331: sb700_devices_por_init(): SMBus Device, BDF:0-20-0
01.332: SMBus controller enabled, sb revision is A15
01.332: sb700_devices_por_init: Disabling ISA DMA support
01.333: sb700_devices_por_init(): IDE Device, BDF:0-20-1
01.337: sb700_devices_por_init(): LPC Device, BDF:0-20-3
01.338: sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
01.338: sb700_devices_por_init(): SATA Device, BDF:0-17-0
01.339: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
01.338: CBFS: Locating 'cmos_layout.bin'
01.339: CBFS: Found @ offset 2b0c0 size e88
01.340: sb700_pmio_por_init()
01.341: start_other_cores()
01.342: init node: 00  cores: 07 pass 1
01.342: Start other core - nodeid: 00  cores: 07
01.342: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
01.423: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
01.423: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
01.440: init node: 01  cores: 07 pass 1
01.443: Start other core - nodeid: 01  cores: 07
01.446: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
01.635: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
01.658: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
01.658: init node: 02  cores: 07 pass 1
01.659: Start other core - nodeid: 02  cores: 07
01.661: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
01.838: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
01.838: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
01.855: init node: 03  cores: 07 pass 1
01.856: Start other core - nodeid: 03  cores: 07
01.858: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
02.011: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
02.035: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
02.058: started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
02.062: * AP 01started
02.063: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
02.065: * AP 02started
02.069: get_boot_apic_id: using 3 as APIC ID for node 0, core 3
02.070: * AP 03started
02.070: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
02.070: * AP 04started
02.071: get_boot_apic_id: using 5 as APIC ID for node 0, core 5
02.072: * AP 05started
02.073: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
02.075: * AP 06started
02.075: get_boot_apic_id: using 7 as APIC ID for node 0, core 7
02.075: * AP 07started
02.075: get_boot_apic_id: using 9 as APIC ID for node 1, core 1
02.077: * AP 09started
02.077: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
02.079: * AP 0astarted
02.079: get_boot_apic_id: using 11 as APIC ID for node 1, core 3
02.079: * AP 0bstarted
02.079: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
02.081: * AP 0cstarted
02.082: get_boot_apic_id: using 13 as APIC ID for node 1, core 5
02.083: * AP 0dstarted
02.083: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
02.083: * AP 0estarted
02.083: get_boot_apic_id: using 15 as APIC ID for node 1, core 7
02.085: * AP 0fstarted
02.085: get_boot_apic_id: using 33 as APIC ID for node 2, core 1
02.085: * AP 21started
02.085: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
02.085: * AP 22started
02.085: get_boot_apic_id: using 35 as APIC ID for node 2, core 3
02.085: * AP 23started
02.086: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
02.086: * AP 24started
02.086: get_boot_apic_id: using 37 as APIC ID for node 2, core 5
02.086: * AP 25started
02.086: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
02.086: * AP 26started
02.086: get_boot_apic_id: using 39 as APIC ID for node 2, core 7
02.086: * AP 27started
02.086: get_boot_apic_id: using 41 as APIC ID for node 3, core 1
02.086: * AP 29started
02.086: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
02.086: * AP 2astarted
02.086: get_boot_apic_id: using 43 as APIC ID for node 3, core 3
02.086: * AP 2bstarted
02.086: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
02.086: * AP 2cstarted
02.086: get_boot_apic_id: using 45 as APIC ID for node 3, core 5
02.086: * AP 2dstarted
02.086: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
02.086: * AP 2estarted
02.086: get_boot_apic_id: using 47 as APIC ID for node 3, core 7
02.086: * AP 2fstarted
02.086: 
02.086: 
02.086: Begin FIDVID MSR 0xc0010071 0x52c2009e 0x3c025408
02.086: End FIDVIDMSR 0xc0010071 0x52c2009e 0x3c025408
02.087: sr5650_htinit: Node 0 Link 1, HT freq=e.
02.087: sr5650_htinit: HT3 mode
02.087: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
02.087: CBFS: Locating 'cmos_layout.bin'
02.087: CBFS: Found @ offset 2b0c0 size e88
02.087: ...WARM RESET...
02.087: 
02.087: 
02.088: <00>
02.191: 
02.191: 
02.191: coreboot-4.5-1206-g589fc34 Fri Mar 10 10:20:39 UTC 2017 romstage starting...
02.192: Initial stack pointer: 000dffb8
02.193: CPU APICID 00 start flag set
02.194: BSP Family_Model: 00600f12
02.194: *sysinfo range: [000c2d20,000cd28c]
02.194: bsp_apicid = 00
02.194: cpu_init_detectedx = 00000000
02.194: sb700 reset flags: 0004
02.195: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
02.195: CBFS: Locating 'microcode_amd.bin'
02.195: CBFS: Found @ offset d0000 size 318c
02.195: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
02.195: CBFS: Locating 'microcode_amd_fam15h.bin'
02.196: CBFS: Found @ offset d3200 size 1ec4
02.210: [microcode] patch id to apply = 0x0600063d
02.210: [microcode] updated to patch id = 0x0600063d success
02.210: cpuSetAMDMSR CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
02.212: CBFS: Locating 'cmos_layout.bin'
02.212: CBFS: Found @ offset 2b0c0 size e88
02.213: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
02.213: CBFS: Locating 'cmos_layout.bin'
02.213: CBFS: Found @ offset 2b0c0 size e88
02.214:  done
02.214: Enter amd_ht_init
02.217: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1
02.217: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2
02.217: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3
02.220: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
02.220: CBFS: Locating 'cmos_layout.bin'
02.220: CBFS: Found @ offset 2b0c0 size e88
02.221: Forcing HT links to isochronous mode due to enabled IOMMU
02.221: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
02.221: CBFS: Locating 'cmos_layout.bin'
02.221: CBFS: Found @ offset 2b0c0 size e88
02.222: Exit amd_ht_init
02.222: amd_ht_fixup
02.222: amd_ht_fixup: node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1)
02.222: amd_ht_fixup: node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1)
02.222: amd_ht_fixup: node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1)
02.222: amd_ht_fixup: node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1)
02.223: cpuSetAMDPCI 00 done
02.225: cpuSetAMDPCI 01 done
02.225: cpuSetAMDPCI 02 done
02.225: cpuSetAMDPCI 03 done
02.225: Prep FID/VID Node:00
02.226:   F3x80: e20be281
02.226:   F3x84: 01e200e2
02.226:   F3xD4: c3312f18
02.226:   F3xD8: 03000016
02.226:   F3xDC: 05475632
02.226: Prep FID/VID Node:01
02.226:   F3x80: e20be281
02.226:   F3x84: 01e200e2
02.226:   F3xD4: c3312f18
02.226:   F3xD8: 03000016
02.226:   F3xDC: 05475632
02.226: Prep FID/VID Node:02
02.226:   F3x80: e20be281
02.226:   F3x84: 01e200e2
02.226:   F3xD4: c3312f18
02.226:   F3xD8: 03000016
02.226:   F3xDC: 05475632
02.226: Prep FID/VID Node:03
02.226:   F3x80: e20be281
02.226:   F3x84: 01e200e2
02.226:   F3xD4: c3312f18
02.226:   F3xD8: 03000016
02.226:   F3xDC: 05475632
02.226: setup_remote_node: 01 done
02.226: Start node 01 done.
02.226: setup_remote_node: 02 done
02.227: Start node 02 done.
02.227: setup_remote_node: 03 done
02.228: Start node 03 done.
02.232: core0 started:  01 02 03
02.234: sr5650_early_setup()
02.235: get_cpu_rev EAX=0x600f12.
02.236: CPU Rev is Fam 15.
02.237: NB Revision is A12.
02.238: fam10_optimization()
02.240: sr5650_por_init
02.241: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
02.242: CBFS: Locating 'cmos_layout.bin'
02.243: CBFS: Found @ offset 2b0c0 size e88
02.243: Enabling IOMMU
02.249: sb700_early_setup()
02.250: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
02.251: CBFS: Locating 'cmos_layout.bin'
02.251: CBFS: Found @ offset 2b0c0 size e88
02.251: sb700_devices_por_init()
02.251: sb700_devices_por_init(): SMBus Device, BDF:0-20-0
02.257: SMBus controller enabled, sb revision is A15
02.258: sb700_devices_por_init: Disabling ISA DMA support
02.258: sb700_devices_por_init(): IDE Device, BDF:0-20-1
02.260: sb700_devices_por_init(): LPC Device, BDF:0-20-3
02.261: sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
02.261: sb700_devices_por_init(): SATA Device, BDF:0-17-0
02.261: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
02.261: CBFS: Locating 'cmos_layout.bin'
02.261: CBFS: Found @ offset 2b0c0 size e88
02.262: sb700_pmio_por_init()
02.262: start_other_cores()
02.262: init node: 00  cores: 07 pass 1
02.262: Start other core - nodeid: 00  cores: 07
02.263: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
02.330: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
02.330: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
02.340: init node: 01  cores: 07 pass 1
02.342: Start other core - nodeid: 01  cores: 07
02.347: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
02.489: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
02.506: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
02.507: init node: 02  cores: 07 pass 1
02.508: Start other core - nodeid: 02  cores: 07
02.510: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
02.657: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
02.674: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
02.688: init node: 03  cores: 07 pass 1
02.689: Start other core - nodeid: 03  cores: 07
02.691: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
02.813: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
02.852: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
02.866: started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
02.869: * AP 01started
02.870: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
02.875: * AP 02started
02.875: get_boot_apic_id: using 3 as APIC ID for node 0, core 3
02.876: * AP 03started
02.876: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
02.876: * AP 04started
02.876: get_boot_apic_id: using 5 as APIC ID for node 0, core 5
02.879: * AP 05started
02.880: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
02.880: * AP 06started
02.880: get_boot_apic_id: using 7 as APIC ID for node 0, core 7
02.880: * AP 07started
02.880: get_boot_apic_id: using 9 as APIC ID for node 1, core 1
02.884: * AP 09started
02.884: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
02.884: * AP 0astarted
02.884: get_boot_apic_id: using 11 as APIC ID for node 1, core 3
02.884: * AP 0bstarted
02.885: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
02.888: * AP 0cstarted
02.888: get_boot_apic_id: using 13 as APIC ID for node 1, core 5
02.888: * AP 0dstarted
02.889: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
02.889: * AP 0estarted
02.890: get_boot_apic_id: using 15 as APIC ID for node 1, core 7
02.891: * AP 0fstarted
02.891: get_boot_apic_id: using 33 as APIC ID for node 2, core 1
02.891: * AP 21started
02.891: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
02.891: * AP 22started
02.891: get_boot_apic_id: using 35 as APIC ID for node 2, core 3
02.891: * AP 23started
02.891: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
02.891: * AP 24started
02.891: get_boot_apic_id: using 37 as APIC ID for node 2, core 5
02.891: * AP 25started
02.891: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
02.891: * AP 26started
02.891: get_boot_apic_id: using 39 as APIC ID for node 2, core 7
02.891: * AP 27started
02.891: get_boot_apic_id: using 41 as APIC ID for node 3, core 1
02.891: * AP 29started
02.891: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
02.891: * AP 2astarted
02.892: get_boot_apic_id: using 43 as APIC ID for node 3, core 3
02.892: * AP 2bstarted
02.892: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
02.892: * AP 2cstarted
02.892: get_boot_apic_id: using 45 as APIC ID for node 3, core 5
02.892: * AP 2dstarted
02.892: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
02.892: * AP 2estarted
02.892: get_boot_apic_id: using 47 as APIC ID for node 3, core 7
02.892: * AP 2fstarted
02.892: 
02.892: 
02.892: Begin FIDVID MSR 0xc0010071 0x52c2009e 0x3c025408
02.892: End FIDVIDMSR 0xc0010071 0x52c2009e 0x3c025408
02.893: sr5650_htinit: Node 0 Link 1, HT freq=e.
02.893: sr5650_htinit: HT3 mode
02.893: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
02.893: CBFS: Locating 'cmos_layout.bin'
02.893: CBFS: Found @ offset 2b0c0 size e88
02.893: Node 00 DIMM voltage set to index 00
02.893: Node 01 DIMM voltage set to index 00
02.893: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
02.893: CBFS: Locating 'cmos_layout.bin'
02.893: CBFS: Found @ offset 2b0c0 size e88
02.894: stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
02.894: * AP 01stopped
02.894: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
02.894: * AP 02stopped
02.894: get_boot_apic_id: using 3 as APIC ID for node 0, core 3
02.894: * AP 03stopped
02.894: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
02.894: * AP 04stopped
02.894: get_boot_apic_id: using 5 as APIC ID for node 0, core 5
02.894: * AP 05stopped
02.894: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
02.894: * AP 06stopped
02.894: get_boot_apic_id: using 7 as APIC ID for node 0, core 7
02.894: * AP 07stopped
02.894: get_boot_apic_id: using 9 as APIC ID for node 1, core 1
02.894: * AP 09stopped
02.894: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
02.894: * AP 0astopped
02.894: get_boot_apic_id: using 11 as APIC ID for node 1, core 3
02.894: * AP 0bstopped
02.894: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
02.894: * AP 0cstopped
02.894: get_boot_apic_id: using 13 as APIC ID for node 1, core 5
02.894: * AP 0dstopped
02.894: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
02.894: * AP 0estopped
02.894: get_boot_apic_id: using 15 as APIC ID for node 1, core 7
02.894: * AP 0fstopped
02.894: get_boot_apic_id: using 33 as APIC ID for node 2, core 1
02.894: * AP 21stopped
02.894: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
02.894: * AP 22stopped
02.894: get_boot_apic_id: using 35 as APIC ID for node 2, core 3
02.894: * AP 23stopped
02.894: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
02.894: * AP 24stopped
02.894: get_boot_apic_id: using 37 as APIC ID for node 2, core 5
02.894: * AP 25stopped
02.894: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
02.894: * AP 26stopped
02.894: get_boot_apic_id: using 39 as APIC ID for node 2, core 7
02.895: * AP 27stopped
02.895: get_boot_apic_id: using 41 as APIC ID for node 3, core 1
02.895: * AP 29stopped
02.895: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
02.895: * AP 2astopped
02.895: get_boot_apic_id: using 43 as APIC ID for node 3, core 3
02.895: * AP 2bstopped
02.895: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
02.895: * AP 2cstopped
02.895: get_boot_apic_id: using 45 as APIC ID for node 3, core 5
02.895: * AP 2dstopped
02.895: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
02.895: * AP 2estopped
02.895: get_boot_apic_id: using 47 as APIC ID for node 3, core 7
02.895: * AP 2fstopped
02.895: 
02.895: fill_mem_ctrl() detected 4 nodes
02.895: raminit_amdmct()
02.895: raminit_amdmct begin:
02.896: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
02.896: CBFS: Locating 'cmos_layout.bin'
02.896: CBFS: Found @ offset 2b0c0 size e88
02.896: mctAutoInitMCT_D: mct_init Node 0
02.897: mctAutoInitMCT_D: mct_InitialMCT_D
02.897: mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
02.897: mctAutoInitMCT_D: mctSMBhub_Init
02.897: activate_spd_rom() for node 00
02.897: enable_spd_node0()
02.897: mctAutoInitMCT_D: mct_preInitDCT
02.898: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
02.898: CBFS: Locating 'cmos_layout.bin'
02.898: CBFS: Found @ offset 2b0c0 size e88
04.507: <09> DIMMPresence: DIMMValid=f
04.507: <09> DIMMPresence: DIMMPresent=f
04.507: <09> DIMMPresence: RegDIMMPresent=f
04.507: <09> DIMMPresence: LRDIMMPresent=0
04.507: <09> DIMMPresence: DimmECCPresent=f
04.507: <09> DIMMPresence: DimmPARPresent=0
04.507: <09> DIMMPresence: Dimmx4Present=f
04.507: <09> DIMMPresence: Dimmx8Present=0
04.507: <09> DIMMPresence: Dimmx16Present=0
04.507: <09> DIMMPresence: DimmPlPresent=0
04.507: <09> DIMMPresence: DimmDRPresent=f
04.507: <09> DIMMPresence: DimmQRPresent=0
04.507: <09> DIMMPresence: DATAload[0]=4
04.507: <09> DIMMPresence: MAload[0]=40
04.507: <09> DIMMPresence: MAdimms[0]=2
04.507: <09> DIMMPresence: DATAload[1]=4
04.507: <09> DIMMPresence: MAload[1]=40
04.507: <09> DIMMPresence: MAdimms[1]=2
04.507: <09> DIMMPresence: Status 2005
04.507: <09> DIMMPresence: ErrStatus 0
04.507: <09> DIMMPresence: ErrCode 0
04.507: <09> DIMMPresence: Done
04.507: 
04.507: <09><09>DCTPreInit_D: mct_DIMMPresence Done
04.508: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
04.508: CBFS: Locating 's3nv'
04.508: CBFS: Found @ offset 2fec0 size 10000
04.508: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
04.508: CBFS: Locating 's3nv'
04.508: CBFS: Found @ offset 2fec0 size 10000
04.508: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
04.508: CBFS: Locating 'cmos_layout.bin'
04.508: CBFS: Found @ offset 2b0c0 size e88
04.509: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
04.509: CBFS: Locating 'cmos_layout.bin'
04.509: CBFS: Found @ offset 2b0c0 size e88
04.509: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
04.509: CBFS: Locating 'cmos_layout.bin'
04.509: CBFS: Found @ offset 2b0c0 size e88
04.509: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
04.509: CBFS: Locating 'cmos_layout.bin'
04.509: CBFS: Found @ offset 2b0c0 size e88
04.509: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
04.509: CBFS: Locating 'cmos_layout.bin'
04.509: CBFS: Found @ offset 2b0c0 size e88
04.510: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
04.510: CBFS: Locating 'cmos_layout.bin'
04.510: CBFS: Found @ offset 2b0c0 size e88
04.510: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
04.510: CBFS: Locating 'cmos_layout.bin'
04.510: CBFS: Found @ offset 2b0c0 size e88
04.510: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
04.510: CBFS: Locating 'cmos_layout.bin'
04.510: CBFS: Found @ offset 2b0c0 size e88
04.510: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
04.510: CBFS: Locating 'cmos_layout.bin'
04.510: CBFS: Found @ offset 2b0c0 size e88
04.510: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
04.510: CBFS: Locating 'cmos_layout.bin'
04.510: CBFS: Found @ offset 2b0c0 size e88
04.511: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
04.511: CBFS: Locating 'cmos_layout.bin'
04.511: CBFS: Found @ offset 2b0c0 size e88
04.511: mctAutoInitMCT_D: mct_init Node 1
04.511: mctAutoInitMCT_D: mct_InitialMCT_D
04.511: mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
04.511: mctAutoInitMCT_D: mctSMBhub_Init
04.511: activate_spd_rom() for node 01
04.511: enable_spd_node1()
04.511: mctAutoInitMCT_D: mct_preInitDCT
04.511: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
04.511: CBFS: Locating 'cmos_layout.bin'
04.511: CBFS: Found @ offset 2b0c0 size e88
06.119: <09> DIMMPresence: DIMMValid=f
06.119: <09> DIMMPresence: DIMMPresent=f
06.119: <09> DIMMPresence: RegDIMMPresent=f
06.119: <09> DIMMPresence: LRDIMMPresent=0
06.119: <09> DIMMPresence: DimmECCPresent=f
06.119: <09> DIMMPresence: DimmPARPresent=0
06.119: <09> DIMMPresence: Dimmx4Present=f
06.119: <09> DIMMPresence: Dimmx8Present=0
06.119: <09> DIMMPresence: Dimmx16Present=0
06.119: <09> DIMMPresence: DimmPlPresent=0
06.119: <09> DIMMPresence: DimmDRPresent=f
06.119: <09> DIMMPresence: DimmQRPresent=0
06.119: <09> DIMMPresence: DATAload[0]=4
06.119: <09> DIMMPresence: MAload[0]=40
06.119: <09> DIMMPresence: MAdimms[0]=2
06.119: <09> DIMMPresence: DATAload[1]=4
06.119: <09> DIMMPresence: MAload[1]=40
06.119: <09> DIMMPresence: MAdimms[1]=2
06.119: <09> DIMMPresence: Status 2005
06.119: <09> DIMMPresence: ErrStatus 0
06.119: <09> DIMMPresence: ErrCode 0
06.119: <09> DIMMPresence: Done
06.119: 
06.119: <09><09>DCTPreInit_D: mct_DIMMPresence Done
06.119: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
06.119: CBFS: Locating 's3nv'
06.119: CBFS: Found @ offset 2fec0 size 10000
06.119: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
06.119: CBFS: Locating 's3nv'
06.120: CBFS: Found @ offset 2fec0 size 10000
06.120: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
06.120: CBFS: Locating 'cmos_layout.bin'
06.120: CBFS: Found @ offset 2b0c0 size e88
06.120: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
06.120: CBFS: Locating 'cmos_layout.bin'
06.120: CBFS: Found @ offset 2b0c0 size e88
06.120: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
06.120: CBFS: Locating 'cmos_layout.bin'
06.120: CBFS: Found @ offset 2b0c0 size e88
06.120: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
06.120: CBFS: Locating 'cmos_layout.bin'
06.120: CBFS: Found @ offset 2b0c0 size e88
06.120: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
06.120: CBFS: Locating 'cmos_layout.bin'
06.120: CBFS: Found @ offset 2b0c0 size e88
06.121: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
06.121: CBFS: Locating 'cmos_layout.bin'
06.121: CBFS: Found @ offset 2b0c0 size e88
06.121: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
06.121: CBFS: Locating 'cmos_layout.bin'
06.121: CBFS: Found @ offset 2b0c0 size e88
06.121: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
06.121: CBFS: Locating 'cmos_layout.bin'
06.121: CBFS: Found @ offset 2b0c0 size e88
06.121: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
06.121: CBFS: Locating 'cmos_layout.bin'
06.121: CBFS: Found @ offset 2b0c0 size e88
06.121: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
06.121: CBFS: Locating 'cmos_layout.bin'
06.121: CBFS: Found @ offset 2b0c0 size e88
06.122: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
06.122: CBFS: Locating 'cmos_layout.bin'
06.122: CBFS: Found @ offset 2b0c0 size e88
06.122: mctAutoInitMCT_D: mct_init Node 2
06.122: mctAutoInitMCT_D: mct_InitialMCT_D
06.122: mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
06.122: mctAutoInitMCT_D: mctSMBhub_Init
06.122: activate_spd_rom() for node 02
06.122: enable_spd_node2()
06.122: mctAutoInitMCT_D: mct_preInitDCT
06.122: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
06.122: CBFS: Locating 'cmos_layout.bin'
06.122: CBFS: Found @ offset 2b0c0 size e88
07.730: <09> DIMMPresence: DIMMValid=f
07.730: <09> DIMMPresence: DIMMPresent=f
07.730: <09> DIMMPresence: RegDIMMPresent=f
07.730: <09> DIMMPresence: LRDIMMPresent=0
07.730: <09> DIMMPresence: DimmECCPresent=f
07.730: <09> DIMMPresence: DimmPARPresent=0
07.730: <09> DIMMPresence: Dimmx4Present=f
07.730: <09> DIMMPresence: Dimmx8Present=0
07.730: <09> DIMMPresence: Dimmx16Present=0
07.730: <09> DIMMPresence: DimmPlPresent=0
07.730: <09> DIMMPresence: DimmDRPresent=f
07.730: <09> DIMMPresence: DimmQRPresent=0
07.730: <09> DIMMPresence: DATAload[0]=4
07.730: <09> DIMMPresence: MAload[0]=40
07.730: <09> DIMMPresence: MAdimms[0]=2
07.730: <09> DIMMPresence: DATAload[1]=4
07.730: <09> DIMMPresence: MAload[1]=40
07.730: <09> DIMMPresence: MAdimms[1]=2
07.730: <09> DIMMPresence: Status 2005
07.730: <09> DIMMPresence: ErrStatus 0
07.730: <09> DIMMPresence: ErrCode 0
07.730: <09> DIMMPresence: Done
07.730: 
07.730: <09><09>DCTPreInit_D: mct_DIMMPresence Done
07.730: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
07.730: CBFS: Locating 's3nv'
07.730: CBFS: Found @ offset 2fec0 size 10000
07.730: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
07.730: CBFS: Locating 's3nv'
07.730: CBFS: Found @ offset 2fec0 size 10000
07.731: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
07.731: CBFS: Locating 'cmos_layout.bin'
07.731: CBFS: Found @ offset 2b0c0 size e88
07.731: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
07.731: CBFS: Locating 'cmos_layout.bin'
07.731: CBFS: Found @ offset 2b0c0 size e88
07.731: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
07.731: CBFS: Locating 'cmos_layout.bin'
07.731: CBFS: Found @ offset 2b0c0 size e88
07.731: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
07.731: CBFS: Locating 'cmos_layout.bin'
07.731: CBFS: Found @ offset 2b0c0 size e88
07.731: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
07.731: CBFS: Locating 'cmos_layout.bin'
07.731: CBFS: Found @ offset 2b0c0 size e88
07.732: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
07.732: CBFS: Locating 'cmos_layout.bin'
07.732: CBFS: Found @ offset 2b0c0 size e88
07.732: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
07.732: CBFS: Locating 'cmos_layout.bin'
07.732: CBFS: Found @ offset 2b0c0 size e88
07.732: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
07.732: CBFS: Locating 'cmos_layout.bin'
07.732: CBFS: Found @ offset 2b0c0 size e88
07.732: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
07.732: CBFS: Locating 'cmos_layout.bin'
07.732: CBFS: Found @ offset 2b0c0 size e88
07.732: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
07.732: CBFS: Locating 'cmos_layout.bin'
07.732: CBFS: Found @ offset 2b0c0 size e88
07.733: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
07.733: CBFS: Locating 'cmos_layout.bin'
07.733: CBFS: Found @ offset 2b0c0 size e88
07.733: mctAutoInitMCT_D: mct_init Node 3
07.733: mctAutoInitMCT_D: mct_InitialMCT_D
07.733: mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
07.733: mctAutoInitMCT_D: mctSMBhub_Init
07.733: activate_spd_rom() for node 03
07.733: enable_spd_node3()
07.733: mctAutoInitMCT_D: mct_preInitDCT
07.733: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
07.733: CBFS: Locating 'cmos_layout.bin'
07.733: CBFS: Found @ offset 2b0c0 size e88
09.341: <09> DIMMPresence: DIMMValid=f
09.341: <09> DIMMPresence: DIMMPresent=f
09.341: <09> DIMMPresence: RegDIMMPresent=f
09.341: <09> DIMMPresence: LRDIMMPresent=0
09.341: <09> DIMMPresence: DimmECCPresent=f
09.341: <09> DIMMPresence: DimmPARPresent=0
09.341: <09> DIMMPresence: Dimmx4Present=f
09.341: <09> DIMMPresence: Dimmx8Present=0
09.341: <09> DIMMPresence: Dimmx16Present=0
09.341: <09> DIMMPresence: DimmPlPresent=0
09.341: <09> DIMMPresence: DimmDRPresent=f
09.341: <09> DIMMPresence: DimmQRPresent=0
09.341: <09> DIMMPresence: DATAload[0]=4
09.341: <09> DIMMPresence: MAload[0]=40
09.341: <09> DIMMPresence: MAdimms[0]=2
09.341: <09> DIMMPresence: DATAload[1]=4
09.341: <09> DIMMPresence: MAload[1]=40
09.341: <09> DIMMPresence: MAdimms[1]=2
09.341: <09> DIMMPresence: Status 2005
09.341: <09> DIMMPresence: ErrStatus 0
09.341: <09> DIMMPresence: ErrCode 0
09.341: <09> DIMMPresence: Done
09.341: 
09.341: <09><09>DCTPreInit_D: mct_DIMMPresence Done
09.341: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.341: CBFS: Locating 's3nv'
09.342: CBFS: Found @ offset 2fec0 size 10000
09.342: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.342: CBFS: Locating 's3nv'
09.342: CBFS: Found @ offset 2fec0 size 10000
09.342: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.342: CBFS: Locating 'cmos_layout.bin'
09.342: CBFS: Found @ offset 2b0c0 size e88
09.342: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.342: CBFS: Locating 'cmos_layout.bin'
09.342: CBFS: Found @ offset 2b0c0 size e88
09.342: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.342: CBFS: Locating 'cmos_layout.bin'
09.342: CBFS: Found @ offset 2b0c0 size e88
09.342: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.342: CBFS: Locating 'cmos_layout.bin'
09.342: CBFS: Found @ offset 2b0c0 size e88
09.343: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.343: CBFS: Locating 'cmos_layout.bin'
09.343: CBFS: Found @ offset 2b0c0 size e88
09.343: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.343: CBFS: Locating 'cmos_layout.bin'
09.343: CBFS: Found @ offset 2b0c0 size e88
09.343: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.343: CBFS: Locating 'cmos_layout.bin'
09.343: CBFS: Found @ offset 2b0c0 size e88
09.343: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.343: CBFS: Locating 'cmos_layout.bin'
09.343: CBFS: Found @ offset 2b0c0 size e88
09.343: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.343: CBFS: Locating 'cmos_layout.bin'
09.343: CBFS: Found @ offset 2b0c0 size e88
09.344: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.344: CBFS: Locating 'cmos_layout.bin'
09.344: CBFS: Found @ offset 2b0c0 size e88
09.344: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.344: CBFS: Locating 'cmos_layout.bin'
09.344: CBFS: Found @ offset 2b0c0 size e88
09.344: mctAutoInitMCT_D: mct_init Node 4
09.344: mctAutoInitMCT_D: mct_init Node 5
09.344: mctAutoInitMCT_D: mct_init Node 6
09.344: mctAutoInitMCT_D: mct_init Node 7
09.344: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.344: CBFS: Locating 'cmos_layout.bin'
09.345: CBFS: Found @ offset 2b0c0 size e88
09.345: mctAutoInitMCT_D: DIMMSetVoltage
09.345: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.345: CBFS: Locating 'cmos_layout.bin'
09.345: CBFS: Found @ offset 2b0c0 size e88
09.346: Node 00 DIMM voltage set to index 00
09.346: Node 01 DIMM voltage set to index 00
09.446: mctAutoInitMCT_D: mctSMBhub_Init
09.446: activate_spd_rom() for node 00
09.446: enable_spd_node0()
09.446: mctAutoInitMCT_D: mct_initDCT
09.446: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.446: CBFS: Locating 'cmos_layout.bin'
09.446: CBFS: Found @ offset 2b0c0 size e88
09.446: SPDCalcWidth: Status 2005
09.446: SPDCalcWidth: ErrStatus 0
09.446: SPDCalcWidth: ErrCode 0
09.447: SPDCalcWidth: Done
09.447: <09><09>DCTInit_D: mct_SPDCalcWidth Done
09.447: AutoCycTiming_D: Start
09.447: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.447: CBFS: Locating 'cmos_layout.bin'
09.447: CBFS: Found @ offset 2b0c0 size e88
09.447: GetPresetmaxF_D: Start
09.447: GetPresetmaxF_D: Done
09.447: SPDGetTCL_D: Start
09.448: SPDGetTCL_D: DIMMCASL 5
09.448: SPDGetTCL_D: DIMMAutoSpeed 4
09.448: SPDGetTCL_D: Status 2005
09.448: SPDGetTCL_D: ErrStatus 0
09.448: SPDGetTCL_D: ErrCode 0
09.448: SPDGetTCL_D: Done
09.448: 
09.448: SPD2ndTiming: Start
09.449: SPD2ndTiming: Done
09.449: AutoCycTiming: Status 2005
09.449: AutoCycTiming: ErrStatus 0
09.449: AutoCycTiming: ErrCode 0
09.449: AutoCycTiming: Done
09.449: 
09.449: <09><09>DCTInit_D: AutoCycTiming_D Done
09.450: SPDSetBanks: CSPresent f
09.450: SPDSetBanks: Status 2005
09.450: SPDSetBanks: ErrStatus 0
09.450: SPDSetBanks: ErrCode 0
09.450: SPDSetBanks: Done
09.450: 
09.450: AfterStitch pDCTstat->NodeSysBase = 0
09.450: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7ffffff
09.450: StitchMemory: Status 2005
09.450: StitchMemory: ErrStatus 0
09.450: StitchMemory: ErrCode 0
09.450: StitchMemory: Done
09.450: 
09.450: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.450: CBFS: Locating 'cmos_layout.bin'
09.450: CBFS: Found @ offset 2b0c0 size e88
09.451: InterleaveBanks_D: Status 2005
09.451: InterleaveBanks_D: ErrStatus 0
09.451: InterleaveBanks_D: ErrCode 0
09.451: InterleaveBanks_D: Done
09.451: 
09.451: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.451: CBFS: Locating 'cmos_layout.bin'
09.451: CBFS: Found @ offset 2b0c0 size e88
09.452: AutoConfig_D: DramControl:     00002a06
09.452: AutoConfig_D: DramTimingLo:    00000000
09.452: AutoConfig_D: DramConfigMisc:  00000000
09.452: AutoConfig_D: DramConfigMisc2: 00000000
09.452: AutoConfig_D: DramConfigLo:    03083000
09.452: AutoConfig_D: DramConfigHi:    0f090084
09.452: InitDDRPhy: Start
09.453: InitDDRPhy: Done
09.453: mct_SetDramConfigHi_D: Start
09.454: set_2t_configuration: Start
09.454: set_2t_configuration: Done
09.454: mct_BeforePlatformSpec: Start
09.454: mct_BeforePlatformSpec: Done
09.454: mct_PlatformSpec: Start
09.454: Programmed DCT 0 timing/termination pattern 00000000 10222222
09.454: mct_PlatformSpec: Done
09.454: mct_SetDramConfigHi_D: DramConfigHi:    0f090084
09.454: *
09.454: mct_SetDramConfigHi_D: Done
09.454: mct_EarlyArbEn_D: Start
09.454: mct_EarlyArbEn_D: Done
09.454: AutoConfig: Status 2005
09.454: AutoConfig: ErrStatus 0
09.454: AutoConfig: ErrCode 0
09.454: AutoConfig: Done
09.454: 
09.454: <09><09>DCTInit_D: AutoConfig_D Done
09.454: <09><09>DCTInit_D: PlatformSpec_D Done
09.454: <09><09>DCTFinalInit_D: StartupDCT_D Start
09.455: mct_BeforeDramInit_Prod_D: Start
09.455: mct_ProgramODT_D: Start
09.455: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
09.455: mct_ProgramODT_D: Done
09.455: mct_BeforeDramInit_Prod_D: Done
09.455: mct_DramInit_Sw_D: Start
09.455: mct_DCTAccessDone: Start
09.455: mct_DCTAccessDone: Done
09.456: mct_DramControlReg_Init_D: Start
09.457: mct_DramControlReg_Init_D: F2xA8: 00000300
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC0: 02
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC1: 00
09.457: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC3: 05
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC4: 05
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC5: 05
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC6: 00
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC7: 00
09.457: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC9: 0d
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC10: 00
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC11: 00
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC12: 00
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC13: 00
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC14: 00
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC15: 00
09.457: mct_DramControlReg_Init_D: F2xA8: 00000c00
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
09.457: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
09.457: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 00
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
09.457: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
09.457: mct_DramControlReg_Init_D: Done
09.458: DIMM 0 RttWr: 2
09.458: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.458: mct_SendMrsCmd: Start
09.458: mct_SendMrsCmd: Done
09.458: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
09.458: mct_SendMrsCmd: Start
09.458: mct_SendMrsCmd: Done
09.459: DIMM 0 RttNom: 3
09.459: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.459: mct_SendMrsCmd: Start
09.459: mct_SendMrsCmd: Done
09.459: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001318
09.459: mct_SendMrsCmd: Start
09.459: mct_SendMrsCmd: Done
09.459: DIMM 0 RttWr: 2
09.459: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.459: mct_SendMrsCmd: Start
09.459: mct_SendMrsCmd: Done
09.459: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
09.459: mct_SendMrsCmd: Start
09.459: mct_SendMrsCmd: Done
09.459: DIMM 0 RttNom: 3
09.459: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.459: mct_SendMrsCmd: Start
09.459: mct_SendMrsCmd: Done
09.459: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201318
09.459: mct_SendMrsCmd: Start
09.459: mct_SendMrsCmd: Done
09.459: DIMM 1 RttWr: 2
09.459: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.459: mct_SendMrsCmd: Start
09.459: mct_SendMrsCmd: Done
09.459: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
09.459: mct_SendMrsCmd: Start
09.459: mct_SendMrsCmd: Done
09.459: DIMM 1 RttNom: 3
09.459: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.459: mct_SendMrsCmd: Start
09.459: mct_SendMrsCmd: Done
09.459: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401318
09.459: mct_SendMrsCmd: Start
09.459: mct_SendMrsCmd: Done
09.459: DIMM 1 RttWr: 2
09.459: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.459: mct_SendMrsCmd: Start
09.459: mct_SendMrsCmd: Done
09.459: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
09.459: mct_SendMrsCmd: Start
09.459: mct_SendMrsCmd: Done
09.459: DIMM 1 RttNom: 3
09.459: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.459: mct_SendMrsCmd: Start
09.459: mct_SendMrsCmd: Done
09.459: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601318
09.459: mct_SendMrsCmd: Start
09.459: mct_SendMrsCmd: Done
09.459: mct_SendZQCmd: Start
09.459: mct_SendZQCmd: Done
09.459: mct_SendZQCmd: Start
09.459: mct_SendZQCmd: Done
09.459: mct_DCTAccessDone: Start
09.460: mct_DCTAccessDone: Done
09.460: mct_DramInit_Sw_D: Done
09.460: <09><09>DCTFinalInit_D: StartupDCT_D Done
09.460: SPDCalcWidth: Status 2005
09.460: SPDCalcWidth: ErrStatus 0
09.460: SPDCalcWidth: ErrCode 0
09.460: SPDCalcWidth: Done
09.460: <09><09>DCTInit_D: mct_SPDCalcWidth Done
09.460: AutoCycTiming_D: Start
09.460: SPD2ndTiming: Start
09.460: SPD2ndTiming: Done
09.460: AutoCycTiming: Status 2005
09.460: AutoCycTiming: ErrStatus 0
09.460: AutoCycTiming: ErrCode 0
09.460: AutoCycTiming: Done
09.460: 
09.460: <09><09>DCTInit_D: AutoCycTiming_D Done
09.460: <09><09>DCTInit_D: enabling intra-channel clock skew
09.460: SPDSetBanks: CSPresent f
09.460: SPDSetBanks: Status 2005
09.460: SPDSetBanks: ErrStatus 0
09.460: SPDSetBanks: ErrCode 0
09.460: SPDSetBanks: Done
09.460: 
09.460: AfterStitch pDCTstat->NodeSysBase = 0
09.460: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffffe
09.460: StitchMemory: Status 2005
09.460: StitchMemory: ErrStatus 0
09.460: StitchMemory: ErrCode 0
09.460: StitchMemory: Done
09.460: 
09.461: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.461: CBFS: Locating 'cmos_layout.bin'
09.461: CBFS: Found @ offset 2b0c0 size e88
09.461: InterleaveBanks_D: Status 2005
09.461: InterleaveBanks_D: ErrStatus 0
09.461: InterleaveBanks_D: ErrCode 0
09.461: InterleaveBanks_D: Done
09.461: 
09.461: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.461: CBFS: Locating 'cmos_layout.bin'
09.461: CBFS: Found @ offset 2b0c0 size e88
09.461: AutoConfig_D: DramControl:     00002a06
09.461: AutoConfig_D: DramTimingLo:    00000000
09.461: AutoConfig_D: DramConfigMisc:  00000000
09.461: AutoConfig_D: DramConfigMisc2: 00000000
09.461: AutoConfig_D: DramConfigLo:    03083000
09.461: AutoConfig_D: DramConfigHi:    0f090084
09.461: InitDDRPhy: Start
09.461: InitDDRPhy: Done
09.462: mct_SetDramConfigHi_D: Start
09.462: set_2t_configuration: Start
09.462: set_2t_configuration: Done
09.462: mct_BeforePlatformSpec: Start
09.462: mct_BeforePlatformSpec: Done
09.462: mct_PlatformSpec: Start
09.462: Programmed DCT 1 timing/termination pattern 00000000 10222222
09.462: mct_PlatformSpec: Done
09.462: mct_SetDramConfigHi_D: DramConfigHi:    0f090084
09.462: *
09.462: mct_SetDramConfigHi_D: Done
09.462: mct_EarlyArbEn_D: Start
09.462: mct_EarlyArbEn_D: Done
09.462: AutoConfig: Status 2005
09.462: AutoConfig: ErrStatus 0
09.462: AutoConfig: ErrCode 0
09.462: AutoConfig: Done
09.462: 
09.462: <09><09>DCTInit_D: AutoConfig_D Done
09.462: <09><09>DCTInit_D: PlatformSpec_D Done
09.462: <09><09>DCTFinalInit_D: StartupDCT_D Start
09.462: mct_BeforeDramInit_Prod_D: Start
09.462: mct_ProgramODT_D: Start
09.462: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
09.462: mct_ProgramODT_D: Done
09.462: mct_BeforeDramInit_Prod_D: Done
09.462: mct_DramInit_Sw_D: Start
09.462: mct_DCTAccessDone: Start
09.462: mct_DCTAccessDone: Done
09.463: mct_DramControlReg_Init_D: Start
09.463: mct_DramControlReg_Init_D: F2xA8: 00000300
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC0: 02
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC1: 00
09.463: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC3: 05
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC4: 05
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC5: 05
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC6: 00
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC7: 00
09.463: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC9: 0d
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC10: 00
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC11: 00
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC12: 00
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC13: 00
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC14: 00
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC15: 00
09.463: mct_DramControlReg_Init_D: F2xA8: 00000c00
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00
09.463: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00
09.463: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 00
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00
09.463: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00
09.463: mct_DramControlReg_Init_D: Done
09.464: DIMM 0 RttWr: 2
09.464: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.464: mct_SendMrsCmd: Start
09.464: mct_SendMrsCmd: Done
09.464: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
09.464: mct_SendMrsCmd: Start
09.464: mct_SendMrsCmd: Done
09.464: DIMM 0 RttNom: 3
09.464: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.464: mct_SendMrsCmd: Start
09.464: mct_SendMrsCmd: Done
09.464: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001318
09.464: mct_SendMrsCmd: Start
09.464: mct_SendMrsCmd: Done
09.464: DIMM 0 RttWr: 2
09.464: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.464: mct_SendMrsCmd: Start
09.464: mct_SendMrsCmd: Done
09.464: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
09.464: mct_SendMrsCmd: Start
09.464: mct_SendMrsCmd: Done
09.464: DIMM 0 RttNom: 3
09.464: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.464: mct_SendMrsCmd: Start
09.464: mct_SendMrsCmd: Done
09.464: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201318
09.464: mct_SendMrsCmd: Start
09.464: mct_SendMrsCmd: Done
09.464: DIMM 1 RttWr: 2
09.464: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.464: mct_SendMrsCmd: Start
09.464: mct_SendMrsCmd: Done
09.464: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
09.464: mct_SendMrsCmd: Start
09.464: mct_SendMrsCmd: Done
09.464: DIMM 1 RttNom: 3
09.464: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.464: mct_SendMrsCmd: Start
09.464: mct_SendMrsCmd: Done
09.464: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401318
09.464: mct_SendMrsCmd: Start
09.464: mct_SendMrsCmd: Done
09.464: DIMM 1 RttWr: 2
09.464: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.464: mct_SendMrsCmd: Start
09.464: mct_SendMrsCmd: Done
09.464: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
09.464: mct_SendMrsCmd: Start
09.464: mct_SendMrsCmd: Done
09.464: DIMM 1 RttNom: 3
09.465: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.465: mct_SendMrsCmd: Start
09.465: mct_SendMrsCmd: Done
09.465: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601318
09.465: mct_SendMrsCmd: Start
09.465: mct_SendMrsCmd: Done
09.465: mct_SendZQCmd: Start
09.465: mct_SendZQCmd: Done
09.465: mct_SendZQCmd: Start
09.465: mct_SendZQCmd: Done
09.465: mct_DCTAccessDone: Start
09.465: mct_DCTAccessDone: Done
09.465: mct_DramInit_Sw_D: Done
09.465: <09><09>DCTFinalInit_D: StartupDCT_D Done
09.465: mctAutoInitMCT_D: mctSMBhub_Init
09.465: activate_spd_rom() for node 01
09.465: enable_spd_node1()
09.465: mctAutoInitMCT_D: mct_initDCT
09.465: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.465: CBFS: Locating 'cmos_layout.bin'
09.465: CBFS: Found @ offset 2b0c0 size e88
09.465: SPDCalcWidth: Status 2005
09.465: SPDCalcWidth: ErrStatus 0
09.465: SPDCalcWidth: ErrCode 0
09.465: SPDCalcWidth: Done
09.465: <09><09>DCTInit_D: mct_SPDCalcWidth Done
09.465: AutoCycTiming_D: Start
09.465: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.465: CBFS: Locating 'cmos_layout.bin'
09.465: CBFS: Found @ offset 2b0c0 size e88
09.466: GetPresetmaxF_D: Start
09.466: GetPresetmaxF_D: Done
09.466: SPDGetTCL_D: Start
09.466: SPDGetTCL_D: DIMMCASL 5
09.466: SPDGetTCL_D: DIMMAutoSpeed 4
09.466: SPDGetTCL_D: Status 2005
09.466: SPDGetTCL_D: ErrStatus 0
09.466: SPDGetTCL_D: ErrCode 0
09.466: SPDGetTCL_D: Done
09.466: 
09.466: SPD2ndTiming: Start
09.466: SPD2ndTiming: Done
09.466: AutoCycTiming: Status 2005
09.466: AutoCycTiming: ErrStatus 0
09.466: AutoCycTiming: ErrCode 0
09.466: AutoCycTiming: Done
09.466: 
09.466: <09><09>DCTInit_D: AutoCycTiming_D Done
09.466: SPDSetBanks: CSPresent f
09.466: SPDSetBanks: Status 2005
09.466: SPDSetBanks: ErrStatus 0
09.466: SPDSetBanks: ErrCode 0
09.466: SPDSetBanks: Done
09.466: 
09.466: AfterStitch pDCTstat->NodeSysBase = 0
09.466: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7ffffff
09.466: StitchMemory: Status 2005
09.466: StitchMemory: ErrStatus 0
09.466: StitchMemory: ErrCode 0
09.466: StitchMemory: Done
09.466: 
09.466: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.466: CBFS: Locating 'cmos_layout.bin'
09.466: CBFS: Found @ offset 2b0c0 size e88
09.467: InterleaveBanks_D: Status 2005
09.467: InterleaveBanks_D: ErrStatus 0
09.467: InterleaveBanks_D: ErrCode 0
09.467: InterleaveBanks_D: Done
09.467: 
09.467: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.467: CBFS: Locating 'cmos_layout.bin'
09.467: CBFS: Found @ offset 2b0c0 size e88
09.467: AutoConfig_D: DramControl:     00002a06
09.467: AutoConfig_D: DramTimingLo:    00000000
09.467: AutoConfig_D: DramConfigMisc:  00000000
09.467: AutoConfig_D: DramConfigMisc2: 00000000
09.467: AutoConfig_D: DramConfigLo:    03083000
09.467: AutoConfig_D: DramConfigHi:    0f090084
09.467: InitDDRPhy: Start
09.467: InitDDRPhy: Done
09.467: mct_SetDramConfigHi_D: Start
09.467: set_2t_configuration: Start
09.467: set_2t_configuration: Done
09.467: mct_BeforePlatformSpec: Start
09.467: mct_BeforePlatformSpec: Done
09.467: mct_PlatformSpec: Start
09.467: Programmed DCT 0 timing/termination pattern 00000000 10222222
09.468: mct_PlatformSpec: Done
09.467: mct_SetDramConfigHi_D: DramConfigHi:    0f090084
09.468: *
09.468: mct_SetDramConfigHi_D: Done
09.468: mct_EarlyArbEn_D: Start
09.468: mct_EarlyArbEn_D: Done
09.468: AutoConfig: Status 2005
09.468: AutoConfig: ErrStatus 0
09.468: AutoConfig: ErrCode 0
09.468: AutoConfig: Done
09.468: 
09.468: <09><09>DCTInit_D: AutoConfig_D Done
09.468: <09><09>DCTInit_D: PlatformSpec_D Done
09.468: <09><09>DCTFinalInit_D: StartupDCT_D Start
09.468: mct_BeforeDramInit_Prod_D: Start
09.468: mct_ProgramODT_D: Start
09.468: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
09.468: mct_ProgramODT_D: Done
09.468: mct_BeforeDramInit_Prod_D: Done
09.468: mct_DramInit_Sw_D: Start
09.468: mct_DCTAccessDone: Start
09.468: mct_DCTAccessDone: Done
09.469: mct_DramControlReg_Init_D: Start
09.469: mct_DramControlReg_Init_D: F2xA8: 00000300
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC0: 02
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC1: 00
09.469: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC3: 05
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC4: 05
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC5: 05
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC6: 00
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC7: 00
09.469: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC9: 0d
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC10: 00
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC11: 00
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC12: 00
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC13: 00
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC14: 00
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC15: 00
09.469: mct_DramControlReg_Init_D: F2xA8: 00000c00
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
09.469: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
09.469: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 00
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
09.469: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
09.469: mct_DramControlReg_Init_D: Done
09.469: DIMM 0 RttWr: 2
09.469: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.469: mct_SendMrsCmd: Start
09.470: mct_SendMrsCmd: Done
09.470: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
09.470: mct_SendMrsCmd: Start
09.470: mct_SendMrsCmd: Done
09.470: DIMM 0 RttNom: 3
09.470: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.470: mct_SendMrsCmd: Start
09.470: mct_SendMrsCmd: Done
09.470: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001318
09.470: mct_SendMrsCmd: Start
09.470: mct_SendMrsCmd: Done
09.470: DIMM 0 RttWr: 2
09.470: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.470: mct_SendMrsCmd: Start
09.470: mct_SendMrsCmd: Done
09.470: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
09.470: mct_SendMrsCmd: Start
09.470: mct_SendMrsCmd: Done
09.470: DIMM 0 RttNom: 3
09.470: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.470: mct_SendMrsCmd: Start
09.470: mct_SendMrsCmd: Done
09.470: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201318
09.470: mct_SendMrsCmd: Start
09.470: mct_SendMrsCmd: Done
09.470: DIMM 1 RttWr: 2
09.470: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.470: mct_SendMrsCmd: Start
09.470: mct_SendMrsCmd: Done
09.470: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
09.470: mct_SendMrsCmd: Start
09.470: mct_SendMrsCmd: Done
09.470: DIMM 1 RttNom: 3
09.470: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.470: mct_SendMrsCmd: Start
09.470: mct_SendMrsCmd: Done
09.470: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401318
09.470: mct_SendMrsCmd: Start
09.470: mct_SendMrsCmd: Done
09.470: DIMM 1 RttWr: 2
09.470: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.470: mct_SendMrsCmd: Start
09.470: mct_SendMrsCmd: Done
09.470: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
09.470: mct_SendMrsCmd: Start
09.470: mct_SendMrsCmd: Done
09.470: DIMM 1 RttNom: 3
09.470: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.470: mct_SendMrsCmd: Start
09.470: mct_SendMrsCmd: Done
09.471: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601318
09.471: mct_SendMrsCmd: Start
09.471: mct_SendMrsCmd: Done
09.471: mct_SendZQCmd: Start
09.471: mct_SendZQCmd: Done
09.471: mct_SendZQCmd: Start
09.471: mct_SendZQCmd: Done
09.471: mct_DCTAccessDone: Start
09.471: mct_DCTAccessDone: Done
09.471: mct_DramInit_Sw_D: Done
09.471: <09><09>DCTFinalInit_D: StartupDCT_D Done
09.471: SPDCalcWidth: Status 2005
09.471: SPDCalcWidth: ErrStatus 0
09.471: SPDCalcWidth: ErrCode 0
09.471: SPDCalcWidth: Done
09.471: <09><09>DCTInit_D: mct_SPDCalcWidth Done
09.471: AutoCycTiming_D: Start
09.471: SPD2ndTiming: Start
09.471: SPD2ndTiming: Done
09.471: AutoCycTiming: Status 2005
09.471: AutoCycTiming: ErrStatus 0
09.471: AutoCycTiming: ErrCode 0
09.471: AutoCycTiming: Done
09.471: 
09.471: <09><09>DCTInit_D: AutoCycTiming_D Done
09.471: <09><09>DCTInit_D: enabling intra-channel clock skew
09.471: SPDSetBanks: CSPresent f
09.471: SPDSetBanks: Status 2005
09.471: SPDSetBanks: ErrStatus 0
09.471: SPDSetBanks: ErrCode 0
09.471: SPDSetBanks: Done
09.471: 
09.471: AfterStitch pDCTstat->NodeSysBase = 0
09.471: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffffe
09.471: StitchMemory: Status 2005
09.471: StitchMemory: ErrStatus 0
09.471: StitchMemory: ErrCode 0
09.472: StitchMemory: Done
09.471: 
09.472: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.472: CBFS: Locating 'cmos_layout.bin'
09.472: CBFS: Found @ offset 2b0c0 size e88
09.472: InterleaveBanks_D: Status 2005
09.472: InterleaveBanks_D: ErrStatus 0
09.472: InterleaveBanks_D: ErrCode 0
09.472: InterleaveBanks_D: Done
09.472: 
09.472: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.472: CBFS: Locating 'cmos_layout.bin'
09.472: CBFS: Found @ offset 2b0c0 size e88
09.472: AutoConfig_D: DramControl:     00002a06
09.472: AutoConfig_D: DramTimingLo:    00000000
09.472: AutoConfig_D: DramConfigMisc:  00000000
09.472: AutoConfig_D: DramConfigMisc2: 00000000
09.472: AutoConfig_D: DramConfigLo:    03083000
09.472: AutoConfig_D: DramConfigHi:    0f090084
09.472: InitDDRPhy: Start
09.472: InitDDRPhy: Done
09.472: mct_SetDramConfigHi_D: Start
09.472: set_2t_configuration: Start
09.472: set_2t_configuration: Done
09.473: mct_BeforePlatformSpec: Start
09.472: mct_BeforePlatformSpec: Done
09.473: mct_PlatformSpec: Start
09.473: Programmed DCT 1 timing/termination pattern 00000000 10222222
09.473: mct_PlatformSpec: Done
09.473: mct_SetDramConfigHi_D: DramConfigHi:    0f090084
09.473: *
09.473: mct_SetDramConfigHi_D: Done
09.473: mct_EarlyArbEn_D: Start
09.473: mct_EarlyArbEn_D: Done
09.473: AutoConfig: Status 2005
09.473: AutoConfig: ErrStatus 0
09.473: AutoConfig: ErrCode 0
09.473: AutoConfig: Done
09.473: 
09.473: <09><09>DCTInit_D: AutoConfig_D Done
09.473: <09><09>DCTInit_D: PlatformSpec_D Done
09.473: <09><09>DCTFinalInit_D: StartupDCT_D Start
09.473: mct_BeforeDramInit_Prod_D: Start
09.473: mct_ProgramODT_D: Start
09.473: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
09.473: mct_ProgramODT_D: Done
09.473: mct_BeforeDramInit_Prod_D: Done
09.473: mct_DramInit_Sw_D: Start
09.473: mct_DCTAccessDone: Start
09.473: mct_DCTAccessDone: Done
09.474: mct_DramControlReg_Init_D: Start
09.474: mct_DramControlReg_Init_D: F2xA8: 00000300
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC0: 02
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC1: 00
09.474: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC3: 05
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC4: 05
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC5: 05
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC6: 00
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC7: 00
09.474: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC9: 0d
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC10: 00
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC11: 00
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC12: 00
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC13: 00
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC14: 00
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC15: 00
09.474: mct_DramControlReg_Init_D: F2xA8: 00000c00
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00
09.474: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00
09.474: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 00
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00
09.474: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00
09.474: mct_DramControlReg_Init_D: Done
09.474: DIMM 0 RttWr: 2
09.475: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.475: mct_SendMrsCmd: Start
09.475: mct_SendMrsCmd: Done
09.475: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
09.475: mct_SendMrsCmd: Start
09.475: mct_SendMrsCmd: Done
09.475: DIMM 0 RttNom: 3
09.475: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.475: mct_SendMrsCmd: Start
09.475: mct_SendMrsCmd: Done
09.475: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001318
09.475: mct_SendMrsCmd: Start
09.475: mct_SendMrsCmd: Done
09.475: DIMM 0 RttWr: 2
09.475: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.475: mct_SendMrsCmd: Start
09.475: mct_SendMrsCmd: Done
09.475: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
09.475: mct_SendMrsCmd: Start
09.475: mct_SendMrsCmd: Done
09.475: DIMM 0 RttNom: 3
09.475: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.475: mct_SendMrsCmd: Start
09.475: mct_SendMrsCmd: Done
09.475: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201318
09.475: mct_SendMrsCmd: Start
09.475: mct_SendMrsCmd: Done
09.475: DIMM 1 RttWr: 2
09.475: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.475: mct_SendMrsCmd: Start
09.475: mct_SendMrsCmd: Done
09.475: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
09.475: mct_SendMrsCmd: Start
09.475: mct_SendMrsCmd: Done
09.475: DIMM 1 RttNom: 3
09.475: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.475: mct_SendMrsCmd: Start
09.475: mct_SendMrsCmd: Done
09.475: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401318
09.475: mct_SendMrsCmd: Start
09.475: mct_SendMrsCmd: Done
09.475: DIMM 1 RttWr: 2
09.475: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.475: mct_SendMrsCmd: Start
09.475: mct_SendMrsCmd: Done
09.475: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
09.475: mct_SendMrsCmd: Start
09.475: mct_SendMrsCmd: Done
09.475: DIMM 1 RttNom: 3
09.475: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.475: mct_SendMrsCmd: Start
09.475: mct_SendMrsCmd: Done
09.476: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601318
09.476: mct_SendMrsCmd: Start
09.476: mct_SendMrsCmd: Done
09.476: mct_SendZQCmd: Start
09.476: mct_SendZQCmd: Done
09.476: mct_SendZQCmd: Start
09.476: mct_SendZQCmd: Done
09.476: mct_DCTAccessDone: Start
09.476: mct_DCTAccessDone: Done
09.476: mct_DramInit_Sw_D: Done
09.476: <09><09>DCTFinalInit_D: StartupDCT_D Done
09.476: mctAutoInitMCT_D: mctSMBhub_Init
09.476: activate_spd_rom() for node 02
09.476: enable_spd_node2()
09.476: mctAutoInitMCT_D: mct_initDCT
09.476: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.476: CBFS: Locating 'cmos_layout.bin'
09.476: CBFS: Found @ offset 2b0c0 size e88
09.476: SPDCalcWidth: Status 2005
09.476: SPDCalcWidth: ErrStatus 0
09.476: SPDCalcWidth: ErrCode 0
09.476: SPDCalcWidth: Done
09.476: <09><09>DCTInit_D: mct_SPDCalcWidth Done
09.476: AutoCycTiming_D: Start
09.476: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.476: CBFS: Locating 'cmos_layout.bin'
09.476: CBFS: Found @ offset 2b0c0 size e88
09.476: GetPresetmaxF_D: Start
09.476: GetPresetmaxF_D: Done
09.476: SPDGetTCL_D: Start
09.477: SPDGetTCL_D: DIMMCASL 5
09.477: SPDGetTCL_D: DIMMAutoSpeed 4
09.477: SPDGetTCL_D: Status 2005
09.477: SPDGetTCL_D: ErrStatus 0
09.477: SPDGetTCL_D: ErrCode 0
09.477: SPDGetTCL_D: Done
09.477: 
09.477: SPD2ndTiming: Start
09.477: SPD2ndTiming: Done
09.477: AutoCycTiming: Status 2005
09.477: AutoCycTiming: ErrStatus 0
09.477: AutoCycTiming: ErrCode 0
09.477: AutoCycTiming: Done
09.477: 
09.477: <09><09>DCTInit_D: AutoCycTiming_D Done
09.477: SPDSetBanks: CSPresent f
09.477: SPDSetBanks: Status 2005
09.477: SPDSetBanks: ErrStatus 0
09.477: SPDSetBanks: ErrCode 0
09.477: SPDSetBanks: Done
09.477: 
09.477: AfterStitch pDCTstat->NodeSysBase = 0
09.477: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7ffffff
09.477: StitchMemory: Status 2005
09.477: StitchMemory: ErrStatus 0
09.477: StitchMemory: ErrCode 0
09.477: StitchMemory: Done
09.477: 
09.477: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.477: CBFS: Locating 'cmos_layout.bin'
09.477: CBFS: Found @ offset 2b0c0 size e88
09.478: InterleaveBanks_D: Status 2005
09.478: InterleaveBanks_D: ErrStatus 0
09.478: InterleaveBanks_D: ErrCode 0
09.478: InterleaveBanks_D: Done
09.478: 
09.478: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.478: CBFS: Locating 'cmos_layout.bin'
09.478: CBFS: Found @ offset 2b0c0 size e88
09.478: AutoConfig_D: DramControl:     00002a06
09.478: AutoConfig_D: DramTimingLo:    00000000
09.478: AutoConfig_D: DramConfigMisc:  00000000
09.478: AutoConfig_D: DramConfigMisc2: 00000000
09.478: AutoConfig_D: DramConfigLo:    03083000
09.478: AutoConfig_D: DramConfigHi:    0f090084
09.478: InitDDRPhy: Start
09.478: InitDDRPhy: Done
09.478: mct_SetDramConfigHi_D: Start
09.478: set_2t_configuration: Start
09.478: set_2t_configuration: Done
09.478: mct_BeforePlatformSpec: Start
09.478: mct_BeforePlatformSpec: Done
09.478: mct_PlatformSpec: Start
09.478: Programmed DCT 0 timing/termination pattern 00000000 10222222
09.478: mct_PlatformSpec: Done
09.478: mct_SetDramConfigHi_D: DramConfigHi:    0f090084
09.478: *
09.478: mct_SetDramConfigHi_D: Done
09.478: mct_EarlyArbEn_D: Start
09.478: mct_EarlyArbEn_D: Done
09.478: AutoConfig: Status 2005
09.479: AutoConfig: ErrStatus 0
09.478: AutoConfig: ErrCode 0
09.479: AutoConfig: Done
09.478: 
09.479: <09><09>DCTInit_D: AutoConfig_D Done
09.479: <09><09>DCTInit_D: PlatformSpec_D Done
09.479: <09><09>DCTFinalInit_D: StartupDCT_D Start
09.479: mct_BeforeDramInit_Prod_D: Start
09.479: mct_ProgramODT_D: Start
09.479: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
09.479: mct_ProgramODT_D: Done
09.479: mct_BeforeDramInit_Prod_D: Done
09.479: mct_DramInit_Sw_D: Start
09.479: mct_DCTAccessDone: Start
09.479: mct_DCTAccessDone: Done
09.480: mct_DramControlReg_Init_D: Start
09.480: mct_DramControlReg_Init_D: F2xA8: 00000300
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC0: 02
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC1: 00
09.480: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC3: 05
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC4: 05
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC5: 05
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC6: 00
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC7: 00
09.480: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC9: 0d
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC10: 00
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC11: 00
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC12: 00
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC13: 00
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC14: 00
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC15: 00
09.480: mct_DramControlReg_Init_D: F2xA8: 00000c00
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
09.480: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
09.480: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 00
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
09.480: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
09.480: mct_DramControlReg_Init_D: Done
09.480: DIMM 0 RttWr: 2
09.480: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.480: mct_SendMrsCmd: Start
09.480: mct_SendMrsCmd: Done
09.480: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
09.480: mct_SendMrsCmd: Start
09.480: mct_SendMrsCmd: Done
09.481: DIMM 0 RttNom: 3
09.481: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.481: mct_SendMrsCmd: Start
09.481: mct_SendMrsCmd: Done
09.481: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001318
09.481: mct_SendMrsCmd: Start
09.481: mct_SendMrsCmd: Done
09.481: DIMM 0 RttWr: 2
09.481: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.481: mct_SendMrsCmd: Start
09.481: mct_SendMrsCmd: Done
09.481: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
09.481: mct_SendMrsCmd: Start
09.481: mct_SendMrsCmd: Done
09.481: DIMM 0 RttNom: 3
09.481: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.481: mct_SendMrsCmd: Start
09.481: mct_SendMrsCmd: Done
09.481: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201318
09.481: mct_SendMrsCmd: Start
09.481: mct_SendMrsCmd: Done
09.481: DIMM 1 RttWr: 2
09.481: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.481: mct_SendMrsCmd: Start
09.481: mct_SendMrsCmd: Done
09.481: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
09.481: mct_SendMrsCmd: Start
09.481: mct_SendMrsCmd: Done
09.481: DIMM 1 RttNom: 3
09.481: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.481: mct_SendMrsCmd: Start
09.481: mct_SendMrsCmd: Done
09.481: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401318
09.481: mct_SendMrsCmd: Start
09.481: mct_SendMrsCmd: Done
09.481: DIMM 1 RttWr: 2
09.481: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.481: mct_SendMrsCmd: Start
09.481: mct_SendMrsCmd: Done
09.481: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
09.481: mct_SendMrsCmd: Start
09.481: mct_SendMrsCmd: Done
09.481: DIMM 1 RttNom: 3
09.481: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.481: mct_SendMrsCmd: Start
09.481: mct_SendMrsCmd: Done
09.481: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601318
09.481: mct_SendMrsCmd: Start
09.481: mct_SendMrsCmd: Done
09.481: mct_SendZQCmd: Start
09.481: mct_SendZQCmd: Done
09.481: mct_SendZQCmd: Start
09.481: mct_SendZQCmd: Done
09.481: mct_DCTAccessDone: Start
09.481: mct_DCTAccessDone: Done
09.481: mct_DramInit_Sw_D: Done
09.481: <09><09>DCTFinalInit_D: StartupDCT_D Done
09.481: SPDCalcWidth: Status 2005
09.481: SPDCalcWidth: ErrStatus 0
09.482: SPDCalcWidth: ErrCode 0
09.481: SPDCalcWidth: Done
09.482: <09><09>DCTInit_D: mct_SPDCalcWidth Done
09.482: AutoCycTiming_D: Start
09.482: SPD2ndTiming: Start
09.482: SPD2ndTiming: Done
09.482: AutoCycTiming: Status 2005
09.482: AutoCycTiming: ErrStatus 0
09.482: AutoCycTiming: ErrCode 0
09.482: AutoCycTiming: Done
09.482: 
09.482: <09><09>DCTInit_D: AutoCycTiming_D Done
09.482: <09><09>DCTInit_D: enabling intra-channel clock skew
09.482: SPDSetBanks: CSPresent f
09.482: SPDSetBanks: Status 2005
09.482: SPDSetBanks: ErrStatus 0
09.482: SPDSetBanks: ErrCode 0
09.482: SPDSetBanks: Done
09.482: 
09.482: AfterStitch pDCTstat->NodeSysBase = 0
09.482: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffffe
09.482: StitchMemory: Status 2005
09.482: StitchMemory: ErrStatus 0
09.482: StitchMemory: ErrCode 0
09.482: StitchMemory: Done
09.482: 
09.482: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.482: CBFS: Locating 'cmos_layout.bin'
09.482: CBFS: Found @ offset 2b0c0 size e88
09.483: InterleaveBanks_D: Status 2005
09.483: InterleaveBanks_D: ErrStatus 0
09.483: InterleaveBanks_D: ErrCode 0
09.483: InterleaveBanks_D: Done
09.483: 
09.483: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.483: CBFS: Locating 'cmos_layout.bin'
09.483: CBFS: Found @ offset 2b0c0 size e88
09.483: AutoConfig_D: DramControl:     00002a06
09.483: AutoConfig_D: DramTimingLo:    00000000
09.483: AutoConfig_D: DramConfigMisc:  00000000
09.483: AutoConfig_D: DramConfigMisc2: 00000000
09.483: AutoConfig_D: DramConfigLo:    03083000
09.483: AutoConfig_D: DramConfigHi:    0f090084
09.483: InitDDRPhy: Start
09.483: InitDDRPhy: Done
09.483: mct_SetDramConfigHi_D: Start
09.483: set_2t_configuration: Start
09.483: set_2t_configuration: Done
09.483: mct_BeforePlatformSpec: Start
09.483: mct_BeforePlatformSpec: Done
09.483: mct_PlatformSpec: Start
09.483: Programmed DCT 1 timing/termination pattern 00000000 10222222
09.483: mct_PlatformSpec: Done
09.483: mct_SetDramConfigHi_D: DramConfigHi:    0f090084
09.483: *
09.483: mct_SetDramConfigHi_D: Done
09.483: mct_EarlyArbEn_D: Start
09.483: mct_EarlyArbEn_D: Done
09.483: AutoConfig: Status 2005
09.483: AutoConfig: ErrStatus 0
09.483: AutoConfig: ErrCode 0
09.483: AutoConfig: Done
09.483: 
09.483: <09><09>DCTInit_D: AutoConfig_D Done
09.484: <09><09>DCTInit_D: PlatformSpec_D Done
09.484: <09><09>DCTFinalInit_D: StartupDCT_D Start
09.484: mct_BeforeDramInit_Prod_D: Start
09.484: mct_ProgramODT_D: Start
09.484: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
09.484: mct_ProgramODT_D: Done
09.484: mct_BeforeDramInit_Prod_D: Done
09.484: mct_DramInit_Sw_D: Start
09.484: mct_DCTAccessDone: Start
09.484: mct_DCTAccessDone: Done
09.485: mct_DramControlReg_Init_D: Start
09.485: mct_DramControlReg_Init_D: F2xA8: 00000300
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC0: 02
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC1: 00
09.485: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC3: 05
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC4: 05
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC5: 05
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC6: 00
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC7: 00
09.485: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC9: 0d
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC10: 00
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC11: 00
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC12: 00
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC13: 00
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC14: 00
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC15: 00
09.485: mct_DramControlReg_Init_D: F2xA8: 00000c00
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00
09.485: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00
09.485: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 00
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00
09.485: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00
09.485: mct_DramControlReg_Init_D: Done
09.485: DIMM 0 RttWr: 2
09.485: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.485: mct_SendMrsCmd: Start
09.485: mct_SendMrsCmd: Done
09.485: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
09.485: mct_SendMrsCmd: Start
09.485: mct_SendMrsCmd: Done
09.485: DIMM 0 RttNom: 3
09.486: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.486: mct_SendMrsCmd: Start
09.486: mct_SendMrsCmd: Done
09.486: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001318
09.486: mct_SendMrsCmd: Start
09.486: mct_SendMrsCmd: Done
09.486: DIMM 0 RttWr: 2
09.486: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.486: mct_SendMrsCmd: Start
09.486: mct_SendMrsCmd: Done
09.486: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
09.486: mct_SendMrsCmd: Start
09.486: mct_SendMrsCmd: Done
09.486: DIMM 0 RttNom: 3
09.486: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.486: mct_SendMrsCmd: Start
09.486: mct_SendMrsCmd: Done
09.486: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201318
09.486: mct_SendMrsCmd: Start
09.486: mct_SendMrsCmd: Done
09.486: DIMM 1 RttWr: 2
09.486: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.486: mct_SendMrsCmd: Start
09.486: mct_SendMrsCmd: Done
09.486: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
09.486: mct_SendMrsCmd: Start
09.486: mct_SendMrsCmd: Done
09.486: DIMM 1 RttNom: 3
09.486: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.486: mct_SendMrsCmd: Start
09.486: mct_SendMrsCmd: Done
09.486: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401318
09.486: mct_SendMrsCmd: Start
09.486: mct_SendMrsCmd: Done
09.486: DIMM 1 RttWr: 2
09.486: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.486: mct_SendMrsCmd: Start
09.486: mct_SendMrsCmd: Done
09.486: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
09.486: mct_SendMrsCmd: Start
09.486: mct_SendMrsCmd: Done
09.486: DIMM 1 RttNom: 3
09.486: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.486: mct_SendMrsCmd: Start
09.486: mct_SendMrsCmd: Done
09.486: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601318
09.486: mct_SendMrsCmd: Start
09.486: mct_SendMrsCmd: Done
09.486: mct_SendZQCmd: Start
09.486: mct_SendZQCmd: Done
09.486: mct_SendZQCmd: Start
09.486: mct_SendZQCmd: Done
09.486: mct_DCTAccessDone: Start
09.486: mct_DCTAccessDone: Done
09.486: mct_DramInit_Sw_D: Done
09.486: <09><09>DCTFinalInit_D: StartupDCT_D Done
09.486: mctAutoInitMCT_D: mctSMBhub_Init
09.486: activate_spd_rom() for node 03
09.486: enable_spd_node3()
09.486: mctAutoInitMCT_D: mct_initDCT
09.486: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.486: CBFS: Locating 'cmos_layout.bin'
09.486: CBFS: Found @ offset 2b0c0 size e88
09.487: SPDCalcWidth: Status 2005
09.487: SPDCalcWidth: ErrStatus 0
09.487: SPDCalcWidth: ErrCode 0
09.487: SPDCalcWidth: Done
09.487: <09><09>DCTInit_D: mct_SPDCalcWidth Done
09.487: AutoCycTiming_D: Start
09.487: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.487: CBFS: Locating 'cmos_layout.bin'
09.487: CBFS: Found @ offset 2b0c0 size e88
09.487: GetPresetmaxF_D: Start
09.487: GetPresetmaxF_D: Done
09.487: SPDGetTCL_D: Start
09.487: SPDGetTCL_D: DIMMCASL 5
09.487: SPDGetTCL_D: DIMMAutoSpeed 4
09.487: SPDGetTCL_D: Status 2005
09.487: SPDGetTCL_D: ErrStatus 0
09.487: SPDGetTCL_D: ErrCode 0
09.487: SPDGetTCL_D: Done
09.487: 
09.487: SPD2ndTiming: Start
09.487: SPD2ndTiming: Done
09.487: AutoCycTiming: Status 2005
09.487: AutoCycTiming: ErrStatus 0
09.487: AutoCycTiming: ErrCode 0
09.487: AutoCycTiming: Done
09.487: 
09.487: <09><09>DCTInit_D: AutoCycTiming_D Done
09.488: SPDSetBanks: CSPresent f
09.488: SPDSetBanks: Status 2005
09.488: SPDSetBanks: ErrStatus 0
09.488: SPDSetBanks: ErrCode 0
09.488: SPDSetBanks: Done
09.488: 
09.488: AfterStitch pDCTstat->NodeSysBase = 0
09.488: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7ffffff
09.488: StitchMemory: Status 2005
09.488: StitchMemory: ErrStatus 0
09.488: StitchMemory: ErrCode 0
09.488: StitchMemory: Done
09.488: 
09.488: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.488: CBFS: Locating 'cmos_layout.bin'
09.488: CBFS: Found @ offset 2b0c0 size e88
09.488: InterleaveBanks_D: Status 2005
09.488: InterleaveBanks_D: ErrStatus 0
09.488: InterleaveBanks_D: ErrCode 0
09.488: InterleaveBanks_D: Done
09.488: 
09.488: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.488: CBFS: Locating 'cmos_layout.bin'
09.488: CBFS: Found @ offset 2b0c0 size e88
09.489: AutoConfig_D: DramControl:     00002a06
09.489: AutoConfig_D: DramTimingLo:    00000000
09.489: AutoConfig_D: DramConfigMisc:  00000000
09.489: AutoConfig_D: DramConfigMisc2: 00000000
09.489: AutoConfig_D: DramConfigLo:    03083000
09.489: AutoConfig_D: DramConfigHi:    0f090084
09.489: InitDDRPhy: Start
09.489: InitDDRPhy: Done
09.489: mct_SetDramConfigHi_D: Start
09.489: set_2t_configuration: Start
09.489: set_2t_configuration: Done
09.489: mct_BeforePlatformSpec: Start
09.489: mct_BeforePlatformSpec: Done
09.489: mct_PlatformSpec: Start
09.489: Programmed DCT 0 timing/termination pattern 00000000 10222222
09.489: mct_PlatformSpec: Done
09.489: mct_SetDramConfigHi_D: DramConfigHi:    0f090084
09.489: *
09.489: mct_SetDramConfigHi_D: Done
09.489: mct_EarlyArbEn_D: Start
09.489: mct_EarlyArbEn_D: Done
09.489: AutoConfig: Status 2005
09.489: AutoConfig: ErrStatus 0
09.489: AutoConfig: ErrCode 0
09.489: AutoConfig: Done
09.489: 
09.489: <09><09>DCTInit_D: AutoConfig_D Done
09.489: <09><09>DCTInit_D: PlatformSpec_D Done
09.489: <09><09>DCTFinalInit_D: StartupDCT_D Start
09.489: mct_BeforeDramInit_Prod_D: Start
09.489: mct_ProgramODT_D: Start
09.489: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
09.489: mct_ProgramODT_D: Done
09.489: mct_BeforeDramInit_Prod_D: Done
09.489: mct_DramInit_Sw_D: Start
09.489: mct_DCTAccessDone: Start
09.489: mct_DCTAccessDone: Done
09.490: mct_DramControlReg_Init_D: Start
09.490: mct_DramControlReg_Init_D: F2xA8: 00000300
09.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC0: 02
09.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC1: 00
09.490: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
09.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC3: 05
09.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC4: 05
09.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC5: 05
09.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC6: 00
09.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC7: 00
09.490: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
09.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC9: 0d
09.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC10: 00
09.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC11: 00
09.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC12: 00
09.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC13: 00
09.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC14: 00
09.490: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC15: 00
09.490: mct_DramControlReg_Init_D: F2xA8: 00000c00
09.490: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
09.490: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
09.491: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
09.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
09.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
09.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
09.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
09.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
09.491: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
09.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
09.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
09.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 00
09.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
09.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
09.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
09.491: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
09.491: mct_DramControlReg_Init_D: Done
09.491: DIMM 0 RttWr: 2
09.491: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.491: mct_SendMrsCmd: Start
09.491: mct_SendMrsCmd: Done
09.491: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
09.491: mct_SendMrsCmd: Start
09.491: mct_SendMrsCmd: Done
09.491: DIMM 0 RttNom: 3
09.491: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.491: mct_SendMrsCmd: Start
09.491: mct_SendMrsCmd: Done
09.491: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001318
09.491: mct_SendMrsCmd: Start
09.491: mct_SendMrsCmd: Done
09.491: DIMM 0 RttWr: 2
09.492: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.492: mct_SendMrsCmd: Start
09.492: mct_SendMrsCmd: Done
09.492: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
09.492: mct_SendMrsCmd: Start
09.492: mct_SendMrsCmd: Done
09.492: DIMM 0 RttNom: 3
09.492: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.492: mct_SendMrsCmd: Start
09.492: mct_SendMrsCmd: Done
09.492: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201318
09.492: mct_SendMrsCmd: Start
09.492: mct_SendMrsCmd: Done
09.492: DIMM 1 RttWr: 2
09.492: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.492: mct_SendMrsCmd: Start
09.492: mct_SendMrsCmd: Done
09.492: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
09.492: mct_SendMrsCmd: Start
09.492: mct_SendMrsCmd: Done
09.492: DIMM 1 RttNom: 3
09.492: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.492: mct_SendMrsCmd: Start
09.492: mct_SendMrsCmd: Done
09.492: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401318
09.492: mct_SendMrsCmd: Start
09.492: mct_SendMrsCmd: Done
09.492: DIMM 1 RttWr: 2
09.492: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.492: mct_SendMrsCmd: Start
09.492: mct_SendMrsCmd: Done
09.492: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
09.492: mct_SendMrsCmd: Start
09.492: mct_SendMrsCmd: Done
09.492: DIMM 1 RttNom: 3
09.492: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.492: mct_SendMrsCmd: Start
09.492: mct_SendMrsCmd: Done
09.492: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601318
09.492: mct_SendMrsCmd: Start
09.492: mct_SendMrsCmd: Done
09.492: mct_SendZQCmd: Start
09.492: mct_SendZQCmd: Done
09.492: mct_SendZQCmd: Start
09.492: mct_SendZQCmd: Done
09.492: mct_DCTAccessDone: Start
09.492: mct_DCTAccessDone: Done
09.492: mct_DramInit_Sw_D: Done
09.492: <09><09>DCTFinalInit_D: StartupDCT_D Done
09.492: SPDCalcWidth: Status 2005
09.492: SPDCalcWidth: ErrStatus 0
09.492: SPDCalcWidth: ErrCode 0
09.492: SPDCalcWidth: Done
09.492: <09><09>DCTInit_D: mct_SPDCalcWidth Done
09.492: AutoCycTiming_D: Start
09.492: SPD2ndTiming: Start
09.492: SPD2ndTiming: Done
09.492: AutoCycTiming: Status 2005
09.492: AutoCycTiming: ErrStatus 0
09.492: AutoCycTiming: ErrCode 0
09.492: AutoCycTiming: Done
09.492: 
09.492: <09><09>DCTInit_D: AutoCycTiming_D Done
09.492: <09><09>DCTInit_D: enabling intra-channel clock skew
09.493: SPDSetBanks: CSPresent f
09.493: SPDSetBanks: Status 2005
09.493: SPDSetBanks: ErrStatus 0
09.493: SPDSetBanks: ErrCode 0
09.493: SPDSetBanks: Done
09.493: 
09.493: AfterStitch pDCTstat->NodeSysBase = 0
09.493: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffffe
09.493: StitchMemory: Status 2005
09.493: StitchMemory: ErrStatus 0
09.493: StitchMemory: ErrCode 0
09.493: StitchMemory: Done
09.493: 
09.493: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.493: CBFS: Locating 'cmos_layout.bin'
09.493: CBFS: Found @ offset 2b0c0 size e88
09.493: InterleaveBanks_D: Status 2005
09.493: InterleaveBanks_D: ErrStatus 0
09.493: InterleaveBanks_D: ErrCode 0
09.493: InterleaveBanks_D: Done
09.493: 
09.494: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
09.494: CBFS: Locating 'cmos_layout.bin'
09.494: CBFS: Found @ offset 2b0c0 size e88
09.494: AutoConfig_D: DramControl:     00002a06
09.494: AutoConfig_D: DramTimingLo:    00000000
09.494: AutoConfig_D: DramConfigMisc:  00000000
09.494: AutoConfig_D: DramConfigMisc2: 00000000
09.494: AutoConfig_D: DramConfigLo:    03083000
09.494: AutoConfig_D: DramConfigHi:    0f090084
09.494: InitDDRPhy: Start
09.494: InitDDRPhy: Done
09.494: mct_SetDramConfigHi_D: Start
09.494: set_2t_configuration: Start
09.494: set_2t_configuration: Done
09.494: mct_BeforePlatformSpec: Start
09.494: mct_BeforePlatformSpec: Done
09.494: mct_PlatformSpec: Start
09.494: Programmed DCT 1 timing/termination pattern 00000000 10222222
09.494: mct_PlatformSpec: Done
09.494: mct_SetDramConfigHi_D: DramConfigHi:    0f090084
09.494: *
09.494: mct_SetDramConfigHi_D: Done
09.494: mct_EarlyArbEn_D: Start
09.494: mct_EarlyArbEn_D: Done
09.494: AutoConfig: Status 2005
09.494: AutoConfig: ErrStatus 0
09.494: AutoConfig: ErrCode 0
09.494: AutoConfig: Done
09.494: 
09.494: <09><09>DCTInit_D: AutoConfig_D Done
09.494: <09><09>DCTInit_D: PlatformSpec_D Done
09.494: <09><09>DCTFinalInit_D: StartupDCT_D Start
09.494: mct_BeforeDramInit_Prod_D: Start
09.494: mct_ProgramODT_D: Start
09.494: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
09.494: mct_ProgramODT_D: Done
09.494: mct_BeforeDramInit_Prod_D: Done
09.494: mct_DramInit_Sw_D: Start
09.494: mct_DCTAccessDone: Start
09.494: mct_DCTAccessDone: Done
09.495: mct_DramControlReg_Init_D: Start
09.495: mct_DramControlReg_Init_D: F2xA8: 00000300
09.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC0: 02
09.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC1: 00
09.495: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
09.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC3: 05
09.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC4: 05
09.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC5: 05
09.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC6: 00
09.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC7: 00
09.495: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
09.496: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC9: 0d
09.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC10: 00
09.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC11: 00
09.495: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC12: 00
09.496: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC13: 00
09.496: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC14: 00
09.496: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC15: 00
09.496: mct_DramControlReg_Init_D: F2xA8: 00000c00
09.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02
09.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00
09.496: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
09.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05
09.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05
09.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05
09.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00
09.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00
09.496: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
09.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d
09.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00
09.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 00
09.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00
09.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00
09.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00
09.496: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00
09.496: mct_DramControlReg_Init_D: Done
09.496: DIMM 0 RttWr: 2
09.496: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.496: mct_SendMrsCmd: Start
09.496: mct_SendMrsCmd: Done
09.496: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
09.496: mct_SendMrsCmd: Start
09.496: mct_SendMrsCmd: Done
09.496: DIMM 0 RttNom: 3
09.496: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.496: mct_SendMrsCmd: Start
09.496: mct_SendMrsCmd: Done
09.496: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001318
09.496: mct_SendMrsCmd: Start
09.496: mct_SendMrsCmd: Done
09.497: DIMM 0 RttWr: 2
09.497: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.497: mct_SendMrsCmd: Start
09.497: mct_SendMrsCmd: Done
09.497: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
09.497: mct_SendMrsCmd: Start
09.497: mct_SendMrsCmd: Done
09.497: DIMM 0 RttNom: 3
09.497: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.497: mct_SendMrsCmd: Start
09.497: mct_SendMrsCmd: Done
09.497: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201318
09.497: mct_SendMrsCmd: Start
09.497: mct_SendMrsCmd: Done
09.497: DIMM 1 RttWr: 2
09.497: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.497: mct_SendMrsCmd: Start
09.497: mct_SendMrsCmd: Done
09.497: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
09.497: mct_SendMrsCmd: Start
09.497: mct_SendMrsCmd: Done
09.497: DIMM 1 RttNom: 3
09.497: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.497: mct_SendMrsCmd: Start
09.497: mct_SendMrsCmd: Done
09.497: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401318
09.497: mct_SendMrsCmd: Start
09.497: mct_SendMrsCmd: Done
09.497: DIMM 1 RttWr: 2
09.497: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.497: mct_SendMrsCmd: Start
09.497: mct_SendMrsCmd: Done
09.497: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
09.497: mct_SendMrsCmd: Start
09.497: mct_SendMrsCmd: Done
09.497: DIMM 1 RttNom: 3
09.497: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.497: mct_SendMrsCmd: Start
09.497: mct_SendMrsCmd: Done
09.497: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601318
09.497: mct_SendMrsCmd: Start
09.497: mct_SendMrsCmd: Done
09.497: mct_SendZQCmd: Start
09.497: mct_SendZQCmd: Done
09.497: mct_SendZQCmd: Start
09.497: mct_SendZQCmd: Done
09.497: mct_DCTAccessDone: Start
09.497: mct_DCTAccessDone: Done
09.497: mct_DramInit_Sw_D: Done
09.497: <09><09>DCTFinalInit_D: StartupDCT_D Done
09.497: mctAutoInitMCT_D: SyncDCTsReady_D
09.497: mctAutoInitMCT_D: HTMemMapInit_D
09.497:  Node: 00  base: 00  limit: fffffff  BottomIO: c00000
09.498:  Node: 00  base: 03  limit: 103fffff
09.498:  Node: 01  base: 10400000  limit: 203fffff  BottomIO: c00000
09.498:  Node: 01  base: 10400003  limit: 203fffff
09.498:  Node: 02  base: 20400000  limit: 303fffff  BottomIO: c00000
09.498:  Node: 02  base: 20400003  limit: 303fffff
09.498:  Node: 03  base: 30400000  limit: 403fffff  BottomIO: c00000
09.498:  Node: 03  base: 30400003  limit: 403fffff
09.498:  Node: 04  base: 00  limit: 00
09.498:  Node: 05  base: 00  limit: 00
09.498:  Node: 06  base: 00  limit: 00
09.498:  Node: 07  base: 00  limit: 00
09.498:  Copy dram map from Node 0 to Node 01
09.498:  Copy dram map from Node 0 to Node 02
09.498:  Copy dram map from Node 0 to Node 03
09.498: mctAutoInitMCT_D: mctHookAfterCPU
09.498: mctAutoInitMCT_D: DQSTiming_D
09.498: phyAssistedMemFnceTraining: Start
09.498: phyAssistedMemFnceTraining: training node 0 DCT 0
09.499: phyAssistedMemFnceTraining: done training node 0 DCT 0
09.499: phyAssistedMemFnceTraining: training node 0 DCT 1
09.499: phyAssistedMemFnceTraining: done training node 0 DCT 1
09.499: phyAssistedMemFnceTraining: training node 1 DCT 0
09.499: phyAssistedMemFnceTraining: done training node 1 DCT 0
09.499: phyAssistedMemFnceTraining: training node 1 DCT 1
09.499: phyAssistedMemFnceTraining: done training node 1 DCT 1
09.499: phyAssistedMemFnceTraining: training node 2 DCT 0
09.499: phyAssistedMemFnceTraining: done training node 2 DCT 0
09.499: phyAssistedMemFnceTraining: training node 2 DCT 1
09.499: phyAssistedMemFnceTraining: done training node 2 DCT 1
09.499: phyAssistedMemFnceTraining: training node 3 DCT 0
09.500: phyAssistedMemFnceTraining: done training node 3 DCT 0
09.500: phyAssistedMemFnceTraining: training node 3 DCT 1
09.500: phyAssistedMemFnceTraining: done training node 3 DCT 1
09.500: phyAssistedMemFnceTraining: Done
09.500: InitPhyCompensation: DCT 0: Start
09.501: Waiting for predriver calibration to be applied...done!
09.501: InitPhyCompensation: DCT 0: Done
09.501: InitPhyCompensation: DCT 1: Start
09.501: Waiting for predriver calibration to be applied...done!
09.501: InitPhyCompensation: DCT 1: Done
09.501: InitPhyCompensation: DCT 0: Start
09.501: Waiting for predriver calibration to be applied...done!
09.501: InitPhyCompensation: DCT 0: Done
09.501: InitPhyCompensation: DCT 1: Start
09.501: Waiting for predriver calibration to be applied...done!
09.501: InitPhyCompensation: DCT 1: Done
09.501: InitPhyCompensation: DCT 0: Start
09.501: Waiting for predriver calibration to be applied...done!
09.501: InitPhyCompensation: DCT 0: Done
09.501: InitPhyCompensation: DCT 1: Start
09.501: Waiting for predriver calibration to be applied...done!
09.501: InitPhyCompensation: DCT 1: Done
09.501: InitPhyCompensation: DCT 0: Start
09.501: Waiting for predriver calibration to be applied...done!
09.502: InitPhyCompensation: DCT 0: Done
09.501: InitPhyCompensation: DCT 1: Start
09.502: Waiting for predriver calibration to be applied...done!
09.502: InitPhyCompensation: DCT 1: Done
09.502: activate_spd_rom() for node 00
09.502: enable_spd_node0()
09.504: AgesaHwWlPhase1: training nibble 0
09.504: DIMM 0 RttNom: 3
09.504: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.504: DIMM 0 RttWr: 2
09.504: DIMM 0 RttWr: 2
09.504: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.504: DIMM 0 RttWr: 2
09.504: DIMM 0 RttNom: 3
09.504: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.504: DIMM 0 RttNom: 3
09.504: DIMM 0 RttWr: 2
09.504: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.504: DIMM 0 RttWr: 2
09.505: DIMM 1 RttNom: 3
09.505: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.505: DIMM 0 RttNom: 3
09.505: DIMM 1 RttWr: 2
09.505: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.505: DIMM 0 RttWr: 2
09.505: DIMM 1 RttNom: 3
09.505: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.505: DIMM 0 RttNom: 3
09.505: DIMM 1 RttWr: 2
09.505: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.505: DIMM 0 RttWr: 2
09.506: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.506: <09>Lane 00 initial seed: 0041
09.506: <09>Lane 01 initial seed: 0041
09.506: <09>Lane 02 initial seed: 0041
09.506: <09>Lane 03 initial seed: 0041
09.506: <09>Lane 04 initial seed: 0041
09.506: <09>Lane 05 initial seed: 0041
09.506: <09>Lane 06 initial seed: 0041
09.506: <09>Lane 07 initial seed: 0041
09.506: <09>Lane 08 initial seed: 0041
09.507: <09>Lane 00 nibble 0 raw readback: 004c
09.507: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004c
09.507: <09>Lane 00 nibble 0 adjusted value (post nibble): 004c
09.507: <09>Lane 01 nibble 0 raw readback: 0047
09.507: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0047
09.507: <09>Lane 01 nibble 0 adjusted value (post nibble): 0047
09.507: <09>Lane 02 nibble 0 raw readback: 0045
09.507: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0045
09.507: <09>Lane 02 nibble 0 adjusted value (post nibble): 0045
09.507: <09>Lane 03 nibble 0 raw readback: 0041
09.507: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0041
09.507: <09>Lane 03 nibble 0 adjusted value (post nibble): 0041
09.507: <09>Lane 04 nibble 0 raw readback: 0039
09.507: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
09.507: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
09.507: <09>Lane 05 nibble 0 raw readback: 003d
09.507: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
09.507: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
09.507: <09>Lane 06 nibble 0 raw readback: 003f
09.507: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003f
09.507: <09>Lane 06 nibble 0 adjusted value (post nibble): 003f
09.507: <09>Lane 07 nibble 0 raw readback: 0041
09.507: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0041
09.507: <09>Lane 07 nibble 0 adjusted value (post nibble): 0041
09.507: <09>Lane 08 nibble 0 raw readback: 003c
09.507: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003c
09.507: <09>Lane 08 nibble 0 adjusted value (post nibble): 003c
09.507: AgesaHwWlPhase1: training nibble 1
09.507: DIMM 0 RttNom: 3
09.507: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.507: DIMM 0 RttWr: 2
09.507: DIMM 0 RttWr: 2
09.507: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.507: DIMM 0 RttWr: 2
09.507: DIMM 0 RttNom: 3
09.507: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.507: DIMM 0 RttNom: 3
09.507: DIMM 0 RttWr: 2
09.507: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.507: DIMM 0 RttWr: 2
09.507: DIMM 1 RttNom: 3
09.507: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.507: DIMM 0 RttNom: 3
09.507: DIMM 1 RttWr: 2
09.507: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.507: DIMM 0 RttWr: 2
09.507: DIMM 1 RttNom: 3
09.507: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.507: DIMM 0 RttNom: 3
09.507: DIMM 1 RttWr: 2
09.507: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.507: DIMM 0 RttWr: 2
09.507: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.507: <09>Lane 00 initial seed: 0041
09.507: <09>Lane 01 initial seed: 0041
09.507: <09>Lane 02 initial seed: 0041
09.507: <09>Lane 03 initial seed: 0041
09.507: <09>Lane 04 initial seed: 0041
09.507: <09>Lane 05 initial seed: 0041
09.507: <09>Lane 06 initial seed: 0041
09.507: <09>Lane 07 initial seed: 0041
09.507: <09>Lane 08 initial seed: 0041
09.507: <09>Lane 00 nibble 1 raw readback: 004c
09.508: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004c
09.508: <09>Lane 00 nibble 1 adjusted value (post nibble): 0046
09.508: <09>Lane 01 nibble 1 raw readback: 0047
09.508: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0047
09.508: <09>Lane 01 nibble 1 adjusted value (post nibble): 0044
09.508: <09>Lane 02 nibble 1 raw readback: 0046
09.508: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0046
09.508: <09>Lane 02 nibble 1 adjusted value (post nibble): 0043
09.508: <09>Lane 03 nibble 1 raw readback: 0043
09.508: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0043
09.508: <09>Lane 03 nibble 1 adjusted value (post nibble): 0042
09.508: <09>Lane 04 nibble 1 raw readback: 003a
09.508: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003a
09.508: <09>Lane 04 nibble 1 adjusted value (post nibble): 003d
09.508: <09>Lane 05 nibble 1 raw readback: 003e
09.508: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003e
09.508: <09>Lane 05 nibble 1 adjusted value (post nibble): 003f
09.508: <09>Lane 06 nibble 1 raw readback: 0040
09.508: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0040
09.508: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
09.508: <09>Lane 07 nibble 1 raw readback: 0041
09.508: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
09.508: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
09.508: <09>Lane 08 nibble 1 raw readback: 003c
09.508: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003c
09.508: <09>Lane 08 nibble 1 adjusted value (post nibble): 003e
09.508: <09>original critical gross delay: 0
09.508: <09>new critical gross delay: 0
09.508: DIMM 0 RttNom: 3
09.508: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.508: DIMM 0 RttNom: 3
09.508: DIMM 0 RttWr: 2
09.508: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.508: DIMM 0 RttWr: 2
09.508: DIMM 0 RttNom: 3
09.508: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.508: DIMM 0 RttNom: 3
09.508: DIMM 0 RttWr: 2
09.508: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.508: DIMM 0 RttWr: 2
09.508: DIMM 1 RttNom: 3
09.508: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.508: DIMM 0 RttNom: 3
09.508: DIMM 1 RttWr: 2
09.508: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.508: DIMM 0 RttWr: 2
09.509: DIMM 1 RttNom: 3
09.508: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.509: DIMM 0 RttNom: 3
09.509: DIMM 1 RttWr: 2
09.509: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.509: DIMM 0 RttWr: 2
09.509: AgesaHwWlPhase1: training nibble 0
09.509: DIMM 1 RttNom: 3
09.509: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.509: DIMM 1 RttWr: 2
09.509: DIMM 1 RttWr: 2
09.509: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.509: DIMM 1 RttWr: 2
09.509: DIMM 1 RttNom: 3
09.509: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.509: DIMM 1 RttNom: 3
09.509: DIMM 1 RttWr: 2
09.509: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.509: DIMM 1 RttWr: 2
09.509: DIMM 0 RttNom: 3
09.509: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.509: DIMM 1 RttNom: 3
09.509: DIMM 0 RttWr: 2
09.509: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.509: DIMM 1 RttWr: 2
09.509: DIMM 0 RttNom: 3
09.509: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.509: DIMM 1 RttNom: 3
09.509: DIMM 0 RttWr: 2
09.509: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.509: DIMM 1 RttWr: 2
09.509: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.509: <09>Lane 00 initial seed: 0041
09.509: <09>Lane 01 initial seed: 0041
09.509: <09>Lane 02 initial seed: 0041
09.509: <09>Lane 03 initial seed: 0041
09.509: <09>Lane 04 initial seed: 0041
09.509: <09>Lane 05 initial seed: 0041
09.509: <09>Lane 06 initial seed: 0041
09.509: <09>Lane 07 initial seed: 0041
09.509: <09>Lane 08 initial seed: 0041
09.509: <09>Lane 00 nibble 0 raw readback: 003f
09.509: <09>Lane 00 nibble 0 adjusted value (pre nibble): 003f
09.509: <09>Lane 00 nibble 0 adjusted value (post nibble): 003f
09.509: <09>Lane 01 nibble 0 raw readback: 003a
09.509: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003a
09.509: <09>Lane 01 nibble 0 adjusted value (post nibble): 003a
09.509: <09>Lane 02 nibble 0 raw readback: 0038
09.509: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0038
09.509: <09>Lane 02 nibble 0 adjusted value (post nibble): 0038
09.509: <09>Lane 03 nibble 0 raw readback: 0035
09.509: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0035
09.509: <09>Lane 03 nibble 0 adjusted value (post nibble): 0035
09.509: <09>Lane 04 nibble 0 raw readback: 002e
09.509: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002e
09.509: <09>Lane 04 nibble 0 adjusted value (post nibble): 002e
09.509: <09>Lane 05 nibble 0 raw readback: 0032
09.509: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0032
09.509: <09>Lane 05 nibble 0 adjusted value (post nibble): 0032
09.509: <09>Lane 06 nibble 0 raw readback: 0033
09.509: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0033
09.509: <09>Lane 06 nibble 0 adjusted value (post nibble): 0033
09.509: <09>Lane 07 nibble 0 raw readback: 0035
09.509: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0035
09.509: <09>Lane 07 nibble 0 adjusted value (post nibble): 0035
09.509: <09>Lane 08 nibble 0 raw readback: 002f
09.509: <09>Lane 08 nibble 0 adjusted value (pre nibble): 002f
09.509: <09>Lane 08 nibble 0 adjusted value (post nibble): 002f
09.509: AgesaHwWlPhase1: training nibble 1
09.509: DIMM 1 RttNom: 3
09.509: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.509: DIMM 1 RttWr: 2
09.509: DIMM 1 RttWr: 2
09.509: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.510: DIMM 1 RttWr: 2
09.510: DIMM 1 RttNom: 3
09.510: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.510: DIMM 1 RttNom: 3
09.510: DIMM 1 RttWr: 2
09.510: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.510: DIMM 1 RttWr: 2
09.510: DIMM 0 RttNom: 3
09.510: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.510: DIMM 1 RttNom: 3
09.510: DIMM 0 RttWr: 2
09.510: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.510: DIMM 1 RttWr: 2
09.510: DIMM 0 RttNom: 3
09.510: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.510: DIMM 1 RttNom: 3
09.510: DIMM 0 RttWr: 2
09.510: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.510: DIMM 1 RttWr: 2
09.510: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.510: <09>Lane 00 initial seed: 0041
09.510: <09>Lane 01 initial seed: 0041
09.510: <09>Lane 02 initial seed: 0041
09.510: <09>Lane 03 initial seed: 0041
09.510: <09>Lane 04 initial seed: 0041
09.510: <09>Lane 05 initial seed: 0041
09.510: <09>Lane 06 initial seed: 0041
09.510: <09>Lane 07 initial seed: 0041
09.510: <09>Lane 08 initial seed: 0041
09.510: <09>Lane 00 nibble 1 raw readback: 003f
09.510: <09>Lane 00 nibble 1 adjusted value (pre nibble): 003f
09.510: <09>Lane 00 nibble 1 adjusted value (post nibble): 0040
09.510: <09>Lane 01 nibble 1 raw readback: 003b
09.510: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003b
09.510: <09>Lane 01 nibble 1 adjusted value (post nibble): 003e
09.510: <09>Lane 02 nibble 1 raw readback: 003a
09.510: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003a
09.510: <09>Lane 02 nibble 1 adjusted value (post nibble): 003d
09.510: <09>Lane 03 nibble 1 raw readback: 0036
09.510: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0036
09.510: <09>Lane 03 nibble 1 adjusted value (post nibble): 003b
09.510: <09>Lane 04 nibble 1 raw readback: 002e
09.510: <09>Lane 04 nibble 1 adjusted value (pre nibble): 002e
09.510: <09>Lane 04 nibble 1 adjusted value (post nibble): 0037
09.510: <09>Lane 05 nibble 1 raw readback: 0032
09.510: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0032
09.510: <09>Lane 05 nibble 1 adjusted value (post nibble): 0039
09.510: <09>Lane 06 nibble 1 raw readback: 0033
09.510: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0033
09.510: <09>Lane 06 nibble 1 adjusted value (post nibble): 003a
09.510: <09>Lane 07 nibble 1 raw readback: 0036
09.510: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0036
09.510: <09>Lane 07 nibble 1 adjusted value (post nibble): 003b
09.510: <09>Lane 08 nibble 1 raw readback: 002f
09.510: <09>Lane 08 nibble 1 adjusted value (pre nibble): 002f
09.510: <09>Lane 08 nibble 1 adjusted value (post nibble): 0038
09.510: <09>original critical gross delay: 0
09.510: <09>new critical gross delay: 0
09.510: DIMM 1 RttNom: 3
09.510: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.510: DIMM 1 RttNom: 3
09.510: DIMM 1 RttWr: 2
09.510: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.510: DIMM 1 RttWr: 2
09.511: DIMM 1 RttNom: 3
09.511: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.511: DIMM 1 RttNom: 3
09.511: DIMM 1 RttWr: 2
09.511: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.511: DIMM 1 RttWr: 2
09.511: DIMM 0 RttNom: 3
09.511: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.511: DIMM 1 RttNom: 3
09.511: DIMM 0 RttWr: 2
09.511: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.511: DIMM 1 RttWr: 2
09.511: DIMM 0 RttNom: 3
09.511: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.511: DIMM 1 RttNom: 3
09.511: DIMM 0 RttWr: 2
09.511: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.511: DIMM 1 RttWr: 2
09.511: AgesaHwWlPhase1: training nibble 0
09.511: DIMM 0 RttNom: 3
09.511: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.511: DIMM 0 RttWr: 2
09.511: DIMM 0 RttWr: 2
09.511: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.511: DIMM 0 RttWr: 2
09.511: DIMM 0 RttNom: 3
09.511: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.511: DIMM 0 RttNom: 3
09.511: DIMM 0 RttWr: 2
09.511: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.511: DIMM 0 RttWr: 2
09.511: DIMM 1 RttNom: 3
09.511: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.511: DIMM 0 RttNom: 3
09.511: DIMM 1 RttWr: 2
09.511: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.511: DIMM 0 RttWr: 2
09.511: DIMM 1 RttNom: 3
09.511: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.511: DIMM 0 RttNom: 3
09.511: DIMM 1 RttWr: 2
09.511: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.511: DIMM 0 RttWr: 2
09.511: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.511: <09>Lane 00 initial seed: 0041
09.511: <09>Lane 01 initial seed: 0041
09.511: <09>Lane 02 initial seed: 0041
09.511: <09>Lane 03 initial seed: 0041
09.511: <09>Lane 04 initial seed: 0041
09.511: <09>Lane 05 initial seed: 0041
09.511: <09>Lane 06 initial seed: 0041
09.511: <09>Lane 07 initial seed: 0041
09.511: <09>Lane 08 initial seed: 0041
09.511: <09>Lane 00 nibble 0 raw readback: 0049
09.511: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0049
09.511: <09>Lane 00 nibble 0 adjusted value (post nibble): 0049
09.511: <09>Lane 01 nibble 0 raw readback: 0046
09.511: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0046
09.511: <09>Lane 01 nibble 0 adjusted value (post nibble): 0046
09.511: <09>Lane 02 nibble 0 raw readback: 0043
09.511: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0043
09.511: <09>Lane 02 nibble 0 adjusted value (post nibble): 0043
09.511: <09>Lane 03 nibble 0 raw readback: 0040
09.511: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0040
09.511: <09>Lane 03 nibble 0 adjusted value (post nibble): 0040
09.511: <09>Lane 04 nibble 0 raw readback: 0039
09.511: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
09.511: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
09.511: <09>Lane 05 nibble 0 raw readback: 003b
09.511: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003b
09.511: <09>Lane 05 nibble 0 adjusted value (post nibble): 003b
09.511: <09>Lane 06 nibble 0 raw readback: 003d
09.511: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003d
09.511: <09>Lane 06 nibble 0 adjusted value (post nibble): 003d
09.512: <09>Lane 07 nibble 0 raw readback: 003f
09.512: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003f
09.512: <09>Lane 07 nibble 0 adjusted value (post nibble): 003f
09.512: <09>Lane 08 nibble 0 raw readback: 003a
09.512: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003a
09.512: <09>Lane 08 nibble 0 adjusted value (post nibble): 003a
09.512: AgesaHwWlPhase1: training nibble 1
09.512: DIMM 0 RttNom: 3
09.512: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.512: DIMM 0 RttWr: 2
09.512: DIMM 0 RttWr: 2
09.512: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.512: DIMM 0 RttWr: 2
09.512: DIMM 0 RttNom: 3
09.512: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.512: DIMM 0 RttNom: 3
09.512: DIMM 0 RttWr: 2
09.512: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.512: DIMM 0 RttWr: 2
09.512: DIMM 1 RttNom: 3
09.512: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.512: DIMM 0 RttNom: 3
09.512: DIMM 1 RttWr: 2
09.512: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.512: DIMM 0 RttWr: 2
09.512: DIMM 1 RttNom: 3
09.512: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.512: DIMM 0 RttNom: 3
09.512: DIMM 1 RttWr: 2
09.512: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.512: DIMM 0 RttWr: 2
09.512: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.512: <09>Lane 00 initial seed: 0041
09.512: <09>Lane 01 initial seed: 0041
09.512: <09>Lane 02 initial seed: 0041
09.512: <09>Lane 03 initial seed: 0041
09.512: <09>Lane 04 initial seed: 0041
09.512: <09>Lane 05 initial seed: 0041
09.512: <09>Lane 06 initial seed: 0041
09.512: <09>Lane 07 initial seed: 0041
09.512: <09>Lane 08 initial seed: 0041
09.512: <09>Lane 00 nibble 1 raw readback: 0049
09.512: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0049
09.512: <09>Lane 00 nibble 1 adjusted value (post nibble): 0045
09.512: <09>Lane 01 nibble 1 raw readback: 0045
09.512: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0045
09.512: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
09.512: <09>Lane 02 nibble 1 raw readback: 0044
09.512: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0044
09.512: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
09.512: <09>Lane 03 nibble 1 raw readback: 0040
09.512: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0040
09.512: <09>Lane 03 nibble 1 adjusted value (post nibble): 0040
09.512: <09>Lane 04 nibble 1 raw readback: 0038
09.512: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
09.512: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
09.512: <09>Lane 05 nibble 1 raw readback: 003a
09.512: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003a
09.512: <09>Lane 05 nibble 1 adjusted value (post nibble): 003d
09.512: <09>Lane 06 nibble 1 raw readback: 003d
09.512: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003d
09.512: <09>Lane 06 nibble 1 adjusted value (post nibble): 003f
09.512: <09>Lane 07 nibble 1 raw readback: 003f
09.512: <09>Lane 07 nibble 1 adjusted value (pre nibble): 003f
09.512: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
09.512: <09>Lane 08 nibble 1 raw readback: 0039
09.512: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0039
09.512: <09>Lane 08 nibble 1 adjusted value (post nibble): 003d
09.512: <09>original critical gross delay: 0
09.512: <09>new critical gross delay: 0
09.513: DIMM 0 RttNom: 3
09.512: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.513: DIMM 0 RttNom: 3
09.513: DIMM 0 RttWr: 2
09.513: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.513: DIMM 0 RttWr: 2
09.513: DIMM 0 RttNom: 3
09.513: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.513: DIMM 0 RttNom: 3
09.513: DIMM 0 RttWr: 2
09.513: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.513: DIMM 0 RttWr: 2
09.513: DIMM 1 RttNom: 3
09.513: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.513: DIMM 0 RttNom: 3
09.513: DIMM 1 RttWr: 2
09.513: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.513: DIMM 0 RttWr: 2
09.513: DIMM 1 RttNom: 3
09.513: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.513: DIMM 0 RttNom: 3
09.513: DIMM 1 RttWr: 2
09.513: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.513: DIMM 0 RttWr: 2
09.513: AgesaHwWlPhase1: training nibble 0
09.513: DIMM 1 RttNom: 3
09.513: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.513: DIMM 1 RttWr: 2
09.513: DIMM 1 RttWr: 2
09.513: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.513: DIMM 1 RttWr: 2
09.513: DIMM 1 RttNom: 3
09.513: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.513: DIMM 1 RttNom: 3
09.513: DIMM 1 RttWr: 2
09.513: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.513: DIMM 1 RttWr: 2
09.513: DIMM 0 RttNom: 3
09.513: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.513: DIMM 1 RttNom: 3
09.513: DIMM 0 RttWr: 2
09.513: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.513: DIMM 1 RttWr: 2
09.513: DIMM 0 RttNom: 3
09.513: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.513: DIMM 1 RttNom: 3
09.513: DIMM 0 RttWr: 2
09.513: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.513: DIMM 1 RttWr: 2
09.513: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.513: <09>Lane 00 initial seed: 0041
09.513: <09>Lane 01 initial seed: 0041
09.513: <09>Lane 02 initial seed: 0041
09.513: <09>Lane 03 initial seed: 0041
09.513: <09>Lane 04 initial seed: 0041
09.513: <09>Lane 05 initial seed: 0041
09.513: <09>Lane 06 initial seed: 0041
09.513: <09>Lane 07 initial seed: 0041
09.513: <09>Lane 08 initial seed: 0041
09.513: <09>Lane 00 nibble 0 raw readback: 003f
09.513: <09>Lane 00 nibble 0 adjusted value (pre nibble): 003f
09.513: <09>Lane 00 nibble 0 adjusted value (post nibble): 003f
09.513: <09>Lane 01 nibble 0 raw readback: 003e
09.513: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003e
09.513: <09>Lane 01 nibble 0 adjusted value (post nibble): 003e
09.513: <09>Lane 02 nibble 0 raw readback: 0038
09.513: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0038
09.513: <09>Lane 02 nibble 0 adjusted value (post nibble): 0038
09.513: <09>Lane 03 nibble 0 raw readback: 0037
09.513: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0037
09.513: <09>Lane 03 nibble 0 adjusted value (post nibble): 0037
09.513: <09>Lane 04 nibble 0 raw readback: 002e
09.513: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002e
09.513: <09>Lane 04 nibble 0 adjusted value (post nibble): 002e
09.514: <09>Lane 05 nibble 0 raw readback: 0031
09.513: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0031
09.514: <09>Lane 05 nibble 0 adjusted value (post nibble): 0031
09.514: <09>Lane 06 nibble 0 raw readback: 0033
09.514: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0033
09.514: <09>Lane 06 nibble 0 adjusted value (post nibble): 0033
09.514: <09>Lane 07 nibble 0 raw readback: 0036
09.514: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0036
09.514: <09>Lane 07 nibble 0 adjusted value (post nibble): 0036
09.514: <09>Lane 08 nibble 0 raw readback: 0030
09.514: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0030
09.514: <09>Lane 08 nibble 0 adjusted value (post nibble): 0030
09.514: AgesaHwWlPhase1: training nibble 1
09.514: DIMM 1 RttNom: 3
09.514: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.514: DIMM 1 RttWr: 2
09.514: DIMM 1 RttWr: 2
09.514: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.514: DIMM 1 RttWr: 2
09.514: DIMM 1 RttNom: 3
09.514: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.514: DIMM 1 RttNom: 3
09.514: DIMM 1 RttWr: 2
09.514: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.514: DIMM 1 RttWr: 2
09.514: DIMM 0 RttNom: 3
09.514: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.514: DIMM 1 RttNom: 3
09.514: DIMM 0 RttWr: 2
09.514: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.514: DIMM 1 RttWr: 2
09.514: DIMM 0 RttNom: 3
09.514: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.514: DIMM 1 RttNom: 3
09.514: DIMM 0 RttWr: 2
09.514: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.514: DIMM 1 RttWr: 2
09.514: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.514: <09>Lane 00 initial seed: 0041
09.514: <09>Lane 01 initial seed: 0041
09.514: <09>Lane 02 initial seed: 0041
09.514: <09>Lane 03 initial seed: 0041
09.514: <09>Lane 04 initial seed: 0041
09.514: <09>Lane 05 initial seed: 0041
09.514: <09>Lane 06 initial seed: 0041
09.514: <09>Lane 07 initial seed: 0041
09.514: <09>Lane 08 initial seed: 0041
09.514: <09>Lane 00 nibble 1 raw readback: 0040
09.514: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0040
09.514: <09>Lane 00 nibble 1 adjusted value (post nibble): 0040
09.514: <09>Lane 01 nibble 1 raw readback: 003d
09.514: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003d
09.514: <09>Lane 01 nibble 1 adjusted value (post nibble): 003f
09.514: <09>Lane 02 nibble 1 raw readback: 0039
09.514: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0039
09.514: <09>Lane 02 nibble 1 adjusted value (post nibble): 003d
09.514: <09>Lane 03 nibble 1 raw readback: 0039
09.514: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0039
09.514: <09>Lane 03 nibble 1 adjusted value (post nibble): 003d
09.514: <09>Lane 04 nibble 1 raw readback: 002f
09.514: <09>Lane 04 nibble 1 adjusted value (pre nibble): 002f
09.514: <09>Lane 04 nibble 1 adjusted value (post nibble): 0038
09.514: <09>Lane 05 nibble 1 raw readback: 0032
09.514: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0032
09.514: <09>Lane 05 nibble 1 adjusted value (post nibble): 0039
09.514: <09>Lane 06 nibble 1 raw readback: 0033
09.514: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0033
09.514: <09>Lane 06 nibble 1 adjusted value (post nibble): 003a
09.514: <09>Lane 07 nibble 1 raw readback: 0036
09.514: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0036
09.514: <09>Lane 07 nibble 1 adjusted value (post nibble): 003b
09.514: <09>Lane 08 nibble 1 raw readback: 0030
09.514: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0030
09.514: <09>Lane 08 nibble 1 adjusted value (post nibble): 0038
09.514: <09>original critical gross delay: 0
09.514: <09>new critical gross delay: 0
09.515: DIMM 1 RttNom: 3
09.515: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.515: DIMM 1 RttNom: 3
09.515: DIMM 1 RttWr: 2
09.515: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.515: DIMM 1 RttWr: 2
09.515: DIMM 1 RttNom: 3
09.515: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.515: DIMM 1 RttNom: 3
09.515: DIMM 1 RttWr: 2
09.515: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.515: DIMM 1 RttWr: 2
09.515: DIMM 0 RttNom: 3
09.515: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.515: DIMM 1 RttNom: 3
09.515: DIMM 0 RttWr: 2
09.515: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.515: DIMM 1 RttWr: 2
09.515: DIMM 0 RttNom: 3
09.515: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.515: DIMM 1 RttNom: 3
09.515: DIMM 0 RttWr: 2
09.515: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.515: DIMM 1 RttWr: 2
09.515: activate_spd_rom() for node 01
09.515: enable_spd_node1()
09.515: AgesaHwWlPhase1: training nibble 0
09.515: DIMM 0 RttNom: 3
09.515: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.515: DIMM 0 RttWr: 2
09.515: DIMM 0 RttWr: 2
09.516: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.515: DIMM 0 RttWr: 2
09.515: DIMM 0 RttNom: 3
09.516: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.516: DIMM 0 RttNom: 3
09.516: DIMM 0 RttWr: 2
09.516: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.516: DIMM 0 RttWr: 2
09.516: DIMM 1 RttNom: 3
09.516: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.516: DIMM 0 RttNom: 3
09.516: DIMM 1 RttWr: 2
09.516: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.516: DIMM 0 RttWr: 2
09.516: DIMM 1 RttNom: 3
09.516: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.516: DIMM 0 RttNom: 3
09.516: DIMM 1 RttWr: 2
09.516: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.516: DIMM 0 RttWr: 2
09.516: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.516: <09>Lane 00 initial seed: 0041
09.516: <09>Lane 01 initial seed: 0041
09.516: <09>Lane 02 initial seed: 0041
09.516: <09>Lane 03 initial seed: 0041
09.516: <09>Lane 04 initial seed: 0041
09.516: <09>Lane 05 initial seed: 0041
09.516: <09>Lane 06 initial seed: 0041
09.516: <09>Lane 07 initial seed: 0041
09.516: <09>Lane 08 initial seed: 0041
09.516: <09>Lane 00 nibble 0 raw readback: 003a
09.516: <09>Lane 00 nibble 0 adjusted value (pre nibble): 003a
09.516: <09>Lane 00 nibble 0 adjusted value (post nibble): 003a
09.516: <09>Lane 01 nibble 0 raw readback: 0037
09.516: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0037
09.516: <09>Lane 01 nibble 0 adjusted value (post nibble): 0037
09.516: <09>Lane 02 nibble 0 raw readback: 0034
09.516: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0034
09.516: <09>Lane 02 nibble 0 adjusted value (post nibble): 0034
09.516: <09>Lane 03 nibble 0 raw readback: 0032
09.516: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0032
09.516: <09>Lane 03 nibble 0 adjusted value (post nibble): 0032
09.516: <09>Lane 04 nibble 0 raw readback: 0030
09.516: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0030
09.516: <09>Lane 04 nibble 0 adjusted value (post nibble): 0030
09.516: <09>Lane 05 nibble 0 raw readback: 0032
09.516: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0032
09.516: <09>Lane 05 nibble 0 adjusted value (post nibble): 0032
09.516: <09>Lane 06 nibble 0 raw readback: 0034
09.516: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0034
09.516: <09>Lane 06 nibble 0 adjusted value (post nibble): 0034
09.516: <09>Lane 07 nibble 0 raw readback: 0038
09.516: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0038
09.516: <09>Lane 07 nibble 0 adjusted value (post nibble): 0038
09.516: <09>Lane 08 nibble 0 raw readback: 002f
09.516: <09>Lane 08 nibble 0 adjusted value (pre nibble): 002f
09.516: <09>Lane 08 nibble 0 adjusted value (post nibble): 002f
09.516: AgesaHwWlPhase1: training nibble 1
09.516: DIMM 0 RttNom: 3
09.516: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.516: DIMM 0 RttWr: 2
09.516: DIMM 0 RttWr: 2
09.516: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.516: DIMM 0 RttWr: 2
09.516: DIMM 0 RttNom: 3
09.516: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.517: DIMM 0 RttNom: 3
09.517: DIMM 0 RttWr: 2
09.517: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.517: DIMM 0 RttWr: 2
09.517: DIMM 1 RttNom: 3
09.517: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.517: DIMM 0 RttNom: 3
09.517: DIMM 1 RttWr: 2
09.517: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.517: DIMM 0 RttWr: 2
09.517: DIMM 1 RttNom: 3
09.517: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.517: DIMM 0 RttNom: 3
09.517: DIMM 1 RttWr: 2
09.517: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.517: DIMM 0 RttWr: 2
09.517: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.517: <09>Lane 00 initial seed: 0041
09.517: <09>Lane 01 initial seed: 0041
09.517: <09>Lane 02 initial seed: 0041
09.517: <09>Lane 03 initial seed: 0041
09.517: <09>Lane 04 initial seed: 0041
09.517: <09>Lane 05 initial seed: 0041
09.517: <09>Lane 06 initial seed: 0041
09.517: <09>Lane 07 initial seed: 0041
09.517: <09>Lane 08 initial seed: 0041
09.517: <09>Lane 00 nibble 1 raw readback: 0039
09.517: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0039
09.517: <09>Lane 00 nibble 1 adjusted value (post nibble): 003d
09.517: <09>Lane 01 nibble 1 raw readback: 0037
09.517: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0037
09.517: <09>Lane 01 nibble 1 adjusted value (post nibble): 003c
09.517: <09>Lane 02 nibble 1 raw readback: 0033
09.517: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0033
09.517: <09>Lane 02 nibble 1 adjusted value (post nibble): 003a
09.517: <09>Lane 03 nibble 1 raw readback: 0032
09.517: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0032
09.517: <09>Lane 03 nibble 1 adjusted value (post nibble): 0039
09.517: <09>Lane 04 nibble 1 raw readback: 0030
09.517: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0030
09.517: <09>Lane 04 nibble 1 adjusted value (post nibble): 0038
09.517: <09>Lane 05 nibble 1 raw readback: 0032
09.517: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0032
09.517: <09>Lane 05 nibble 1 adjusted value (post nibble): 0039
09.517: <09>Lane 06 nibble 1 raw readback: 0035
09.517: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0035
09.517: <09>Lane 06 nibble 1 adjusted value (post nibble): 003b
09.517: <09>Lane 07 nibble 1 raw readback: 0038
09.517: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0038
09.517: <09>Lane 07 nibble 1 adjusted value (post nibble): 003c
09.517: <09>Lane 08 nibble 1 raw readback: 002e
09.517: <09>Lane 08 nibble 1 adjusted value (pre nibble): 002e
09.517: <09>Lane 08 nibble 1 adjusted value (post nibble): 0037
09.517: <09>original critical gross delay: 0
09.517: <09>new critical gross delay: 0
09.517: DIMM 0 RttNom: 3
09.517: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.517: DIMM 0 RttNom: 3
09.517: DIMM 0 RttWr: 2
09.517: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.517: DIMM 0 RttWr: 2
09.518: DIMM 0 RttNom: 3
09.518: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.518: DIMM 0 RttNom: 3
09.518: DIMM 0 RttWr: 2
09.518: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.518: DIMM 0 RttWr: 2
09.518: DIMM 1 RttNom: 3
09.518: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.518: DIMM 0 RttNom: 3
09.518: DIMM 1 RttWr: 2
09.518: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.518: DIMM 0 RttWr: 2
09.518: DIMM 1 RttNom: 3
09.518: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.518: DIMM 0 RttNom: 3
09.518: DIMM 1 RttWr: 2
09.518: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.518: DIMM 0 RttWr: 2
09.518: AgesaHwWlPhase1: training nibble 0
09.518: DIMM 1 RttNom: 3
09.518: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.518: DIMM 1 RttWr: 2
09.518: DIMM 1 RttWr: 2
09.518: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.518: DIMM 1 RttWr: 2
09.518: DIMM 1 RttNom: 3
09.518: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.518: DIMM 1 RttNom: 3
09.518: DIMM 1 RttWr: 2
09.518: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.518: DIMM 1 RttWr: 2
09.518: DIMM 0 RttNom: 3
09.518: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.518: DIMM 1 RttNom: 3
09.518: DIMM 0 RttWr: 2
09.518: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.518: DIMM 1 RttWr: 2
09.518: DIMM 0 RttNom: 3
09.518: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.518: DIMM 1 RttNom: 3
09.518: DIMM 0 RttWr: 2
09.518: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.518: DIMM 1 RttWr: 2
09.518: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.518: <09>Lane 00 initial seed: 0041
09.518: <09>Lane 01 initial seed: 0041
09.518: <09>Lane 02 initial seed: 0041
09.518: <09>Lane 03 initial seed: 0041
09.518: <09>Lane 04 initial seed: 0041
09.518: <09>Lane 05 initial seed: 0041
09.518: <09>Lane 06 initial seed: 0041
09.518: <09>Lane 07 initial seed: 0041
09.518: <09>Lane 08 initial seed: 0041
09.518: <09>Lane 00 nibble 0 raw readback: 0043
09.518: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0043
09.518: <09>Lane 00 nibble 0 adjusted value (post nibble): 0043
09.518: <09>Lane 01 nibble 0 raw readback: 003e
09.518: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003e
09.518: <09>Lane 01 nibble 0 adjusted value (post nibble): 003e
09.518: <09>Lane 02 nibble 0 raw readback: 003b
09.518: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003b
09.519: <09>Lane 02 nibble 0 adjusted value (post nibble): 003b
09.518: <09>Lane 03 nibble 0 raw readback: 003a
09.518: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003a
09.518: <09>Lane 03 nibble 0 adjusted value (post nibble): 003a
09.518: <09>Lane 04 nibble 0 raw readback: 0038
09.519: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0038
09.519: <09>Lane 04 nibble 0 adjusted value (post nibble): 0038
09.518: <09>Lane 05 nibble 0 raw readback: 003c
09.519: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003c
09.519: <09>Lane 05 nibble 0 adjusted value (post nibble): 003c
09.519: <09>Lane 06 nibble 0 raw readback: 003c
09.519: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003c
09.519: <09>Lane 06 nibble 0 adjusted value (post nibble): 003c
09.519: <09>Lane 07 nibble 0 raw readback: 0040
09.519: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0040
09.519: <09>Lane 07 nibble 0 adjusted value (post nibble): 0040
09.519: <09>Lane 08 nibble 0 raw readback: 0036
09.519: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
09.519: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
09.519: AgesaHwWlPhase1: training nibble 1
09.519: DIMM 1 RttNom: 3
09.519: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.519: DIMM 1 RttWr: 2
09.519: DIMM 1 RttWr: 2
09.519: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.519: DIMM 1 RttWr: 2
09.519: DIMM 1 RttNom: 3
09.519: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.519: DIMM 1 RttNom: 3
09.519: DIMM 1 RttWr: 2
09.519: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.519: DIMM 1 RttWr: 2
09.519: DIMM 0 RttNom: 3
09.519: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.519: DIMM 1 RttNom: 3
09.519: DIMM 0 RttWr: 2
09.519: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.519: DIMM 1 RttWr: 2
09.519: DIMM 0 RttNom: 3
09.519: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.519: DIMM 1 RttNom: 3
09.519: DIMM 0 RttWr: 2
09.519: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.519: DIMM 1 RttWr: 2
09.519: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.519: <09>Lane 00 initial seed: 0041
09.519: <09>Lane 01 initial seed: 0041
09.519: <09>Lane 02 initial seed: 0041
09.519: <09>Lane 03 initial seed: 0041
09.519: <09>Lane 04 initial seed: 0041
09.519: <09>Lane 05 initial seed: 0041
09.519: <09>Lane 06 initial seed: 0041
09.519: <09>Lane 07 initial seed: 0041
09.519: <09>Lane 08 initial seed: 0041
09.519: <09>Lane 00 nibble 1 raw readback: 0043
09.519: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0043
09.519: <09>Lane 00 nibble 1 adjusted value (post nibble): 0042
09.519: <09>Lane 01 nibble 1 raw readback: 003e
09.519: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003e
09.519: <09>Lane 01 nibble 1 adjusted value (post nibble): 003f
09.519: <09>Lane 02 nibble 1 raw readback: 003b
09.519: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003b
09.519: <09>Lane 02 nibble 1 adjusted value (post nibble): 003e
09.519: <09>Lane 03 nibble 1 raw readback: 003a
09.519: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003a
09.519: <09>Lane 03 nibble 1 adjusted value (post nibble): 003d
09.519: <09>Lane 04 nibble 1 raw readback: 0036
09.519: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0036
09.519: <09>Lane 04 nibble 1 adjusted value (post nibble): 003b
09.519: <09>Lane 05 nibble 1 raw readback: 003a
09.519: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003a
09.519: <09>Lane 05 nibble 1 adjusted value (post nibble): 003d
09.519: <09>Lane 06 nibble 1 raw readback: 003c
09.519: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003c
09.519: <09>Lane 06 nibble 1 adjusted value (post nibble): 003e
09.519: <09>Lane 07 nibble 1 raw readback: 003f
09.519: <09>Lane 07 nibble 1 adjusted value (pre nibble): 003f
09.519: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
09.519: <09>Lane 08 nibble 1 raw readback: 0036
09.519: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0036
09.519: <09>Lane 08 nibble 1 adjusted value (post nibble): 003b
09.520: <09>original critical gross delay: 0
09.520: <09>new critical gross delay: 0
09.520: DIMM 1 RttNom: 3
09.520: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.520: DIMM 1 RttNom: 3
09.520: DIMM 1 RttWr: 2
09.520: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.520: DIMM 1 RttWr: 2
09.520: DIMM 1 RttNom: 3
09.520: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.520: DIMM 1 RttNom: 3
09.520: DIMM 1 RttWr: 2
09.520: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.520: DIMM 1 RttWr: 2
09.520: DIMM 0 RttNom: 3
09.520: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.520: DIMM 1 RttNom: 3
09.520: DIMM 0 RttWr: 2
09.520: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.520: DIMM 1 RttWr: 2
09.520: DIMM 0 RttNom: 3
09.520: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.520: DIMM 1 RttNom: 3
09.520: DIMM 0 RttWr: 2
09.520: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.520: DIMM 1 RttWr: 2
09.520: AgesaHwWlPhase1: training nibble 0
09.520: DIMM 0 RttNom: 3
09.520: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.520: DIMM 0 RttWr: 2
09.520: DIMM 0 RttWr: 2
09.520: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.520: DIMM 0 RttWr: 2
09.520: DIMM 0 RttNom: 3
09.520: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.520: DIMM 0 RttNom: 3
09.520: DIMM 0 RttWr: 2
09.520: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.520: DIMM 0 RttWr: 2
09.520: DIMM 1 RttNom: 3
09.520: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.520: DIMM 0 RttNom: 3
09.520: DIMM 1 RttWr: 2
09.520: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.520: DIMM 0 RttWr: 2
09.520: DIMM 1 RttNom: 3
09.520: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.520: DIMM 0 RttNom: 3
09.520: DIMM 1 RttWr: 2
09.520: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.520: DIMM 0 RttWr: 2
09.520: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.520: <09>Lane 00 initial seed: 0041
09.520: <09>Lane 01 initial seed: 0041
09.520: <09>Lane 02 initial seed: 0041
09.520: <09>Lane 03 initial seed: 0041
09.520: <09>Lane 04 initial seed: 0041
09.520: <09>Lane 05 initial seed: 0041
09.520: <09>Lane 06 initial seed: 0041
09.521: <09>Lane 07 initial seed: 0041
09.521: <09>Lane 08 initial seed: 0041
09.521: <09>Lane 00 nibble 0 raw readback: 003c
09.521: <09>Lane 00 nibble 0 adjusted value (pre nibble): 003c
09.521: <09>Lane 00 nibble 0 adjusted value (post nibble): 003c
09.521: <09>Lane 01 nibble 0 raw readback: 0037
09.521: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0037
09.521: <09>Lane 01 nibble 0 adjusted value (post nibble): 0037
09.521: <09>Lane 02 nibble 0 raw readback: 0034
09.521: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0034
09.521: <09>Lane 02 nibble 0 adjusted value (post nibble): 0034
09.521: <09>Lane 03 nibble 0 raw readback: 0032
09.521: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0032
09.521: <09>Lane 03 nibble 0 adjusted value (post nibble): 0032
09.521: <09>Lane 04 nibble 0 raw readback: 0030
09.521: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0030
09.521: <09>Lane 04 nibble 0 adjusted value (post nibble): 0030
09.521: <09>Lane 05 nibble 0 raw readback: 0034
09.521: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0034
09.521: <09>Lane 05 nibble 0 adjusted value (post nibble): 0034
09.521: <09>Lane 06 nibble 0 raw readback: 0036
09.521: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0036
09.521: <09>Lane 06 nibble 0 adjusted value (post nibble): 0036
09.521: <09>Lane 07 nibble 0 raw readback: 0039
09.521: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0039
09.521: <09>Lane 07 nibble 0 adjusted value (post nibble): 0039
09.521: <09>Lane 08 nibble 0 raw readback: 002f
09.521: <09>Lane 08 nibble 0 adjusted value (pre nibble): 002f
09.521: <09>Lane 08 nibble 0 adjusted value (post nibble): 002f
09.521: AgesaHwWlPhase1: training nibble 1
09.521: DIMM 0 RttNom: 3
09.521: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.521: DIMM 0 RttWr: 2
09.521: DIMM 0 RttWr: 2
09.521: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.521: DIMM 0 RttWr: 2
09.521: DIMM 0 RttNom: 3
09.521: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.521: DIMM 0 RttNom: 3
09.521: DIMM 0 RttWr: 2
09.521: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.521: DIMM 0 RttWr: 2
09.521: DIMM 1 RttNom: 3
09.521: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.521: DIMM 0 RttNom: 3
09.521: DIMM 1 RttWr: 2
09.521: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.521: DIMM 0 RttWr: 2
09.521: DIMM 1 RttNom: 3
09.521: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.521: DIMM 0 RttNom: 3
09.521: DIMM 1 RttWr: 2
09.521: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.521: DIMM 0 RttWr: 2
09.521: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.521: <09>Lane 00 initial seed: 0041
09.521: <09>Lane 01 initial seed: 0041
09.521: <09>Lane 02 initial seed: 0041
09.521: <09>Lane 03 initial seed: 0041
09.521: <09>Lane 04 initial seed: 0041
09.521: <09>Lane 05 initial seed: 0041
09.521: <09>Lane 06 initial seed: 0041
09.521: <09>Lane 07 initial seed: 0041
09.521: <09>Lane 08 initial seed: 0041
09.521: <09>Lane 00 nibble 1 raw readback: 003b
09.521: <09>Lane 00 nibble 1 adjusted value (pre nibble): 003b
09.521: <09>Lane 00 nibble 1 adjusted value (post nibble): 003e
09.521: <09>Lane 01 nibble 1 raw readback: 0037
09.521: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0037
09.521: <09>Lane 01 nibble 1 adjusted value (post nibble): 003c
09.521: <09>Lane 02 nibble 1 raw readback: 0034
09.521: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0034
09.521: <09>Lane 02 nibble 1 adjusted value (post nibble): 003a
09.522: <09>Lane 03 nibble 1 raw readback: 0032
09.522: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0032
09.522: <09>Lane 03 nibble 1 adjusted value (post nibble): 0039
09.522: <09>Lane 04 nibble 1 raw readback: 0030
09.522: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0030
09.522: <09>Lane 04 nibble 1 adjusted value (post nibble): 0038
09.522: <09>Lane 05 nibble 1 raw readback: 0033
09.522: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0033
09.522: <09>Lane 05 nibble 1 adjusted value (post nibble): 003a
09.522: <09>Lane 06 nibble 1 raw readback: 0035
09.522: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0035
09.522: <09>Lane 06 nibble 1 adjusted value (post nibble): 003b
09.522: <09>Lane 07 nibble 1 raw readback: 0039
09.522: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0039
09.522: <09>Lane 07 nibble 1 adjusted value (post nibble): 003d
09.522: <09>Lane 08 nibble 1 raw readback: 002e
09.522: <09>Lane 08 nibble 1 adjusted value (pre nibble): 002e
09.522: <09>Lane 08 nibble 1 adjusted value (post nibble): 0037
09.522: <09>original critical gross delay: 0
09.522: <09>new critical gross delay: 0
09.522: DIMM 0 RttNom: 3
09.522: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.522: DIMM 0 RttNom: 3
09.522: DIMM 0 RttWr: 2
09.522: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.522: DIMM 0 RttWr: 2
09.522: DIMM 0 RttNom: 3
09.522: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.522: DIMM 0 RttNom: 3
09.522: DIMM 0 RttWr: 2
09.522: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.522: DIMM 0 RttWr: 2
09.522: DIMM 1 RttNom: 3
09.522: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.522: DIMM 0 RttNom: 3
09.522: DIMM 1 RttWr: 2
09.522: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.522: DIMM 0 RttWr: 2
09.522: DIMM 1 RttNom: 3
09.522: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.522: DIMM 0 RttNom: 3
09.522: DIMM 1 RttWr: 2
09.522: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.522: DIMM 0 RttWr: 2
09.522: AgesaHwWlPhase1: training nibble 0
09.522: DIMM 1 RttNom: 3
09.522: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.522: DIMM 1 RttWr: 2
09.522: DIMM 1 RttWr: 2
09.522: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.522: DIMM 1 RttWr: 2
09.522: DIMM 1 RttNom: 3
09.522: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.522: DIMM 1 RttNom: 3
09.522: DIMM 1 RttWr: 2
09.522: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.522: DIMM 1 RttWr: 2
09.522: DIMM 0 RttNom: 3
09.522: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.522: DIMM 1 RttNom: 3
09.522: DIMM 0 RttWr: 2
09.523: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.522: DIMM 1 RttWr: 2
09.523: DIMM 0 RttNom: 3
09.523: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.523: DIMM 1 RttNom: 3
09.523: DIMM 0 RttWr: 2
09.523: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.523: DIMM 1 RttWr: 2
09.523: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.523: <09>Lane 00 initial seed: 0041
09.523: <09>Lane 01 initial seed: 0041
09.523: <09>Lane 02 initial seed: 0041
09.523: <09>Lane 03 initial seed: 0041
09.523: <09>Lane 04 initial seed: 0041
09.523: <09>Lane 05 initial seed: 0041
09.523: <09>Lane 06 initial seed: 0041
09.523: <09>Lane 07 initial seed: 0041
09.523: <09>Lane 08 initial seed: 0041
09.523: <09>Lane 00 nibble 0 raw readback: 0042
09.523: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0042
09.523: <09>Lane 00 nibble 0 adjusted value (post nibble): 0042
09.523: <09>Lane 01 nibble 0 raw readback: 0040
09.523: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0040
09.523: <09>Lane 01 nibble 0 adjusted value (post nibble): 0040
09.523: <09>Lane 02 nibble 0 raw readback: 003c
09.523: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003c
09.523: <09>Lane 02 nibble 0 adjusted value (post nibble): 003c
09.523: <09>Lane 03 nibble 0 raw readback: 0039
09.523: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0039
09.523: <09>Lane 03 nibble 0 adjusted value (post nibble): 0039
09.523: <09>Lane 04 nibble 0 raw readback: 0038
09.523: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0038
09.523: <09>Lane 04 nibble 0 adjusted value (post nibble): 0038
09.523: <09>Lane 05 nibble 0 raw readback: 003b
09.523: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003b
09.523: <09>Lane 05 nibble 0 adjusted value (post nibble): 003b
09.523: <09>Lane 06 nibble 0 raw readback: 003e
09.523: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003e
09.523: <09>Lane 06 nibble 0 adjusted value (post nibble): 003e
09.523: <09>Lane 07 nibble 0 raw readback: 0040
09.523: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0040
09.523: <09>Lane 07 nibble 0 adjusted value (post nibble): 0040
09.523: <09>Lane 08 nibble 0 raw readback: 0036
09.523: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
09.523: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
09.523: AgesaHwWlPhase1: training nibble 1
09.523: DIMM 1 RttNom: 3
09.523: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.523: DIMM 1 RttWr: 2
09.523: DIMM 1 RttWr: 2
09.523: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.523: DIMM 1 RttWr: 2
09.523: DIMM 1 RttNom: 3
09.523: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.523: DIMM 1 RttNom: 3
09.523: DIMM 1 RttWr: 2
09.523: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.523: DIMM 1 RttWr: 2
09.523: DIMM 0 RttNom: 3
09.523: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.523: DIMM 1 RttNom: 3
09.523: DIMM 0 RttWr: 2
09.523: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.523: DIMM 1 RttWr: 2
09.523: DIMM 0 RttNom: 3
09.523: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.523: DIMM 1 RttNom: 3
09.523: DIMM 0 RttWr: 2
09.523: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.523: DIMM 1 RttWr: 2
09.524: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.523: <09>Lane 00 initial seed: 0041
09.523: <09>Lane 01 initial seed: 0041
09.523: <09>Lane 02 initial seed: 0041
09.524: <09>Lane 03 initial seed: 0041
09.524: <09>Lane 04 initial seed: 0041
09.524: <09>Lane 05 initial seed: 0041
09.524: <09>Lane 06 initial seed: 0041
09.524: <09>Lane 07 initial seed: 0041
09.524: <09>Lane 08 initial seed: 0041
09.524: <09>Lane 00 nibble 1 raw readback: 0043
09.524: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0043
09.524: <09>Lane 00 nibble 1 adjusted value (post nibble): 0042
09.524: <09>Lane 01 nibble 1 raw readback: 003f
09.524: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003f
09.524: <09>Lane 01 nibble 1 adjusted value (post nibble): 0040
09.524: <09>Lane 02 nibble 1 raw readback: 003c
09.524: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003c
09.524: <09>Lane 02 nibble 1 adjusted value (post nibble): 003e
09.524: <09>Lane 03 nibble 1 raw readback: 003a
09.524: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003a
09.524: <09>Lane 03 nibble 1 adjusted value (post nibble): 003d
09.524: <09>Lane 04 nibble 1 raw readback: 0038
09.524: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
09.524: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
09.524: <09>Lane 05 nibble 1 raw readback: 003a
09.524: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003a
09.524: <09>Lane 05 nibble 1 adjusted value (post nibble): 003d
09.524: <09>Lane 06 nibble 1 raw readback: 003f
09.524: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
09.524: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
09.524: <09>Lane 07 nibble 1 raw readback: 0041
09.524: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
09.524: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
09.524: <09>Lane 08 nibble 1 raw readback: 0037
09.524: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
09.524: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
09.524: <09>original critical gross delay: 0
09.524: <09>new critical gross delay: 0
09.524: DIMM 1 RttNom: 3
09.524: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.524: DIMM 1 RttNom: 3
09.524: DIMM 1 RttWr: 2
09.524: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.524: DIMM 1 RttWr: 2
09.524: DIMM 1 RttNom: 3
09.524: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.524: DIMM 1 RttNom: 3
09.524: DIMM 1 RttWr: 2
09.524: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.524: DIMM 1 RttWr: 2
09.524: DIMM 0 RttNom: 3
09.524: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.524: DIMM 1 RttNom: 3
09.524: DIMM 0 RttWr: 2
09.524: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.524: DIMM 1 RttWr: 2
09.524: DIMM 0 RttNom: 3
09.524: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.524: DIMM 1 RttNom: 3
09.524: DIMM 0 RttWr: 2
09.524: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.524: DIMM 1 RttWr: 2
09.525: activate_spd_rom() for node 02
09.525: enable_spd_node2()
09.525: AgesaHwWlPhase1: training nibble 0
09.525: DIMM 0 RttNom: 3
09.525: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.525: DIMM 0 RttWr: 2
09.525: DIMM 0 RttWr: 2
09.525: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.525: DIMM 0 RttWr: 2
09.525: DIMM 0 RttNom: 3
09.525: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.525: DIMM 0 RttNom: 3
09.525: DIMM 0 RttWr: 2
09.525: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.525: DIMM 0 RttWr: 2
09.525: DIMM 1 RttNom: 3
09.525: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.525: DIMM 0 RttNom: 3
09.525: DIMM 1 RttWr: 2
09.525: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.525: DIMM 0 RttWr: 2
09.525: DIMM 1 RttNom: 3
09.525: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.525: DIMM 0 RttNom: 3
09.525: DIMM 1 RttWr: 2
09.525: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.525: DIMM 0 RttWr: 2
09.525: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.525: <09>Lane 00 initial seed: 0041
09.525: <09>Lane 01 initial seed: 0041
09.525: <09>Lane 02 initial seed: 0041
09.525: <09>Lane 03 initial seed: 0041
09.525: <09>Lane 04 initial seed: 0041
09.525: <09>Lane 05 initial seed: 0041
09.525: <09>Lane 06 initial seed: 0041
09.525: <09>Lane 07 initial seed: 0041
09.525: <09>Lane 08 initial seed: 0041
09.525: <09>Lane 00 nibble 0 raw readback: 004c
09.525: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004c
09.525: <09>Lane 00 nibble 0 adjusted value (post nibble): 004c
09.525: <09>Lane 01 nibble 0 raw readback: 0045
09.525: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0045
09.525: <09>Lane 01 nibble 0 adjusted value (post nibble): 0045
09.525: <09>Lane 02 nibble 0 raw readback: 0044
09.525: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0044
09.525: <09>Lane 02 nibble 0 adjusted value (post nibble): 0044
09.525: <09>Lane 03 nibble 0 raw readback: 0042
09.525: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0042
09.525: <09>Lane 03 nibble 0 adjusted value (post nibble): 0042
09.525: <09>Lane 04 nibble 0 raw readback: 003a
09.525: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
09.525: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
09.525: <09>Lane 05 nibble 0 raw readback: 003d
09.525: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
09.526: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
09.526: <09>Lane 06 nibble 0 raw readback: 0040
09.526: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
09.526: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
09.526: <09>Lane 07 nibble 0 raw readback: 0042
09.526: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0042
09.526: <09>Lane 07 nibble 0 adjusted value (post nibble): 0042
09.526: <09>Lane 08 nibble 0 raw readback: 003b
09.526: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003b
09.526: <09>Lane 08 nibble 0 adjusted value (post nibble): 003b
09.526: AgesaHwWlPhase1: training nibble 1
09.526: DIMM 0 RttNom: 3
09.526: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.526: DIMM 0 RttWr: 2
09.526: DIMM 0 RttWr: 2
09.526: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.526: DIMM 0 RttWr: 2
09.526: DIMM 0 RttNom: 3
09.526: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.526: DIMM 0 RttNom: 3
09.526: DIMM 0 RttWr: 2
09.526: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.526: DIMM 0 RttWr: 2
09.526: DIMM 1 RttNom: 3
09.526: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.526: DIMM 0 RttNom: 3
09.526: DIMM 1 RttWr: 2
09.526: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.526: DIMM 0 RttWr: 2
09.526: DIMM 1 RttNom: 3
09.526: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.526: DIMM 0 RttNom: 3
09.526: DIMM 1 RttWr: 2
09.526: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.526: DIMM 0 RttWr: 2
09.526: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.526: <09>Lane 00 initial seed: 0041
09.526: <09>Lane 01 initial seed: 0041
09.526: <09>Lane 02 initial seed: 0041
09.526: <09>Lane 03 initial seed: 0041
09.526: <09>Lane 04 initial seed: 0041
09.526: <09>Lane 05 initial seed: 0041
09.526: <09>Lane 06 initial seed: 0041
09.526: <09>Lane 07 initial seed: 0041
09.526: <09>Lane 08 initial seed: 0041
09.526: <09>Lane 00 nibble 1 raw readback: 004a
09.526: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004a
09.526: <09>Lane 00 nibble 1 adjusted value (post nibble): 0045
09.526: <09>Lane 01 nibble 1 raw readback: 0046
09.526: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0046
09.526: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
09.526: <09>Lane 02 nibble 1 raw readback: 0045
09.526: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0045
09.526: <09>Lane 02 nibble 1 adjusted value (post nibble): 0043
09.526: <09>Lane 03 nibble 1 raw readback: 0041
09.526: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0041
09.526: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
09.526: <09>Lane 04 nibble 1 raw readback: 0039
09.526: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
09.526: <09>Lane 04 nibble 1 adjusted value (post nibble): 003d
09.526: <09>Lane 05 nibble 1 raw readback: 003c
09.526: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
09.526: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
09.526: <09>Lane 06 nibble 1 raw readback: 003f
09.526: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
09.526: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
09.527: <09>Lane 07 nibble 1 raw readback: 0041
09.526: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
09.526: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
09.527: <09>Lane 08 nibble 1 raw readback: 003a
09.527: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003a
09.527: <09>Lane 08 nibble 1 adjusted value (post nibble): 003d
09.527: <09>original critical gross delay: 0
09.527: <09>new critical gross delay: 0
09.527: DIMM 0 RttNom: 3
09.527: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.527: DIMM 0 RttNom: 3
09.527: DIMM 0 RttWr: 2
09.527: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.527: DIMM 0 RttWr: 2
09.527: DIMM 0 RttNom: 3
09.527: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.527: DIMM 0 RttNom: 3
09.527: DIMM 0 RttWr: 2
09.527: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.527: DIMM 0 RttWr: 2
09.527: DIMM 1 RttNom: 3
09.527: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.527: DIMM 0 RttNom: 3
09.527: DIMM 1 RttWr: 2
09.527: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.527: DIMM 0 RttWr: 2
09.527: DIMM 1 RttNom: 3
09.527: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.527: DIMM 0 RttNom: 3
09.527: DIMM 1 RttWr: 2
09.527: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.527: DIMM 0 RttWr: 2
09.527: AgesaHwWlPhase1: training nibble 0
09.527: DIMM 1 RttNom: 3
09.527: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.527: DIMM 1 RttWr: 2
09.527: DIMM 1 RttWr: 2
09.527: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.527: DIMM 1 RttWr: 2
09.527: DIMM 1 RttNom: 3
09.527: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.527: DIMM 1 RttNom: 3
09.527: DIMM 1 RttWr: 2
09.527: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.527: DIMM 1 RttWr: 2
09.527: DIMM 0 RttNom: 3
09.527: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.527: DIMM 1 RttNom: 3
09.527: DIMM 0 RttWr: 2
09.527: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.527: DIMM 1 RttWr: 2
09.527: DIMM 0 RttNom: 3
09.527: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.527: DIMM 1 RttNom: 3
09.527: DIMM 0 RttWr: 2
09.527: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.527: DIMM 1 RttWr: 2
09.527: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.527: <09>Lane 00 initial seed: 0041
09.527: <09>Lane 01 initial seed: 0041
09.528: <09>Lane 02 initial seed: 0041
09.528: <09>Lane 03 initial seed: 0041
09.528: <09>Lane 04 initial seed: 0041
09.528: <09>Lane 05 initial seed: 0041
09.528: <09>Lane 06 initial seed: 0041
09.528: <09>Lane 07 initial seed: 0041
09.528: <09>Lane 08 initial seed: 0041
09.528: <09>Lane 00 nibble 0 raw readback: 0040
09.528: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0040
09.528: <09>Lane 00 nibble 0 adjusted value (post nibble): 0040
09.528: <09>Lane 01 nibble 0 raw readback: 003b
09.528: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003b
09.528: <09>Lane 01 nibble 0 adjusted value (post nibble): 003b
09.528: <09>Lane 02 nibble 0 raw readback: 0039
09.528: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0039
09.528: <09>Lane 02 nibble 0 adjusted value (post nibble): 0039
09.528: <09>Lane 03 nibble 0 raw readback: 0036
09.528: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0036
09.528: <09>Lane 03 nibble 0 adjusted value (post nibble): 0036
09.528: <09>Lane 04 nibble 0 raw readback: 002e
09.528: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002e
09.528: <09>Lane 04 nibble 0 adjusted value (post nibble): 002e
09.528: <09>Lane 05 nibble 0 raw readback: 0032
09.528: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0032
09.528: <09>Lane 05 nibble 0 adjusted value (post nibble): 0032
09.528: <09>Lane 06 nibble 0 raw readback: 0034
09.528: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0034
09.528: <09>Lane 06 nibble 0 adjusted value (post nibble): 0034
09.528: <09>Lane 07 nibble 0 raw readback: 0036
09.528: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0036
09.528: <09>Lane 07 nibble 0 adjusted value (post nibble): 0036
09.528: <09>Lane 08 nibble 0 raw readback: 0030
09.528: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0030
09.528: <09>Lane 08 nibble 0 adjusted value (post nibble): 0030
09.528: AgesaHwWlPhase1: training nibble 1
09.528: DIMM 1 RttNom: 3
09.528: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.528: DIMM 1 RttWr: 2
09.528: DIMM 1 RttWr: 2
09.528: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.528: DIMM 1 RttWr: 2
09.528: DIMM 1 RttNom: 3
09.528: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.528: DIMM 1 RttNom: 3
09.528: DIMM 1 RttWr: 2
09.528: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.528: DIMM 1 RttWr: 2
09.528: DIMM 0 RttNom: 3
09.528: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.528: DIMM 1 RttNom: 3
09.528: DIMM 0 RttWr: 2
09.528: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.528: DIMM 1 RttWr: 2
09.528: DIMM 0 RttNom: 3
09.528: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.528: DIMM 1 RttNom: 3
09.528: DIMM 0 RttWr: 2
09.528: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.528: DIMM 1 RttWr: 2
09.528: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.528: <09>Lane 00 initial seed: 0041
09.528: <09>Lane 01 initial seed: 0041
09.528: <09>Lane 02 initial seed: 0041
09.528: <09>Lane 03 initial seed: 0041
09.528: <09>Lane 04 initial seed: 0041
09.528: <09>Lane 05 initial seed: 0041
09.528: <09>Lane 06 initial seed: 0041
09.528: <09>Lane 07 initial seed: 0041
09.528: <09>Lane 08 initial seed: 0041
09.528: <09>Lane 00 nibble 1 raw readback: 003f
09.529: <09>Lane 00 nibble 1 adjusted value (pre nibble): 003f
09.529: <09>Lane 00 nibble 1 adjusted value (post nibble): 0040
09.529: <09>Lane 01 nibble 1 raw readback: 003b
09.529: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003b
09.529: <09>Lane 01 nibble 1 adjusted value (post nibble): 003e
09.529: <09>Lane 02 nibble 1 raw readback: 003a
09.529: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003a
09.529: <09>Lane 02 nibble 1 adjusted value (post nibble): 003d
09.529: <09>Lane 03 nibble 1 raw readback: 0037
09.529: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0037
09.529: <09>Lane 03 nibble 1 adjusted value (post nibble): 003c
09.529: <09>Lane 04 nibble 1 raw readback: 002e
09.529: <09>Lane 04 nibble 1 adjusted value (pre nibble): 002e
09.529: <09>Lane 04 nibble 1 adjusted value (post nibble): 0037
09.529: <09>Lane 05 nibble 1 raw readback: 0031
09.529: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0031
09.529: <09>Lane 05 nibble 1 adjusted value (post nibble): 0039
09.529: <09>Lane 06 nibble 1 raw readback: 0033
09.529: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0033
09.529: <09>Lane 06 nibble 1 adjusted value (post nibble): 003a
09.529: <09>Lane 07 nibble 1 raw readback: 0037
09.529: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0037
09.529: <09>Lane 07 nibble 1 adjusted value (post nibble): 003c
09.529: <09>Lane 08 nibble 1 raw readback: 002f
09.529: <09>Lane 08 nibble 1 adjusted value (pre nibble): 002f
09.529: <09>Lane 08 nibble 1 adjusted value (post nibble): 0038
09.529: <09>original critical gross delay: 0
09.529: <09>new critical gross delay: 0
09.529: DIMM 1 RttNom: 3
09.529: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.529: DIMM 1 RttNom: 3
09.529: DIMM 1 RttWr: 2
09.529: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.529: DIMM 1 RttWr: 2
09.529: DIMM 1 RttNom: 3
09.529: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.529: DIMM 1 RttNom: 3
09.529: DIMM 1 RttWr: 2
09.529: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.529: DIMM 1 RttWr: 2
09.529: DIMM 0 RttNom: 3
09.529: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.529: DIMM 1 RttNom: 3
09.529: DIMM 0 RttWr: 2
09.529: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.529: DIMM 1 RttWr: 2
09.529: DIMM 0 RttNom: 3
09.529: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.529: DIMM 1 RttNom: 3
09.529: DIMM 0 RttWr: 2
09.529: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.529: DIMM 1 RttWr: 2
09.529: AgesaHwWlPhase1: training nibble 0
09.529: DIMM 0 RttNom: 3
09.529: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.529: DIMM 0 RttWr: 2
09.529: DIMM 0 RttWr: 2
09.529: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.529: DIMM 0 RttWr: 2
09.529: DIMM 0 RttNom: 3
09.529: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.529: DIMM 0 RttNom: 3
09.529: DIMM 0 RttWr: 2
09.529: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.529: DIMM 0 RttWr: 2
09.529: DIMM 1 RttNom: 3
09.530: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.530: DIMM 0 RttNom: 3
09.530: DIMM 1 RttWr: 2
09.530: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.530: DIMM 0 RttWr: 2
09.530: DIMM 1 RttNom: 3
09.530: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.530: DIMM 0 RttNom: 3
09.530: DIMM 1 RttWr: 2
09.530: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.530: DIMM 0 RttWr: 2
09.530: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.530: <09>Lane 00 initial seed: 0041
09.530: <09>Lane 01 initial seed: 0041
09.530: <09>Lane 02 initial seed: 0041
09.530: <09>Lane 03 initial seed: 0041
09.530: <09>Lane 04 initial seed: 0041
09.530: <09>Lane 05 initial seed: 0041
09.530: <09>Lane 06 initial seed: 0041
09.530: <09>Lane 07 initial seed: 0041
09.530: <09>Lane 08 initial seed: 0041
09.530: <09>Lane 00 nibble 0 raw readback: 004a
09.530: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004a
09.530: <09>Lane 00 nibble 0 adjusted value (post nibble): 004a
09.530: <09>Lane 01 nibble 0 raw readback: 0047
09.530: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0047
09.530: <09>Lane 01 nibble 0 adjusted value (post nibble): 0047
09.530: <09>Lane 02 nibble 0 raw readback: 0044
09.530: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0044
09.530: <09>Lane 02 nibble 0 adjusted value (post nibble): 0044
09.530: <09>Lane 03 nibble 0 raw readback: 0041
09.530: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0041
09.530: <09>Lane 03 nibble 0 adjusted value (post nibble): 0041
09.530: <09>Lane 04 nibble 0 raw readback: 0039
09.530: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
09.530: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
09.530: <09>Lane 05 nibble 0 raw readback: 003c
09.530: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003c
09.530: <09>Lane 05 nibble 0 adjusted value (post nibble): 003c
09.530: <09>Lane 06 nibble 0 raw readback: 003f
09.530: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003f
09.530: <09>Lane 06 nibble 0 adjusted value (post nibble): 003f
09.530: <09>Lane 07 nibble 0 raw readback: 0041
09.530: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0041
09.530: <09>Lane 07 nibble 0 adjusted value (post nibble): 0041
09.530: <09>Lane 08 nibble 0 raw readback: 003b
09.530: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003b
09.530: <09>Lane 08 nibble 0 adjusted value (post nibble): 003b
09.530: AgesaHwWlPhase1: training nibble 1
09.530: DIMM 0 RttNom: 3
09.530: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.530: DIMM 0 RttWr: 2
09.530: DIMM 0 RttWr: 2
09.530: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.530: DIMM 0 RttWr: 2
09.530: DIMM 0 RttNom: 3
09.530: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.530: DIMM 0 RttNom: 3
09.530: DIMM 0 RttWr: 2
09.530: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.530: DIMM 0 RttWr: 2
09.530: DIMM 1 RttNom: 3
09.530: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.530: DIMM 0 RttNom: 3
09.530: DIMM 1 RttWr: 2
09.530: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.530: DIMM 0 RttWr: 2
09.530: DIMM 1 RttNom: 3
09.530: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.531: DIMM 0 RttNom: 3
09.531: DIMM 1 RttWr: 2
09.531: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.531: DIMM 0 RttWr: 2
09.531: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.531: <09>Lane 00 initial seed: 0041
09.531: <09>Lane 01 initial seed: 0041
09.531: <09>Lane 02 initial seed: 0041
09.531: <09>Lane 03 initial seed: 0041
09.531: <09>Lane 04 initial seed: 0041
09.531: <09>Lane 05 initial seed: 0041
09.531: <09>Lane 06 initial seed: 0041
09.531: <09>Lane 07 initial seed: 0041
09.531: <09>Lane 08 initial seed: 0041
09.531: <09>Lane 00 nibble 1 raw readback: 004a
09.531: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004a
09.531: <09>Lane 00 nibble 1 adjusted value (post nibble): 0045
09.531: <09>Lane 01 nibble 1 raw readback: 0047
09.531: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0047
09.531: <09>Lane 01 nibble 1 adjusted value (post nibble): 0044
09.531: <09>Lane 02 nibble 1 raw readback: 0044
09.531: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0044
09.531: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
09.531: <09>Lane 03 nibble 1 raw readback: 0042
09.531: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0042
09.531: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
09.531: <09>Lane 04 nibble 1 raw readback: 0039
09.531: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
09.531: <09>Lane 04 nibble 1 adjusted value (post nibble): 003d
09.531: <09>Lane 05 nibble 1 raw readback: 003c
09.531: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
09.531: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
09.531: <09>Lane 06 nibble 1 raw readback: 003f
09.531: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
09.531: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
09.531: <09>Lane 07 nibble 1 raw readback: 0041
09.531: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
09.531: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
09.531: <09>Lane 08 nibble 1 raw readback: 003b
09.531: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003b
09.531: <09>Lane 08 nibble 1 adjusted value (post nibble): 003e
09.531: <09>original critical gross delay: 0
09.531: <09>new critical gross delay: 0
09.531: DIMM 0 RttNom: 3
09.531: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.531: DIMM 0 RttNom: 3
09.531: DIMM 0 RttWr: 2
09.531: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.531: DIMM 0 RttWr: 2
09.531: DIMM 0 RttNom: 3
09.531: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.531: DIMM 0 RttNom: 3
09.531: DIMM 0 RttWr: 2
09.531: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.531: DIMM 0 RttWr: 2
09.531: DIMM 1 RttNom: 3
09.531: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.531: DIMM 0 RttNom: 3
09.531: DIMM 1 RttWr: 2
09.531: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.531: DIMM 0 RttWr: 2
09.531: DIMM 1 RttNom: 3
09.531: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.531: DIMM 0 RttNom: 3
09.531: DIMM 1 RttWr: 2
09.531: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.531: DIMM 0 RttWr: 2
09.532: AgesaHwWlPhase1: training nibble 0
09.532: DIMM 1 RttNom: 3
09.532: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.532: DIMM 1 RttWr: 2
09.532: DIMM 1 RttWr: 2
09.532: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.532: DIMM 1 RttWr: 2
09.532: DIMM 1 RttNom: 3
09.532: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.532: DIMM 1 RttNom: 3
09.532: DIMM 1 RttWr: 2
09.532: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.532: DIMM 1 RttWr: 2
09.532: DIMM 0 RttNom: 3
09.532: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.532: DIMM 1 RttNom: 3
09.532: DIMM 0 RttWr: 2
09.532: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.532: DIMM 1 RttWr: 2
09.532: DIMM 0 RttNom: 3
09.532: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.532: DIMM 1 RttNom: 3
09.532: DIMM 0 RttWr: 2
09.532: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.532: DIMM 1 RttWr: 2
09.532: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.532: <09>Lane 00 initial seed: 0041
09.532: <09>Lane 01 initial seed: 0041
09.532: <09>Lane 02 initial seed: 0041
09.532: <09>Lane 03 initial seed: 0041
09.532: <09>Lane 04 initial seed: 0041
09.532: <09>Lane 05 initial seed: 0041
09.532: <09>Lane 06 initial seed: 0041
09.532: <09>Lane 07 initial seed: 0041
09.532: <09>Lane 08 initial seed: 0041
09.532: <09>Lane 00 nibble 0 raw readback: 003f
09.532: <09>Lane 00 nibble 0 adjusted value (pre nibble): 003f
09.532: <09>Lane 00 nibble 0 adjusted value (post nibble): 003f
09.532: <09>Lane 01 nibble 0 raw readback: 003c
09.532: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003c
09.532: <09>Lane 01 nibble 0 adjusted value (post nibble): 003c
09.532: <09>Lane 02 nibble 0 raw readback: 0038
09.532: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0038
09.532: <09>Lane 02 nibble 0 adjusted value (post nibble): 0038
09.532: <09>Lane 03 nibble 0 raw readback: 0035
09.532: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0035
09.532: <09>Lane 03 nibble 0 adjusted value (post nibble): 0035
09.532: <09>Lane 04 nibble 0 raw readback: 002d
09.532: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002d
09.532: <09>Lane 04 nibble 0 adjusted value (post nibble): 002d
09.532: <09>Lane 05 nibble 0 raw readback: 0030
09.532: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0030
09.532: <09>Lane 05 nibble 0 adjusted value (post nibble): 0030
09.532: <09>Lane 06 nibble 0 raw readback: 0033
09.532: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0033
09.532: <09>Lane 06 nibble 0 adjusted value (post nibble): 0033
09.532: <09>Lane 07 nibble 0 raw readback: 0036
09.532: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0036
09.532: <09>Lane 07 nibble 0 adjusted value (post nibble): 0036
09.532: <09>Lane 08 nibble 0 raw readback: 0030
09.532: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0030
09.532: <09>Lane 08 nibble 0 adjusted value (post nibble): 0030
09.532: AgesaHwWlPhase1: training nibble 1
09.532: DIMM 1 RttNom: 3
09.532: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.532: DIMM 1 RttWr: 2
09.532: DIMM 1 RttWr: 2
09.532: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.532: DIMM 1 RttWr: 2
09.533: DIMM 1 RttNom: 3
09.533: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.533: DIMM 1 RttNom: 3
09.533: DIMM 1 RttWr: 2
09.533: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.533: DIMM 1 RttWr: 2
09.533: DIMM 0 RttNom: 3
09.533: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.533: DIMM 1 RttNom: 3
09.533: DIMM 0 RttWr: 2
09.533: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.533: DIMM 1 RttWr: 2
09.533: DIMM 0 RttNom: 3
09.533: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.533: DIMM 1 RttNom: 3
09.533: DIMM 0 RttWr: 2
09.533: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.533: DIMM 1 RttWr: 2
09.533: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.533: <09>Lane 00 initial seed: 0041
09.533: <09>Lane 01 initial seed: 0041
09.533: <09>Lane 02 initial seed: 0041
09.533: <09>Lane 03 initial seed: 0041
09.533: <09>Lane 04 initial seed: 0041
09.533: <09>Lane 05 initial seed: 0041
09.533: <09>Lane 06 initial seed: 0041
09.533: <09>Lane 07 initial seed: 0041
09.533: <09>Lane 08 initial seed: 0041
09.533: <09>Lane 00 nibble 1 raw readback: 003d
09.533: <09>Lane 00 nibble 1 adjusted value (pre nibble): 003d
09.533: <09>Lane 00 nibble 1 adjusted value (post nibble): 003f
09.533: <09>Lane 01 nibble 1 raw readback: 003c
09.533: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003c
09.533: <09>Lane 01 nibble 1 adjusted value (post nibble): 003e
09.533: <09>Lane 02 nibble 1 raw readback: 0038
09.533: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0038
09.533: <09>Lane 02 nibble 1 adjusted value (post nibble): 003c
09.533: <09>Lane 03 nibble 1 raw readback: 0036
09.533: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0036
09.533: <09>Lane 03 nibble 1 adjusted value (post nibble): 003b
09.533: <09>Lane 04 nibble 1 raw readback: 002e
09.533: <09>Lane 04 nibble 1 adjusted value (pre nibble): 002e
09.533: <09>Lane 04 nibble 1 adjusted value (post nibble): 0037
09.533: <09>Lane 05 nibble 1 raw readback: 0030
09.533: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0030
09.533: <09>Lane 05 nibble 1 adjusted value (post nibble): 0038
09.533: <09>Lane 06 nibble 1 raw readback: 0034
09.533: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0034
09.533: <09>Lane 06 nibble 1 adjusted value (post nibble): 003a
09.533: <09>Lane 07 nibble 1 raw readback: 0036
09.533: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0036
09.533: <09>Lane 07 nibble 1 adjusted value (post nibble): 003b
09.533: <09>Lane 08 nibble 1 raw readback: 002f
09.533: <09>Lane 08 nibble 1 adjusted value (pre nibble): 002f
09.533: <09>Lane 08 nibble 1 adjusted value (post nibble): 0038
09.533: <09>original critical gross delay: 0
09.533: <09>new critical gross delay: 0
09.533: DIMM 1 RttNom: 3
09.533: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.533: DIMM 1 RttNom: 3
09.533: DIMM 1 RttWr: 2
09.533: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.533: DIMM 1 RttWr: 2
09.533: DIMM 1 RttNom: 3
09.534: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.533: DIMM 1 RttNom: 3
09.534: DIMM 1 RttWr: 2
09.534: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.534: DIMM 1 RttWr: 2
09.534: DIMM 0 RttNom: 3
09.534: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.534: DIMM 1 RttNom: 3
09.534: DIMM 0 RttWr: 2
09.534: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.534: DIMM 1 RttWr: 2
09.534: DIMM 0 RttNom: 3
09.534: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.534: DIMM 1 RttNom: 3
09.534: DIMM 0 RttWr: 2
09.534: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.534: DIMM 1 RttWr: 2
09.534: activate_spd_rom() for node 03
09.534: enable_spd_node3()
09.534: AgesaHwWlPhase1: training nibble 0
09.534: DIMM 0 RttNom: 3
09.534: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.534: DIMM 0 RttWr: 2
09.534: DIMM 0 RttWr: 2
09.534: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.534: DIMM 0 RttWr: 2
09.534: DIMM 0 RttNom: 3
09.534: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.534: DIMM 0 RttNom: 3
09.534: DIMM 0 RttWr: 2
09.534: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.534: DIMM 0 RttWr: 2
09.534: DIMM 1 RttNom: 3
09.534: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.534: DIMM 0 RttNom: 3
09.534: DIMM 1 RttWr: 2
09.534: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.534: DIMM 0 RttWr: 2
09.534: DIMM 1 RttNom: 3
09.534: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.534: DIMM 0 RttNom: 3
09.534: DIMM 1 RttWr: 2
09.534: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.534: DIMM 0 RttWr: 2
09.534: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.534: <09>Lane 00 initial seed: 0041
09.534: <09>Lane 01 initial seed: 0041
09.534: <09>Lane 02 initial seed: 0041
09.534: <09>Lane 03 initial seed: 0041
09.534: <09>Lane 04 initial seed: 0041
09.535: <09>Lane 05 initial seed: 0041
09.535: <09>Lane 06 initial seed: 0041
09.535: <09>Lane 07 initial seed: 0041
09.535: <09>Lane 08 initial seed: 0041
09.535: <09>Lane 00 nibble 0 raw readback: 0043
09.535: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0043
09.535: <09>Lane 00 nibble 0 adjusted value (post nibble): 0043
09.535: <09>Lane 01 nibble 0 raw readback: 003d
09.535: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003d
09.535: <09>Lane 01 nibble 0 adjusted value (post nibble): 003d
09.535: <09>Lane 02 nibble 0 raw readback: 003b
09.535: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003b
09.535: <09>Lane 02 nibble 0 adjusted value (post nibble): 003b
09.535: <09>Lane 03 nibble 0 raw readback: 003b
09.535: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
09.535: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
09.535: <09>Lane 04 nibble 0 raw readback: 003a
09.535: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
09.535: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
09.535: <09>Lane 05 nibble 0 raw readback: 003c
09.535: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003c
09.535: <09>Lane 05 nibble 0 adjusted value (post nibble): 003c
09.535: <09>Lane 06 nibble 0 raw readback: 003e
09.535: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003e
09.535: <09>Lane 06 nibble 0 adjusted value (post nibble): 003e
09.535: <09>Lane 07 nibble 0 raw readback: 0040
09.535: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0040
09.535: <09>Lane 07 nibble 0 adjusted value (post nibble): 0040
09.535: <09>Lane 08 nibble 0 raw readback: 0036
09.535: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
09.535: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
09.535: AgesaHwWlPhase1: training nibble 1
09.535: DIMM 0 RttNom: 3
09.535: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.535: DIMM 0 RttWr: 2
09.535: DIMM 0 RttWr: 2
09.535: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.535: DIMM 0 RttWr: 2
09.535: DIMM 0 RttNom: 3
09.535: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.535: DIMM 0 RttNom: 3
09.535: DIMM 0 RttWr: 2
09.535: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.535: DIMM 0 RttWr: 2
09.535: DIMM 1 RttNom: 3
09.535: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.535: DIMM 0 RttNom: 3
09.535: DIMM 1 RttWr: 2
09.535: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.535: DIMM 0 RttWr: 2
09.535: DIMM 1 RttNom: 3
09.535: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.535: DIMM 0 RttNom: 3
09.535: DIMM 1 RttWr: 2
09.535: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.535: DIMM 0 RttWr: 2
09.535: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.535: <09>Lane 00 initial seed: 0041
09.535: <09>Lane 01 initial seed: 0041
09.535: <09>Lane 02 initial seed: 0041
09.535: <09>Lane 03 initial seed: 0041
09.535: <09>Lane 04 initial seed: 0041
09.535: <09>Lane 05 initial seed: 0041
09.535: <09>Lane 06 initial seed: 0041
09.535: <09>Lane 07 initial seed: 0041
09.535: <09>Lane 08 initial seed: 0041
09.536: <09>Lane 00 nibble 1 raw readback: 0043
09.536: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0043
09.536: <09>Lane 00 nibble 1 adjusted value (post nibble): 0042
09.536: <09>Lane 01 nibble 1 raw readback: 0040
09.536: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0040
09.536: <09>Lane 01 nibble 1 adjusted value (post nibble): 0040
09.536: <09>Lane 02 nibble 1 raw readback: 003d
09.536: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003d
09.536: <09>Lane 02 nibble 1 adjusted value (post nibble): 003f
09.536: <09>Lane 03 nibble 1 raw readback: 003a
09.536: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003a
09.536: <09>Lane 03 nibble 1 adjusted value (post nibble): 003d
09.536: <09>Lane 04 nibble 1 raw readback: 0039
09.536: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
09.536: <09>Lane 04 nibble 1 adjusted value (post nibble): 003d
09.536: <09>Lane 05 nibble 1 raw readback: 003b
09.536: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003b
09.536: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
09.536: <09>Lane 06 nibble 1 raw readback: 003e
09.536: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003e
09.536: <09>Lane 06 nibble 1 adjusted value (post nibble): 003f
09.536: <09>Lane 07 nibble 1 raw readback: 0042
09.536: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
09.536: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
09.536: <09>Lane 08 nibble 1 raw readback: 0037
09.536: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
09.536: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
09.536: <09>original critical gross delay: 0
09.536: <09>new critical gross delay: 0
09.536: DIMM 0 RttNom: 3
09.536: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.536: DIMM 0 RttNom: 3
09.536: DIMM 0 RttWr: 2
09.536: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.536: DIMM 0 RttWr: 2
09.536: DIMM 0 RttNom: 3
09.536: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.536: DIMM 0 RttNom: 3
09.536: DIMM 0 RttWr: 2
09.536: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.536: DIMM 0 RttWr: 2
09.536: DIMM 1 RttNom: 3
09.536: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.536: DIMM 0 RttNom: 3
09.536: DIMM 1 RttWr: 2
09.536: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.536: DIMM 0 RttWr: 2
09.536: DIMM 1 RttNom: 3
09.536: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.536: DIMM 0 RttNom: 3
09.536: DIMM 1 RttWr: 2
09.536: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.536: DIMM 0 RttWr: 2
09.536: AgesaHwWlPhase1: training nibble 0
09.536: DIMM 1 RttNom: 3
09.536: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.536: DIMM 1 RttWr: 2
09.536: DIMM 1 RttWr: 2
09.536: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.536: DIMM 1 RttWr: 2
09.536: DIMM 1 RttNom: 3
09.536: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.536: DIMM 1 RttNom: 3
09.536: DIMM 1 RttWr: 2
09.537: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.537: DIMM 1 RttWr: 2
09.537: DIMM 0 RttNom: 3
09.537: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.537: DIMM 1 RttNom: 3
09.537: DIMM 0 RttWr: 2
09.537: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.537: DIMM 1 RttWr: 2
09.537: DIMM 0 RttNom: 3
09.537: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.537: DIMM 1 RttNom: 3
09.537: DIMM 0 RttWr: 2
09.537: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.537: DIMM 1 RttWr: 2
09.537: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.537: <09>Lane 00 initial seed: 0041
09.537: <09>Lane 01 initial seed: 0041
09.537: <09>Lane 02 initial seed: 0041
09.537: <09>Lane 03 initial seed: 0041
09.537: <09>Lane 04 initial seed: 0041
09.537: <09>Lane 05 initial seed: 0041
09.537: <09>Lane 06 initial seed: 0041
09.537: <09>Lane 07 initial seed: 0041
09.537: <09>Lane 08 initial seed: 0041
09.537: <09>Lane 00 nibble 0 raw readback: 0043
09.537: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0043
09.537: <09>Lane 00 nibble 0 adjusted value (post nibble): 0043
09.537: <09>Lane 01 nibble 0 raw readback: 003e
09.537: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003e
09.537: <09>Lane 01 nibble 0 adjusted value (post nibble): 003e
09.537: <09>Lane 02 nibble 0 raw readback: 003b
09.537: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003b
09.537: <09>Lane 02 nibble 0 adjusted value (post nibble): 003b
09.537: <09>Lane 03 nibble 0 raw readback: 003a
09.537: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003a
09.537: <09>Lane 03 nibble 0 adjusted value (post nibble): 003a
09.537: <09>Lane 04 nibble 0 raw readback: 0038
09.537: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0038
09.537: <09>Lane 04 nibble 0 adjusted value (post nibble): 0038
09.537: <09>Lane 05 nibble 0 raw readback: 003b
09.537: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003b
09.537: <09>Lane 05 nibble 0 adjusted value (post nibble): 003b
09.537: <09>Lane 06 nibble 0 raw readback: 003c
09.537: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003c
09.537: <09>Lane 06 nibble 0 adjusted value (post nibble): 003c
09.537: <09>Lane 07 nibble 0 raw readback: 0040
09.537: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0040
09.537: <09>Lane 07 nibble 0 adjusted value (post nibble): 0040
09.537: <09>Lane 08 nibble 0 raw readback: 0036
09.537: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
09.537: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
09.537: AgesaHwWlPhase1: training nibble 1
09.537: DIMM 1 RttNom: 3
09.537: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.537: DIMM 1 RttWr: 2
09.537: DIMM 1 RttWr: 2
09.537: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.537: DIMM 1 RttWr: 2
09.537: DIMM 1 RttNom: 3
09.537: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.537: DIMM 1 RttNom: 3
09.537: DIMM 1 RttWr: 2
09.537: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.537: DIMM 1 RttWr: 2
09.537: DIMM 0 RttNom: 3
09.537: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.537: DIMM 1 RttNom: 3
09.537: DIMM 0 RttWr: 2
09.537: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.537: DIMM 1 RttWr: 2
09.537: DIMM 0 RttNom: 3
09.537: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.538: DIMM 1 RttNom: 3
09.538: DIMM 0 RttWr: 2
09.538: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.538: DIMM 1 RttWr: 2
09.538: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.538: <09>Lane 00 initial seed: 0041
09.538: <09>Lane 01 initial seed: 0041
09.538: <09>Lane 02 initial seed: 0041
09.538: <09>Lane 03 initial seed: 0041
09.538: <09>Lane 04 initial seed: 0041
09.538: <09>Lane 05 initial seed: 0041
09.538: <09>Lane 06 initial seed: 0041
09.538: <09>Lane 07 initial seed: 0041
09.538: <09>Lane 08 initial seed: 0041
09.538: <09>Lane 00 nibble 1 raw readback: 0042
09.538: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0042
09.538: <09>Lane 00 nibble 1 adjusted value (post nibble): 0041
09.538: <09>Lane 01 nibble 1 raw readback: 003f
09.538: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003f
09.538: <09>Lane 01 nibble 1 adjusted value (post nibble): 0040
09.538: <09>Lane 02 nibble 1 raw readback: 003b
09.538: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003b
09.538: <09>Lane 02 nibble 1 adjusted value (post nibble): 003e
09.538: <09>Lane 03 nibble 1 raw readback: 003a
09.538: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003a
09.538: <09>Lane 03 nibble 1 adjusted value (post nibble): 003d
09.538: <09>Lane 04 nibble 1 raw readback: 0038
09.538: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
09.538: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
09.538: <09>Lane 05 nibble 1 raw readback: 003a
09.538: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003a
09.538: <09>Lane 05 nibble 1 adjusted value (post nibble): 003d
09.538: <09>Lane 06 nibble 1 raw readback: 003b
09.538: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003b
09.538: <09>Lane 06 nibble 1 adjusted value (post nibble): 003e
09.538: <09>Lane 07 nibble 1 raw readback: 0040
09.538: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0040
09.538: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
09.538: <09>Lane 08 nibble 1 raw readback: 0035
09.538: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0035
09.538: <09>Lane 08 nibble 1 adjusted value (post nibble): 003b
09.538: <09>original critical gross delay: 0
09.538: <09>new critical gross delay: 0
09.538: DIMM 1 RttNom: 3
09.538: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.538: DIMM 1 RttNom: 3
09.538: DIMM 1 RttWr: 2
09.538: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.538: DIMM 1 RttWr: 2
09.538: DIMM 1 RttNom: 3
09.538: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.538: DIMM 1 RttNom: 3
09.538: DIMM 1 RttWr: 2
09.538: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.538: DIMM 1 RttWr: 2
09.538: DIMM 0 RttNom: 3
09.538: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.538: DIMM 1 RttNom: 3
09.538: DIMM 0 RttWr: 2
09.538: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.538: DIMM 1 RttWr: 2
09.538: DIMM 0 RttNom: 3
09.538: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.538: DIMM 1 RttNom: 3
09.539: DIMM 0 RttWr: 2
09.539: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.539: DIMM 1 RttWr: 2
09.539: AgesaHwWlPhase1: training nibble 0
09.539: DIMM 0 RttNom: 3
09.539: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.539: DIMM 0 RttWr: 2
09.539: DIMM 0 RttWr: 2
09.539: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.539: DIMM 0 RttWr: 2
09.539: DIMM 0 RttNom: 3
09.539: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.539: DIMM 0 RttNom: 3
09.539: DIMM 0 RttWr: 2
09.539: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.539: DIMM 0 RttWr: 2
09.539: DIMM 1 RttNom: 3
09.539: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.539: DIMM 0 RttNom: 3
09.539: DIMM 1 RttWr: 2
09.539: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.539: DIMM 0 RttWr: 2
09.539: DIMM 1 RttNom: 3
09.539: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.539: DIMM 0 RttNom: 3
09.539: DIMM 1 RttWr: 2
09.539: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.539: DIMM 0 RttWr: 2
09.539: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.539: <09>Lane 00 initial seed: 0041
09.539: <09>Lane 01 initial seed: 0041
09.539: <09>Lane 02 initial seed: 0041
09.539: <09>Lane 03 initial seed: 0041
09.539: <09>Lane 04 initial seed: 0041
09.539: <09>Lane 05 initial seed: 0041
09.539: <09>Lane 06 initial seed: 0041
09.539: <09>Lane 07 initial seed: 0041
09.539: <09>Lane 08 initial seed: 0041
09.539: <09>Lane 00 nibble 0 raw readback: 0044
09.539: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0044
09.539: <09>Lane 00 nibble 0 adjusted value (post nibble): 0044
09.539: <09>Lane 01 nibble 0 raw readback: 0040
09.539: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0040
09.539: <09>Lane 01 nibble 0 adjusted value (post nibble): 0040
09.539: <09>Lane 02 nibble 0 raw readback: 003c
09.539: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003c
09.539: <09>Lane 02 nibble 0 adjusted value (post nibble): 003c
09.539: <09>Lane 03 nibble 0 raw readback: 003a
09.539: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003a
09.539: <09>Lane 03 nibble 0 adjusted value (post nibble): 003a
09.539: <09>Lane 04 nibble 0 raw readback: 003a
09.539: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
09.539: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
09.539: <09>Lane 05 nibble 0 raw readback: 003d
09.539: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
09.539: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
09.539: <09>Lane 06 nibble 0 raw readback: 0040
09.539: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
09.539: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
09.539: <09>Lane 07 nibble 0 raw readback: 0043
09.539: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0043
09.539: <09>Lane 07 nibble 0 adjusted value (post nibble): 0043
09.539: <09>Lane 08 nibble 0 raw readback: 0038
09.539: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0038
09.539: <09>Lane 08 nibble 0 adjusted value (post nibble): 0038
09.539: AgesaHwWlPhase1: training nibble 1
09.539: DIMM 0 RttNom: 3
09.539: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.540: DIMM 0 RttWr: 2
09.540: DIMM 0 RttWr: 2
09.540: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.539: DIMM 0 RttWr: 2
09.540: DIMM 0 RttNom: 3
09.540: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.540: DIMM 0 RttNom: 3
09.540: DIMM 0 RttWr: 2
09.540: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.540: DIMM 0 RttWr: 2
09.540: DIMM 1 RttNom: 3
09.540: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.540: DIMM 0 RttNom: 3
09.540: DIMM 1 RttWr: 2
09.540: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.540: DIMM 0 RttWr: 2
09.540: DIMM 1 RttNom: 3
09.540: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.540: DIMM 0 RttNom: 3
09.540: DIMM 1 RttWr: 2
09.540: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.540: DIMM 0 RttWr: 2
09.540: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.540: <09>Lane 00 initial seed: 0041
09.540: <09>Lane 01 initial seed: 0041
09.540: <09>Lane 02 initial seed: 0041
09.540: <09>Lane 03 initial seed: 0041
09.540: <09>Lane 04 initial seed: 0041
09.540: <09>Lane 05 initial seed: 0041
09.540: <09>Lane 06 initial seed: 0041
09.540: <09>Lane 07 initial seed: 0041
09.540: <09>Lane 08 initial seed: 0041
09.540: <09>Lane 00 nibble 1 raw readback: 0044
09.540: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0044
09.540: <09>Lane 00 nibble 1 adjusted value (post nibble): 0042
09.540: <09>Lane 01 nibble 1 raw readback: 0041
09.540: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0041
09.540: <09>Lane 01 nibble 1 adjusted value (post nibble): 0041
09.540: <09>Lane 02 nibble 1 raw readback: 003d
09.540: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003d
09.540: <09>Lane 02 nibble 1 adjusted value (post nibble): 003f
09.540: <09>Lane 03 nibble 1 raw readback: 003b
09.540: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
09.540: <09>Lane 03 nibble 1 adjusted value (post nibble): 003e
09.540: <09>Lane 04 nibble 1 raw readback: 0039
09.540: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
09.540: <09>Lane 04 nibble 1 adjusted value (post nibble): 003d
09.540: <09>Lane 05 nibble 1 raw readback: 003c
09.540: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
09.540: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
09.540: <09>Lane 06 nibble 1 raw readback: 003f
09.540: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
09.540: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
09.540: <09>Lane 07 nibble 1 raw readback: 0042
09.540: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
09.540: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
09.540: <09>Lane 08 nibble 1 raw readback: 0038
09.540: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0038
09.540: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
09.540: <09>original critical gross delay: 0
09.540: <09>new critical gross delay: 0
09.540: DIMM 0 RttNom: 3
09.540: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.540: DIMM 0 RttNom: 3
09.541: DIMM 0 RttWr: 2
09.540: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.540: DIMM 0 RttWr: 2
09.540: DIMM 0 RttNom: 3
09.541: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.541: DIMM 0 RttNom: 3
09.541: DIMM 0 RttWr: 2
09.541: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.541: DIMM 0 RttWr: 2
09.541: DIMM 1 RttNom: 3
09.541: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.541: DIMM 0 RttNom: 3
09.541: DIMM 1 RttWr: 2
09.541: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.541: DIMM 0 RttWr: 2
09.541: DIMM 1 RttNom: 3
09.541: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.541: DIMM 0 RttNom: 3
09.541: DIMM 1 RttWr: 2
09.541: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.541: DIMM 0 RttWr: 2
09.541: AgesaHwWlPhase1: training nibble 0
09.541: DIMM 1 RttNom: 3
09.541: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.541: DIMM 1 RttWr: 2
09.541: DIMM 1 RttWr: 2
09.541: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.541: DIMM 1 RttWr: 2
09.541: DIMM 1 RttNom: 3
09.541: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.541: DIMM 1 RttNom: 3
09.541: DIMM 1 RttWr: 2
09.541: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.541: DIMM 1 RttWr: 2
09.541: DIMM 0 RttNom: 3
09.541: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.541: DIMM 1 RttNom: 3
09.541: DIMM 0 RttWr: 2
09.541: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.541: DIMM 1 RttWr: 2
09.541: DIMM 0 RttNom: 3
09.541: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.541: DIMM 1 RttNom: 3
09.541: DIMM 0 RttWr: 2
09.541: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.541: DIMM 1 RttWr: 2
09.541: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.541: <09>Lane 00 initial seed: 0041
09.541: <09>Lane 01 initial seed: 0041
09.541: <09>Lane 02 initial seed: 0041
09.541: <09>Lane 03 initial seed: 0041
09.541: <09>Lane 04 initial seed: 0041
09.541: <09>Lane 05 initial seed: 0041
09.541: <09>Lane 06 initial seed: 0041
09.541: <09>Lane 07 initial seed: 0041
09.541: <09>Lane 08 initial seed: 0041
09.541: <09>Lane 00 nibble 0 raw readback: 0044
09.541: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0044
09.541: <09>Lane 00 nibble 0 adjusted value (post nibble): 0044
09.541: <09>Lane 01 nibble 0 raw readback: 0040
09.541: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0040
09.541: <09>Lane 01 nibble 0 adjusted value (post nibble): 0040
09.541: <09>Lane 02 nibble 0 raw readback: 003c
09.541: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003c
09.541: <09>Lane 02 nibble 0 adjusted value (post nibble): 003c
09.541: <09>Lane 03 nibble 0 raw readback: 003a
09.541: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003a
09.541: <09>Lane 03 nibble 0 adjusted value (post nibble): 003a
09.541: <09>Lane 04 nibble 0 raw readback: 0039
09.541: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
09.541: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
09.541: <09>Lane 05 nibble 0 raw readback: 003d
09.542: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
09.542: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
09.542: <09>Lane 06 nibble 0 raw readback: 0040
09.542: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
09.542: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
09.542: <09>Lane 07 nibble 0 raw readback: 0043
09.542: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0043
09.542: <09>Lane 07 nibble 0 adjusted value (post nibble): 0043
09.542: <09>Lane 08 nibble 0 raw readback: 0038
09.542: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0038
09.542: <09>Lane 08 nibble 0 adjusted value (post nibble): 0038
09.542: AgesaHwWlPhase1: training nibble 1
09.542: DIMM 1 RttNom: 3
09.542: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.542: DIMM 1 RttWr: 2
09.542: DIMM 1 RttWr: 2
09.542: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.542: DIMM 1 RttWr: 2
09.542: DIMM 1 RttNom: 3
09.542: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.542: DIMM 1 RttNom: 3
09.542: DIMM 1 RttWr: 2
09.542: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.542: DIMM 1 RttWr: 2
09.542: DIMM 0 RttNom: 3
09.542: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.542: DIMM 1 RttNom: 3
09.542: DIMM 0 RttWr: 2
09.542: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.542: DIMM 1 RttWr: 2
09.542: DIMM 0 RttNom: 3
09.542: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.542: DIMM 1 RttNom: 3
09.542: DIMM 0 RttWr: 2
09.542: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.542: DIMM 1 RttWr: 2
09.542: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.542: <09>Lane 00 initial seed: 0041
09.542: <09>Lane 01 initial seed: 0041
09.542: <09>Lane 02 initial seed: 0041
09.542: <09>Lane 03 initial seed: 0041
09.542: <09>Lane 04 initial seed: 0041
09.542: <09>Lane 05 initial seed: 0041
09.542: <09>Lane 06 initial seed: 0041
09.542: <09>Lane 07 initial seed: 0041
09.542: <09>Lane 08 initial seed: 0041
09.542: <09>Lane 00 nibble 1 raw readback: 0044
09.542: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0044
09.542: <09>Lane 00 nibble 1 adjusted value (post nibble): 0042
09.542: <09>Lane 01 nibble 1 raw readback: 0041
09.542: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0041
09.542: <09>Lane 01 nibble 1 adjusted value (post nibble): 0041
09.542: <09>Lane 02 nibble 1 raw readback: 003d
09.542: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003d
09.542: <09>Lane 02 nibble 1 adjusted value (post nibble): 003f
09.542: <09>Lane 03 nibble 1 raw readback: 003b
09.542: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
09.542: <09>Lane 03 nibble 1 adjusted value (post nibble): 003e
09.542: <09>Lane 04 nibble 1 raw readback: 0038
09.542: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
09.542: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
09.542: <09>Lane 05 nibble 1 raw readback: 003c
09.542: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
09.542: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
09.542: <09>Lane 06 nibble 1 raw readback: 003f
09.542: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
09.542: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
09.542: <09>Lane 07 nibble 1 raw readback: 0042
09.542: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
09.542: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
09.542: <09>Lane 08 nibble 1 raw readback: 0037
09.542: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
09.542: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
09.543: <09>original critical gross delay: 0
09.542: <09>new critical gross delay: 0
09.543: DIMM 1 RttNom: 3
09.543: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.543: DIMM 1 RttNom: 3
09.543: DIMM 1 RttWr: 2
09.543: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.543: DIMM 1 RttWr: 2
09.543: DIMM 1 RttNom: 3
09.543: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.543: DIMM 1 RttNom: 3
09.543: DIMM 1 RttWr: 2
09.543: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.543: DIMM 1 RttWr: 2
09.543: DIMM 0 RttNom: 3
09.543: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.543: DIMM 1 RttNom: 3
09.543: DIMM 0 RttWr: 2
09.543: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.543: DIMM 1 RttWr: 2
09.543: DIMM 0 RttNom: 3
09.543: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.543: DIMM 1 RttNom: 3
09.543: DIMM 0 RttWr: 2
09.543: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.543: DIMM 1 RttWr: 2
09.545: fam15_receiver_enable_training_seed: using seed: 0054
09.546: fam15_receiver_enable_training_seed: using seed: 0054
09.546: fam15_receiver_enable_training_seed: using seed: 0054
09.546: fam15_receiver_enable_training_seed: using seed: 0054
09.547: fam15_receiver_enable_training_seed: using seed: 0054
09.547: fam15_receiver_enable_training_seed: using seed: 0054
09.547: fam15_receiver_enable_training_seed: using seed: 0054
09.547: fam15_receiver_enable_training_seed: using seed: 0054
09.547: fam15_receiver_enable_training_seed: using seed: 004d
09.547: fam15_receiver_enable_training_seed: using seed: 004d
09.547: fam15_receiver_enable_training_seed: using seed: 004d
09.547: fam15_receiver_enable_training_seed: using seed: 004d
09.547: fam15_receiver_enable_training_seed: using seed: 004d
09.547: fam15_receiver_enable_training_seed: using seed: 004d
09.547: fam15_receiver_enable_training_seed: using seed: 004d
09.547: fam15_receiver_enable_training_seed: using seed: 004d
09.548: TrainRcvrEn: Status 2205
09.548: TrainRcvrEn: ErrStatus 0
09.548: TrainRcvrEn: ErrCode 0
09.548: TrainRcvrEn: Done
09.548: 
09.548: fam15_receiver_enable_training_seed: using seed: 0045
09.548: fam15_receiver_enable_training_seed: using seed: 0045
09.549: fam15_receiver_enable_training_seed: using seed: 0045
09.549: fam15_receiver_enable_training_seed: using seed: 0045
09.549: fam15_receiver_enable_training_seed: using seed: 0045
09.549: fam15_receiver_enable_training_seed: using seed: 0045
09.549: fam15_receiver_enable_training_seed: using seed: 0045
09.549: fam15_receiver_enable_training_seed: using seed: 0045
09.549: fam15_receiver_enable_training_seed: using seed: 0040
09.549: fam15_receiver_enable_training_seed: using seed: 0040
09.549: fam15_receiver_enable_training_seed: using seed: 0040
09.549: fam15_receiver_enable_training_seed: using seed: 0040
09.549: fam15_receiver_enable_training_seed: using seed: 0040
09.549: fam15_receiver_enable_training_seed: using seed: 0040
09.550: fam15_receiver_enable_training_seed: using seed: 0040
09.550: fam15_receiver_enable_training_seed: using seed: 0040
09.550: TrainRcvrEn: Status 2005
09.550: TrainRcvrEn: ErrStatus 0
09.550: TrainRcvrEn: ErrCode 0
09.550: TrainRcvrEn: Done
09.550: 
09.550: fam15_receiver_enable_training_seed: using seed: 0054
09.550: fam15_receiver_enable_training_seed: using seed: 0054
09.550: fam15_receiver_enable_training_seed: using seed: 0054
09.550: fam15_receiver_enable_training_seed: using seed: 0054
09.550: fam15_receiver_enable_training_seed: using seed: 0054
09.550: fam15_receiver_enable_training_seed: using seed: 0054
09.551: fam15_receiver_enable_training_seed: using seed: 0054
09.551: fam15_receiver_enable_training_seed: using seed: 0054
09.551: fam15_receiver_enable_training_seed: using seed: 004d
09.551: fam15_receiver_enable_training_seed: using seed: 004d
09.551: fam15_receiver_enable_training_seed: using seed: 004d
09.551: fam15_receiver_enable_training_seed: using seed: 004d
09.551: fam15_receiver_enable_training_seed: using seed: 004d
09.551: fam15_receiver_enable_training_seed: using seed: 004d
09.551: fam15_receiver_enable_training_seed: using seed: 004d
09.551: fam15_receiver_enable_training_seed: using seed: 004d
09.552: TrainRcvrEn: Status 2005
09.552: TrainRcvrEn: ErrStatus 0
09.552: TrainRcvrEn: ErrCode 0
09.552: TrainRcvrEn: Done
09.552: 
09.552: fam15_receiver_enable_training_seed: using seed: 0045
09.552: fam15_receiver_enable_training_seed: using seed: 0045
09.552: fam15_receiver_enable_training_seed: using seed: 0045
09.552: fam15_receiver_enable_training_seed: using seed: 0045
09.552: fam15_receiver_enable_training_seed: using seed: 0045
09.552: fam15_receiver_enable_training_seed: using seed: 0045
09.552: fam15_receiver_enable_training_seed: using seed: 0045
09.552: fam15_receiver_enable_training_seed: using seed: 0045
09.552: fam15_receiver_enable_training_seed: using seed: 0040
09.553: fam15_receiver_enable_training_seed: using seed: 0040
09.553: fam15_receiver_enable_training_seed: using seed: 0040
09.553: fam15_receiver_enable_training_seed: using seed: 0040
09.553: fam15_receiver_enable_training_seed: using seed: 0040
09.553: fam15_receiver_enable_training_seed: using seed: 0040
09.553: fam15_receiver_enable_training_seed: using seed: 0040
09.553: fam15_receiver_enable_training_seed: using seed: 0040
09.553: TrainRcvrEn: Status 2005
09.553: TrainRcvrEn: ErrStatus 0
09.553: TrainRcvrEn: ErrCode 0
09.553: TrainRcvrEn: Done
09.553: 
09.553: activate_spd_rom() for node 00
09.553: enable_spd_node0()
09.554: SetTargetFreq: Start
09.554: SetTargetFreq: Node 0: New frequency code: 0006
09.554: ChangeMemClk: Start
09.554: set_2t_configuration: Start
09.554: set_2t_configuration: Done
09.554: mct_BeforePlatformSpec: Start
09.554: mct_BeforePlatformSpec: Done
09.554: mct_PlatformSpec: Start
09.554: Programmed DCT 0 timing/termination pattern 00000000 20222222
09.554: mct_PlatformSpec: Done
09.554: set_2t_configuration: Start
09.554: set_2t_configuration: Done
09.555: mct_BeforePlatformSpec: Start
09.555: mct_BeforePlatformSpec: Done
09.555: mct_PlatformSpec: Start
09.555: Programmed DCT 1 timing/termination pattern 00000000 20222222
09.555: mct_PlatformSpec: Done
09.555: ChangeMemClk: Done
09.555: phyAssistedMemFnceTraining: Start
09.555: phyAssistedMemFnceTraining: training node 0 DCT 0
09.555: phyAssistedMemFnceTraining: done training node 0 DCT 0
09.555: phyAssistedMemFnceTraining: training node 0 DCT 1
09.555: phyAssistedMemFnceTraining: done training node 0 DCT 1
09.555: phyAssistedMemFnceTraining: Done
09.555: InitPhyCompensation: DCT 0: Start
09.555: Waiting for predriver calibration to be applied...done!
09.555: InitPhyCompensation: DCT 0: Done
09.555: phyAssistedMemFnceTraining: Start
09.555: phyAssistedMemFnceTraining: training node 0 DCT 0
09.555: phyAssistedMemFnceTraining: done training node 0 DCT 0
09.555: phyAssistedMemFnceTraining: training node 0 DCT 1
09.556: phyAssistedMemFnceTraining: done training node 0 DCT 1
09.556: phyAssistedMemFnceTraining: Done
09.556: InitPhyCompensation: DCT 1: Start
09.556: Waiting for predriver calibration to be applied...done!
09.556: InitPhyCompensation: DCT 1: Done
09.556: Preparing to send DCT 0 DIMM 0 RC10: 00 (F2xA8: 02000300)
09.556: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.556: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
09.556: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.556: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
09.556: Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 02000c00)
09.556: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.556: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
09.556: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.556: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
09.556: Preparing to send DCT 1 DIMM 0 RC10: 00 (F2xA8: 02000300)
09.556: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.556: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
09.557: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.557: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
09.557: Preparing to send DCT 1 DIMM 1 RC10: 00 (F2xA8: 02000c00)
09.557: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.557: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
09.557: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.557: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
09.557: SetTargetFreq: Done
09.557: SPD2ndTiming: Start
09.557: SPD2ndTiming: Done
09.557: mct_BeforeDramInit_Prod_D: Start
09.557: mct_ProgramODT_D: Start
09.557: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
09.557: mct_ProgramODT_D: Done
09.557: mct_BeforeDramInit_Prod_D: Done
09.557: mct_DramInit_Sw_D: Start
09.557: DIMM 0 RttWr: 2
09.558: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.558: mct_SendMrsCmd: Start
09.558: mct_SendMrsCmd: Done
09.558: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
09.558: mct_SendMrsCmd: Start
09.558: mct_SendMrsCmd: Done
09.558: DIMM 0 RttNom: 3
09.558: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.558: mct_SendMrsCmd: Start
09.558: mct_SendMrsCmd: Done
09.558: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001578
09.558: mct_SendMrsCmd: Start
09.558: mct_SendMrsCmd: Done
09.558: DIMM 0 RttWr: 2
09.558: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.558: mct_SendMrsCmd: Start
09.558: mct_SendMrsCmd: Done
09.558: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
09.558: mct_SendMrsCmd: Start
09.558: mct_SendMrsCmd: Done
09.558: DIMM 0 RttNom: 3
09.558: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.558: mct_SendMrsCmd: Start
09.558: mct_SendMrsCmd: Done
09.558: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201578
09.558: mct_SendMrsCmd: Start
09.558: mct_SendMrsCmd: Done
09.558: DIMM 1 RttWr: 2
09.558: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.558: mct_SendMrsCmd: Start
09.558: mct_SendMrsCmd: Done
09.558: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
09.558: mct_SendMrsCmd: Start
09.558: mct_SendMrsCmd: Done
09.558: DIMM 1 RttNom: 3
09.558: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.558: mct_SendMrsCmd: Start
09.558: mct_SendMrsCmd: Done
09.558: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401578
09.558: mct_SendMrsCmd: Start
09.558: mct_SendMrsCmd: Done
09.558: DIMM 1 RttWr: 2
09.558: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.558: mct_SendMrsCmd: Start
09.558: mct_SendMrsCmd: Done
09.558: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
09.558: mct_SendMrsCmd: Start
09.558: mct_SendMrsCmd: Done
09.558: DIMM 1 RttNom: 3
09.558: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.558: mct_SendMrsCmd: Start
09.558: mct_SendMrsCmd: Done
09.558: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601578
09.558: mct_SendMrsCmd: Start
09.558: mct_SendMrsCmd: Done
09.558: mct_DramInit_Sw_D: Done
09.559: AgesaHwWlPhase1: training nibble 0
09.559: DIMM 0 RttNom: 3
09.559: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.559: DIMM 0 RttWr: 2
09.559: DIMM 0 RttWr: 2
09.559: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.559: DIMM 0 RttWr: 2
09.559: DIMM 0 RttNom: 3
09.559: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.559: DIMM 0 RttNom: 3
09.559: DIMM 0 RttWr: 2
09.559: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.559: DIMM 0 RttWr: 2
09.559: DIMM 1 RttNom: 3
09.559: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.559: DIMM 0 RttNom: 3
09.559: DIMM 1 RttWr: 2
09.559: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.559: DIMM 0 RttWr: 2
09.559: DIMM 1 RttNom: 3
09.559: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.559: DIMM 0 RttNom: 3
09.559: DIMM 1 RttWr: 2
09.559: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.559: DIMM 0 RttWr: 2
09.559: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.559: <09>Lane 00 scaled delay: 0047
09.559: <09>Lane 00 new seed: 0047
09.559: <09>Lane 01 scaled delay: 0047
09.559: <09>Lane 01 new seed: 0047
09.559: <09>Lane 02 scaled delay: 0047
09.559: <09>Lane 02 new seed: 0047
09.559: <09>Lane 03 scaled delay: 0047
09.560: <09>Lane 03 new seed: 0047
09.560: <09>Lane 04 scaled delay: 0047
09.560: <09>Lane 04 new seed: 0047
09.560: <09>Lane 05 scaled delay: 0047
09.560: <09>Lane 05 new seed: 0047
09.560: <09>Lane 06 scaled delay: 0047
09.560: <09>Lane 06 new seed: 0047
09.560: <09>Lane 07 scaled delay: 0047
09.560: <09>Lane 07 new seed: 0047
09.560: <09>Lane 08 scaled delay: 0047
09.560: <09>Lane 08 new seed: 0047
09.560: <09>Lane 00 nibble 0 raw readback: 0050
09.560: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0050
09.560: <09>Lane 00 nibble 0 adjusted value (post nibble): 0050
09.560: <09>Lane 01 nibble 0 raw readback: 004a
09.560: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004a
09.560: <09>Lane 01 nibble 0 adjusted value (post nibble): 004a
09.560: <09>Lane 02 nibble 0 raw readback: 0047
09.560: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0047
09.560: <09>Lane 02 nibble 0 adjusted value (post nibble): 0047
09.560: <09>Lane 03 nibble 0 raw readback: 0044
09.560: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
09.560: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
09.560: <09>Lane 04 nibble 0 raw readback: 003a
09.560: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
09.560: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
09.560: <09>Lane 05 nibble 0 raw readback: 003e
09.560: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003e
09.560: <09>Lane 05 nibble 0 adjusted value (post nibble): 003e
09.560: <09>Lane 06 nibble 0 raw readback: 0041
09.560: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0041
09.560: <09>Lane 06 nibble 0 adjusted value (post nibble): 0041
09.560: <09>Lane 07 nibble 0 raw readback: 0042
09.560: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0042
09.560: <09>Lane 07 nibble 0 adjusted value (post nibble): 0042
09.560: <09>Lane 08 nibble 0 raw readback: 003c
09.560: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003c
09.560: <09>Lane 08 nibble 0 adjusted value (post nibble): 003c
09.560: AgesaHwWlPhase1: training nibble 1
09.560: DIMM 0 RttNom: 3
09.560: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.560: DIMM 0 RttWr: 2
09.560: DIMM 0 RttWr: 2
09.560: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.560: DIMM 0 RttWr: 2
09.560: DIMM 0 RttNom: 3
09.560: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.560: DIMM 0 RttNom: 3
09.560: DIMM 0 RttWr: 2
09.560: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.560: DIMM 0 RttWr: 2
09.560: DIMM 1 RttNom: 3
09.560: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.560: DIMM 0 RttNom: 3
09.560: DIMM 1 RttWr: 2
09.560: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.560: DIMM 0 RttWr: 2
09.560: DIMM 1 RttNom: 3
09.560: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.560: DIMM 0 RttNom: 3
09.560: DIMM 1 RttWr: 2
09.561: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.561: DIMM 0 RttWr: 2
09.561: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.561: <09>Lane 00 new seed: 0047
09.561: <09>Lane 01 new seed: 0047
09.561: <09>Lane 02 new seed: 0047
09.561: <09>Lane 03 new seed: 0047
09.561: <09>Lane 04 new seed: 0047
09.561: <09>Lane 05 new seed: 0047
09.561: <09>Lane 06 new seed: 0047
09.561: <09>Lane 07 new seed: 0047
09.561: <09>Lane 08 new seed: 0047
09.561: <09>Lane 00 nibble 1 raw readback: 004f
09.561: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004f
09.561: <09>Lane 00 nibble 1 adjusted value (post nibble): 004b
09.561: <09>Lane 01 nibble 1 raw readback: 004a
09.561: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004a
09.561: <09>Lane 01 nibble 1 adjusted value (post nibble): 0048
09.561: <09>Lane 02 nibble 1 raw readback: 0048
09.561: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0048
09.561: <09>Lane 02 nibble 1 adjusted value (post nibble): 0047
09.561: <09>Lane 03 nibble 1 raw readback: 0045
09.561: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
09.561: <09>Lane 03 nibble 1 adjusted value (post nibble): 0046
09.561: <09>Lane 04 nibble 1 raw readback: 003a
09.561: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003a
09.561: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
09.561: <09>Lane 05 nibble 1 raw readback: 003e
09.561: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003e
09.561: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
09.561: <09>Lane 06 nibble 1 raw readback: 0041
09.561: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0041
09.561: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
09.561: <09>Lane 07 nibble 1 raw readback: 0042
09.561: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
09.561: <09>Lane 07 nibble 1 adjusted value (post nibble): 0044
09.561: <09>Lane 08 nibble 1 raw readback: 003c
09.561: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003c
09.561: <09>Lane 08 nibble 1 adjusted value (post nibble): 0041
09.561: <09>original critical gross delay: 0
09.561: <09>new critical gross delay: 0
09.561: DIMM 0 RttNom: 3
09.561: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.561: DIMM 0 RttNom: 3
09.561: DIMM 0 RttWr: 2
09.561: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.561: DIMM 0 RttWr: 2
09.561: DIMM 0 RttNom: 3
09.561: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.561: DIMM 0 RttNom: 3
09.561: DIMM 0 RttWr: 2
09.561: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.561: DIMM 0 RttWr: 2
09.561: DIMM 1 RttNom: 3
09.561: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.561: DIMM 0 RttNom: 3
09.561: DIMM 1 RttWr: 2
09.561: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.561: DIMM 0 RttWr: 2
09.561: DIMM 1 RttNom: 3
09.562: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.562: DIMM 0 RttNom: 3
09.562: DIMM 1 RttWr: 2
09.562: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.562: DIMM 0 RttWr: 2
09.562: AgesaHwWlPhase1: training nibble 0
09.562: DIMM 1 RttNom: 3
09.562: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.562: DIMM 1 RttWr: 2
09.562: DIMM 1 RttWr: 2
09.562: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.562: DIMM 1 RttWr: 2
09.562: DIMM 1 RttNom: 3
09.562: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.562: DIMM 1 RttNom: 3
09.562: DIMM 1 RttWr: 2
09.562: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.562: DIMM 1 RttWr: 2
09.562: DIMM 0 RttNom: 3
09.562: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.562: DIMM 1 RttNom: 3
09.562: DIMM 0 RttWr: 2
09.562: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.562: DIMM 1 RttWr: 2
09.562: DIMM 0 RttNom: 3
09.562: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.562: DIMM 1 RttNom: 3
09.562: DIMM 0 RttWr: 2
09.562: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.562: DIMM 1 RttWr: 2
09.562: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.562: <09>Lane 00 scaled delay: 0047
09.562: <09>Lane 00 new seed: 0047
09.562: <09>Lane 01 scaled delay: 0047
09.562: <09>Lane 01 new seed: 0047
09.562: <09>Lane 02 scaled delay: 0047
09.562: <09>Lane 02 new seed: 0047
09.562: <09>Lane 03 scaled delay: 0047
09.562: <09>Lane 03 new seed: 0047
09.562: <09>Lane 04 scaled delay: 0047
09.562: <09>Lane 04 new seed: 0047
09.562: <09>Lane 05 scaled delay: 0047
09.562: <09>Lane 05 new seed: 0047
09.562: <09>Lane 06 scaled delay: 0047
09.562: <09>Lane 06 new seed: 0047
09.562: <09>Lane 07 scaled delay: 0047
09.562: <09>Lane 07 new seed: 0047
09.562: <09>Lane 08 scaled delay: 0047
09.562: <09>Lane 08 new seed: 0047
09.562: <09>Lane 00 nibble 0 raw readback: 0046
09.562: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0046
09.562: <09>Lane 00 nibble 0 adjusted value (post nibble): 0046
09.562: <09>Lane 01 nibble 0 raw readback: 003f
09.562: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003f
09.562: <09>Lane 01 nibble 0 adjusted value (post nibble): 003f
09.562: <09>Lane 02 nibble 0 raw readback: 003e
09.562: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003e
09.562: <09>Lane 02 nibble 0 adjusted value (post nibble): 003e
09.562: <09>Lane 03 nibble 0 raw readback: 003b
09.562: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
09.562: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
09.562: <09>Lane 04 nibble 0 raw readback: 0030
09.562: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0030
09.562: <09>Lane 04 nibble 0 adjusted value (post nibble): 0030
09.562: <09>Lane 05 nibble 0 raw readback: 0035
09.562: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0035
09.562: <09>Lane 05 nibble 0 adjusted value (post nibble): 0035
09.562: <09>Lane 06 nibble 0 raw readback: 0037
09.562: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0037
09.562: <09>Lane 06 nibble 0 adjusted value (post nibble): 0037
09.563: <09>Lane 07 nibble 0 raw readback: 003a
09.563: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003a
09.563: <09>Lane 07 nibble 0 adjusted value (post nibble): 003a
09.563: <09>Lane 08 nibble 0 raw readback: 0033
09.563: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0033
09.563: <09>Lane 08 nibble 0 adjusted value (post nibble): 0033
09.563: AgesaHwWlPhase1: training nibble 1
09.563: DIMM 1 RttNom: 3
09.563: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.563: DIMM 1 RttWr: 2
09.563: DIMM 1 RttWr: 2
09.563: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.563: DIMM 1 RttWr: 2
09.563: DIMM 1 RttNom: 3
09.563: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.563: DIMM 1 RttNom: 3
09.563: DIMM 1 RttWr: 2
09.563: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.563: DIMM 1 RttWr: 2
09.563: DIMM 0 RttNom: 3
09.563: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.563: DIMM 1 RttNom: 3
09.563: DIMM 0 RttWr: 2
09.563: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.563: DIMM 1 RttWr: 2
09.563: DIMM 0 RttNom: 3
09.563: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.563: DIMM 1 RttNom: 3
09.563: DIMM 0 RttWr: 2
09.563: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.563: DIMM 1 RttWr: 2
09.563: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.563: <09>Lane 00 new seed: 0047
09.563: <09>Lane 01 new seed: 0047
09.563: <09>Lane 02 new seed: 0047
09.563: <09>Lane 03 new seed: 0047
09.563: <09>Lane 04 new seed: 0047
09.563: <09>Lane 05 new seed: 0047
09.563: <09>Lane 06 new seed: 0047
09.563: <09>Lane 07 new seed: 0047
09.563: <09>Lane 08 new seed: 0047
09.563: <09>Lane 00 nibble 1 raw readback: 0046
09.563: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0046
09.563: <09>Lane 00 nibble 1 adjusted value (post nibble): 0046
09.563: <09>Lane 01 nibble 1 raw readback: 0040
09.563: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0040
09.563: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
09.563: <09>Lane 02 nibble 1 raw readback: 003f
09.563: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003f
09.563: <09>Lane 02 nibble 1 adjusted value (post nibble): 0043
09.563: <09>Lane 03 nibble 1 raw readback: 003b
09.563: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
09.563: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
09.563: <09>Lane 04 nibble 1 raw readback: 0030
09.563: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0030
09.563: <09>Lane 04 nibble 1 adjusted value (post nibble): 003b
09.563: <09>Lane 05 nibble 1 raw readback: 0035
09.563: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0035
09.563: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
09.563: <09>Lane 06 nibble 1 raw readback: 0037
09.563: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0037
09.563: <09>Lane 06 nibble 1 adjusted value (post nibble): 003f
09.563: <09>Lane 07 nibble 1 raw readback: 003a
09.563: <09>Lane 07 nibble 1 adjusted value (pre nibble): 003a
09.563: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
09.563: <09>Lane 08 nibble 1 raw readback: 0032
09.563: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0032
09.563: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
09.563: <09>original critical gross delay: 0
09.563: <09>new critical gross delay: 0
09.563: DIMM 1 RttNom: 3
09.563: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.564: DIMM 1 RttNom: 3
09.564: DIMM 1 RttWr: 2
09.564: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.564: DIMM 1 RttWr: 2
09.564: DIMM 1 RttNom: 3
09.564: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.564: DIMM 1 RttNom: 3
09.564: DIMM 1 RttWr: 2
09.564: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.564: DIMM 1 RttWr: 2
09.564: DIMM 0 RttNom: 3
09.564: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.564: DIMM 1 RttNom: 3
09.564: DIMM 0 RttWr: 2
09.564: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.564: DIMM 1 RttWr: 2
09.564: DIMM 0 RttNom: 3
09.564: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.564: DIMM 1 RttNom: 3
09.564: DIMM 0 RttWr: 2
09.564: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.564: DIMM 1 RttWr: 2
09.564: SPD2ndTiming: Start
09.564: SPD2ndTiming: Done
09.564: mct_BeforeDramInit_Prod_D: Start
09.564: mct_ProgramODT_D: Start
09.564: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
09.564: mct_ProgramODT_D: Done
09.565: mct_BeforeDramInit_Prod_D: Done
09.565: mct_DramInit_Sw_D: Start
09.565: DIMM 0 RttWr: 2
09.565: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.565: mct_SendMrsCmd: Start
09.565: mct_SendMrsCmd: Done
09.565: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
09.565: mct_SendMrsCmd: Start
09.565: mct_SendMrsCmd: Done
09.565: DIMM 0 RttNom: 3
09.565: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.565: mct_SendMrsCmd: Start
09.565: mct_SendMrsCmd: Done
09.565: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001578
09.565: mct_SendMrsCmd: Start
09.565: mct_SendMrsCmd: Done
09.565: DIMM 0 RttWr: 2
09.565: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.565: mct_SendMrsCmd: Start
09.565: mct_SendMrsCmd: Done
09.565: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
09.565: mct_SendMrsCmd: Start
09.565: mct_SendMrsCmd: Done
09.565: DIMM 0 RttNom: 3
09.565: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.565: mct_SendMrsCmd: Start
09.565: mct_SendMrsCmd: Done
09.565: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201578
09.565: mct_SendMrsCmd: Start
09.565: mct_SendMrsCmd: Done
09.565: DIMM 1 RttWr: 2
09.565: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.565: mct_SendMrsCmd: Start
09.565: mct_SendMrsCmd: Done
09.565: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
09.565: mct_SendMrsCmd: Start
09.565: mct_SendMrsCmd: Done
09.565: DIMM 1 RttNom: 3
09.565: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.565: mct_SendMrsCmd: Start
09.565: mct_SendMrsCmd: Done
09.565: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401578
09.565: mct_SendMrsCmd: Start
09.565: mct_SendMrsCmd: Done
09.565: DIMM 1 RttWr: 2
09.565: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.565: mct_SendMrsCmd: Start
09.565: mct_SendMrsCmd: Done
09.565: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
09.565: mct_SendMrsCmd: Start
09.565: mct_SendMrsCmd: Done
09.565: DIMM 1 RttNom: 3
09.565: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.565: mct_SendMrsCmd: Start
09.565: mct_SendMrsCmd: Done
09.565: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601578
09.565: mct_SendMrsCmd: Start
09.565: mct_SendMrsCmd: Done
09.565: mct_DramInit_Sw_D: Done
09.565: AgesaHwWlPhase1: training nibble 0
09.565: DIMM 0 RttNom: 3
09.565: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.565: DIMM 0 RttWr: 2
09.565: DIMM 0 RttWr: 2
09.565: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.565: DIMM 0 RttWr: 2
09.565: DIMM 0 RttNom: 3
09.565: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.565: DIMM 0 RttNom: 3
09.566: DIMM 0 RttWr: 2
09.566: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.566: DIMM 0 RttWr: 2
09.566: DIMM 1 RttNom: 3
09.566: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.566: DIMM 0 RttNom: 3
09.566: DIMM 1 RttWr: 2
09.566: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.566: DIMM 0 RttWr: 2
09.566: DIMM 1 RttNom: 3
09.566: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.566: DIMM 0 RttNom: 3
09.566: DIMM 1 RttWr: 2
09.566: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.566: DIMM 0 RttWr: 2
09.566: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.566: <09>Lane 00 scaled delay: 0047
09.566: <09>Lane 00 new seed: 0047
09.566: <09>Lane 01 scaled delay: 0047
09.566: <09>Lane 01 new seed: 0047
09.566: <09>Lane 02 scaled delay: 0047
09.566: <09>Lane 02 new seed: 0047
09.566: <09>Lane 03 scaled delay: 0047
09.566: <09>Lane 03 new seed: 0047
09.566: <09>Lane 04 scaled delay: 0047
09.566: <09>Lane 04 new seed: 0047
09.566: <09>Lane 05 scaled delay: 0047
09.566: <09>Lane 05 new seed: 0047
09.566: <09>Lane 06 scaled delay: 0047
09.566: <09>Lane 06 new seed: 0047
09.566: <09>Lane 07 scaled delay: 0047
09.566: <09>Lane 07 new seed: 0047
09.566: <09>Lane 08 scaled delay: 0047
09.566: <09>Lane 08 new seed: 0047
09.566: <09>Lane 00 nibble 0 raw readback: 004c
09.566: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004c
09.566: <09>Lane 00 nibble 0 adjusted value (post nibble): 004c
09.566: <09>Lane 01 nibble 0 raw readback: 0049
09.566: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0049
09.566: <09>Lane 01 nibble 0 adjusted value (post nibble): 0049
09.566: <09>Lane 02 nibble 0 raw readback: 0045
09.566: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0045
09.566: <09>Lane 02 nibble 0 adjusted value (post nibble): 0045
09.566: <09>Lane 03 nibble 0 raw readback: 0042
09.566: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0042
09.566: <09>Lane 03 nibble 0 adjusted value (post nibble): 0042
09.566: <09>Lane 04 nibble 0 raw readback: 0039
09.566: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
09.566: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
09.566: <09>Lane 05 nibble 0 raw readback: 003b
09.566: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003b
09.566: <09>Lane 05 nibble 0 adjusted value (post nibble): 003b
09.566: <09>Lane 06 nibble 0 raw readback: 003d
09.566: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003d
09.566: <09>Lane 06 nibble 0 adjusted value (post nibble): 003d
09.566: <09>Lane 07 nibble 0 raw readback: 003f
09.566: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003f
09.566: <09>Lane 07 nibble 0 adjusted value (post nibble): 003f
09.566: <09>Lane 08 nibble 0 raw readback: 003a
09.566: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003a
09.566: <09>Lane 08 nibble 0 adjusted value (post nibble): 003a
09.566: AgesaHwWlPhase1: training nibble 1
09.566: DIMM 0 RttNom: 3
09.566: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.567: DIMM 0 RttWr: 2
09.567: DIMM 0 RttWr: 2
09.567: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.567: DIMM 0 RttWr: 2
09.567: DIMM 0 RttNom: 3
09.567: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.567: DIMM 0 RttNom: 3
09.567: DIMM 0 RttWr: 2
09.567: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.567: DIMM 0 RttWr: 2
09.567: DIMM 1 RttNom: 3
09.567: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.567: DIMM 0 RttNom: 3
09.567: DIMM 1 RttWr: 2
09.567: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.567: DIMM 0 RttWr: 2
09.567: DIMM 1 RttNom: 3
09.567: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.567: DIMM 0 RttNom: 3
09.567: DIMM 1 RttWr: 2
09.567: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.567: DIMM 0 RttWr: 2
09.567: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.567: <09>Lane 00 new seed: 0047
09.567: <09>Lane 01 new seed: 0047
09.567: <09>Lane 02 new seed: 0047
09.567: <09>Lane 03 new seed: 0047
09.567: <09>Lane 04 new seed: 0047
09.567: <09>Lane 05 new seed: 0047
09.567: <09>Lane 06 new seed: 0047
09.567: <09>Lane 07 new seed: 0047
09.567: <09>Lane 08 new seed: 0047
09.567: <09>Lane 00 nibble 1 raw readback: 004c
09.567: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004c
09.567: <09>Lane 00 nibble 1 adjusted value (post nibble): 0049
09.567: <09>Lane 01 nibble 1 raw readback: 0048
09.567: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0048
09.567: <09>Lane 01 nibble 1 adjusted value (post nibble): 0047
09.567: <09>Lane 02 nibble 1 raw readback: 0046
09.567: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0046
09.567: <09>Lane 02 nibble 1 adjusted value (post nibble): 0046
09.567: <09>Lane 03 nibble 1 raw readback: 0043
09.567: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0043
09.567: <09>Lane 03 nibble 1 adjusted value (post nibble): 0045
09.567: <09>Lane 04 nibble 1 raw readback: 0038
09.567: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
09.567: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
09.567: <09>Lane 05 nibble 1 raw readback: 003b
09.567: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003b
09.567: <09>Lane 05 nibble 1 adjusted value (post nibble): 0041
09.567: <09>Lane 06 nibble 1 raw readback: 003e
09.567: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003e
09.567: <09>Lane 06 nibble 1 adjusted value (post nibble): 0042
09.567: <09>Lane 07 nibble 1 raw readback: 0041
09.567: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
09.567: <09>Lane 07 nibble 1 adjusted value (post nibble): 0044
09.567: <09>Lane 08 nibble 1 raw readback: 003a
09.567: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003a
09.567: <09>Lane 08 nibble 1 adjusted value (post nibble): 0040
09.567: <09>original critical gross delay: 0
09.567: <09>new critical gross delay: 0
09.567: DIMM 0 RttNom: 3
09.567: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.567: DIMM 0 RttNom: 3
09.567: DIMM 0 RttWr: 2
09.568: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.568: DIMM 0 RttWr: 2
09.568: DIMM 0 RttNom: 3
09.568: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.568: DIMM 0 RttNom: 3
09.568: DIMM 0 RttWr: 2
09.568: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.568: DIMM 0 RttWr: 2
09.568: DIMM 1 RttNom: 3
09.568: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.568: DIMM 0 RttNom: 3
09.568: DIMM 1 RttWr: 2
09.568: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.568: DIMM 0 RttWr: 2
09.568: DIMM 1 RttNom: 3
09.568: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.568: DIMM 0 RttNom: 3
09.568: DIMM 1 RttWr: 2
09.568: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.568: DIMM 0 RttWr: 2
09.568: AgesaHwWlPhase1: training nibble 0
09.568: DIMM 1 RttNom: 3
09.568: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.568: DIMM 1 RttWr: 2
09.568: DIMM 1 RttWr: 2
09.568: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.568: DIMM 1 RttWr: 2
09.568: DIMM 1 RttNom: 3
09.568: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.568: DIMM 1 RttNom: 3
09.568: DIMM 1 RttWr: 2
09.568: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.568: DIMM 1 RttWr: 2
09.568: DIMM 0 RttNom: 3
09.568: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.568: DIMM 1 RttNom: 3
09.568: DIMM 0 RttWr: 2
09.568: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.568: DIMM 1 RttWr: 2
09.568: DIMM 0 RttNom: 3
09.568: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.568: DIMM 1 RttNom: 3
09.568: DIMM 0 RttWr: 2
09.568: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.568: DIMM 1 RttWr: 2
09.568: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.568: <09>Lane 00 scaled delay: 0047
09.568: <09>Lane 00 new seed: 0047
09.568: <09>Lane 01 scaled delay: 0047
09.568: <09>Lane 01 new seed: 0047
09.568: <09>Lane 02 scaled delay: 0047
09.568: <09>Lane 02 new seed: 0047
09.568: <09>Lane 03 scaled delay: 0047
09.568: <09>Lane 03 new seed: 0047
09.568: <09>Lane 04 scaled delay: 0047
09.568: <09>Lane 04 new seed: 0047
09.568: <09>Lane 05 scaled delay: 0047
09.568: <09>Lane 05 new seed: 0047
09.568: <09>Lane 06 scaled delay: 0047
09.568: <09>Lane 06 new seed: 0047
09.568: <09>Lane 07 scaled delay: 0047
09.568: <09>Lane 07 new seed: 0047
09.568: <09>Lane 08 scaled delay: 0047
09.569: <09>Lane 08 new seed: 0047
09.569: <09>Lane 00 nibble 0 raw readback: 0045
09.569: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0045
09.569: <09>Lane 00 nibble 0 adjusted value (post nibble): 0045
09.569: <09>Lane 01 nibble 0 raw readback: 0042
09.569: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0042
09.569: <09>Lane 01 nibble 0 adjusted value (post nibble): 0042
09.569: <09>Lane 02 nibble 0 raw readback: 003e
09.569: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003e
09.569: <09>Lane 02 nibble 0 adjusted value (post nibble): 003e
09.569: <09>Lane 03 nibble 0 raw readback: 003c
09.569: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003c
09.569: <09>Lane 03 nibble 0 adjusted value (post nibble): 003c
09.569: <09>Lane 04 nibble 0 raw readback: 0031
09.569: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0031
09.569: <09>Lane 04 nibble 0 adjusted value (post nibble): 0031
09.569: <09>Lane 05 nibble 0 raw readback: 0033
09.569: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0033
09.569: <09>Lane 05 nibble 0 adjusted value (post nibble): 0033
09.569: <09>Lane 06 nibble 0 raw readback: 0037
09.569: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0037
09.569: <09>Lane 06 nibble 0 adjusted value (post nibble): 0037
09.569: <09>Lane 07 nibble 0 raw readback: 003a
09.569: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003a
09.569: <09>Lane 07 nibble 0 adjusted value (post nibble): 003a
09.569: <09>Lane 08 nibble 0 raw readback: 0033
09.569: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0033
09.569: <09>Lane 08 nibble 0 adjusted value (post nibble): 0033
09.569: AgesaHwWlPhase1: training nibble 1
09.569: DIMM 1 RttNom: 3
09.569: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.569: DIMM 1 RttWr: 2
09.569: DIMM 1 RttWr: 2
09.569: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.569: DIMM 1 RttWr: 2
09.569: DIMM 1 RttNom: 3
09.569: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.569: DIMM 1 RttNom: 3
09.569: DIMM 1 RttWr: 2
09.569: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.569: DIMM 1 RttWr: 2
09.569: DIMM 0 RttNom: 3
09.569: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.569: DIMM 1 RttNom: 3
09.569: DIMM 0 RttWr: 2
09.569: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.569: DIMM 1 RttWr: 2
09.569: DIMM 0 RttNom: 3
09.569: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.569: DIMM 1 RttNom: 3
09.569: DIMM 0 RttWr: 2
09.569: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.569: DIMM 1 RttWr: 2
09.569: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.569: <09>Lane 00 new seed: 0047
09.569: <09>Lane 01 new seed: 0047
09.569: <09>Lane 02 new seed: 0047
09.569: <09>Lane 03 new seed: 0047
09.569: <09>Lane 04 new seed: 0047
09.569: <09>Lane 05 new seed: 0047
09.569: <09>Lane 06 new seed: 0047
09.569: <09>Lane 07 new seed: 0047
09.569: <09>Lane 08 new seed: 0047
09.569: <09>Lane 00 nibble 1 raw readback: 0045
09.569: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0045
09.569: <09>Lane 00 nibble 1 adjusted value (post nibble): 0046
09.569: <09>Lane 01 nibble 1 raw readback: 0042
09.569: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0042
09.569: <09>Lane 01 nibble 1 adjusted value (post nibble): 0044
09.569: <09>Lane 02 nibble 1 raw readback: 003e
09.569: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003e
09.569: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
09.569: <09>Lane 03 nibble 1 raw readback: 003d
09.569: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003d
09.569: <09>Lane 03 nibble 1 adjusted value (post nibble): 0042
09.569: <09>Lane 04 nibble 1 raw readback: 0031
09.569: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0031
09.569: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
09.569: <09>Lane 05 nibble 1 raw readback: 0035
09.569: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0035
09.569: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
09.570: <09>Lane 06 nibble 1 raw readback: 0037
09.570: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0037
09.570: <09>Lane 06 nibble 1 adjusted value (post nibble): 003f
09.570: <09>Lane 07 nibble 1 raw readback: 0039
09.570: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0039
09.570: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
09.570: <09>Lane 08 nibble 1 raw readback: 0035
09.570: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0035
09.570: <09>Lane 08 nibble 1 adjusted value (post nibble): 003e
09.570: <09>original critical gross delay: 0
09.570: <09>new critical gross delay: 0
09.570: DIMM 1 RttNom: 3
09.570: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.570: DIMM 1 RttNom: 3
09.570: DIMM 1 RttWr: 2
09.570: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.570: DIMM 1 RttWr: 2
09.570: DIMM 1 RttNom: 3
09.570: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.570: DIMM 1 RttNom: 3
09.570: DIMM 1 RttWr: 2
09.570: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.570: DIMM 1 RttWr: 2
09.570: DIMM 0 RttNom: 3
09.570: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.570: DIMM 1 RttNom: 3
09.570: DIMM 0 RttWr: 2
09.570: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.570: DIMM 1 RttWr: 2
09.570: DIMM 0 RttNom: 3
09.570: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.570: DIMM 1 RttNom: 3
09.570: DIMM 0 RttWr: 2
09.570: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.570: DIMM 1 RttWr: 2
09.570: SetTargetFreq: Start
09.570: SetTargetFreq: Node 0: New frequency code: 000a
09.570: ChangeMemClk: Start
09.570: set_2t_configuration: Start
09.570: set_2t_configuration: Done
09.570: mct_BeforePlatformSpec: Start
09.570: mct_BeforePlatformSpec: Done
09.571: mct_PlatformSpec: Start
09.571: Programmed DCT 0 timing/termination pattern 003a3c3a 30222222
09.571: mct_PlatformSpec: Done
09.571: set_2t_configuration: Start
09.571: set_2t_configuration: Done
09.571: mct_BeforePlatformSpec: Start
09.571: mct_BeforePlatformSpec: Done
09.571: mct_PlatformSpec: Start
09.571: Programmed DCT 1 timing/termination pattern 003a3c3a 30222222
09.571: mct_PlatformSpec: Done
09.571: ChangeMemClk: Done
09.571: phyAssistedMemFnceTraining: Start
09.571: phyAssistedMemFnceTraining: training node 0 DCT 0
09.571: phyAssistedMemFnceTraining: done training node 0 DCT 0
09.571: phyAssistedMemFnceTraining: training node 0 DCT 1
09.571: phyAssistedMemFnceTraining: done training node 0 DCT 1
09.571: phyAssistedMemFnceTraining: Done
09.571: InitPhyCompensation: DCT 0: Start
09.571: Waiting for predriver calibration to be applied...done!
09.571: InitPhyCompensation: DCT 0: Done
09.571: phyAssistedMemFnceTraining: Start
09.571: phyAssistedMemFnceTraining: training node 0 DCT 0
09.571: phyAssistedMemFnceTraining: done training node 0 DCT 0
09.571: phyAssistedMemFnceTraining: training node 0 DCT 1
09.572: phyAssistedMemFnceTraining: done training node 0 DCT 1
09.572: phyAssistedMemFnceTraining: Done
09.572: InitPhyCompensation: DCT 1: Start
09.572: Waiting for predriver calibration to be applied...done!
09.572: InitPhyCompensation: DCT 1: Done
09.572: Preparing to send DCT 0 DIMM 0 RC10: 01 (F2xA8: 02000300)
09.572: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.572: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
09.572: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.572: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
09.572: Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 02000c00)
09.572: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.572: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
09.572: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.572: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
09.572: Preparing to send DCT 1 DIMM 0 RC10: 01 (F2xA8: 02000300)
09.572: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.572: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
09.572: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.572: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
09.572: Preparing to send DCT 1 DIMM 1 RC10: 01 (F2xA8: 02000c00)
09.572: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.572: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
09.572: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.572: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
09.572: SetTargetFreq: Done
09.572: SPD2ndTiming: Start
09.573: SPD2ndTiming: Done
09.573: mct_BeforeDramInit_Prod_D: Start
09.573: mct_ProgramODT_D: Start
09.573: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
09.573: mct_ProgramODT_D: Done
09.573: mct_BeforeDramInit_Prod_D: Done
09.573: mct_DramInit_Sw_D: Start
09.573: DIMM 0 RttWr: 1
09.573: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.573: mct_SendMrsCmd: Start
09.573: mct_SendMrsCmd: Done
09.573: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
09.573: mct_SendMrsCmd: Start
09.573: mct_SendMrsCmd: Done
09.573: DIMM 0 RttNom: 3
09.573: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.573: mct_SendMrsCmd: Start
09.573: mct_SendMrsCmd: Done
09.573: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001978
09.573: mct_SendMrsCmd: Start
09.573: mct_SendMrsCmd: Done
09.573: DIMM 0 RttWr: 1
09.573: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.573: mct_SendMrsCmd: Start
09.573: mct_SendMrsCmd: Done
09.573: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
09.573: mct_SendMrsCmd: Start
09.573: mct_SendMrsCmd: Done
09.573: DIMM 0 RttNom: 3
09.573: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.573: mct_SendMrsCmd: Start
09.573: mct_SendMrsCmd: Done
09.573: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201978
09.573: mct_SendMrsCmd: Start
09.573: mct_SendMrsCmd: Done
09.573: DIMM 1 RttWr: 1
09.573: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.573: mct_SendMrsCmd: Start
09.573: mct_SendMrsCmd: Done
09.573: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
09.573: mct_SendMrsCmd: Start
09.573: mct_SendMrsCmd: Done
09.573: DIMM 1 RttNom: 3
09.573: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.573: mct_SendMrsCmd: Start
09.573: mct_SendMrsCmd: Done
09.573: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401978
09.573: mct_SendMrsCmd: Start
09.573: mct_SendMrsCmd: Done
09.573: DIMM 1 RttWr: 1
09.573: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.573: mct_SendMrsCmd: Start
09.573: mct_SendMrsCmd: Done
09.573: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
09.573: mct_SendMrsCmd: Start
09.573: mct_SendMrsCmd: Done
09.573: DIMM 1 RttNom: 3
09.573: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.573: mct_SendMrsCmd: Start
09.574: mct_SendMrsCmd: Done
09.574: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601978
09.574: mct_SendMrsCmd: Start
09.574: mct_SendMrsCmd: Done
09.574: mct_DramInit_Sw_D: Done
09.574: AgesaHwWlPhase1: training nibble 0
09.574: DIMM 0 RttNom: 3
09.574: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.574: DIMM 0 RttWr: 1
09.574: DIMM 0 RttWr: 1
09.574: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.574: DIMM 0 RttWr: 1
09.574: DIMM 0 RttNom: 3
09.574: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.574: DIMM 0 RttNom: 3
09.574: DIMM 0 RttWr: 1
09.574: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.574: DIMM 0 RttWr: 1
09.574: DIMM 1 RttNom: 3
09.574: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.574: DIMM 0 RttNom: 3
09.574: DIMM 1 RttWr: 1
09.574: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.574: DIMM 0 RttWr: 1
09.574: DIMM 1 RttNom: 3
09.574: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.574: DIMM 0 RttNom: 3
09.574: DIMM 1 RttWr: 1
09.574: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.574: DIMM 0 RttWr: 1
09.574: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.574: <09>Lane 00 scaled delay: 0059
09.574: <09>Lane 00 new seed: 0059
09.574: <09>Lane 01 scaled delay: 0055
09.574: <09>Lane 01 new seed: 0055
09.574: <09>Lane 02 scaled delay: 0053
09.574: <09>Lane 02 new seed: 0053
09.574: <09>Lane 03 scaled delay: 0052
09.574: <09>Lane 03 new seed: 0052
09.574: <09>Lane 04 scaled delay: 004a
09.575: <09>Lane 04 new seed: 004a
09.575: <09>Lane 05 scaled delay: 004d
09.575: <09>Lane 05 new seed: 004d
09.575: <09>Lane 06 scaled delay: 004f
09.575: <09>Lane 06 new seed: 004f
09.575: <09>Lane 07 scaled delay: 004f
09.575: <09>Lane 07 new seed: 004f
09.575: <09>Lane 08 scaled delay: 004b
09.575: <09>Lane 08 new seed: 004b
09.575: <09>Lane 00 nibble 0 raw readback: 0060
09.575: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0060
09.575: <09>Lane 00 nibble 0 adjusted value (post nibble): 0060
09.575: <09>Lane 01 nibble 0 raw readback: 0058
09.575: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0058
09.575: <09>Lane 01 nibble 0 adjusted value (post nibble): 0058
09.575: <09>Lane 02 nibble 0 raw readback: 0055
09.575: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0055
09.575: <09>Lane 02 nibble 0 adjusted value (post nibble): 0055
09.575: <09>Lane 03 nibble 0 raw readback: 004f
09.575: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004f
09.575: <09>Lane 03 nibble 0 adjusted value (post nibble): 004f
09.575: <09>Lane 04 nibble 0 raw readback: 0042
09.575: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0042
09.575: <09>Lane 04 nibble 0 adjusted value (post nibble): 0042
09.575: <09>Lane 05 nibble 0 raw readback: 0048
09.575: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0048
09.575: <09>Lane 05 nibble 0 adjusted value (post nibble): 0048
09.575: <09>Lane 06 nibble 0 raw readback: 004d
09.575: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004d
09.575: <09>Lane 06 nibble 0 adjusted value (post nibble): 004d
09.575: <09>Lane 07 nibble 0 raw readback: 004f
09.575: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004f
09.575: <09>Lane 07 nibble 0 adjusted value (post nibble): 004f
09.575: <09>Lane 08 nibble 0 raw readback: 0045
09.575: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0045
09.575: <09>Lane 08 nibble 0 adjusted value (post nibble): 0045
09.575: AgesaHwWlPhase1: training nibble 1
09.575: DIMM 0 RttNom: 3
09.575: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.575: DIMM 0 RttWr: 1
09.575: DIMM 0 RttWr: 1
09.575: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.575: DIMM 0 RttWr: 1
09.575: DIMM 0 RttNom: 3
09.575: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.575: DIMM 0 RttNom: 3
09.575: DIMM 0 RttWr: 1
09.575: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.575: DIMM 0 RttWr: 1
09.575: DIMM 1 RttNom: 3
09.575: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.575: DIMM 0 RttNom: 3
09.575: DIMM 1 RttWr: 1
09.575: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.575: DIMM 0 RttWr: 1
09.575: DIMM 1 RttNom: 3
09.575: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.575: DIMM 0 RttNom: 3
09.575: DIMM 1 RttWr: 1
09.575: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.575: DIMM 0 RttWr: 1
09.575: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.575: <09>Lane 00 new seed: 0059
09.575: <09>Lane 01 new seed: 0055
09.575: <09>Lane 02 new seed: 0053
09.575: <09>Lane 03 new seed: 0052
09.576: <09>Lane 04 new seed: 004a
09.576: <09>Lane 05 new seed: 004d
09.576: <09>Lane 06 new seed: 004f
09.576: <09>Lane 07 new seed: 004f
09.576: <09>Lane 08 new seed: 004b
09.576: <09>Lane 00 nibble 1 raw readback: 0060
09.576: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0060
09.576: <09>Lane 00 nibble 1 adjusted value (post nibble): 005c
09.576: <09>Lane 01 nibble 1 raw readback: 0058
09.576: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0058
09.576: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
09.576: <09>Lane 02 nibble 1 raw readback: 0056
09.576: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0056
09.576: <09>Lane 02 nibble 1 adjusted value (post nibble): 0054
09.576: <09>Lane 03 nibble 1 raw readback: 0052
09.576: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0052
09.576: <09>Lane 03 nibble 1 adjusted value (post nibble): 0052
09.576: <09>Lane 04 nibble 1 raw readback: 0042
09.576: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0042
09.576: <09>Lane 04 nibble 1 adjusted value (post nibble): 0046
09.576: <09>Lane 05 nibble 1 raw readback: 0049
09.576: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0049
09.576: <09>Lane 05 nibble 1 adjusted value (post nibble): 004b
09.576: <09>Lane 06 nibble 1 raw readback: 004d
09.576: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004d
09.576: <09>Lane 06 nibble 1 adjusted value (post nibble): 004e
09.576: <09>Lane 07 nibble 1 raw readback: 0050
09.576: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0050
09.576: <09>Lane 07 nibble 1 adjusted value (post nibble): 004f
09.576: <09>Lane 08 nibble 1 raw readback: 0046
09.576: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0046
09.576: <09>Lane 08 nibble 1 adjusted value (post nibble): 0048
09.576: <09>original critical gross delay: 0
09.576: <09>new critical gross delay: 0
09.576: DIMM 0 RttNom: 3
09.576: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.576: DIMM 0 RttNom: 3
09.576: DIMM 0 RttWr: 1
09.576: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.576: DIMM 0 RttWr: 1
09.576: DIMM 0 RttNom: 3
09.576: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.576: DIMM 0 RttNom: 3
09.576: DIMM 0 RttWr: 1
09.576: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.576: DIMM 0 RttWr: 1
09.576: DIMM 1 RttNom: 3
09.576: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.576: DIMM 0 RttNom: 3
09.576: DIMM 1 RttWr: 1
09.576: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.576: DIMM 0 RttWr: 1
09.576: DIMM 1 RttNom: 3
09.576: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.576: DIMM 0 RttNom: 3
09.576: DIMM 1 RttWr: 1
09.576: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.576: DIMM 0 RttWr: 1
09.576: AgesaHwWlPhase1: training nibble 0
09.576: DIMM 1 RttNom: 3
09.576: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.576: DIMM 1 RttWr: 1
09.576: DIMM 1 RttWr: 1
09.576: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.576: DIMM 1 RttWr: 1
09.577: DIMM 1 RttNom: 3
09.577: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.577: DIMM 1 RttNom: 3
09.577: DIMM 1 RttWr: 1
09.577: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.577: DIMM 1 RttWr: 1
09.577: DIMM 0 RttNom: 3
09.577: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.577: DIMM 1 RttNom: 3
09.577: DIMM 0 RttWr: 1
09.577: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.577: DIMM 1 RttWr: 1
09.577: DIMM 0 RttNom: 3
09.577: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.577: DIMM 1 RttNom: 3
09.577: DIMM 0 RttWr: 1
09.577: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.577: DIMM 1 RttWr: 1
09.577: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.577: <09>Lane 00 scaled delay: 0052
09.577: <09>Lane 00 new seed: 0052
09.577: <09>Lane 01 scaled delay: 004e
09.577: <09>Lane 01 new seed: 004e
09.577: <09>Lane 02 scaled delay: 004e
09.577: <09>Lane 02 new seed: 004e
09.577: <09>Lane 03 scaled delay: 004b
09.577: <09>Lane 03 new seed: 004b
09.577: <09>Lane 04 scaled delay: 0043
09.577: <09>Lane 04 new seed: 0043
09.577: <09>Lane 05 scaled delay: 0047
09.577: <09>Lane 05 new seed: 0047
09.577: <09>Lane 06 scaled delay: 0049
09.577: <09>Lane 06 new seed: 0049
09.577: <09>Lane 07 scaled delay: 004a
09.577: <09>Lane 07 new seed: 004a
09.577: <09>Lane 08 scaled delay: 0045
09.577: <09>Lane 08 new seed: 0045
09.577: <09>Lane 00 nibble 0 raw readback: 0052
09.577: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0052
09.577: <09>Lane 00 nibble 0 adjusted value (post nibble): 0052
09.577: <09>Lane 01 nibble 0 raw readback: 004b
09.577: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004b
09.577: <09>Lane 01 nibble 0 adjusted value (post nibble): 004b
09.577: <09>Lane 02 nibble 0 raw readback: 0048
09.577: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0048
09.577: <09>Lane 02 nibble 0 adjusted value (post nibble): 0048
09.577: <09>Lane 03 nibble 0 raw readback: 0044
09.577: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
09.577: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
09.577: <09>Lane 04 nibble 0 raw readback: 0037
09.577: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0037
09.577: <09>Lane 04 nibble 0 adjusted value (post nibble): 0037
09.577: <09>Lane 05 nibble 0 raw readback: 003d
09.577: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
09.577: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
09.577: <09>Lane 06 nibble 0 raw readback: 003f
09.577: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003f
09.577: <09>Lane 06 nibble 0 adjusted value (post nibble): 003f
09.577: <09>Lane 07 nibble 0 raw readback: 0044
09.577: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0044
09.577: <09>Lane 07 nibble 0 adjusted value (post nibble): 0044
09.577: <09>Lane 08 nibble 0 raw readback: 0039
09.577: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0039
09.577: <09>Lane 08 nibble 0 adjusted value (post nibble): 0039
09.577: AgesaHwWlPhase1: training nibble 1
09.577: DIMM 1 RttNom: 3
09.577: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.577: DIMM 1 RttWr: 1
09.577: DIMM 1 RttWr: 1
09.577: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.577: DIMM 1 RttWr: 1
09.577: DIMM 1 RttNom: 3
09.577: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.577: DIMM 1 RttNom: 3
09.578: DIMM 1 RttWr: 1
09.577: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.578: DIMM 1 RttWr: 1
09.578: DIMM 0 RttNom: 3
09.578: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.578: DIMM 1 RttNom: 3
09.578: DIMM 0 RttWr: 1
09.578: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.578: DIMM 1 RttWr: 1
09.578: DIMM 0 RttNom: 3
09.578: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.578: DIMM 1 RttNom: 3
09.578: DIMM 0 RttWr: 1
09.578: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.578: DIMM 1 RttWr: 1
09.578: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.578: <09>Lane 00 new seed: 0052
09.578: <09>Lane 01 new seed: 004e
09.578: <09>Lane 02 new seed: 004e
09.578: <09>Lane 03 new seed: 004b
09.578: <09>Lane 04 new seed: 0043
09.578: <09>Lane 05 new seed: 0047
09.578: <09>Lane 06 new seed: 0049
09.578: <09>Lane 07 new seed: 004a
09.578: <09>Lane 08 new seed: 0045
09.578: <09>Lane 00 nibble 1 raw readback: 0053
09.578: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0053
09.578: <09>Lane 00 nibble 1 adjusted value (post nibble): 0052
09.578: <09>Lane 01 nibble 1 raw readback: 004c
09.578: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004c
09.578: <09>Lane 01 nibble 1 adjusted value (post nibble): 004d
09.578: <09>Lane 02 nibble 1 raw readback: 004a
09.578: <09>Lane 02 nibble 1 adjusted value (pre nibble): 004a
09.578: <09>Lane 02 nibble 1 adjusted value (post nibble): 004c
09.578: <09>Lane 03 nibble 1 raw readback: 0045
09.578: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
09.578: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
09.578: <09>Lane 04 nibble 1 raw readback: 0036
09.578: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0036
09.578: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
09.578: <09>Lane 05 nibble 1 raw readback: 003d
09.578: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003d
09.578: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
09.578: <09>Lane 06 nibble 1 raw readback: 0040
09.578: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0040
09.578: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
09.578: <09>Lane 07 nibble 1 raw readback: 0045
09.578: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0045
09.578: <09>Lane 07 nibble 1 adjusted value (post nibble): 0047
09.578: <09>Lane 08 nibble 1 raw readback: 0038
09.578: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0038
09.578: <09>Lane 08 nibble 1 adjusted value (post nibble): 003e
09.578: <09>original critical gross delay: 0
09.578: <09>new critical gross delay: 0
09.578: DIMM 1 RttNom: 3
09.578: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.578: DIMM 1 RttNom: 3
09.578: DIMM 1 RttWr: 1
09.578: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.578: DIMM 1 RttWr: 1
09.578: DIMM 1 RttNom: 3
09.578: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.578: DIMM 1 RttNom: 3
09.578: DIMM 1 RttWr: 1
09.578: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.578: DIMM 1 RttWr: 1
09.578: DIMM 0 RttNom: 3
09.578: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.578: DIMM 1 RttNom: 3
09.579: DIMM 0 RttWr: 1
09.578: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.578: DIMM 1 RttWr: 1
09.579: DIMM 0 RttNom: 3
09.579: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.579: DIMM 1 RttNom: 3
09.579: DIMM 0 RttWr: 1
09.579: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.579: DIMM 1 RttWr: 1
09.579: SPD2ndTiming: Start
09.579: SPD2ndTiming: Done
09.579: mct_BeforeDramInit_Prod_D: Start
09.579: mct_ProgramODT_D: Start
09.579: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
09.579: mct_ProgramODT_D: Done
09.579: mct_BeforeDramInit_Prod_D: Done
09.579: mct_DramInit_Sw_D: Start
09.579: DIMM 0 RttWr: 1
09.579: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.579: mct_SendMrsCmd: Start
09.579: mct_SendMrsCmd: Done
09.579: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
09.579: mct_SendMrsCmd: Start
09.579: mct_SendMrsCmd: Done
09.579: DIMM 0 RttNom: 3
09.579: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.579: mct_SendMrsCmd: Start
09.579: mct_SendMrsCmd: Done
09.579: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001978
09.579: mct_SendMrsCmd: Start
09.579: mct_SendMrsCmd: Done
09.579: DIMM 0 RttWr: 1
09.579: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.579: mct_SendMrsCmd: Start
09.579: mct_SendMrsCmd: Done
09.580: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
09.579: mct_SendMrsCmd: Start
09.579: mct_SendMrsCmd: Done
09.580: DIMM 0 RttNom: 3
09.580: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.580: mct_SendMrsCmd: Start
09.580: mct_SendMrsCmd: Done
09.580: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201978
09.580: mct_SendMrsCmd: Start
09.580: mct_SendMrsCmd: Done
09.580: DIMM 1 RttWr: 1
09.580: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.580: mct_SendMrsCmd: Start
09.580: mct_SendMrsCmd: Done
09.580: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
09.580: mct_SendMrsCmd: Start
09.580: mct_SendMrsCmd: Done
09.580: DIMM 1 RttNom: 3
09.580: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.580: mct_SendMrsCmd: Start
09.580: mct_SendMrsCmd: Done
09.580: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401978
09.580: mct_SendMrsCmd: Start
09.580: mct_SendMrsCmd: Done
09.580: DIMM 1 RttWr: 1
09.580: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.580: mct_SendMrsCmd: Start
09.580: mct_SendMrsCmd: Done
09.580: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
09.580: mct_SendMrsCmd: Start
09.580: mct_SendMrsCmd: Done
09.580: DIMM 1 RttNom: 3
09.580: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.580: mct_SendMrsCmd: Start
09.580: mct_SendMrsCmd: Done
09.580: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601978
09.580: mct_SendMrsCmd: Start
09.580: mct_SendMrsCmd: Done
09.580: mct_DramInit_Sw_D: Done
09.580: AgesaHwWlPhase1: training nibble 0
09.580: DIMM 0 RttNom: 3
09.580: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.580: DIMM 0 RttWr: 1
09.580: DIMM 0 RttWr: 1
09.580: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.580: DIMM 0 RttWr: 1
09.580: DIMM 0 RttNom: 3
09.580: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.580: DIMM 0 RttNom: 3
09.580: DIMM 0 RttWr: 1
09.580: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.580: DIMM 0 RttWr: 1
09.580: DIMM 1 RttNom: 3
09.580: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.580: DIMM 0 RttNom: 3
09.580: DIMM 1 RttWr: 1
09.580: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.580: DIMM 0 RttWr: 1
09.580: DIMM 1 RttNom: 3
09.580: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.580: DIMM 0 RttNom: 3
09.580: DIMM 1 RttWr: 1
09.580: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.580: DIMM 0 RttWr: 1
09.580: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.581: <09>Lane 00 scaled delay: 0056
09.580: <09>Lane 00 new seed: 0056
09.580: <09>Lane 01 scaled delay: 0053
09.580: <09>Lane 01 new seed: 0053
09.581: <09>Lane 02 scaled delay: 0052
09.581: <09>Lane 02 new seed: 0052
09.581: <09>Lane 03 scaled delay: 0051
09.581: <09>Lane 03 new seed: 0051
09.581: <09>Lane 04 scaled delay: 0049
09.581: <09>Lane 04 new seed: 0049
09.581: <09>Lane 05 scaled delay: 004b
09.581: <09>Lane 05 new seed: 004b
09.581: <09>Lane 06 scaled delay: 004d
09.581: <09>Lane 06 new seed: 004d
09.581: <09>Lane 07 scaled delay: 004f
09.581: <09>Lane 07 new seed: 004f
09.581: <09>Lane 08 scaled delay: 004a
09.581: <09>Lane 08 new seed: 004a
09.581: <09>Lane 00 nibble 0 raw readback: 005c
09.581: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005c
09.581: <09>Lane 00 nibble 0 adjusted value (post nibble): 005c
09.581: <09>Lane 01 nibble 0 raw readback: 0059
09.581: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0059
09.581: <09>Lane 01 nibble 0 adjusted value (post nibble): 0059
09.581: <09>Lane 02 nibble 0 raw readback: 0054
09.581: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0054
09.581: <09>Lane 02 nibble 0 adjusted value (post nibble): 0054
09.581: <09>Lane 03 nibble 0 raw readback: 0050
09.581: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0050
09.581: <09>Lane 03 nibble 0 adjusted value (post nibble): 0050
09.581: <09>Lane 04 nibble 0 raw readback: 0043
09.581: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0043
09.581: <09>Lane 04 nibble 0 adjusted value (post nibble): 0043
09.581: <09>Lane 05 nibble 0 raw readback: 0046
09.581: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0046
09.581: <09>Lane 05 nibble 0 adjusted value (post nibble): 0046
09.581: <09>Lane 06 nibble 0 raw readback: 0048
09.581: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0048
09.581: <09>Lane 06 nibble 0 adjusted value (post nibble): 0048
09.581: <09>Lane 07 nibble 0 raw readback: 004d
09.581: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004d
09.581: <09>Lane 07 nibble 0 adjusted value (post nibble): 004d
09.581: <09>Lane 08 nibble 0 raw readback: 0045
09.581: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0045
09.581: <09>Lane 08 nibble 0 adjusted value (post nibble): 0045
09.581: AgesaHwWlPhase1: training nibble 1
09.581: DIMM 0 RttNom: 3
09.581: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.581: DIMM 0 RttWr: 1
09.581: DIMM 0 RttWr: 1
09.581: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.581: DIMM 0 RttWr: 1
09.581: DIMM 0 RttNom: 3
09.581: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.581: DIMM 0 RttNom: 3
09.581: DIMM 0 RttWr: 1
09.581: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.581: DIMM 0 RttWr: 1
09.581: DIMM 1 RttNom: 3
09.581: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.581: DIMM 0 RttNom: 3
09.581: DIMM 1 RttWr: 1
09.581: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.581: DIMM 0 RttWr: 1
09.581: DIMM 1 RttNom: 3
09.581: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.581: DIMM 0 RttNom: 3
09.581: DIMM 1 RttWr: 1
09.581: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.581: DIMM 0 RttWr: 1
09.581: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.582: <09>Lane 00 new seed: 0056
09.582: <09>Lane 01 new seed: 0053
09.582: <09>Lane 02 new seed: 0052
09.582: <09>Lane 03 new seed: 0051
09.582: <09>Lane 04 new seed: 0049
09.582: <09>Lane 05 new seed: 004b
09.582: <09>Lane 06 new seed: 004d
09.582: <09>Lane 07 new seed: 004f
09.582: <09>Lane 08 new seed: 004a
09.582: <09>Lane 00 nibble 1 raw readback: 005c
09.582: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005c
09.582: <09>Lane 00 nibble 1 adjusted value (post nibble): 0059
09.582: <09>Lane 01 nibble 1 raw readback: 0056
09.582: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0056
09.582: <09>Lane 01 nibble 1 adjusted value (post nibble): 0054
09.582: <09>Lane 02 nibble 1 raw readback: 0054
09.582: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0054
09.582: <09>Lane 02 nibble 1 adjusted value (post nibble): 0053
09.582: <09>Lane 03 nibble 1 raw readback: 0050
09.582: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0050
09.582: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
09.582: <09>Lane 04 nibble 1 raw readback: 0041
09.582: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0041
09.582: <09>Lane 04 nibble 1 adjusted value (post nibble): 0045
09.582: <09>Lane 05 nibble 1 raw readback: 0045
09.582: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0045
09.582: <09>Lane 05 nibble 1 adjusted value (post nibble): 0048
09.582: <09>Lane 06 nibble 1 raw readback: 004a
09.582: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004a
09.582: <09>Lane 06 nibble 1 adjusted value (post nibble): 004b
09.582: <09>Lane 07 nibble 1 raw readback: 004c
09.582: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004c
09.582: <09>Lane 07 nibble 1 adjusted value (post nibble): 004d
09.582: <09>Lane 08 nibble 1 raw readback: 0044
09.582: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0044
09.582: <09>Lane 08 nibble 1 adjusted value (post nibble): 0047
09.582: <09>original critical gross delay: 0
09.582: <09>new critical gross delay: 0
09.582: DIMM 0 RttNom: 3
09.582: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.582: DIMM 0 RttNom: 3
09.582: DIMM 0 RttWr: 1
09.582: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.582: DIMM 0 RttWr: 1
09.582: DIMM 0 RttNom: 3
09.582: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.582: DIMM 0 RttNom: 3
09.582: DIMM 0 RttWr: 1
09.582: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.582: DIMM 0 RttWr: 1
09.582: DIMM 1 RttNom: 3
09.582: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.582: DIMM 0 RttNom: 3
09.582: DIMM 1 RttWr: 1
09.582: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.582: DIMM 0 RttWr: 1
09.582: DIMM 1 RttNom: 3
09.582: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.582: DIMM 0 RttNom: 3
09.582: DIMM 1 RttWr: 1
09.582: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.582: DIMM 0 RttWr: 1
09.582: AgesaHwWlPhase1: training nibble 0
09.582: DIMM 1 RttNom: 3
09.582: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.582: DIMM 1 RttWr: 1
09.583: DIMM 1 RttWr: 1
09.582: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.583: DIMM 1 RttWr: 1
09.583: DIMM 1 RttNom: 3
09.583: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.583: DIMM 1 RttNom: 3
09.583: DIMM 1 RttWr: 1
09.583: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.583: DIMM 1 RttWr: 1
09.583: DIMM 0 RttNom: 3
09.583: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.583: DIMM 1 RttNom: 3
09.583: DIMM 0 RttWr: 1
09.583: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.583: DIMM 1 RttWr: 1
09.583: DIMM 0 RttNom: 3
09.583: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.583: DIMM 1 RttNom: 3
09.583: DIMM 0 RttWr: 1
09.583: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.583: DIMM 1 RttWr: 1
09.583: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.583: <09>Lane 00 scaled delay: 0052
09.583: <09>Lane 00 new seed: 0052
09.583: <09>Lane 01 scaled delay: 004f
09.583: <09>Lane 01 new seed: 004f
09.583: <09>Lane 02 scaled delay: 004d
09.583: <09>Lane 02 new seed: 004d
09.583: <09>Lane 03 scaled delay: 004d
09.583: <09>Lane 03 new seed: 004d
09.583: <09>Lane 04 scaled delay: 0045
09.583: <09>Lane 04 new seed: 0045
09.583: <09>Lane 05 scaled delay: 0047
09.583: <09>Lane 05 new seed: 0047
09.583: <09>Lane 06 scaled delay: 0049
09.583: <09>Lane 06 new seed: 0049
09.583: <09>Lane 07 scaled delay: 004a
09.583: <09>Lane 07 new seed: 004a
09.583: <09>Lane 08 scaled delay: 0047
09.583: <09>Lane 08 new seed: 0047
09.583: <09>Lane 00 nibble 0 raw readback: 0052
09.583: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0052
09.583: <09>Lane 00 nibble 0 adjusted value (post nibble): 0052
09.583: <09>Lane 01 nibble 0 raw readback: 004f
09.583: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004f
09.583: <09>Lane 01 nibble 0 adjusted value (post nibble): 004f
09.583: <09>Lane 02 nibble 0 raw readback: 0049
09.583: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0049
09.583: <09>Lane 02 nibble 0 adjusted value (post nibble): 0049
09.583: <09>Lane 03 nibble 0 raw readback: 0045
09.583: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0045
09.583: <09>Lane 03 nibble 0 adjusted value (post nibble): 0045
09.583: <09>Lane 04 nibble 0 raw readback: 0038
09.583: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0038
09.583: <09>Lane 04 nibble 0 adjusted value (post nibble): 0038
09.583: <09>Lane 05 nibble 0 raw readback: 003b
09.583: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003b
09.583: <09>Lane 05 nibble 0 adjusted value (post nibble): 003b
09.583: <09>Lane 06 nibble 0 raw readback: 0040
09.583: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
09.583: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
09.583: <09>Lane 07 nibble 0 raw readback: 0044
09.583: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0044
09.583: <09>Lane 07 nibble 0 adjusted value (post nibble): 0044
09.583: <09>Lane 08 nibble 0 raw readback: 003c
09.583: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003c
09.583: <09>Lane 08 nibble 0 adjusted value (post nibble): 003c
09.583: AgesaHwWlPhase1: training nibble 1
09.583: DIMM 1 RttNom: 3
09.583: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.583: DIMM 1 RttWr: 1
09.583: DIMM 1 RttWr: 1
09.583: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.583: DIMM 1 RttWr: 1
09.583: DIMM 1 RttNom: 3
09.583: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.584: DIMM 1 RttNom: 3
09.584: DIMM 1 RttWr: 1
09.584: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.584: DIMM 1 RttWr: 1
09.584: DIMM 0 RttNom: 3
09.584: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.584: DIMM 1 RttNom: 3
09.584: DIMM 0 RttWr: 1
09.584: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.584: DIMM 1 RttWr: 1
09.584: DIMM 0 RttNom: 3
09.584: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.584: DIMM 1 RttNom: 3
09.584: DIMM 0 RttWr: 1
09.584: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.584: DIMM 1 RttWr: 1
09.584: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.584: <09>Lane 00 new seed: 0052
09.584: <09>Lane 01 new seed: 004f
09.584: <09>Lane 02 new seed: 004d
09.584: <09>Lane 03 new seed: 004d
09.584: <09>Lane 04 new seed: 0045
09.584: <09>Lane 05 new seed: 0047
09.584: <09>Lane 06 new seed: 0049
09.584: <09>Lane 07 new seed: 004a
09.584: <09>Lane 08 new seed: 0047
09.584: <09>Lane 00 nibble 1 raw readback: 0051
09.584: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0051
09.584: <09>Lane 00 nibble 1 adjusted value (post nibble): 0051
09.584: <09>Lane 01 nibble 1 raw readback: 004d
09.584: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004d
09.584: <09>Lane 01 nibble 1 adjusted value (post nibble): 004e
09.584: <09>Lane 02 nibble 1 raw readback: 0049
09.584: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0049
09.584: <09>Lane 02 nibble 1 adjusted value (post nibble): 004b
09.584: <09>Lane 03 nibble 1 raw readback: 0046
09.584: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0046
09.584: <09>Lane 03 nibble 1 adjusted value (post nibble): 0049
09.584: <09>Lane 04 nibble 1 raw readback: 0037
09.584: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0037
09.584: <09>Lane 04 nibble 1 adjusted value (post nibble): 003e
09.584: <09>Lane 05 nibble 1 raw readback: 003c
09.584: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
09.584: <09>Lane 05 nibble 1 adjusted value (post nibble): 0041
09.584: <09>Lane 06 nibble 1 raw readback: 003f
09.584: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
09.584: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
09.584: <09>Lane 07 nibble 1 raw readback: 0042
09.584: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
09.584: <09>Lane 07 nibble 1 adjusted value (post nibble): 0046
09.584: <09>Lane 08 nibble 1 raw readback: 003c
09.584: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003c
09.584: <09>Lane 08 nibble 1 adjusted value (post nibble): 0041
09.584: <09>original critical gross delay: 0
09.584: <09>new critical gross delay: 0
09.584: DIMM 1 RttNom: 3
09.584: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.584: DIMM 1 RttNom: 3
09.584: DIMM 1 RttWr: 1
09.584: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.584: DIMM 1 RttWr: 1
09.584: DIMM 1 RttNom: 3
09.584: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.584: DIMM 1 RttNom: 3
09.584: DIMM 1 RttWr: 1
09.584: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.584: DIMM 1 RttWr: 1
09.584: DIMM 0 RttNom: 3
09.584: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.584: DIMM 1 RttNom: 3
09.585: DIMM 0 RttWr: 1
09.585: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.585: DIMM 1 RttWr: 1
09.585: DIMM 0 RttNom: 3
09.585: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.585: DIMM 1 RttNom: 3
09.585: DIMM 0 RttWr: 1
09.585: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.585: DIMM 1 RttWr: 1
09.585: SetTargetFreq: Start
09.585: SetTargetFreq: Node 0: New frequency code: 000e
09.585: ChangeMemClk: Start
09.585: set_2t_configuration: Start
09.585: set_2t_configuration: Done
09.585: mct_BeforePlatformSpec: Start
09.585: mct_BeforePlatformSpec: Done
09.585: mct_PlatformSpec: Start
09.585: Programmed DCT 0 timing/termination pattern 00383a38 30222222
09.585: mct_PlatformSpec: Done
09.585: set_2t_configuration: Start
09.585: set_2t_configuration: Done
09.585: mct_BeforePlatformSpec: Start
09.585: mct_BeforePlatformSpec: Done
09.585: mct_PlatformSpec: Start
09.585: Programmed DCT 1 timing/termination pattern 00383a38 30222222
09.585: mct_PlatformSpec: Done
09.585: ChangeMemClk: Done
09.585: phyAssistedMemFnceTraining: Start
09.585: phyAssistedMemFnceTraining: training node 0 DCT 0
09.585: phyAssistedMemFnceTraining: done training node 0 DCT 0
09.585: phyAssistedMemFnceTraining: training node 0 DCT 1
09.586: phyAssistedMemFnceTraining: done training node 0 DCT 1
09.586: phyAssistedMemFnceTraining: Done
09.586: InitPhyCompensation: DCT 0: Start
09.586: Waiting for predriver calibration to be applied...done!
09.586: InitPhyCompensation: DCT 0: Done
09.586: phyAssistedMemFnceTraining: Start
09.586: phyAssistedMemFnceTraining: training node 0 DCT 0
09.586: phyAssistedMemFnceTraining: done training node 0 DCT 0
09.586: phyAssistedMemFnceTraining: training node 0 DCT 1
09.586: phyAssistedMemFnceTraining: done training node 0 DCT 1
09.586: phyAssistedMemFnceTraining: Done
09.586: InitPhyCompensation: DCT 1: Start
09.586: Waiting for predriver calibration to be applied...done!
09.586: InitPhyCompensation: DCT 1: Done
09.586: Preparing to send DCT 0 DIMM 0 RC10: 02 (F2xA8: 02000300)
09.586: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.586: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
09.586: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.586: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
09.586: Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 02000c00)
09.586: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.586: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
09.586: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.586: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
09.586: Preparing to send DCT 1 DIMM 0 RC10: 02 (F2xA8: 02000300)
09.586: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.587: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
09.587: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.587: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
09.587: Preparing to send DCT 1 DIMM 1 RC10: 02 (F2xA8: 02000c00)
09.587: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.587: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
09.587: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.587: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
09.587: SetTargetFreq: Done
09.587: SPD2ndTiming: Start
09.587: SPD2ndTiming: Done
09.587: mct_BeforeDramInit_Prod_D: Start
09.587: mct_ProgramODT_D: Start
09.587: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
09.587: mct_ProgramODT_D: Done
09.587: mct_BeforeDramInit_Prod_D: Done
09.587: mct_DramInit_Sw_D: Start
09.587: DIMM 0 RttWr: 2
09.587: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.587: mct_SendMrsCmd: Start
09.587: mct_SendMrsCmd: Done
09.587: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
09.587: mct_SendMrsCmd: Start
09.587: mct_SendMrsCmd: Done
09.587: DIMM 0 RttNom: 5
09.587: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.587: mct_SendMrsCmd: Start
09.587: mct_SendMrsCmd: Done
09.587: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001b78
09.587: mct_SendMrsCmd: Start
09.587: mct_SendMrsCmd: Done
09.587: DIMM 0 RttWr: 2
09.587: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.587: mct_SendMrsCmd: Start
09.587: mct_SendMrsCmd: Done
09.587: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
09.587: mct_SendMrsCmd: Start
09.587: mct_SendMrsCmd: Done
09.587: DIMM 0 RttNom: 5
09.588: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.587: mct_SendMrsCmd: Start
09.587: mct_SendMrsCmd: Done
09.588: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201b78
09.588: mct_SendMrsCmd: Start
09.588: mct_SendMrsCmd: Done
09.588: DIMM 1 RttWr: 2
09.588: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.588: mct_SendMrsCmd: Start
09.588: mct_SendMrsCmd: Done
09.588: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
09.588: mct_SendMrsCmd: Start
09.588: mct_SendMrsCmd: Done
09.588: DIMM 1 RttNom: 5
09.588: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.588: mct_SendMrsCmd: Start
09.588: mct_SendMrsCmd: Done
09.588: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b78
09.588: mct_SendMrsCmd: Start
09.588: mct_SendMrsCmd: Done
09.588: DIMM 1 RttWr: 2
09.588: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.588: mct_SendMrsCmd: Start
09.588: mct_SendMrsCmd: Done
09.588: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
09.588: mct_SendMrsCmd: Start
09.588: mct_SendMrsCmd: Done
09.588: DIMM 1 RttNom: 5
09.588: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.588: mct_SendMrsCmd: Start
09.588: mct_SendMrsCmd: Done
09.588: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b78
09.588: mct_SendMrsCmd: Start
09.588: mct_SendMrsCmd: Done
09.588: mct_DramInit_Sw_D: Done
09.588: AgesaHwWlPhase1: training nibble 0
09.588: DIMM 0 RttNom: 5
09.588: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.588: DIMM 0 RttWr: 2
09.588: DIMM 0 RttWr: 2
09.588: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.588: DIMM 0 RttWr: 2
09.588: DIMM 0 RttNom: 5
09.588: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.588: DIMM 0 RttNom: 5
09.588: DIMM 0 RttWr: 2
09.588: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.588: DIMM 0 RttWr: 2
09.588: DIMM 1 RttNom: 5
09.588: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.588: DIMM 0 RttNom: 5
09.588: DIMM 1 RttWr: 2
09.588: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.588: DIMM 0 RttWr: 2
09.588: DIMM 1 RttNom: 5
09.588: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.588: DIMM 0 RttNom: 5
09.588: DIMM 1 RttWr: 2
09.588: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.588: DIMM 0 RttWr: 2
09.588: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.589: <09>Lane 00 scaled delay: 006b
09.589: <09>Lane 00 new seed: 006b
09.589: <09>Lane 01 scaled delay: 0063
09.589: <09>Lane 01 new seed: 0063
09.589: <09>Lane 02 scaled delay: 0061
09.589: <09>Lane 02 new seed: 0061
09.589: <09>Lane 03 scaled delay: 005e
09.589: <09>Lane 03 new seed: 005e
09.589: <09>Lane 04 scaled delay: 004f
09.589: <09>Lane 04 new seed: 004f
09.589: <09>Lane 05 scaled delay: 0055
09.589: <09>Lane 05 new seed: 0055
09.589: <09>Lane 06 scaled delay: 0059
09.589: <09>Lane 06 new seed: 0059
09.589: <09>Lane 07 scaled delay: 005a
09.589: <09>Lane 07 new seed: 005a
09.589: <09>Lane 08 scaled delay: 0052
09.589: <09>Lane 08 new seed: 0052
09.589: <09>Lane 00 nibble 0 raw readback: 0030
09.589: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0070
09.589: <09>Lane 00 nibble 0 adjusted value (post nibble): 0070
09.589: <09>Lane 01 nibble 0 raw readback: 0026
09.589: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0066
09.589: <09>Lane 01 nibble 0 adjusted value (post nibble): 0066
09.589: <09>Lane 02 nibble 0 raw readback: 0021
09.589: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0061
09.589: <09>Lane 02 nibble 0 adjusted value (post nibble): 0061
09.589: <09>Lane 03 nibble 0 raw readback: 005c
09.589: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005c
09.589: <09>Lane 03 nibble 0 adjusted value (post nibble): 005c
09.589: <09>Lane 04 nibble 0 raw readback: 004a
09.589: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004a
09.589: <09>Lane 04 nibble 0 adjusted value (post nibble): 004a
09.589: <09>Lane 05 nibble 0 raw readback: 0053
09.589: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0053
09.589: <09>Lane 05 nibble 0 adjusted value (post nibble): 0053
09.589: <09>Lane 06 nibble 0 raw readback: 0057
09.589: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0057
09.589: <09>Lane 06 nibble 0 adjusted value (post nibble): 0057
09.589: <09>Lane 07 nibble 0 raw readback: 005b
09.589: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005b
09.589: <09>Lane 07 nibble 0 adjusted value (post nibble): 005b
09.589: <09>Lane 08 nibble 0 raw readback: 004e
09.589: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004e
09.589: <09>Lane 08 nibble 0 adjusted value (post nibble): 004e
09.589: AgesaHwWlPhase1: training nibble 1
09.589: DIMM 0 RttNom: 5
09.589: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.589: DIMM 0 RttWr: 2
09.589: DIMM 0 RttWr: 2
09.589: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.589: DIMM 0 RttWr: 2
09.589: DIMM 0 RttNom: 5
09.589: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.589: DIMM 0 RttNom: 5
09.590: DIMM 0 RttWr: 2
09.590: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.590: DIMM 0 RttWr: 2
09.590: DIMM 1 RttNom: 5
09.590: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.590: DIMM 0 RttNom: 5
09.590: DIMM 1 RttWr: 2
09.590: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.590: DIMM 0 RttWr: 2
09.590: DIMM 1 RttNom: 5
09.590: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.590: DIMM 0 RttNom: 5
09.590: DIMM 1 RttWr: 2
09.590: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.590: DIMM 0 RttWr: 2
09.590: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.590: <09>Lane 00 new seed: 006b
09.590: <09>Lane 01 new seed: 0063
09.590: <09>Lane 02 new seed: 0061
09.590: <09>Lane 03 new seed: 005e
09.590: <09>Lane 04 new seed: 004f
09.590: <09>Lane 05 new seed: 0055
09.590: <09>Lane 06 new seed: 0059
09.590: <09>Lane 07 new seed: 005a
09.590: <09>Lane 08 new seed: 0052
09.590: <09>Lane 00 nibble 1 raw readback: 002e
09.590: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006e
09.590: <09>Lane 00 nibble 1 adjusted value (post nibble): 006c
09.590: <09>Lane 01 nibble 1 raw readback: 0025
09.590: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0065
09.590: <09>Lane 01 nibble 1 adjusted value (post nibble): 0064
09.590: <09>Lane 02 nibble 1 raw readback: 0022
09.590: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0062
09.590: <09>Lane 02 nibble 1 adjusted value (post nibble): 0061
09.590: <09>Lane 03 nibble 1 raw readback: 005d
09.590: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005d
09.590: <09>Lane 03 nibble 1 adjusted value (post nibble): 005d
09.590: <09>Lane 04 nibble 1 raw readback: 004a
09.590: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004a
09.590: <09>Lane 04 nibble 1 adjusted value (post nibble): 004c
09.590: <09>Lane 05 nibble 1 raw readback: 0052
09.590: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0052
09.590: <09>Lane 05 nibble 1 adjusted value (post nibble): 0053
09.590: <09>Lane 06 nibble 1 raw readback: 0058
09.590: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0058
09.590: <09>Lane 06 nibble 1 adjusted value (post nibble): 0058
09.590: <09>Lane 07 nibble 1 raw readback: 005a
09.590: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005a
09.590: <09>Lane 07 nibble 1 adjusted value (post nibble): 005a
09.590: <09>Lane 08 nibble 1 raw readback: 004e
09.590: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004e
09.590: <09>Lane 08 nibble 1 adjusted value (post nibble): 0050
09.590: <09>original critical gross delay: 0
09.590: <09>new critical gross delay: 0
09.590: DIMM 0 RttNom: 5
09.590: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.590: DIMM 0 RttNom: 5
09.590: DIMM 0 RttWr: 2
09.590: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.590: DIMM 0 RttWr: 2
09.590: DIMM 0 RttNom: 5
09.590: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.590: DIMM 0 RttNom: 5
09.590: DIMM 0 RttWr: 2
09.590: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.590: DIMM 0 RttWr: 2
09.590: DIMM 1 RttNom: 5
09.590: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.590: DIMM 0 RttNom: 5
09.591: DIMM 1 RttWr: 2
09.591: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.591: DIMM 0 RttWr: 2
09.591: DIMM 1 RttNom: 5
09.591: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.591: DIMM 0 RttNom: 5
09.591: DIMM 1 RttWr: 2
09.591: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.591: DIMM 0 RttWr: 2
09.591: AgesaHwWlPhase1: training nibble 0
09.591: DIMM 1 RttNom: 5
09.591: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.591: DIMM 1 RttWr: 2
09.591: DIMM 1 RttWr: 2
09.591: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.591: DIMM 1 RttWr: 2
09.591: DIMM 1 RttNom: 5
09.591: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.591: DIMM 1 RttNom: 5
09.591: DIMM 1 RttWr: 2
09.591: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.591: DIMM 1 RttWr: 2
09.591: DIMM 0 RttNom: 5
09.591: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.591: DIMM 1 RttNom: 5
09.591: DIMM 0 RttWr: 2
09.591: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.591: DIMM 1 RttWr: 2
09.591: DIMM 0 RttNom: 5
09.591: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.591: DIMM 1 RttNom: 5
09.591: DIMM 0 RttWr: 2
09.591: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.591: DIMM 1 RttWr: 2
09.591: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.591: <09>Lane 00 scaled delay: 005e
09.591: <09>Lane 00 new seed: 005e
09.591: <09>Lane 01 scaled delay: 0058
09.591: <09>Lane 01 new seed: 0058
09.591: <09>Lane 02 scaled delay: 0057
09.591: <09>Lane 02 new seed: 0057
09.591: <09>Lane 03 scaled delay: 0052
09.591: <09>Lane 03 new seed: 0052
09.591: <09>Lane 04 scaled delay: 0043
09.591: <09>Lane 04 new seed: 0043
09.591: <09>Lane 05 scaled delay: 004a
09.591: <09>Lane 05 new seed: 004a
09.591: <09>Lane 06 scaled delay: 004d
09.591: <09>Lane 06 new seed: 004d
09.591: <09>Lane 07 scaled delay: 0050
09.591: <09>Lane 07 new seed: 0050
09.591: <09>Lane 08 scaled delay: 0045
09.591: <09>Lane 08 new seed: 0045
09.591: <09>Lane 00 nibble 0 raw readback: 005f
09.591: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005f
09.591: <09>Lane 00 nibble 0 adjusted value (post nibble): 005f
09.591: <09>Lane 01 nibble 0 raw readback: 0056
09.591: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0056
09.591: <09>Lane 01 nibble 0 adjusted value (post nibble): 0056
09.591: <09>Lane 02 nibble 0 raw readback: 0052
09.591: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0052
09.591: <09>Lane 02 nibble 0 adjusted value (post nibble): 0052
09.591: <09>Lane 03 nibble 0 raw readback: 004c
09.591: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004c
09.591: <09>Lane 03 nibble 0 adjusted value (post nibble): 004c
09.591: <09>Lane 04 nibble 0 raw readback: 003d
09.591: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003d
09.591: <09>Lane 04 nibble 0 adjusted value (post nibble): 003d
09.591: <09>Lane 05 nibble 0 raw readback: 0046
09.591: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0046
09.591: <09>Lane 05 nibble 0 adjusted value (post nibble): 0046
09.592: <09>Lane 06 nibble 0 raw readback: 0048
09.592: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0048
09.592: <09>Lane 06 nibble 0 adjusted value (post nibble): 0048
09.592: <09>Lane 07 nibble 0 raw readback: 004c
09.592: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004c
09.592: <09>Lane 07 nibble 0 adjusted value (post nibble): 004c
09.592: <09>Lane 08 nibble 0 raw readback: 003e
09.592: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003e
09.592: <09>Lane 08 nibble 0 adjusted value (post nibble): 003e
09.592: AgesaHwWlPhase1: training nibble 1
09.592: DIMM 1 RttNom: 5
09.592: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.592: DIMM 1 RttWr: 2
09.592: DIMM 1 RttWr: 2
09.592: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.592: DIMM 1 RttWr: 2
09.592: DIMM 1 RttNom: 5
09.592: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.592: DIMM 1 RttNom: 5
09.592: DIMM 1 RttWr: 2
09.592: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.592: DIMM 1 RttWr: 2
09.592: DIMM 0 RttNom: 5
09.592: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.592: DIMM 1 RttNom: 5
09.592: DIMM 0 RttWr: 2
09.592: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.592: DIMM 1 RttWr: 2
09.592: DIMM 0 RttNom: 5
09.592: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.592: DIMM 1 RttNom: 5
09.592: DIMM 0 RttWr: 2
09.592: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.592: DIMM 1 RttWr: 2
09.592: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.592: <09>Lane 00 new seed: 005e
09.592: <09>Lane 01 new seed: 0058
09.592: <09>Lane 02 new seed: 0057
09.592: <09>Lane 03 new seed: 0052
09.592: <09>Lane 04 new seed: 0043
09.592: <09>Lane 05 new seed: 004a
09.592: <09>Lane 06 new seed: 004d
09.592: <09>Lane 07 new seed: 0050
09.592: <09>Lane 08 new seed: 0045
09.592: <09>Lane 00 nibble 1 raw readback: 0060
09.592: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0060
09.592: <09>Lane 00 nibble 1 adjusted value (post nibble): 005f
09.592: <09>Lane 01 nibble 1 raw readback: 0057
09.592: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0057
09.592: <09>Lane 01 nibble 1 adjusted value (post nibble): 0057
09.592: <09>Lane 02 nibble 1 raw readback: 0054
09.592: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0054
09.592: <09>Lane 02 nibble 1 adjusted value (post nibble): 0055
09.592: <09>Lane 03 nibble 1 raw readback: 004e
09.592: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004e
09.592: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
09.592: <09>Lane 04 nibble 1 raw readback: 003c
09.592: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003c
09.592: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
09.592: <09>Lane 05 nibble 1 raw readback: 0045
09.592: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0045
09.592: <09>Lane 05 nibble 1 adjusted value (post nibble): 0047
09.592: <09>Lane 06 nibble 1 raw readback: 0048
09.592: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0048
09.592: <09>Lane 06 nibble 1 adjusted value (post nibble): 004a
09.592: <09>Lane 07 nibble 1 raw readback: 004e
09.592: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004e
09.592: <09>Lane 07 nibble 1 adjusted value (post nibble): 004f
09.592: <09>Lane 08 nibble 1 raw readback: 003f
09.592: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003f
09.592: <09>Lane 08 nibble 1 adjusted value (post nibble): 0042
09.592: <09>original critical gross delay: 0
09.592: <09>new critical gross delay: 0
09.593: DIMM 1 RttNom: 5
09.593: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.593: DIMM 1 RttNom: 5
09.593: DIMM 1 RttWr: 2
09.593: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.593: DIMM 1 RttWr: 2
09.593: DIMM 1 RttNom: 5
09.593: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.593: DIMM 1 RttNom: 5
09.593: DIMM 1 RttWr: 2
09.593: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.593: DIMM 1 RttWr: 2
09.593: DIMM 0 RttNom: 5
09.593: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.593: DIMM 1 RttNom: 5
09.593: DIMM 0 RttWr: 2
09.593: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.593: DIMM 1 RttWr: 2
09.593: DIMM 0 RttNom: 5
09.593: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.593: DIMM 1 RttNom: 5
09.593: DIMM 0 RttWr: 2
09.593: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.593: DIMM 1 RttWr: 2
09.593: SPD2ndTiming: Start
09.593: SPD2ndTiming: Done
09.593: mct_BeforeDramInit_Prod_D: Start
09.593: mct_ProgramODT_D: Start
09.593: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
09.593: mct_ProgramODT_D: Done
09.593: mct_BeforeDramInit_Prod_D: Done
09.593: mct_DramInit_Sw_D: Start
09.594: DIMM 0 RttWr: 2
09.594: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.594: mct_SendMrsCmd: Start
09.594: mct_SendMrsCmd: Done
09.594: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
09.594: mct_SendMrsCmd: Start
09.594: mct_SendMrsCmd: Done
09.594: DIMM 0 RttNom: 5
09.594: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.594: mct_SendMrsCmd: Start
09.594: mct_SendMrsCmd: Done
09.594: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001b78
09.594: mct_SendMrsCmd: Start
09.594: mct_SendMrsCmd: Done
09.594: DIMM 0 RttWr: 2
09.594: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.594: mct_SendMrsCmd: Start
09.594: mct_SendMrsCmd: Done
09.594: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
09.594: mct_SendMrsCmd: Start
09.594: mct_SendMrsCmd: Done
09.594: DIMM 0 RttNom: 5
09.594: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.594: mct_SendMrsCmd: Start
09.594: mct_SendMrsCmd: Done
09.594: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201b78
09.594: mct_SendMrsCmd: Start
09.594: mct_SendMrsCmd: Done
09.594: DIMM 1 RttWr: 2
09.594: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.594: mct_SendMrsCmd: Start
09.594: mct_SendMrsCmd: Done
09.594: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
09.594: mct_SendMrsCmd: Start
09.594: mct_SendMrsCmd: Done
09.594: DIMM 1 RttNom: 5
09.594: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.594: mct_SendMrsCmd: Start
09.594: mct_SendMrsCmd: Done
09.594: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401b78
09.594: mct_SendMrsCmd: Start
09.594: mct_SendMrsCmd: Done
09.594: DIMM 1 RttWr: 2
09.594: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.594: mct_SendMrsCmd: Start
09.594: mct_SendMrsCmd: Done
09.594: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
09.594: mct_SendMrsCmd: Start
09.594: mct_SendMrsCmd: Done
09.594: DIMM 1 RttNom: 5
09.594: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.594: mct_SendMrsCmd: Start
09.594: mct_SendMrsCmd: Done
09.594: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601b78
09.594: mct_SendMrsCmd: Start
09.594: mct_SendMrsCmd: Done
09.594: mct_DramInit_Sw_D: Done
09.594: AgesaHwWlPhase1: training nibble 0
09.594: DIMM 0 RttNom: 5
09.594: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.594: DIMM 0 RttWr: 2
09.594: DIMM 0 RttWr: 2
09.594: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.594: DIMM 0 RttWr: 2
09.594: DIMM 0 RttNom: 5
09.594: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.594: DIMM 0 RttNom: 5
09.594: DIMM 0 RttWr: 2
09.594: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.594: DIMM 0 RttWr: 2
09.595: DIMM 1 RttNom: 5
09.595: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.595: DIMM 0 RttNom: 5
09.595: DIMM 1 RttWr: 2
09.595: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.595: DIMM 0 RttWr: 2
09.595: DIMM 1 RttNom: 5
09.595: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.595: DIMM 0 RttNom: 5
09.595: DIMM 1 RttWr: 2
09.595: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.595: DIMM 0 RttWr: 2
09.595: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.595: <09>Lane 00 scaled delay: 0067
09.595: <09>Lane 00 new seed: 0067
09.595: <09>Lane 01 scaled delay: 0061
09.595: <09>Lane 01 new seed: 0061
09.595: <09>Lane 02 scaled delay: 005f
09.595: <09>Lane 02 new seed: 005f
09.595: <09>Lane 03 scaled delay: 005c
09.595: <09>Lane 03 new seed: 005c
09.595: <09>Lane 04 scaled delay: 004e
09.595: <09>Lane 04 new seed: 004e
09.595: <09>Lane 05 scaled delay: 0052
09.595: <09>Lane 05 new seed: 0052
09.595: <09>Lane 06 scaled delay: 0055
09.595: <09>Lane 06 new seed: 0055
09.595: <09>Lane 07 scaled delay: 0058
09.595: <09>Lane 07 new seed: 0058
09.595: <09>Lane 08 scaled delay: 0050
09.595: <09>Lane 08 new seed: 0050
09.595: <09>Lane 00 nibble 0 raw readback: 002b
09.595: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006b
09.595: <09>Lane 00 nibble 0 adjusted value (post nibble): 006b
09.595: <09>Lane 01 nibble 0 raw readback: 0026
09.595: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0066
09.595: <09>Lane 01 nibble 0 adjusted value (post nibble): 0066
09.595: <09>Lane 02 nibble 0 raw readback: 0060
09.595: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0060
09.595: <09>Lane 02 nibble 0 adjusted value (post nibble): 0060
09.595: <09>Lane 03 nibble 0 raw readback: 005b
09.595: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005b
09.595: <09>Lane 03 nibble 0 adjusted value (post nibble): 005b
09.595: <09>Lane 04 nibble 0 raw readback: 004a
09.595: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004a
09.595: <09>Lane 04 nibble 0 adjusted value (post nibble): 004a
09.595: <09>Lane 05 nibble 0 raw readback: 0050
09.595: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0050
09.595: <09>Lane 05 nibble 0 adjusted value (post nibble): 0050
09.595: <09>Lane 06 nibble 0 raw readback: 0053
09.595: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0053
09.595: <09>Lane 06 nibble 0 adjusted value (post nibble): 0053
09.595: <09>Lane 07 nibble 0 raw readback: 0059
09.595: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0059
09.595: <09>Lane 07 nibble 0 adjusted value (post nibble): 0059
09.595: <09>Lane 08 nibble 0 raw readback: 004e
09.595: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004e
09.595: <09>Lane 08 nibble 0 adjusted value (post nibble): 004e
09.595: AgesaHwWlPhase1: training nibble 1
09.595: DIMM 0 RttNom: 5
09.595: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.595: DIMM 0 RttWr: 2
09.595: DIMM 0 RttWr: 2
09.596: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.596: DIMM 0 RttWr: 2
09.596: DIMM 0 RttNom: 5
09.596: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.596: DIMM 0 RttNom: 5
09.596: DIMM 0 RttWr: 2
09.596: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.596: DIMM 0 RttWr: 2
09.596: DIMM 1 RttNom: 5
09.596: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.596: DIMM 0 RttNom: 5
09.596: DIMM 1 RttWr: 2
09.596: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.596: DIMM 0 RttWr: 2
09.596: DIMM 1 RttNom: 5
09.596: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.596: DIMM 0 RttNom: 5
09.596: DIMM 1 RttWr: 2
09.596: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.596: DIMM 0 RttWr: 2
09.596: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.596: <09>Lane 00 new seed: 0067
09.596: <09>Lane 01 new seed: 0061
09.596: <09>Lane 02 new seed: 005f
09.596: <09>Lane 03 new seed: 005c
09.596: <09>Lane 04 new seed: 004e
09.596: <09>Lane 05 new seed: 0052
09.596: <09>Lane 06 new seed: 0055
09.596: <09>Lane 07 new seed: 0058
09.596: <09>Lane 08 new seed: 0050
09.596: <09>Lane 00 nibble 1 raw readback: 002b
09.596: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006b
09.596: <09>Lane 00 nibble 1 adjusted value (post nibble): 0069
09.596: <09>Lane 01 nibble 1 raw readback: 0025
09.596: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0065
09.596: <09>Lane 01 nibble 1 adjusted value (post nibble): 0063
09.596: <09>Lane 02 nibble 1 raw readback: 0061
09.596: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0061
09.596: <09>Lane 02 nibble 1 adjusted value (post nibble): 0060
09.596: <09>Lane 03 nibble 1 raw readback: 005c
09.596: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005c
09.596: <09>Lane 03 nibble 1 adjusted value (post nibble): 005c
09.596: <09>Lane 04 nibble 1 raw readback: 004a
09.596: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004a
09.596: <09>Lane 04 nibble 1 adjusted value (post nibble): 004c
09.596: <09>Lane 05 nibble 1 raw readback: 004f
09.596: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004f
09.596: <09>Lane 05 nibble 1 adjusted value (post nibble): 0050
09.596: <09>Lane 06 nibble 1 raw readback: 0055
09.596: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0055
09.596: <09>Lane 06 nibble 1 adjusted value (post nibble): 0055
09.596: <09>Lane 07 nibble 1 raw readback: 0059
09.596: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0059
09.596: <09>Lane 07 nibble 1 adjusted value (post nibble): 0058
09.596: <09>Lane 08 nibble 1 raw readback: 004e
09.596: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004e
09.596: <09>Lane 08 nibble 1 adjusted value (post nibble): 004f
09.596: <09>original critical gross delay: 0
09.596: <09>new critical gross delay: 0
09.596: DIMM 0 RttNom: 5
09.596: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.596: DIMM 0 RttNom: 5
09.596: DIMM 0 RttWr: 2
09.596: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.596: DIMM 0 RttWr: 2
09.597: DIMM 0 RttNom: 5
09.597: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.597: DIMM 0 RttNom: 5
09.597: DIMM 0 RttWr: 2
09.597: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.597: DIMM 0 RttWr: 2
09.597: DIMM 1 RttNom: 5
09.597: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.597: DIMM 0 RttNom: 5
09.597: DIMM 1 RttWr: 2
09.597: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.597: DIMM 0 RttWr: 2
09.597: DIMM 1 RttNom: 5
09.597: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.597: DIMM 0 RttNom: 5
09.597: DIMM 1 RttWr: 2
09.597: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.597: DIMM 0 RttWr: 2
09.597: AgesaHwWlPhase1: training nibble 0
09.597: DIMM 1 RttNom: 5
09.597: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.597: DIMM 1 RttWr: 2
09.597: DIMM 1 RttWr: 2
09.597: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.597: DIMM 1 RttWr: 2
09.597: DIMM 1 RttNom: 5
09.597: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.597: DIMM 1 RttNom: 5
09.597: DIMM 1 RttWr: 2
09.597: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.597: DIMM 1 RttWr: 2
09.597: DIMM 0 RttNom: 5
09.597: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.597: DIMM 1 RttNom: 5
09.597: DIMM 0 RttWr: 2
09.597: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.597: DIMM 1 RttWr: 2
09.597: DIMM 0 RttNom: 5
09.597: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.597: DIMM 1 RttNom: 5
09.597: DIMM 0 RttWr: 2
09.597: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.597: DIMM 1 RttWr: 2
09.597: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.597: <09>Lane 00 scaled delay: 005d
09.597: <09>Lane 00 new seed: 005d
09.597: <09>Lane 01 scaled delay: 0059
09.597: <09>Lane 01 new seed: 0059
09.597: <09>Lane 02 scaled delay: 0055
09.597: <09>Lane 02 new seed: 0055
09.597: <09>Lane 03 scaled delay: 0053
09.597: <09>Lane 03 new seed: 0053
09.597: <09>Lane 04 scaled delay: 0045
09.597: <09>Lane 04 new seed: 0045
09.597: <09>Lane 05 scaled delay: 0049
09.597: <09>Lane 05 new seed: 0049
09.597: <09>Lane 06 scaled delay: 004d
09.597: <09>Lane 06 new seed: 004d
09.597: <09>Lane 07 scaled delay: 004f
09.597: <09>Lane 07 new seed: 004f
09.597: <09>Lane 08 scaled delay: 0049
09.597: <09>Lane 08 new seed: 0049
09.597: <09>Lane 00 nibble 0 raw readback: 005f
09.597: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005f
09.597: <09>Lane 00 nibble 0 adjusted value (post nibble): 005f
09.597: <09>Lane 01 nibble 0 raw readback: 005a
09.597: <09>Lane 01 nibble 0 adjusted value (pre nibble): 005a
09.598: <09>Lane 01 nibble 0 adjusted value (post nibble): 005a
09.597: <09>Lane 02 nibble 0 raw readback: 0052
09.597: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0052
09.597: <09>Lane 02 nibble 0 adjusted value (post nibble): 0052
09.597: <09>Lane 03 nibble 0 raw readback: 004e
09.598: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004e
09.598: <09>Lane 03 nibble 0 adjusted value (post nibble): 004e
09.598: <09>Lane 04 nibble 0 raw readback: 003e
09.598: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003e
09.598: <09>Lane 04 nibble 0 adjusted value (post nibble): 003e
09.598: <09>Lane 05 nibble 0 raw readback: 0042
09.598: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0042
09.598: <09>Lane 05 nibble 0 adjusted value (post nibble): 0042
09.598: <09>Lane 06 nibble 0 raw readback: 0049
09.598: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0049
09.598: <09>Lane 06 nibble 0 adjusted value (post nibble): 0049
09.598: <09>Lane 07 nibble 0 raw readback: 004d
09.598: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004d
09.598: <09>Lane 07 nibble 0 adjusted value (post nibble): 004d
09.598: <09>Lane 08 nibble 0 raw readback: 0041
09.598: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0041
09.598: <09>Lane 08 nibble 0 adjusted value (post nibble): 0041
09.598: AgesaHwWlPhase1: training nibble 1
09.598: DIMM 1 RttNom: 5
09.598: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.598: DIMM 1 RttWr: 2
09.598: DIMM 1 RttWr: 2
09.598: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.598: DIMM 1 RttWr: 2
09.598: DIMM 1 RttNom: 5
09.598: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.598: DIMM 1 RttNom: 5
09.598: DIMM 1 RttWr: 2
09.598: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.598: DIMM 1 RttWr: 2
09.598: DIMM 0 RttNom: 5
09.598: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.598: DIMM 1 RttNom: 5
09.598: DIMM 0 RttWr: 2
09.598: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.598: DIMM 1 RttWr: 2
09.598: DIMM 0 RttNom: 5
09.598: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.598: DIMM 1 RttNom: 5
09.598: DIMM 0 RttWr: 2
09.598: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.598: DIMM 1 RttWr: 2
09.598: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.598: <09>Lane 00 new seed: 005d
09.598: <09>Lane 01 new seed: 0059
09.598: <09>Lane 02 new seed: 0055
09.598: <09>Lane 03 new seed: 0053
09.598: <09>Lane 04 new seed: 0045
09.598: <09>Lane 05 new seed: 0049
09.598: <09>Lane 06 new seed: 004d
09.598: <09>Lane 07 new seed: 004f
09.598: <09>Lane 08 new seed: 0049
09.598: <09>Lane 00 nibble 1 raw readback: 005d
09.598: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005d
09.598: <09>Lane 00 nibble 1 adjusted value (post nibble): 005d
09.598: <09>Lane 01 nibble 1 raw readback: 0058
09.598: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0058
09.598: <09>Lane 01 nibble 1 adjusted value (post nibble): 0058
09.598: <09>Lane 02 nibble 1 raw readback: 0051
09.598: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0051
09.598: <09>Lane 02 nibble 1 adjusted value (post nibble): 0053
09.598: <09>Lane 03 nibble 1 raw readback: 004f
09.598: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004f
09.598: <09>Lane 03 nibble 1 adjusted value (post nibble): 0051
09.598: <09>Lane 04 nibble 1 raw readback: 003c
09.598: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003c
09.598: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
09.598: <09>Lane 05 nibble 1 raw readback: 0043
09.598: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0043
09.598: <09>Lane 05 nibble 1 adjusted value (post nibble): 0046
09.598: <09>Lane 06 nibble 1 raw readback: 0048
09.598: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0048
09.598: <09>Lane 06 nibble 1 adjusted value (post nibble): 004a
09.598: <09>Lane 07 nibble 1 raw readback: 004c
09.598: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004c
09.598: <09>Lane 07 nibble 1 adjusted value (post nibble): 004d
09.598: <09>Lane 08 nibble 1 raw readback: 0041
09.598: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0041
09.598: <09>Lane 08 nibble 1 adjusted value (post nibble): 0045
09.598: <09>original critical gross delay: 0
09.598: <09>new critical gross delay: 0
09.599: DIMM 1 RttNom: 5
09.599: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.599: DIMM 1 RttNom: 5
09.599: DIMM 1 RttWr: 2
09.599: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.599: DIMM 1 RttWr: 2
09.599: DIMM 1 RttNom: 5
09.599: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.599: DIMM 1 RttNom: 5
09.599: DIMM 1 RttWr: 2
09.599: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.599: DIMM 1 RttWr: 2
09.599: DIMM 0 RttNom: 5
09.599: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.599: DIMM 1 RttNom: 5
09.599: DIMM 0 RttWr: 2
09.599: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.599: DIMM 1 RttWr: 2
09.599: DIMM 0 RttNom: 5
09.599: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.599: DIMM 1 RttNom: 5
09.599: DIMM 0 RttWr: 2
09.599: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.599: DIMM 1 RttWr: 2
09.599: SetTargetFreq: Start
09.599: SetTargetFreq: Node 0: New frequency code: 0012
09.599: ChangeMemClk: Start
09.599: set_2t_configuration: Start
09.599: set_2t_configuration: Done
09.599: mct_BeforePlatformSpec: Start
09.599: mct_BeforePlatformSpec: Done
09.599: mct_PlatformSpec: Start
09.599: Programmed DCT 0 timing/termination pattern 00353935 30222222
09.599: mct_PlatformSpec: Done
09.599: set_2t_configuration: Start
09.600: set_2t_configuration: Done
09.599: mct_BeforePlatformSpec: Start
09.600: mct_BeforePlatformSpec: Done
09.600: mct_PlatformSpec: Start
09.600: Programmed DCT 1 timing/termination pattern 00353935 30222222
09.600: mct_PlatformSpec: Done
09.600: ChangeMemClk: Done
09.600: phyAssistedMemFnceTraining: Start
09.600: phyAssistedMemFnceTraining: training node 0 DCT 0
09.600: phyAssistedMemFnceTraining: done training node 0 DCT 0
09.600: phyAssistedMemFnceTraining: training node 0 DCT 1
09.600: phyAssistedMemFnceTraining: done training node 0 DCT 1
09.600: phyAssistedMemFnceTraining: Done
09.600: InitPhyCompensation: DCT 0: Start
09.600: Waiting for predriver calibration to be applied...done!
09.600: InitPhyCompensation: DCT 0: Done
09.600: phyAssistedMemFnceTraining: Start
09.600: phyAssistedMemFnceTraining: training node 0 DCT 0
09.600: phyAssistedMemFnceTraining: done training node 0 DCT 0
09.600: phyAssistedMemFnceTraining: training node 0 DCT 1
09.600: phyAssistedMemFnceTraining: done training node 0 DCT 1
09.600: phyAssistedMemFnceTraining: Done
09.600: InitPhyCompensation: DCT 1: Start
09.600: Waiting for predriver calibration to be applied...done!
09.600: InitPhyCompensation: DCT 1: Done
09.600: Preparing to send DCT 0 DIMM 0 RC10: 03 (F2xA8: 02000300)
09.601: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.601: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
09.601: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.601: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
09.601: Preparing to send DCT 0 DIMM 1 RC10: 03 (F2xA8: 02000c00)
09.601: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.601: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
09.601: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.601: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
09.601: Preparing to send DCT 1 DIMM 0 RC10: 03 (F2xA8: 02000300)
09.601: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.601: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
09.601: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.601: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
09.601: Preparing to send DCT 1 DIMM 1 RC10: 03 (F2xA8: 02000c00)
09.601: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.601: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
09.601: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.601: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
09.601: SetTargetFreq: Done
09.601: SPD2ndTiming: Start
09.601: SPD2ndTiming: Done
09.601: mct_BeforeDramInit_Prod_D: Start
09.601: mct_ProgramODT_D: Start
09.601: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
09.601: mct_ProgramODT_D: Done
09.601: mct_BeforeDramInit_Prod_D: Done
09.601: mct_DramInit_Sw_D: Start
09.601: DIMM 0 RttWr: 1
09.601: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.602: mct_SendMrsCmd: Start
09.601: mct_SendMrsCmd: Done
09.601: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
09.601: mct_SendMrsCmd: Start
09.601: mct_SendMrsCmd: Done
09.602: DIMM 0 RttNom: 4
09.602: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.602: mct_SendMrsCmd: Start
09.602: mct_SendMrsCmd: Done
09.602: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001d78
09.602: mct_SendMrsCmd: Start
09.602: mct_SendMrsCmd: Done
09.602: DIMM 0 RttWr: 1
09.602: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.602: mct_SendMrsCmd: Start
09.602: mct_SendMrsCmd: Done
09.602: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
09.602: mct_SendMrsCmd: Start
09.602: mct_SendMrsCmd: Done
09.602: DIMM 0 RttNom: 4
09.602: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.602: mct_SendMrsCmd: Start
09.602: mct_SendMrsCmd: Done
09.602: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201d78
09.602: mct_SendMrsCmd: Start
09.602: mct_SendMrsCmd: Done
09.602: DIMM 1 RttWr: 1
09.602: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.602: mct_SendMrsCmd: Start
09.602: mct_SendMrsCmd: Done
09.602: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
09.602: mct_SendMrsCmd: Start
09.602: mct_SendMrsCmd: Done
09.602: DIMM 1 RttNom: 4
09.602: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.602: mct_SendMrsCmd: Start
09.602: mct_SendMrsCmd: Done
09.602: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401d78
09.602: mct_SendMrsCmd: Start
09.602: mct_SendMrsCmd: Done
09.602: DIMM 1 RttWr: 1
09.602: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.602: mct_SendMrsCmd: Start
09.602: mct_SendMrsCmd: Done
09.602: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
09.602: mct_SendMrsCmd: Start
09.602: mct_SendMrsCmd: Done
09.602: DIMM 1 RttNom: 4
09.602: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.602: mct_SendMrsCmd: Start
09.602: mct_SendMrsCmd: Done
09.602: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601d78
09.602: mct_SendMrsCmd: Start
09.602: mct_SendMrsCmd: Done
09.602: mct_DramInit_Sw_D: Done
09.603: AgesaHwWlPhase1: training nibble 0
09.603: DIMM 0 RttNom: 4
09.603: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.603: DIMM 0 RttWr: 1
09.603: DIMM 0 RttWr: 1
09.603: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.603: DIMM 0 RttWr: 1
09.603: DIMM 0 RttNom: 4
09.603: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.603: DIMM 0 RttNom: 4
09.603: DIMM 0 RttWr: 1
09.603: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.603: DIMM 0 RttWr: 1
09.603: DIMM 1 RttNom: 4
09.603: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.603: DIMM 0 RttNom: 4
09.603: DIMM 1 RttWr: 1
09.603: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.603: DIMM 0 RttWr: 1
09.603: DIMM 1 RttNom: 4
09.603: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.603: DIMM 0 RttNom: 4
09.603: DIMM 1 RttWr: 1
09.603: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.603: DIMM 0 RttWr: 1
09.603: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.603: <09>Lane 00 scaled delay: 007b
09.603: <09>Lane 00 new seed: 007b
09.603: <09>Lane 01 scaled delay: 0071
09.603: <09>Lane 01 new seed: 0071
09.603: <09>Lane 02 scaled delay: 006d
09.603: <09>Lane 02 new seed: 006d
09.603: <09>Lane 03 scaled delay: 0069
09.603: <09>Lane 03 new seed: 0069
09.603: <09>Lane 04 scaled delay: 0054
09.603: <09>Lane 04 new seed: 0054
09.603: <09>Lane 05 scaled delay: 005d
09.603: <09>Lane 05 new seed: 005d
09.603: <09>Lane 06 scaled delay: 0063
09.603: <09>Lane 06 new seed: 0063
09.603: <09>Lane 07 scaled delay: 0065
09.603: <09>Lane 07 new seed: 0065
09.603: <09>Lane 08 scaled delay: 0059
09.603: <09>Lane 08 new seed: 0059
09.603: <09>Lane 00 nibble 0 raw readback: 0042
09.604: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0082
09.604: <09>Lane 00 nibble 0 adjusted value (post nibble): 0082
09.604: <09>Lane 01 nibble 0 raw readback: 0036
09.604: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0076
09.604: <09>Lane 01 nibble 0 adjusted value (post nibble): 0076
09.604: <09>Lane 02 nibble 0 raw readback: 0031
09.604: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0071
09.604: <09>Lane 02 nibble 0 adjusted value (post nibble): 0071
09.604: <09>Lane 03 nibble 0 raw readback: 002a
09.604: <09>Lane 03 nibble 0 adjusted value (pre nibble): 006a
09.604: <09>Lane 03 nibble 0 adjusted value (post nibble): 006a
09.604: <09>Lane 04 nibble 0 raw readback: 0056
09.604: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0056
09.604: <09>Lane 04 nibble 0 adjusted value (post nibble): 0056
09.604: <09>Lane 05 nibble 0 raw readback: 005f
09.604: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005f
09.604: <09>Lane 05 nibble 0 adjusted value (post nibble): 005f
09.604: <09>Lane 06 nibble 0 raw readback: 0025
09.604: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0065
09.604: <09>Lane 06 nibble 0 adjusted value (post nibble): 0065
09.604: <09>Lane 07 nibble 0 raw readback: 0029
09.604: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0069
09.604: <09>Lane 07 nibble 0 adjusted value (post nibble): 0069
09.604: <09>Lane 08 nibble 0 raw readback: 005b
09.604: <09>Lane 08 nibble 0 adjusted value (pre nibble): 005b
09.604: <09>Lane 08 nibble 0 adjusted value (post nibble): 005b
09.604: AgesaHwWlPhase1: training nibble 1
09.604: DIMM 0 RttNom: 4
09.604: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.604: DIMM 0 RttWr: 1
09.604: DIMM 0 RttWr: 1
09.604: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.604: DIMM 0 RttWr: 1
09.604: DIMM 0 RttNom: 4
09.604: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.604: DIMM 0 RttNom: 4
09.604: DIMM 0 RttWr: 1
09.604: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.604: DIMM 0 RttWr: 1
09.604: DIMM 1 RttNom: 4
09.604: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.604: DIMM 0 RttNom: 4
09.604: DIMM 1 RttWr: 1
09.604: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.604: DIMM 0 RttWr: 1
09.604: DIMM 1 RttNom: 4
09.604: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.604: DIMM 0 RttNom: 4
09.604: DIMM 1 RttWr: 1
09.604: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.604: DIMM 0 RttWr: 1
09.604: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.604: <09>Lane 00 new seed: 007b
09.604: <09>Lane 01 new seed: 0071
09.604: <09>Lane 02 new seed: 006d
09.604: <09>Lane 03 new seed: 0069
09.604: <09>Lane 04 new seed: 0054
09.604: <09>Lane 05 new seed: 005d
09.604: <09>Lane 06 new seed: 0063
09.604: <09>Lane 07 new seed: 0065
09.604: <09>Lane 08 new seed: 0059
09.604: <09>Lane 00 nibble 1 raw readback: 0040
09.604: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0080
09.604: <09>Lane 00 nibble 1 adjusted value (post nibble): 007d
09.604: <09>Lane 01 nibble 1 raw readback: 0036
09.604: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0076
09.604: <09>Lane 01 nibble 1 adjusted value (post nibble): 0073
09.604: <09>Lane 02 nibble 1 raw readback: 0032
09.604: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0072
09.605: <09>Lane 02 nibble 1 adjusted value (post nibble): 006f
09.605: <09>Lane 03 nibble 1 raw readback: 002c
09.605: <09>Lane 03 nibble 1 adjusted value (pre nibble): 006c
09.605: <09>Lane 03 nibble 1 adjusted value (post nibble): 006a
09.605: <09>Lane 04 nibble 1 raw readback: 0056
09.605: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0056
09.605: <09>Lane 04 nibble 1 adjusted value (post nibble): 0055
09.605: <09>Lane 05 nibble 1 raw readback: 0060
09.605: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0060
09.605: <09>Lane 05 nibble 1 adjusted value (post nibble): 005e
09.605: <09>Lane 06 nibble 1 raw readback: 0025
09.605: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0065
09.605: <09>Lane 06 nibble 1 adjusted value (post nibble): 0064
09.605: <09>Lane 07 nibble 1 raw readback: 0028
09.605: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0068
09.605: <09>Lane 07 nibble 1 adjusted value (post nibble): 0066
09.605: <09>Lane 08 nibble 1 raw readback: 005c
09.605: <09>Lane 08 nibble 1 adjusted value (pre nibble): 005c
09.605: <09>Lane 08 nibble 1 adjusted value (post nibble): 005a
09.605: <09>original critical gross delay: 0
09.605: <09>new critical gross delay: 0
09.605: DIMM 0 RttNom: 4
09.605: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.605: DIMM 0 RttNom: 4
09.605: DIMM 0 RttWr: 1
09.605: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.605: DIMM 0 RttWr: 1
09.605: DIMM 0 RttNom: 4
09.605: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.605: DIMM 0 RttNom: 4
09.605: DIMM 0 RttWr: 1
09.605: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.605: DIMM 0 RttWr: 1
09.605: DIMM 1 RttNom: 4
09.605: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.605: DIMM 0 RttNom: 4
09.605: DIMM 1 RttWr: 1
09.605: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.605: DIMM 0 RttWr: 1
09.605: DIMM 1 RttNom: 4
09.605: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.605: DIMM 0 RttNom: 4
09.605: DIMM 1 RttWr: 1
09.605: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.605: DIMM 0 RttWr: 1
09.605: AgesaHwWlPhase1: training nibble 0
09.605: DIMM 1 RttNom: 4
09.605: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.605: DIMM 1 RttWr: 1
09.605: DIMM 1 RttWr: 1
09.605: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.605: DIMM 1 RttWr: 1
09.605: DIMM 1 RttNom: 4
09.605: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.605: DIMM 1 RttNom: 4
09.605: DIMM 1 RttWr: 1
09.605: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.605: DIMM 1 RttWr: 1
09.605: DIMM 0 RttNom: 4
09.605: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.605: DIMM 1 RttNom: 4
09.605: DIMM 0 RttWr: 1
09.605: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.605: DIMM 1 RttWr: 1
09.606: DIMM 0 RttNom: 4
09.606: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.606: DIMM 1 RttNom: 4
09.606: DIMM 0 RttWr: 1
09.606: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.606: DIMM 1 RttWr: 1
09.606: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.606: <09>Lane 00 scaled delay: 006b
09.606: <09>Lane 00 new seed: 006b
09.606: <09>Lane 01 scaled delay: 0061
09.606: <09>Lane 01 new seed: 0061
09.606: <09>Lane 02 scaled delay: 005f
09.606: <09>Lane 02 new seed: 005f
09.606: <09>Lane 03 scaled delay: 0059
09.606: <09>Lane 03 new seed: 0059
09.606: <09>Lane 04 scaled delay: 0045
09.606: <09>Lane 04 new seed: 0045
09.606: <09>Lane 05 scaled delay: 004e
09.606: <09>Lane 05 new seed: 004e
09.606: <09>Lane 06 scaled delay: 0052
09.606: <09>Lane 06 new seed: 0052
09.606: <09>Lane 07 scaled delay: 0058
09.606: <09>Lane 07 new seed: 0058
09.606: <09>Lane 08 scaled delay: 0048
09.606: <09>Lane 08 new seed: 0048
09.606: <09>Lane 00 nibble 0 raw readback: 0031
09.606: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0071
09.606: <09>Lane 00 nibble 0 adjusted value (post nibble): 0071
09.606: <09>Lane 01 nibble 0 raw readback: 0026
09.606: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0066
09.606: <09>Lane 01 nibble 0 adjusted value (post nibble): 0066
09.606: <09>Lane 02 nibble 0 raw readback: 0061
09.606: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0061
09.606: <09>Lane 02 nibble 0 adjusted value (post nibble): 0061
09.606: <09>Lane 03 nibble 0 raw readback: 005b
09.606: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005b
09.606: <09>Lane 03 nibble 0 adjusted value (post nibble): 005b
09.606: <09>Lane 04 nibble 0 raw readback: 0048
09.606: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0048
09.606: <09>Lane 04 nibble 0 adjusted value (post nibble): 0048
09.606: <09>Lane 05 nibble 0 raw readback: 0051
09.606: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0051
09.606: <09>Lane 05 nibble 0 adjusted value (post nibble): 0051
09.606: <09>Lane 06 nibble 0 raw readback: 0055
09.606: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0055
09.606: <09>Lane 06 nibble 0 adjusted value (post nibble): 0055
09.606: <09>Lane 07 nibble 0 raw readback: 005a
09.606: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005a
09.606: <09>Lane 07 nibble 0 adjusted value (post nibble): 005a
09.606: <09>Lane 08 nibble 0 raw readback: 004b
09.606: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004b
09.606: <09>Lane 08 nibble 0 adjusted value (post nibble): 004b
09.606: AgesaHwWlPhase1: training nibble 1
09.606: DIMM 1 RttNom: 4
09.606: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.606: DIMM 1 RttWr: 1
09.606: DIMM 1 RttWr: 1
09.606: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.606: DIMM 1 RttWr: 1
09.606: DIMM 1 RttNom: 4
09.606: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.606: DIMM 1 RttNom: 4
09.606: DIMM 1 RttWr: 1
09.606: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.606: DIMM 1 RttWr: 1
09.606: DIMM 0 RttNom: 4
09.606: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.606: DIMM 1 RttNom: 4
09.606: DIMM 0 RttWr: 1
09.606: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.606: DIMM 1 RttWr: 1
09.606: DIMM 0 RttNom: 4
09.606: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.606: DIMM 1 RttNom: 4
09.606: DIMM 0 RttWr: 1
09.606: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.606: DIMM 1 RttWr: 1
09.606: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.606: <09>Lane 00 new seed: 006b
09.606: <09>Lane 01 new seed: 0061
09.607: <09>Lane 02 new seed: 005f
09.607: <09>Lane 03 new seed: 0059
09.607: <09>Lane 04 new seed: 0045
09.607: <09>Lane 05 new seed: 004e
09.607: <09>Lane 06 new seed: 0052
09.607: <09>Lane 07 new seed: 0058
09.607: <09>Lane 08 new seed: 0048
09.607: <09>Lane 00 nibble 1 raw readback: 0031
09.607: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0071
09.607: <09>Lane 00 nibble 1 adjusted value (post nibble): 006e
09.607: <09>Lane 01 nibble 1 raw readback: 0027
09.607: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0067
09.607: <09>Lane 01 nibble 1 adjusted value (post nibble): 0064
09.607: <09>Lane 02 nibble 1 raw readback: 0063
09.607: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0063
09.607: <09>Lane 02 nibble 1 adjusted value (post nibble): 0061
09.607: <09>Lane 03 nibble 1 raw readback: 005c
09.607: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005c
09.607: <09>Lane 03 nibble 1 adjusted value (post nibble): 005a
09.607: <09>Lane 04 nibble 1 raw readback: 0047
09.607: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0047
09.607: <09>Lane 04 nibble 1 adjusted value (post nibble): 0046
09.607: <09>Lane 05 nibble 1 raw readback: 0050
09.607: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0050
09.607: <09>Lane 05 nibble 1 adjusted value (post nibble): 004f
09.607: <09>Lane 06 nibble 1 raw readback: 0055
09.607: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0055
09.607: <09>Lane 06 nibble 1 adjusted value (post nibble): 0053
09.607: <09>Lane 07 nibble 1 raw readback: 005b
09.607: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005b
09.607: <09>Lane 07 nibble 1 adjusted value (post nibble): 0059
09.607: <09>Lane 08 nibble 1 raw readback: 004a
09.607: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004a
09.607: <09>Lane 08 nibble 1 adjusted value (post nibble): 0049
09.607: <09>original critical gross delay: 0
09.607: <09>new critical gross delay: 0
09.607: DIMM 1 RttNom: 4
09.607: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.607: DIMM 1 RttNom: 4
09.607: DIMM 1 RttWr: 1
09.607: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.607: DIMM 1 RttWr: 1
09.607: DIMM 1 RttNom: 4
09.607: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.607: DIMM 1 RttNom: 4
09.607: DIMM 1 RttWr: 1
09.607: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.607: DIMM 1 RttWr: 1
09.607: DIMM 0 RttNom: 4
09.607: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.607: DIMM 1 RttNom: 4
09.607: DIMM 0 RttWr: 1
09.607: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.607: DIMM 1 RttWr: 1
09.607: DIMM 0 RttNom: 4
09.607: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.607: DIMM 1 RttNom: 4
09.607: DIMM 0 RttWr: 1
09.607: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.607: DIMM 1 RttWr: 1
09.607: SPD2ndTiming: Start
09.608: SPD2ndTiming: Done
09.608: mct_BeforeDramInit_Prod_D: Start
09.608: mct_ProgramODT_D: Start
09.608: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
09.608: mct_ProgramODT_D: Done
09.608: mct_BeforeDramInit_Prod_D: Done
09.608: mct_DramInit_Sw_D: Start
09.608: DIMM 0 RttWr: 1
09.608: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.608: mct_SendMrsCmd: Start
09.608: mct_SendMrsCmd: Done
09.608: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
09.608: mct_SendMrsCmd: Start
09.608: mct_SendMrsCmd: Done
09.608: DIMM 0 RttNom: 4
09.608: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.608: mct_SendMrsCmd: Start
09.608: mct_SendMrsCmd: Done
09.608: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001d78
09.608: mct_SendMrsCmd: Start
09.608: mct_SendMrsCmd: Done
09.608: DIMM 0 RttWr: 1
09.608: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.608: mct_SendMrsCmd: Start
09.608: mct_SendMrsCmd: Done
09.608: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
09.608: mct_SendMrsCmd: Start
09.608: mct_SendMrsCmd: Done
09.608: DIMM 0 RttNom: 4
09.608: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.608: mct_SendMrsCmd: Start
09.608: mct_SendMrsCmd: Done
09.608: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201d78
09.608: mct_SendMrsCmd: Start
09.608: mct_SendMrsCmd: Done
09.608: DIMM 1 RttWr: 1
09.608: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.608: mct_SendMrsCmd: Start
09.608: mct_SendMrsCmd: Done
09.608: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
09.608: mct_SendMrsCmd: Start
09.608: mct_SendMrsCmd: Done
09.609: DIMM 1 RttNom: 4
09.609: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.609: mct_SendMrsCmd: Start
09.609: mct_SendMrsCmd: Done
09.609: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401d78
09.609: mct_SendMrsCmd: Start
09.609: mct_SendMrsCmd: Done
09.609: DIMM 1 RttWr: 1
09.609: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.609: mct_SendMrsCmd: Start
09.609: mct_SendMrsCmd: Done
09.609: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
09.609: mct_SendMrsCmd: Start
09.609: mct_SendMrsCmd: Done
09.609: DIMM 1 RttNom: 4
09.609: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.609: mct_SendMrsCmd: Start
09.609: mct_SendMrsCmd: Done
09.609: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601d78
09.609: mct_SendMrsCmd: Start
09.609: mct_SendMrsCmd: Done
09.609: mct_DramInit_Sw_D: Done
09.609: AgesaHwWlPhase1: training nibble 0
09.609: DIMM 0 RttNom: 4
09.609: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.609: DIMM 0 RttWr: 1
09.609: DIMM 0 RttWr: 1
09.609: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.609: DIMM 0 RttWr: 1
09.609: DIMM 0 RttNom: 4
09.609: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.609: DIMM 0 RttNom: 4
09.609: DIMM 0 RttWr: 1
09.609: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.609: DIMM 0 RttWr: 1
09.609: DIMM 1 RttNom: 4
09.609: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.609: DIMM 0 RttNom: 4
09.609: DIMM 1 RttWr: 1
09.609: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.609: DIMM 0 RttWr: 1
09.609: DIMM 1 RttNom: 4
09.609: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.609: DIMM 0 RttNom: 4
09.609: DIMM 1 RttWr: 1
09.609: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.609: DIMM 0 RttWr: 1
09.609: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.609: <09>Lane 00 scaled delay: 0077
09.609: <09>Lane 00 new seed: 0077
09.609: <09>Lane 01 scaled delay: 0070
09.609: <09>Lane 01 new seed: 0070
09.609: <09>Lane 02 scaled delay: 006c
09.609: <09>Lane 02 new seed: 006c
09.610: <09>Lane 03 scaled delay: 0067
09.609: <09>Lane 03 new seed: 0067
09.609: <09>Lane 04 scaled delay: 0054
09.609: <09>Lane 04 new seed: 0054
09.609: <09>Lane 05 scaled delay: 0059
09.610: <09>Lane 05 new seed: 0059
09.610: <09>Lane 06 scaled delay: 005f
09.610: <09>Lane 06 new seed: 005f
09.610: <09>Lane 07 scaled delay: 0063
09.610: <09>Lane 07 new seed: 0063
09.610: <09>Lane 08 scaled delay: 0058
09.610: <09>Lane 08 new seed: 0058
09.610: <09>Lane 00 nibble 0 raw readback: 003d
09.610: <09>Lane 00 nibble 0 adjusted value (pre nibble): 007d
09.610: <09>Lane 00 nibble 0 adjusted value (post nibble): 007d
09.610: <09>Lane 01 nibble 0 raw readback: 0037
09.610: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0077
09.610: <09>Lane 01 nibble 0 adjusted value (post nibble): 0077
09.610: <09>Lane 02 nibble 0 raw readback: 002e
09.610: <09>Lane 02 nibble 0 adjusted value (pre nibble): 006e
09.610: <09>Lane 02 nibble 0 adjusted value (post nibble): 006e
09.610: <09>Lane 03 nibble 0 raw readback: 0029
09.610: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0069
09.610: <09>Lane 03 nibble 0 adjusted value (post nibble): 0069
09.610: <09>Lane 04 nibble 0 raw readback: 0056
09.610: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0056
09.610: <09>Lane 04 nibble 0 adjusted value (post nibble): 0056
09.610: <09>Lane 05 nibble 0 raw readback: 005d
09.610: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005d
09.610: <09>Lane 05 nibble 0 adjusted value (post nibble): 005d
09.610: <09>Lane 06 nibble 0 raw readback: 0060
09.610: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0060
09.610: <09>Lane 06 nibble 0 adjusted value (post nibble): 0060
09.610: <09>Lane 07 nibble 0 raw readback: 0025
09.610: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0065
09.610: <09>Lane 07 nibble 0 adjusted value (post nibble): 0065
09.610: <09>Lane 08 nibble 0 raw readback: 0059
09.610: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0059
09.610: <09>Lane 08 nibble 0 adjusted value (post nibble): 0059
09.610: AgesaHwWlPhase1: training nibble 1
09.610: DIMM 0 RttNom: 4
09.610: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.610: DIMM 0 RttWr: 1
09.610: DIMM 0 RttWr: 1
09.610: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.610: DIMM 0 RttWr: 1
09.610: DIMM 0 RttNom: 4
09.610: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.610: DIMM 0 RttNom: 4
09.610: DIMM 0 RttWr: 1
09.610: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.610: DIMM 0 RttWr: 1
09.610: DIMM 1 RttNom: 4
09.610: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.610: DIMM 0 RttNom: 4
09.610: DIMM 1 RttWr: 1
09.610: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.610: DIMM 0 RttWr: 1
09.610: DIMM 1 RttNom: 4
09.610: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.610: DIMM 0 RttNom: 4
09.610: DIMM 1 RttWr: 1
09.610: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.610: DIMM 0 RttWr: 1
09.610: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.610: <09>Lane 00 new seed: 0077
09.610: <09>Lane 01 new seed: 0070
09.610: <09>Lane 02 new seed: 006c
09.611: <09>Lane 03 new seed: 0067
09.611: <09>Lane 04 new seed: 0054
09.611: <09>Lane 05 new seed: 0059
09.611: <09>Lane 06 new seed: 005f
09.611: <09>Lane 07 new seed: 0063
09.611: <09>Lane 08 new seed: 0058
09.611: <09>Lane 00 nibble 1 raw readback: 003d
09.611: <09>Lane 00 nibble 1 adjusted value (pre nibble): 007d
09.611: <09>Lane 00 nibble 1 adjusted value (post nibble): 007a
09.611: <09>Lane 01 nibble 1 raw readback: 0035
09.611: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0075
09.611: <09>Lane 01 nibble 1 adjusted value (post nibble): 0072
09.611: <09>Lane 02 nibble 1 raw readback: 0030
09.611: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0070
09.611: <09>Lane 02 nibble 1 adjusted value (post nibble): 006e
09.611: <09>Lane 03 nibble 1 raw readback: 0029
09.611: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0069
09.611: <09>Lane 03 nibble 1 adjusted value (post nibble): 0068
09.611: <09>Lane 04 nibble 1 raw readback: 0054
09.611: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0054
09.611: <09>Lane 04 nibble 1 adjusted value (post nibble): 0054
09.611: <09>Lane 05 nibble 1 raw readback: 005b
09.611: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005b
09.611: <09>Lane 05 nibble 1 adjusted value (post nibble): 005a
09.611: <09>Lane 06 nibble 1 raw readback: 0062
09.611: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0062
09.611: <09>Lane 06 nibble 1 adjusted value (post nibble): 0060
09.611: <09>Lane 07 nibble 1 raw readback: 0026
09.611: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0066
09.611: <09>Lane 07 nibble 1 adjusted value (post nibble): 0064
09.611: <09>Lane 08 nibble 1 raw readback: 0059
09.611: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0059
09.611: <09>Lane 08 nibble 1 adjusted value (post nibble): 0058
09.611: <09>original critical gross delay: 0
09.611: <09>new critical gross delay: 0
09.611: DIMM 0 RttNom: 4
09.611: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.611: DIMM 0 RttNom: 4
09.611: DIMM 0 RttWr: 1
09.611: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.611: DIMM 0 RttWr: 1
09.611: DIMM 0 RttNom: 4
09.611: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.611: DIMM 0 RttNom: 4
09.611: DIMM 0 RttWr: 1
09.611: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.611: DIMM 0 RttWr: 1
09.611: DIMM 1 RttNom: 4
09.611: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.611: DIMM 0 RttNom: 4
09.611: DIMM 1 RttWr: 1
09.611: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.611: DIMM 0 RttWr: 1
09.611: DIMM 1 RttNom: 4
09.611: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.611: DIMM 0 RttNom: 4
09.611: DIMM 1 RttWr: 1
09.611: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.611: DIMM 0 RttWr: 1
09.611: AgesaHwWlPhase1: training nibble 0
09.611: DIMM 1 RttNom: 4
09.611: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.611: DIMM 1 RttWr: 1
09.611: DIMM 1 RttWr: 1
09.611: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.611: DIMM 1 RttWr: 1
09.611: DIMM 1 RttNom: 4
09.611: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.611: DIMM 1 RttNom: 4
09.611: DIMM 1 RttWr: 1
09.612: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.612: DIMM 1 RttWr: 1
09.612: DIMM 0 RttNom: 4
09.612: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.612: DIMM 1 RttNom: 4
09.612: DIMM 0 RttWr: 1
09.612: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.612: DIMM 1 RttWr: 1
09.612: DIMM 0 RttNom: 4
09.612: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.612: DIMM 1 RttNom: 4
09.612: DIMM 0 RttWr: 1
09.612: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.612: DIMM 1 RttWr: 1
09.612: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.612: <09>Lane 00 scaled delay: 0069
09.612: <09>Lane 00 new seed: 0069
09.612: <09>Lane 01 scaled delay: 0063
09.612: <09>Lane 01 new seed: 0063
09.612: <09>Lane 02 scaled delay: 005d
09.612: <09>Lane 02 new seed: 005d
09.612: <09>Lane 03 scaled delay: 005a
09.612: <09>Lane 03 new seed: 005a
09.612: <09>Lane 04 scaled delay: 0046
09.612: <09>Lane 04 new seed: 0046
09.612: <09>Lane 05 scaled delay: 004d
09.612: <09>Lane 05 new seed: 004d
09.612: <09>Lane 06 scaled delay: 0052
09.612: <09>Lane 06 new seed: 0052
09.612: <09>Lane 07 scaled delay: 0055
09.612: <09>Lane 07 new seed: 0055
09.612: <09>Lane 08 scaled delay: 004c
09.612: <09>Lane 08 new seed: 004c
09.612: <09>Lane 00 nibble 0 raw readback: 002e
09.612: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006e
09.612: <09>Lane 00 nibble 0 adjusted value (post nibble): 006e
09.612: <09>Lane 01 nibble 0 raw readback: 0029
09.612: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0069
09.612: <09>Lane 01 nibble 0 adjusted value (post nibble): 0069
09.612: <09>Lane 02 nibble 0 raw readback: 005f
09.612: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005f
09.612: <09>Lane 02 nibble 0 adjusted value (post nibble): 005f
09.612: <09>Lane 03 nibble 0 raw readback: 005a
09.612: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005a
09.612: <09>Lane 03 nibble 0 adjusted value (post nibble): 005a
09.612: <09>Lane 04 nibble 0 raw readback: 0047
09.612: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0047
09.612: <09>Lane 04 nibble 0 adjusted value (post nibble): 0047
09.612: <09>Lane 05 nibble 0 raw readback: 004c
09.612: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004c
09.612: <09>Lane 05 nibble 0 adjusted value (post nibble): 004c
09.612: <09>Lane 06 nibble 0 raw readback: 0053
09.612: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0053
09.612: <09>Lane 06 nibble 0 adjusted value (post nibble): 0053
09.612: <09>Lane 07 nibble 0 raw readback: 0058
09.612: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0058
09.612: <09>Lane 07 nibble 0 adjusted value (post nibble): 0058
09.612: <09>Lane 08 nibble 0 raw readback: 004a
09.612: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004a
09.612: <09>Lane 08 nibble 0 adjusted value (post nibble): 004a
09.612: AgesaHwWlPhase1: training nibble 1
09.612: DIMM 1 RttNom: 4
09.612: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.612: DIMM 1 RttWr: 1
09.612: DIMM 1 RttWr: 1
09.612: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.612: DIMM 1 RttWr: 1
09.612: DIMM 1 RttNom: 4
09.612: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.613: DIMM 1 RttNom: 4
09.612: DIMM 1 RttWr: 1
09.612: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.612: DIMM 1 RttWr: 1
09.612: DIMM 0 RttNom: 4
09.612: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.612: DIMM 1 RttNom: 4
09.613: DIMM 0 RttWr: 1
09.613: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.613: DIMM 1 RttWr: 1
09.613: DIMM 0 RttNom: 4
09.613: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.613: DIMM 1 RttNom: 4
09.613: DIMM 0 RttWr: 1
09.613: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.613: DIMM 1 RttWr: 1
09.613: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.613: <09>Lane 00 new seed: 0069
09.613: <09>Lane 01 new seed: 0063
09.613: <09>Lane 02 new seed: 005d
09.613: <09>Lane 03 new seed: 005a
09.613: <09>Lane 04 new seed: 0046
09.613: <09>Lane 05 new seed: 004d
09.613: <09>Lane 06 new seed: 0052
09.613: <09>Lane 07 new seed: 0055
09.613: <09>Lane 08 new seed: 004c
09.613: <09>Lane 00 nibble 1 raw readback: 002e
09.613: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006e
09.613: <09>Lane 00 nibble 1 adjusted value (post nibble): 006b
09.613: <09>Lane 01 nibble 1 raw readback: 0027
09.613: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0067
09.613: <09>Lane 01 nibble 1 adjusted value (post nibble): 0065
09.613: <09>Lane 02 nibble 1 raw readback: 0060
09.613: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0060
09.613: <09>Lane 02 nibble 1 adjusted value (post nibble): 005e
09.613: <09>Lane 03 nibble 1 raw readback: 005c
09.613: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005c
09.613: <09>Lane 03 nibble 1 adjusted value (post nibble): 005b
09.613: <09>Lane 04 nibble 1 raw readback: 0046
09.613: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0046
09.613: <09>Lane 04 nibble 1 adjusted value (post nibble): 0046
09.613: <09>Lane 05 nibble 1 raw readback: 004f
09.613: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004f
09.613: <09>Lane 05 nibble 1 adjusted value (post nibble): 004e
09.613: <09>Lane 06 nibble 1 raw readback: 0053
09.613: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0053
09.613: <09>Lane 06 nibble 1 adjusted value (post nibble): 0052
09.613: <09>Lane 07 nibble 1 raw readback: 0057
09.613: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0057
09.613: <09>Lane 07 nibble 1 adjusted value (post nibble): 0056
09.613: <09>Lane 08 nibble 1 raw readback: 004d
09.613: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004d
09.613: <09>Lane 08 nibble 1 adjusted value (post nibble): 004c
09.613: <09>original critical gross delay: 0
09.613: <09>new critical gross delay: 0
09.613: DIMM 1 RttNom: 4
09.613: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.613: DIMM 1 RttNom: 4
09.613: DIMM 1 RttWr: 1
09.613: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.613: DIMM 1 RttWr: 1
09.613: DIMM 1 RttNom: 4
09.613: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.613: DIMM 1 RttNom: 4
09.613: DIMM 1 RttWr: 1
09.613: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.613: DIMM 1 RttWr: 1
09.613: DIMM 0 RttNom: 4
09.613: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.613: DIMM 1 RttNom: 4
09.613: DIMM 0 RttWr: 1
09.613: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.613: DIMM 1 RttWr: 1
09.613: DIMM 0 RttNom: 4
09.613: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.613: DIMM 1 RttNom: 4
09.614: DIMM 0 RttWr: 1
09.614: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.614: DIMM 1 RttWr: 1
09.614: activate_spd_rom() for node 01
09.614: enable_spd_node1()
09.614: SetTargetFreq: Start
09.614: SetTargetFreq: Node 1: New frequency code: 0006
09.614: ChangeMemClk: Start
09.614: set_2t_configuration: Start
09.614: set_2t_configuration: Done
09.614: mct_BeforePlatformSpec: Start
09.614: mct_BeforePlatformSpec: Done
09.614: mct_PlatformSpec: Start
09.614: Programmed DCT 0 timing/termination pattern 00000000 20222222
09.614: mct_PlatformSpec: Done
09.614: set_2t_configuration: Start
09.615: set_2t_configuration: Done
09.615: mct_BeforePlatformSpec: Start
09.615: mct_BeforePlatformSpec: Done
09.615: mct_PlatformSpec: Start
09.615: Programmed DCT 1 timing/termination pattern 00000000 20222222
09.615: mct_PlatformSpec: Done
09.615: ChangeMemClk: Done
09.615: phyAssistedMemFnceTraining: Start
09.615: phyAssistedMemFnceTraining: training node 1 DCT 0
09.615: phyAssistedMemFnceTraining: done training node 1 DCT 0
09.615: phyAssistedMemFnceTraining: training node 1 DCT 1
09.615: phyAssistedMemFnceTraining: done training node 1 DCT 1
09.615: phyAssistedMemFnceTraining: Done
09.615: InitPhyCompensation: DCT 0: Start
09.615: Waiting for predriver calibration to be applied...done!
09.615: InitPhyCompensation: DCT 0: Done
09.615: phyAssistedMemFnceTraining: Start
09.615: phyAssistedMemFnceTraining: training node 1 DCT 0
09.615: phyAssistedMemFnceTraining: done training node 1 DCT 0
09.615: phyAssistedMemFnceTraining: training node 1 DCT 1
09.615: phyAssistedMemFnceTraining: done training node 1 DCT 1
09.615: phyAssistedMemFnceTraining: Done
09.615: InitPhyCompensation: DCT 1: Start
09.615: Waiting for predriver calibration to be applied...done!
09.615: InitPhyCompensation: DCT 1: Done
09.616: Preparing to send DCT 0 DIMM 0 RC10: 00 (F2xA8: 02000300)
09.616: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.616: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
09.616: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.616: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
09.616: Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 02000c00)
09.616: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.616: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
09.616: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.616: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
09.616: Preparing to send DCT 1 DIMM 0 RC10: 00 (F2xA8: 02000300)
09.616: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.616: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
09.616: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.616: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
09.616: Preparing to send DCT 1 DIMM 1 RC10: 00 (F2xA8: 02000c00)
09.616: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.616: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
09.616: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.616: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
09.616: SetTargetFreq: Done
09.616: SPD2ndTiming: Start
09.617: SPD2ndTiming: Done
09.617: mct_BeforeDramInit_Prod_D: Start
09.617: mct_ProgramODT_D: Start
09.617: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
09.617: mct_ProgramODT_D: Done
09.617: mct_BeforeDramInit_Prod_D: Done
09.617: mct_DramInit_Sw_D: Start
09.617: DIMM 0 RttWr: 2
09.617: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.617: mct_SendMrsCmd: Start
09.617: mct_SendMrsCmd: Done
09.617: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
09.617: mct_SendMrsCmd: Start
09.617: mct_SendMrsCmd: Done
09.617: DIMM 0 RttNom: 3
09.617: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.617: mct_SendMrsCmd: Start
09.617: mct_SendMrsCmd: Done
09.617: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001578
09.617: mct_SendMrsCmd: Start
09.617: mct_SendMrsCmd: Done
09.617: DIMM 0 RttWr: 2
09.617: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.617: mct_SendMrsCmd: Start
09.617: mct_SendMrsCmd: Done
09.617: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
09.617: mct_SendMrsCmd: Start
09.617: mct_SendMrsCmd: Done
09.617: DIMM 0 RttNom: 3
09.617: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.617: mct_SendMrsCmd: Start
09.617: mct_SendMrsCmd: Done
09.617: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201578
09.617: mct_SendMrsCmd: Start
09.617: mct_SendMrsCmd: Done
09.617: DIMM 1 RttWr: 2
09.617: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.617: mct_SendMrsCmd: Start
09.617: mct_SendMrsCmd: Done
09.617: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
09.617: mct_SendMrsCmd: Start
09.617: mct_SendMrsCmd: Done
09.617: DIMM 1 RttNom: 3
09.617: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.617: mct_SendMrsCmd: Start
09.617: mct_SendMrsCmd: Done
09.617: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401578
09.617: mct_SendMrsCmd: Start
09.617: mct_SendMrsCmd: Done
09.617: DIMM 1 RttWr: 2
09.617: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.617: mct_SendMrsCmd: Start
09.617: mct_SendMrsCmd: Done
09.617: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
09.617: mct_SendMrsCmd: Start
09.617: mct_SendMrsCmd: Done
09.617: DIMM 1 RttNom: 3
09.617: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.617: mct_SendMrsCmd: Start
09.617: mct_SendMrsCmd: Done
09.617: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601578
09.617: mct_SendMrsCmd: Start
09.617: mct_SendMrsCmd: Done
09.617: mct_DramInit_Sw_D: Done
09.618: AgesaHwWlPhase1: training nibble 0
09.618: DIMM 0 RttNom: 3
09.618: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.618: DIMM 0 RttWr: 2
09.618: DIMM 0 RttWr: 2
09.618: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.618: DIMM 0 RttWr: 2
09.618: DIMM 0 RttNom: 3
09.618: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.618: DIMM 0 RttNom: 3
09.618: DIMM 0 RttWr: 2
09.618: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.618: DIMM 0 RttWr: 2
09.618: DIMM 1 RttNom: 3
09.618: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.618: DIMM 0 RttNom: 3
09.618: DIMM 1 RttWr: 2
09.618: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.618: DIMM 0 RttWr: 2
09.618: DIMM 1 RttNom: 3
09.618: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.618: DIMM 0 RttNom: 3
09.618: DIMM 1 RttWr: 2
09.618: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.618: DIMM 0 RttWr: 2
09.618: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.618: <09>Lane 00 scaled delay: 0047
09.618: <09>Lane 00 new seed: 0047
09.618: <09>Lane 01 scaled delay: 0047
09.618: <09>Lane 01 new seed: 0047
09.618: <09>Lane 02 scaled delay: 0047
09.618: <09>Lane 02 new seed: 0047
09.618: <09>Lane 03 scaled delay: 0047
09.618: <09>Lane 03 new seed: 0047
09.618: <09>Lane 04 scaled delay: 0047
09.618: <09>Lane 04 new seed: 0047
09.618: <09>Lane 05 scaled delay: 0047
09.618: <09>Lane 05 new seed: 0047
09.618: <09>Lane 06 scaled delay: 0047
09.618: <09>Lane 06 new seed: 0047
09.618: <09>Lane 07 scaled delay: 0047
09.619: <09>Lane 07 new seed: 0047
09.619: <09>Lane 08 scaled delay: 0047
09.619: <09>Lane 08 new seed: 0047
09.619: <09>Lane 00 nibble 0 raw readback: 003f
09.619: <09>Lane 00 nibble 0 adjusted value (pre nibble): 003f
09.619: <09>Lane 00 nibble 0 adjusted value (post nibble): 003f
09.619: <09>Lane 01 nibble 0 raw readback: 003c
09.619: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003c
09.619: <09>Lane 01 nibble 0 adjusted value (post nibble): 003c
09.619: <09>Lane 02 nibble 0 raw readback: 0038
09.619: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0038
09.619: <09>Lane 02 nibble 0 adjusted value (post nibble): 0038
09.619: <09>Lane 03 nibble 0 raw readback: 0036
09.619: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0036
09.619: <09>Lane 03 nibble 0 adjusted value (post nibble): 0036
09.619: <09>Lane 04 nibble 0 raw readback: 0034
09.619: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0034
09.619: <09>Lane 04 nibble 0 adjusted value (post nibble): 0034
09.619: <09>Lane 05 nibble 0 raw readback: 0036
09.619: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0036
09.619: <09>Lane 05 nibble 0 adjusted value (post nibble): 0036
09.619: <09>Lane 06 nibble 0 raw readback: 0039
09.619: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0039
09.619: <09>Lane 06 nibble 0 adjusted value (post nibble): 0039
09.619: <09>Lane 07 nibble 0 raw readback: 003d
09.619: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003d
09.619: <09>Lane 07 nibble 0 adjusted value (post nibble): 003d
09.619: <09>Lane 08 nibble 0 raw readback: 0031
09.619: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0031
09.619: <09>Lane 08 nibble 0 adjusted value (post nibble): 0031
09.619: AgesaHwWlPhase1: training nibble 1
09.619: DIMM 0 RttNom: 3
09.619: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.619: DIMM 0 RttWr: 2
09.619: DIMM 0 RttWr: 2
09.619: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.619: DIMM 0 RttWr: 2
09.619: DIMM 0 RttNom: 3
09.619: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.619: DIMM 0 RttNom: 3
09.619: DIMM 0 RttWr: 2
09.619: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.619: DIMM 0 RttWr: 2
09.619: DIMM 1 RttNom: 3
09.619: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.619: DIMM 0 RttNom: 3
09.619: DIMM 1 RttWr: 2
09.619: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.619: DIMM 0 RttWr: 2
09.619: DIMM 1 RttNom: 3
09.619: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.619: DIMM 0 RttNom: 3
09.619: DIMM 1 RttWr: 2
09.619: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.619: DIMM 0 RttWr: 2
09.619: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.619: <09>Lane 00 new seed: 0047
09.620: <09>Lane 01 new seed: 0047
09.620: <09>Lane 02 new seed: 0047
09.620: <09>Lane 03 new seed: 0047
09.620: <09>Lane 04 new seed: 0047
09.620: <09>Lane 05 new seed: 0047
09.620: <09>Lane 06 new seed: 0047
09.620: <09>Lane 07 new seed: 0047
09.620: <09>Lane 08 new seed: 0047
09.620: <09>Lane 00 nibble 1 raw readback: 003f
09.620: <09>Lane 00 nibble 1 adjusted value (pre nibble): 003f
09.620: <09>Lane 00 nibble 1 adjusted value (post nibble): 0043
09.620: <09>Lane 01 nibble 1 raw readback: 003c
09.620: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003c
09.620: <09>Lane 01 nibble 1 adjusted value (post nibble): 0041
09.620: <09>Lane 02 nibble 1 raw readback: 0038
09.620: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0038
09.620: <09>Lane 02 nibble 1 adjusted value (post nibble): 003f
09.620: <09>Lane 03 nibble 1 raw readback: 0037
09.620: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0037
09.620: <09>Lane 03 nibble 1 adjusted value (post nibble): 003f
09.620: <09>Lane 04 nibble 1 raw readback: 0032
09.620: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0032
09.620: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
09.620: <09>Lane 05 nibble 1 raw readback: 0036
09.620: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0036
09.620: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
09.620: <09>Lane 06 nibble 1 raw readback: 0039
09.620: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0039
09.620: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
09.620: <09>Lane 07 nibble 1 raw readback: 003d
09.620: <09>Lane 07 nibble 1 adjusted value (pre nibble): 003d
09.620: <09>Lane 07 nibble 1 adjusted value (post nibble): 0042
09.620: <09>Lane 08 nibble 1 raw readback: 0031
09.620: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0031
09.620: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
09.620: <09>original critical gross delay: 0
09.620: <09>new critical gross delay: 0
09.620: DIMM 0 RttNom: 3
09.620: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.620: DIMM 0 RttNom: 3
09.620: DIMM 0 RttWr: 2
09.620: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.620: DIMM 0 RttWr: 2
09.620: DIMM 0 RttNom: 3
09.620: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.620: DIMM 0 RttNom: 3
09.620: DIMM 0 RttWr: 2
09.620: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.620: DIMM 0 RttWr: 2
09.620: DIMM 1 RttNom: 3
09.620: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.620: DIMM 0 RttNom: 3
09.620: DIMM 1 RttWr: 2
09.620: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.620: DIMM 0 RttWr: 2
09.620: DIMM 1 RttNom: 3
09.620: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.620: DIMM 0 RttNom: 3
09.620: DIMM 1 RttWr: 2
09.620: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.620: DIMM 0 RttWr: 2
09.621: AgesaHwWlPhase1: training nibble 0
09.621: DIMM 1 RttNom: 3
09.621: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.621: DIMM 1 RttWr: 2
09.621: DIMM 1 RttWr: 2
09.621: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.621: DIMM 1 RttWr: 2
09.621: DIMM 1 RttNom: 3
09.621: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.621: DIMM 1 RttNom: 3
09.621: DIMM 1 RttWr: 2
09.621: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.621: DIMM 1 RttWr: 2
09.621: DIMM 0 RttNom: 3
09.621: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.621: DIMM 1 RttNom: 3
09.621: DIMM 0 RttWr: 2
09.621: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.621: DIMM 1 RttWr: 2
09.621: DIMM 0 RttNom: 3
09.621: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.621: DIMM 1 RttNom: 3
09.621: DIMM 0 RttWr: 2
09.621: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.621: DIMM 1 RttWr: 2
09.621: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.621: <09>Lane 00 scaled delay: 0047
09.621: <09>Lane 00 new seed: 0047
09.621: <09>Lane 01 scaled delay: 0047
09.621: <09>Lane 01 new seed: 0047
09.621: <09>Lane 02 scaled delay: 0047
09.621: <09>Lane 02 new seed: 0047
09.621: <09>Lane 03 scaled delay: 0047
09.621: <09>Lane 03 new seed: 0047
09.621: <09>Lane 04 scaled delay: 0047
09.621: <09>Lane 04 new seed: 0047
09.621: <09>Lane 05 scaled delay: 0047
09.621: <09>Lane 05 new seed: 0047
09.621: <09>Lane 06 scaled delay: 0047
09.621: <09>Lane 06 new seed: 0047
09.621: <09>Lane 07 scaled delay: 0047
09.621: <09>Lane 07 new seed: 0047
09.621: <09>Lane 08 scaled delay: 0047
09.621: <09>Lane 08 new seed: 0047
09.621: <09>Lane 00 nibble 0 raw readback: 0045
09.621: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0045
09.621: <09>Lane 00 nibble 0 adjusted value (post nibble): 0045
09.621: <09>Lane 01 nibble 0 raw readback: 0040
09.621: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0040
09.621: <09>Lane 01 nibble 0 adjusted value (post nibble): 0040
09.621: <09>Lane 02 nibble 0 raw readback: 003b
09.621: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003b
09.621: <09>Lane 02 nibble 0 adjusted value (post nibble): 003b
09.621: <09>Lane 03 nibble 0 raw readback: 003b
09.621: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
09.621: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
09.621: <09>Lane 04 nibble 0 raw readback: 0039
09.621: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
09.621: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
09.621: <09>Lane 05 nibble 0 raw readback: 003d
09.621: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
09.621: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
09.621: <09>Lane 06 nibble 0 raw readback: 003d
09.621: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003d
09.621: <09>Lane 06 nibble 0 adjusted value (post nibble): 003d
09.621: <09>Lane 07 nibble 0 raw readback: 0042
09.621: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0042
09.621: <09>Lane 07 nibble 0 adjusted value (post nibble): 0042
09.621: <09>Lane 08 nibble 0 raw readback: 0036
09.621: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
09.621: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
09.621: AgesaHwWlPhase1: training nibble 1
09.622: DIMM 1 RttNom: 3
09.622: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.622: DIMM 1 RttWr: 2
09.622: DIMM 1 RttWr: 2
09.622: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.622: DIMM 1 RttWr: 2
09.622: DIMM 1 RttNom: 3
09.622: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.622: DIMM 1 RttNom: 3
09.622: DIMM 1 RttWr: 2
09.622: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.622: DIMM 1 RttWr: 2
09.622: DIMM 0 RttNom: 3
09.622: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.622: DIMM 1 RttNom: 3
09.622: DIMM 0 RttWr: 2
09.622: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.622: DIMM 1 RttWr: 2
09.622: DIMM 0 RttNom: 3
09.622: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.622: DIMM 1 RttNom: 3
09.622: DIMM 0 RttWr: 2
09.622: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.622: DIMM 1 RttWr: 2
09.622: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.622: <09>Lane 00 new seed: 0047
09.622: <09>Lane 01 new seed: 0047
09.622: <09>Lane 02 new seed: 0047
09.622: <09>Lane 03 new seed: 0047
09.622: <09>Lane 04 new seed: 0047
09.622: <09>Lane 05 new seed: 0047
09.622: <09>Lane 06 new seed: 0047
09.622: <09>Lane 07 new seed: 0047
09.622: <09>Lane 08 new seed: 0047
09.622: <09>Lane 00 nibble 1 raw readback: 0045
09.622: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0045
09.622: <09>Lane 00 nibble 1 adjusted value (post nibble): 0046
09.622: <09>Lane 01 nibble 1 raw readback: 003f
09.622: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003f
09.622: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
09.622: <09>Lane 02 nibble 1 raw readback: 003c
09.622: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003c
09.622: <09>Lane 02 nibble 1 adjusted value (post nibble): 0041
09.622: <09>Lane 03 nibble 1 raw readback: 003b
09.622: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
09.622: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
09.622: <09>Lane 04 nibble 1 raw readback: 0037
09.622: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0037
09.622: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
09.622: <09>Lane 05 nibble 1 raw readback: 003b
09.622: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003b
09.622: <09>Lane 05 nibble 1 adjusted value (post nibble): 0041
09.622: <09>Lane 06 nibble 1 raw readback: 003e
09.622: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003e
09.622: <09>Lane 06 nibble 1 adjusted value (post nibble): 0042
09.622: <09>Lane 07 nibble 1 raw readback: 0041
09.622: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
09.622: <09>Lane 07 nibble 1 adjusted value (post nibble): 0044
09.622: <09>Lane 08 nibble 1 raw readback: 0037
09.622: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
09.622: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
09.622: <09>original critical gross delay: 0
09.622: <09>new critical gross delay: 0
09.623: DIMM 1 RttNom: 3
09.623: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.623: DIMM 1 RttNom: 3
09.623: DIMM 1 RttWr: 2
09.623: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.623: DIMM 1 RttWr: 2
09.623: DIMM 1 RttNom: 3
09.623: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.623: DIMM 1 RttNom: 3
09.623: DIMM 1 RttWr: 2
09.623: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.623: DIMM 1 RttWr: 2
09.623: DIMM 0 RttNom: 3
09.623: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.623: DIMM 1 RttNom: 3
09.623: DIMM 0 RttWr: 2
09.623: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.623: DIMM 1 RttWr: 2
09.623: DIMM 0 RttNom: 3
09.623: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.623: DIMM 1 RttNom: 3
09.623: DIMM 0 RttWr: 2
09.623: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.623: DIMM 1 RttWr: 2
09.623: SPD2ndTiming: Start
09.623: SPD2ndTiming: Done
09.623: mct_BeforeDramInit_Prod_D: Start
09.623: mct_ProgramODT_D: Start
09.623: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
09.623: mct_ProgramODT_D: Done
09.623: mct_BeforeDramInit_Prod_D: Done
09.623: mct_DramInit_Sw_D: Start
09.624: DIMM 0 RttWr: 2
09.624: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.624: mct_SendMrsCmd: Start
09.624: mct_SendMrsCmd: Done
09.624: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
09.624: mct_SendMrsCmd: Start
09.624: mct_SendMrsCmd: Done
09.624: DIMM 0 RttNom: 3
09.624: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.624: mct_SendMrsCmd: Start
09.624: mct_SendMrsCmd: Done
09.624: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001578
09.624: mct_SendMrsCmd: Start
09.624: mct_SendMrsCmd: Done
09.624: DIMM 0 RttWr: 2
09.624: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.624: mct_SendMrsCmd: Start
09.624: mct_SendMrsCmd: Done
09.624: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
09.624: mct_SendMrsCmd: Start
09.624: mct_SendMrsCmd: Done
09.624: DIMM 0 RttNom: 3
09.624: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.624: mct_SendMrsCmd: Start
09.624: mct_SendMrsCmd: Done
09.624: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201578
09.624: mct_SendMrsCmd: Start
09.624: mct_SendMrsCmd: Done
09.624: DIMM 1 RttWr: 2
09.624: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.624: mct_SendMrsCmd: Start
09.624: mct_SendMrsCmd: Done
09.624: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
09.624: mct_SendMrsCmd: Start
09.624: mct_SendMrsCmd: Done
09.624: DIMM 1 RttNom: 3
09.624: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.624: mct_SendMrsCmd: Start
09.624: mct_SendMrsCmd: Done
09.624: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401578
09.624: mct_SendMrsCmd: Start
09.624: mct_SendMrsCmd: Done
09.624: DIMM 1 RttWr: 2
09.624: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.624: mct_SendMrsCmd: Start
09.624: mct_SendMrsCmd: Done
09.624: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
09.624: mct_SendMrsCmd: Start
09.624: mct_SendMrsCmd: Done
09.624: DIMM 1 RttNom: 3
09.624: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.624: mct_SendMrsCmd: Start
09.624: mct_SendMrsCmd: Done
09.624: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601578
09.624: mct_SendMrsCmd: Start
09.624: mct_SendMrsCmd: Done
09.624: mct_DramInit_Sw_D: Done
09.624: AgesaHwWlPhase1: training nibble 0
09.624: DIMM 0 RttNom: 3
09.624: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.624: DIMM 0 RttWr: 2
09.624: DIMM 0 RttWr: 2
09.624: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.624: DIMM 0 RttWr: 2
09.624: DIMM 0 RttNom: 3
09.624: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.624: DIMM 0 RttNom: 3
09.624: DIMM 0 RttWr: 2
09.624: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.624: DIMM 0 RttWr: 2
09.625: DIMM 1 RttNom: 3
09.625: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.625: DIMM 0 RttNom: 3
09.625: DIMM 1 RttWr: 2
09.625: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.625: DIMM 0 RttWr: 2
09.625: DIMM 1 RttNom: 3
09.625: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.625: DIMM 0 RttNom: 3
09.625: DIMM 1 RttWr: 2
09.625: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.625: DIMM 0 RttWr: 2
09.625: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.625: <09>Lane 00 scaled delay: 0047
09.625: <09>Lane 00 new seed: 0047
09.625: <09>Lane 01 scaled delay: 0047
09.625: <09>Lane 01 new seed: 0047
09.625: <09>Lane 02 scaled delay: 0047
09.625: <09>Lane 02 new seed: 0047
09.625: <09>Lane 03 scaled delay: 0047
09.625: <09>Lane 03 new seed: 0047
09.625: <09>Lane 04 scaled delay: 0047
09.625: <09>Lane 04 new seed: 0047
09.625: <09>Lane 05 scaled delay: 0047
09.625: <09>Lane 05 new seed: 0047
09.625: <09>Lane 06 scaled delay: 0047
09.625: <09>Lane 06 new seed: 0047
09.625: <09>Lane 07 scaled delay: 0047
09.625: <09>Lane 07 new seed: 0047
09.625: <09>Lane 08 scaled delay: 0047
09.625: <09>Lane 08 new seed: 0047
09.625: <09>Lane 00 nibble 0 raw readback: 0041
09.625: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0041
09.625: <09>Lane 00 nibble 0 adjusted value (post nibble): 0041
09.625: <09>Lane 01 nibble 0 raw readback: 003d
09.625: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003d
09.625: <09>Lane 01 nibble 0 adjusted value (post nibble): 003d
09.625: <09>Lane 02 nibble 0 raw readback: 0039
09.625: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0039
09.625: <09>Lane 02 nibble 0 adjusted value (post nibble): 0039
09.625: <09>Lane 03 nibble 0 raw readback: 0036
09.625: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0036
09.625: <09>Lane 03 nibble 0 adjusted value (post nibble): 0036
09.625: <09>Lane 04 nibble 0 raw readback: 0034
09.625: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0034
09.625: <09>Lane 04 nibble 0 adjusted value (post nibble): 0034
09.625: <09>Lane 05 nibble 0 raw readback: 0038
09.625: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0038
09.625: <09>Lane 05 nibble 0 adjusted value (post nibble): 0038
09.625: <09>Lane 06 nibble 0 raw readback: 003a
09.625: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003a
09.625: <09>Lane 06 nibble 0 adjusted value (post nibble): 003a
09.625: <09>Lane 07 nibble 0 raw readback: 003f
09.625: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003f
09.625: <09>Lane 07 nibble 0 adjusted value (post nibble): 003f
09.625: <09>Lane 08 nibble 0 raw readback: 0032
09.625: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0032
09.625: <09>Lane 08 nibble 0 adjusted value (post nibble): 0032
09.625: AgesaHwWlPhase1: training nibble 1
09.625: DIMM 0 RttNom: 3
09.625: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.625: DIMM 0 RttWr: 2
09.626: DIMM 0 RttWr: 2
09.626: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.626: DIMM 0 RttWr: 2
09.626: DIMM 0 RttNom: 3
09.626: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.626: DIMM 0 RttNom: 3
09.626: DIMM 0 RttWr: 2
09.626: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.626: DIMM 0 RttWr: 2
09.626: DIMM 1 RttNom: 3
09.626: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.626: DIMM 0 RttNom: 3
09.626: DIMM 1 RttWr: 2
09.626: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.626: DIMM 0 RttWr: 2
09.626: DIMM 1 RttNom: 3
09.626: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.626: DIMM 0 RttNom: 3
09.626: DIMM 1 RttWr: 2
09.626: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.626: DIMM 0 RttWr: 2
09.626: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.626: <09>Lane 00 new seed: 0047
09.626: <09>Lane 01 new seed: 0047
09.626: <09>Lane 02 new seed: 0047
09.626: <09>Lane 03 new seed: 0047
09.626: <09>Lane 04 new seed: 0047
09.626: <09>Lane 05 new seed: 0047
09.626: <09>Lane 06 new seed: 0047
09.626: <09>Lane 07 new seed: 0047
09.626: <09>Lane 08 new seed: 0047
09.626: <09>Lane 00 nibble 1 raw readback: 0041
09.626: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0041
09.626: <09>Lane 00 nibble 1 adjusted value (post nibble): 0044
09.626: <09>Lane 01 nibble 1 raw readback: 003d
09.626: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003d
09.626: <09>Lane 01 nibble 1 adjusted value (post nibble): 0042
09.626: <09>Lane 02 nibble 1 raw readback: 0039
09.626: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0039
09.626: <09>Lane 02 nibble 1 adjusted value (post nibble): 0040
09.626: <09>Lane 03 nibble 1 raw readback: 0036
09.626: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0036
09.626: <09>Lane 03 nibble 1 adjusted value (post nibble): 003e
09.626: <09>Lane 04 nibble 1 raw readback: 0033
09.626: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0033
09.626: <09>Lane 04 nibble 1 adjusted value (post nibble): 003d
09.626: <09>Lane 05 nibble 1 raw readback: 0038
09.626: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0038
09.626: <09>Lane 05 nibble 1 adjusted value (post nibble): 003f
09.626: <09>Lane 06 nibble 1 raw readback: 003b
09.626: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003b
09.626: <09>Lane 06 nibble 1 adjusted value (post nibble): 0041
09.626: <09>Lane 07 nibble 1 raw readback: 003f
09.626: <09>Lane 07 nibble 1 adjusted value (pre nibble): 003f
09.626: <09>Lane 07 nibble 1 adjusted value (post nibble): 0043
09.626: <09>Lane 08 nibble 1 raw readback: 0031
09.626: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0031
09.626: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
09.626: <09>original critical gross delay: 0
09.626: <09>new critical gross delay: 0
09.626: DIMM 0 RttNom: 3
09.627: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.627: DIMM 0 RttNom: 3
09.627: DIMM 0 RttWr: 2
09.627: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.627: DIMM 0 RttWr: 2
09.627: DIMM 0 RttNom: 3
09.627: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.627: DIMM 0 RttNom: 3
09.627: DIMM 0 RttWr: 2
09.627: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.627: DIMM 0 RttWr: 2
09.627: DIMM 1 RttNom: 3
09.627: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.627: DIMM 0 RttNom: 3
09.627: DIMM 1 RttWr: 2
09.627: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.627: DIMM 0 RttWr: 2
09.627: DIMM 1 RttNom: 3
09.627: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.627: DIMM 0 RttNom: 3
09.627: DIMM 1 RttWr: 2
09.627: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.627: DIMM 0 RttWr: 2
09.627: AgesaHwWlPhase1: training nibble 0
09.627: DIMM 1 RttNom: 3
09.627: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.627: DIMM 1 RttWr: 2
09.627: DIMM 1 RttWr: 2
09.627: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.627: DIMM 1 RttWr: 2
09.627: DIMM 1 RttNom: 3
09.627: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.627: DIMM 1 RttNom: 3
09.627: DIMM 1 RttWr: 2
09.627: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.627: DIMM 1 RttWr: 2
09.627: DIMM 0 RttNom: 3
09.627: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.627: DIMM 1 RttNom: 3
09.627: DIMM 0 RttWr: 2
09.627: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.627: DIMM 1 RttWr: 2
09.627: DIMM 0 RttNom: 3
09.627: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.627: DIMM 1 RttNom: 3
09.627: DIMM 0 RttWr: 2
09.627: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.627: DIMM 1 RttWr: 2
09.627: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.627: <09>Lane 00 scaled delay: 0047
09.627: <09>Lane 00 new seed: 0047
09.627: <09>Lane 01 scaled delay: 0047
09.627: <09>Lane 01 new seed: 0047
09.627: <09>Lane 02 scaled delay: 0047
09.627: <09>Lane 02 new seed: 0047
09.627: <09>Lane 03 scaled delay: 0047
09.627: <09>Lane 03 new seed: 0047
09.627: <09>Lane 04 scaled delay: 0047
09.627: <09>Lane 04 new seed: 0047
09.627: <09>Lane 05 scaled delay: 0047
09.627: <09>Lane 05 new seed: 0047
09.627: <09>Lane 06 scaled delay: 0047
09.627: <09>Lane 06 new seed: 0047
09.627: <09>Lane 07 scaled delay: 0047
09.627: <09>Lane 07 new seed: 0047
09.628: <09>Lane 08 scaled delay: 0047
09.628: <09>Lane 08 new seed: 0047
09.628: <09>Lane 00 nibble 0 raw readback: 0044
09.628: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0044
09.628: <09>Lane 00 nibble 0 adjusted value (post nibble): 0044
09.628: <09>Lane 01 nibble 0 raw readback: 0042
09.628: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0042
09.628: <09>Lane 01 nibble 0 adjusted value (post nibble): 0042
09.628: <09>Lane 02 nibble 0 raw readback: 003e
09.628: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003e
09.628: <09>Lane 02 nibble 0 adjusted value (post nibble): 003e
09.628: <09>Lane 03 nibble 0 raw readback: 003a
09.628: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003a
09.628: <09>Lane 03 nibble 0 adjusted value (post nibble): 003a
09.628: <09>Lane 04 nibble 0 raw readback: 0039
09.628: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
09.628: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
09.628: <09>Lane 05 nibble 0 raw readback: 003c
09.628: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003c
09.628: <09>Lane 05 nibble 0 adjusted value (post nibble): 003c
09.628: <09>Lane 06 nibble 0 raw readback: 0040
09.628: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
09.628: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
09.628: <09>Lane 07 nibble 0 raw readback: 0043
09.628: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0043
09.628: <09>Lane 07 nibble 0 adjusted value (post nibble): 0043
09.628: <09>Lane 08 nibble 0 raw readback: 0036
09.628: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
09.628: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
09.628: AgesaHwWlPhase1: training nibble 1
09.628: DIMM 1 RttNom: 3
09.628: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.628: DIMM 1 RttWr: 2
09.628: DIMM 1 RttWr: 2
09.628: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.628: DIMM 1 RttWr: 2
09.628: DIMM 1 RttNom: 3
09.628: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.628: DIMM 1 RttNom: 3
09.628: DIMM 1 RttWr: 2
09.628: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.628: DIMM 1 RttWr: 2
09.628: DIMM 0 RttNom: 3
09.628: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.628: DIMM 1 RttNom: 3
09.628: DIMM 0 RttWr: 2
09.628: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.628: DIMM 1 RttWr: 2
09.628: DIMM 0 RttNom: 3
09.628: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.628: DIMM 1 RttNom: 3
09.628: DIMM 0 RttWr: 2
09.628: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.628: DIMM 1 RttWr: 2
09.628: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.628: <09>Lane 00 new seed: 0047
09.628: <09>Lane 01 new seed: 0047
09.628: <09>Lane 02 new seed: 0047
09.628: <09>Lane 03 new seed: 0047
09.628: <09>Lane 04 new seed: 0047
09.628: <09>Lane 05 new seed: 0047
09.628: <09>Lane 06 new seed: 0047
09.628: <09>Lane 07 new seed: 0047
09.628: <09>Lane 08 new seed: 0047
09.628: <09>Lane 00 nibble 1 raw readback: 0047
09.628: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0047
09.628: <09>Lane 00 nibble 1 adjusted value (post nibble): 0047
09.628: <09>Lane 01 nibble 1 raw readback: 0042
09.628: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0042
09.628: <09>Lane 01 nibble 1 adjusted value (post nibble): 0044
09.628: <09>Lane 02 nibble 1 raw readback: 003e
09.628: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003e
09.628: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
09.629: <09>Lane 03 nibble 1 raw readback: 003b
09.629: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
09.629: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
09.629: <09>Lane 04 nibble 1 raw readback: 0038
09.629: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
09.629: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
09.629: <09>Lane 05 nibble 1 raw readback: 003b
09.629: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003b
09.629: <09>Lane 05 nibble 1 adjusted value (post nibble): 0041
09.629: <09>Lane 06 nibble 1 raw readback: 003f
09.629: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
09.629: <09>Lane 06 nibble 1 adjusted value (post nibble): 0043
09.629: <09>Lane 07 nibble 1 raw readback: 0045
09.629: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0045
09.629: <09>Lane 07 nibble 1 adjusted value (post nibble): 0046
09.629: <09>Lane 08 nibble 1 raw readback: 0037
09.629: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
09.629: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
09.629: <09>original critical gross delay: 0
09.629: <09>new critical gross delay: 0
09.629: DIMM 1 RttNom: 3
09.629: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.629: DIMM 1 RttNom: 3
09.629: DIMM 1 RttWr: 2
09.629: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.629: DIMM 1 RttWr: 2
09.629: DIMM 1 RttNom: 3
09.629: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.629: DIMM 1 RttNom: 3
09.629: DIMM 1 RttWr: 2
09.629: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.629: DIMM 1 RttWr: 2
09.629: DIMM 0 RttNom: 3
09.629: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.629: DIMM 1 RttNom: 3
09.629: DIMM 0 RttWr: 2
09.629: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.629: DIMM 1 RttWr: 2
09.629: DIMM 0 RttNom: 3
09.629: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.629: DIMM 1 RttNom: 3
09.629: DIMM 0 RttWr: 2
09.629: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.629: DIMM 1 RttWr: 2
09.629: SetTargetFreq: Start
09.629: SetTargetFreq: Node 1: New frequency code: 000a
09.629: ChangeMemClk: Start
09.630: set_2t_configuration: Start
09.630: set_2t_configuration: Done
09.630: mct_BeforePlatformSpec: Start
09.630: mct_BeforePlatformSpec: Done
09.630: mct_PlatformSpec: Start
09.630: Programmed DCT 0 timing/termination pattern 003a3c3a 30222222
09.630: mct_PlatformSpec: Done
09.630: set_2t_configuration: Start
09.630: set_2t_configuration: Done
09.630: mct_BeforePlatformSpec: Start
09.630: mct_BeforePlatformSpec: Done
09.630: mct_PlatformSpec: Start
09.630: Programmed DCT 1 timing/termination pattern 003a3c3a 30222222
09.630: mct_PlatformSpec: Done
09.630: ChangeMemClk: Done
09.630: phyAssistedMemFnceTraining: Start
09.630: phyAssistedMemFnceTraining: training node 1 DCT 0
09.630: phyAssistedMemFnceTraining: done training node 1 DCT 0
09.630: phyAssistedMemFnceTraining: training node 1 DCT 1
09.630: phyAssistedMemFnceTraining: done training node 1 DCT 1
09.630: phyAssistedMemFnceTraining: Done
09.630: InitPhyCompensation: DCT 0: Start
09.630: Waiting for predriver calibration to be applied...done!
09.630: InitPhyCompensation: DCT 0: Done
09.630: phyAssistedMemFnceTraining: Start
09.630: phyAssistedMemFnceTraining: training node 1 DCT 0
09.630: phyAssistedMemFnceTraining: done training node 1 DCT 0
09.630: phyAssistedMemFnceTraining: training node 1 DCT 1
09.631: phyAssistedMemFnceTraining: done training node 1 DCT 1
09.631: phyAssistedMemFnceTraining: Done
09.631: InitPhyCompensation: DCT 1: Start
09.631: Waiting for predriver calibration to be applied...done!
09.631: InitPhyCompensation: DCT 1: Done
09.631: Preparing to send DCT 0 DIMM 0 RC10: 01 (F2xA8: 02000300)
09.631: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.631: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
09.631: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.631: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
09.631: Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 02000c00)
09.631: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.631: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
09.631: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.631: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
09.631: Preparing to send DCT 1 DIMM 0 RC10: 01 (F2xA8: 02000300)
09.631: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.631: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
09.631: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.631: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
09.631: Preparing to send DCT 1 DIMM 1 RC10: 01 (F2xA8: 02000c00)
09.631: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.631: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
09.631: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.631: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
09.631: SetTargetFreq: Done
09.631: SPD2ndTiming: Start
09.632: SPD2ndTiming: Done
09.632: mct_BeforeDramInit_Prod_D: Start
09.632: mct_ProgramODT_D: Start
09.632: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
09.632: mct_ProgramODT_D: Done
09.632: mct_BeforeDramInit_Prod_D: Done
09.632: mct_DramInit_Sw_D: Start
09.632: DIMM 0 RttWr: 1
09.632: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.632: mct_SendMrsCmd: Start
09.632: mct_SendMrsCmd: Done
09.632: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
09.632: mct_SendMrsCmd: Start
09.632: mct_SendMrsCmd: Done
09.632: DIMM 0 RttNom: 3
09.632: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.632: mct_SendMrsCmd: Start
09.632: mct_SendMrsCmd: Done
09.632: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001978
09.632: mct_SendMrsCmd: Start
09.632: mct_SendMrsCmd: Done
09.632: DIMM 0 RttWr: 1
09.632: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.632: mct_SendMrsCmd: Start
09.632: mct_SendMrsCmd: Done
09.632: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
09.632: mct_SendMrsCmd: Start
09.632: mct_SendMrsCmd: Done
09.632: DIMM 0 RttNom: 3
09.632: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.632: mct_SendMrsCmd: Start
09.632: mct_SendMrsCmd: Done
09.632: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201978
09.632: mct_SendMrsCmd: Start
09.632: mct_SendMrsCmd: Done
09.632: DIMM 1 RttWr: 1
09.632: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.632: mct_SendMrsCmd: Start
09.632: mct_SendMrsCmd: Done
09.632: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
09.632: mct_SendMrsCmd: Start
09.632: mct_SendMrsCmd: Done
09.632: DIMM 1 RttNom: 3
09.632: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.632: mct_SendMrsCmd: Start
09.632: mct_SendMrsCmd: Done
09.632: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401978
09.632: mct_SendMrsCmd: Start
09.632: mct_SendMrsCmd: Done
09.632: DIMM 1 RttWr: 1
09.632: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.633: mct_SendMrsCmd: Start
09.632: mct_SendMrsCmd: Done
09.632: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
09.632: mct_SendMrsCmd: Start
09.633: mct_SendMrsCmd: Done
09.633: DIMM 1 RttNom: 3
09.633: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.633: mct_SendMrsCmd: Start
09.633: mct_SendMrsCmd: Done
09.633: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601978
09.633: mct_SendMrsCmd: Start
09.633: mct_SendMrsCmd: Done
09.633: mct_DramInit_Sw_D: Done
09.633: AgesaHwWlPhase1: training nibble 0
09.633: DIMM 0 RttNom: 3
09.633: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.633: DIMM 0 RttWr: 1
09.633: DIMM 0 RttWr: 1
09.633: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.633: DIMM 0 RttWr: 1
09.633: DIMM 0 RttNom: 3
09.633: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.633: DIMM 0 RttNom: 3
09.633: DIMM 0 RttWr: 1
09.633: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.633: DIMM 0 RttWr: 1
09.633: DIMM 1 RttNom: 3
09.633: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.633: DIMM 0 RttNom: 3
09.633: DIMM 1 RttWr: 1
09.633: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.633: DIMM 0 RttWr: 1
09.633: DIMM 1 RttNom: 3
09.633: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.633: DIMM 0 RttNom: 3
09.633: DIMM 1 RttWr: 1
09.633: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.633: DIMM 0 RttWr: 1
09.633: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.633: <09>Lane 00 scaled delay: 004e
09.633: <09>Lane 00 new seed: 004e
09.633: <09>Lane 01 scaled delay: 004b
09.633: <09>Lane 01 new seed: 004b
09.633: <09>Lane 02 scaled delay: 0049
09.633: <09>Lane 02 new seed: 0049
09.634: <09>Lane 03 scaled delay: 0049
09.634: <09>Lane 03 new seed: 0049
09.634: <09>Lane 04 scaled delay: 0045
09.634: <09>Lane 04 new seed: 0045
09.634: <09>Lane 05 scaled delay: 0047
09.634: <09>Lane 05 new seed: 0047
09.634: <09>Lane 06 scaled delay: 004a
09.634: <09>Lane 06 new seed: 004a
09.634: <09>Lane 07 scaled delay: 004d
09.634: <09>Lane 07 new seed: 004d
09.634: <09>Lane 08 scaled delay: 0045
09.634: <09>Lane 08 new seed: 0045
09.634: <09>Lane 00 nibble 0 raw readback: 0049
09.634: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0049
09.634: <09>Lane 00 nibble 0 adjusted value (post nibble): 0049
09.634: <09>Lane 01 nibble 0 raw readback: 0043
09.634: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0043
09.634: <09>Lane 01 nibble 0 adjusted value (post nibble): 0043
09.634: <09>Lane 02 nibble 0 raw readback: 0040
09.634: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0040
09.634: <09>Lane 02 nibble 0 adjusted value (post nibble): 0040
09.634: <09>Lane 03 nibble 0 raw readback: 003d
09.634: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003d
09.634: <09>Lane 03 nibble 0 adjusted value (post nibble): 003d
09.634: <09>Lane 04 nibble 0 raw readback: 003a
09.634: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
09.634: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
09.634: <09>Lane 05 nibble 0 raw readback: 003e
09.634: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003e
09.634: <09>Lane 05 nibble 0 adjusted value (post nibble): 003e
09.634: <09>Lane 06 nibble 0 raw readback: 0041
09.634: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0041
09.634: <09>Lane 06 nibble 0 adjusted value (post nibble): 0041
09.634: <09>Lane 07 nibble 0 raw readback: 0046
09.634: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0046
09.634: <09>Lane 07 nibble 0 adjusted value (post nibble): 0046
09.634: <09>Lane 08 nibble 0 raw readback: 0037
09.634: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0037
09.634: <09>Lane 08 nibble 0 adjusted value (post nibble): 0037
09.634: AgesaHwWlPhase1: training nibble 1
09.634: DIMM 0 RttNom: 3
09.634: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.634: DIMM 0 RttWr: 1
09.634: DIMM 0 RttWr: 1
09.634: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.634: DIMM 0 RttWr: 1
09.634: DIMM 0 RttNom: 3
09.634: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.634: DIMM 0 RttNom: 3
09.634: DIMM 0 RttWr: 1
09.634: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.634: DIMM 0 RttWr: 1
09.634: DIMM 1 RttNom: 3
09.634: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.634: DIMM 0 RttNom: 3
09.634: DIMM 1 RttWr: 1
09.634: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.634: DIMM 0 RttWr: 1
09.634: DIMM 1 RttNom: 3
09.634: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.634: DIMM 0 RttNom: 3
09.634: DIMM 1 RttWr: 1
09.634: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.634: DIMM 0 RttWr: 1
09.635: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.635: <09>Lane 00 new seed: 004e
09.635: <09>Lane 01 new seed: 004b
09.635: <09>Lane 02 new seed: 0049
09.635: <09>Lane 03 new seed: 0049
09.635: <09>Lane 04 new seed: 0045
09.635: <09>Lane 05 new seed: 0047
09.635: <09>Lane 06 new seed: 004a
09.635: <09>Lane 07 new seed: 004d
09.635: <09>Lane 08 new seed: 0045
09.635: <09>Lane 00 nibble 1 raw readback: 0049
09.635: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0049
09.635: <09>Lane 00 nibble 1 adjusted value (post nibble): 004b
09.635: <09>Lane 01 nibble 1 raw readback: 0044
09.635: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0044
09.635: <09>Lane 01 nibble 1 adjusted value (post nibble): 0047
09.635: <09>Lane 02 nibble 1 raw readback: 0040
09.635: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0040
09.635: <09>Lane 02 nibble 1 adjusted value (post nibble): 0044
09.635: <09>Lane 03 nibble 1 raw readback: 003f
09.635: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003f
09.635: <09>Lane 03 nibble 1 adjusted value (post nibble): 0044
09.635: <09>Lane 04 nibble 1 raw readback: 0039
09.635: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
09.635: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
09.635: <09>Lane 05 nibble 1 raw readback: 003f
09.635: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003f
09.635: <09>Lane 05 nibble 1 adjusted value (post nibble): 0043
09.635: <09>Lane 06 nibble 1 raw readback: 0041
09.635: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0041
09.635: <09>Lane 06 nibble 1 adjusted value (post nibble): 0045
09.635: <09>Lane 07 nibble 1 raw readback: 0046
09.635: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0046
09.635: <09>Lane 07 nibble 1 adjusted value (post nibble): 0049
09.635: <09>Lane 08 nibble 1 raw readback: 0037
09.635: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
09.635: <09>Lane 08 nibble 1 adjusted value (post nibble): 003e
09.635: <09>original critical gross delay: 0
09.635: <09>new critical gross delay: 0
09.635: DIMM 0 RttNom: 3
09.635: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.635: DIMM 0 RttNom: 3
09.635: DIMM 0 RttWr: 1
09.635: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.635: DIMM 0 RttWr: 1
09.635: DIMM 0 RttNom: 3
09.635: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.635: DIMM 0 RttNom: 3
09.635: DIMM 0 RttWr: 1
09.635: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.635: DIMM 0 RttWr: 1
09.635: DIMM 1 RttNom: 3
09.635: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.635: DIMM 0 RttNom: 3
09.635: DIMM 1 RttWr: 1
09.635: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.635: DIMM 0 RttWr: 1
09.635: DIMM 1 RttNom: 3
09.635: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.635: DIMM 0 RttNom: 3
09.635: DIMM 1 RttWr: 1
09.635: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.635: DIMM 0 RttWr: 1
09.636: AgesaHwWlPhase1: training nibble 0
09.636: DIMM 1 RttNom: 3
09.636: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.636: DIMM 1 RttWr: 1
09.636: DIMM 1 RttWr: 1
09.636: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.636: DIMM 1 RttWr: 1
09.636: DIMM 1 RttNom: 3
09.636: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.636: DIMM 1 RttNom: 3
09.636: DIMM 1 RttWr: 1
09.636: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.636: DIMM 1 RttWr: 1
09.636: DIMM 0 RttNom: 3
09.636: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.636: DIMM 1 RttNom: 3
09.636: DIMM 0 RttWr: 1
09.636: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.636: DIMM 1 RttWr: 1
09.636: DIMM 0 RttNom: 3
09.636: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.636: DIMM 1 RttNom: 3
09.636: DIMM 0 RttWr: 1
09.636: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.636: DIMM 1 RttWr: 1
09.636: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.636: <09>Lane 00 scaled delay: 0052
09.636: <09>Lane 00 new seed: 0052
09.636: <09>Lane 01 scaled delay: 004e
09.636: <09>Lane 01 new seed: 004e
09.636: <09>Lane 02 scaled delay: 004b
09.636: <09>Lane 02 new seed: 004b
09.636: <09>Lane 03 scaled delay: 004b
09.636: <09>Lane 03 new seed: 004b
09.636: <09>Lane 04 scaled delay: 0049
09.636: <09>Lane 04 new seed: 0049
09.636: <09>Lane 05 scaled delay: 004b
09.636: <09>Lane 05 new seed: 004b
09.636: <09>Lane 06 scaled delay: 004d
09.636: <09>Lane 06 new seed: 004d
09.636: <09>Lane 07 scaled delay: 004f
09.636: <09>Lane 07 new seed: 004f
09.636: <09>Lane 08 scaled delay: 0049
09.636: <09>Lane 08 new seed: 0049
09.636: <09>Lane 00 nibble 0 raw readback: 0051
09.636: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0051
09.636: <09>Lane 00 nibble 0 adjusted value (post nibble): 0051
09.636: <09>Lane 01 nibble 0 raw readback: 004a
09.636: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004a
09.636: <09>Lane 01 nibble 0 adjusted value (post nibble): 004a
09.636: <09>Lane 02 nibble 0 raw readback: 0046
09.636: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0046
09.636: <09>Lane 02 nibble 0 adjusted value (post nibble): 0046
09.636: <09>Lane 03 nibble 0 raw readback: 0045
09.636: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0045
09.636: <09>Lane 03 nibble 0 adjusted value (post nibble): 0045
09.636: <09>Lane 04 nibble 0 raw readback: 0042
09.636: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0042
09.636: <09>Lane 04 nibble 0 adjusted value (post nibble): 0042
09.636: <09>Lane 05 nibble 0 raw readback: 0047
09.636: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0047
09.636: <09>Lane 05 nibble 0 adjusted value (post nibble): 0047
09.636: <09>Lane 06 nibble 0 raw readback: 0048
09.636: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0048
09.636: <09>Lane 06 nibble 0 adjusted value (post nibble): 0048
09.636: <09>Lane 07 nibble 0 raw readback: 004e
09.636: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004e
09.636: <09>Lane 07 nibble 0 adjusted value (post nibble): 004e
09.636: <09>Lane 08 nibble 0 raw readback: 003e
09.636: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003e
09.636: <09>Lane 08 nibble 0 adjusted value (post nibble): 003e
09.636: AgesaHwWlPhase1: training nibble 1
09.637: DIMM 1 RttNom: 3
09.637: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.637: DIMM 1 RttWr: 1
09.637: DIMM 1 RttWr: 1
09.637: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.637: DIMM 1 RttWr: 1
09.637: DIMM 1 RttNom: 3
09.637: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.637: DIMM 1 RttNom: 3
09.637: DIMM 1 RttWr: 1
09.637: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.637: DIMM 1 RttWr: 1
09.637: DIMM 0 RttNom: 3
09.637: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.637: DIMM 1 RttNom: 3
09.637: DIMM 0 RttWr: 1
09.637: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.637: DIMM 1 RttWr: 1
09.637: DIMM 0 RttNom: 3
09.637: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.637: DIMM 1 RttNom: 3
09.637: DIMM 0 RttWr: 1
09.637: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.637: DIMM 1 RttWr: 1
09.637: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.637: <09>Lane 00 new seed: 0052
09.637: <09>Lane 01 new seed: 004e
09.637: <09>Lane 02 new seed: 004b
09.637: <09>Lane 03 new seed: 004b
09.637: <09>Lane 04 new seed: 0049
09.637: <09>Lane 05 new seed: 004b
09.637: <09>Lane 06 new seed: 004d
09.637: <09>Lane 07 new seed: 004f
09.637: <09>Lane 08 new seed: 0049
09.637: <09>Lane 00 nibble 1 raw readback: 0051
09.637: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0051
09.637: <09>Lane 00 nibble 1 adjusted value (post nibble): 0051
09.637: <09>Lane 01 nibble 1 raw readback: 004b
09.637: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004b
09.637: <09>Lane 01 nibble 1 adjusted value (post nibble): 004c
09.637: <09>Lane 02 nibble 1 raw readback: 0047
09.637: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0047
09.637: <09>Lane 02 nibble 1 adjusted value (post nibble): 0049
09.637: <09>Lane 03 nibble 1 raw readback: 0045
09.637: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
09.637: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
09.637: <09>Lane 04 nibble 1 raw readback: 0040
09.637: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0040
09.637: <09>Lane 04 nibble 1 adjusted value (post nibble): 0044
09.637: <09>Lane 05 nibble 1 raw readback: 0046
09.637: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0046
09.637: <09>Lane 05 nibble 1 adjusted value (post nibble): 0048
09.637: <09>Lane 06 nibble 1 raw readback: 0049
09.637: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0049
09.637: <09>Lane 06 nibble 1 adjusted value (post nibble): 004b
09.637: <09>Lane 07 nibble 1 raw readback: 004e
09.637: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004e
09.637: <09>Lane 07 nibble 1 adjusted value (post nibble): 004e
09.637: <09>Lane 08 nibble 1 raw readback: 0040
09.637: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0040
09.637: <09>Lane 08 nibble 1 adjusted value (post nibble): 0044
09.637: <09>original critical gross delay: 0
09.637: <09>new critical gross delay: 0
09.637: DIMM 1 RttNom: 3
09.638: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.638: DIMM 1 RttNom: 3
09.638: DIMM 1 RttWr: 1
09.638: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.638: DIMM 1 RttWr: 1
09.638: DIMM 1 RttNom: 3
09.638: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.638: DIMM 1 RttNom: 3
09.638: DIMM 1 RttWr: 1
09.638: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.638: DIMM 1 RttWr: 1
09.638: DIMM 0 RttNom: 3
09.638: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.638: DIMM 1 RttNom: 3
09.638: DIMM 0 RttWr: 1
09.638: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.638: DIMM 1 RttWr: 1
09.638: DIMM 0 RttNom: 3
09.638: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.638: DIMM 1 RttNom: 3
09.638: DIMM 0 RttWr: 1
09.638: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.638: DIMM 1 RttWr: 1
09.638: SPD2ndTiming: Start
09.638: SPD2ndTiming: Done
09.638: mct_BeforeDramInit_Prod_D: Start
09.638: mct_ProgramODT_D: Start
09.638: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
09.638: mct_ProgramODT_D: Done
09.638: mct_BeforeDramInit_Prod_D: Done
09.638: mct_DramInit_Sw_D: Start
09.638: DIMM 0 RttWr: 1
09.638: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.639: mct_SendMrsCmd: Start
09.639: mct_SendMrsCmd: Done
09.639: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
09.639: mct_SendMrsCmd: Start
09.639: mct_SendMrsCmd: Done
09.639: DIMM 0 RttNom: 3
09.639: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.639: mct_SendMrsCmd: Start
09.639: mct_SendMrsCmd: Done
09.639: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001978
09.639: mct_SendMrsCmd: Start
09.639: mct_SendMrsCmd: Done
09.639: DIMM 0 RttWr: 1
09.639: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.639: mct_SendMrsCmd: Start
09.639: mct_SendMrsCmd: Done
09.639: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
09.639: mct_SendMrsCmd: Start
09.639: mct_SendMrsCmd: Done
09.639: DIMM 0 RttNom: 3
09.639: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.639: mct_SendMrsCmd: Start
09.639: mct_SendMrsCmd: Done
09.639: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201978
09.639: mct_SendMrsCmd: Start
09.639: mct_SendMrsCmd: Done
09.639: DIMM 1 RttWr: 1
09.639: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.639: mct_SendMrsCmd: Start
09.639: mct_SendMrsCmd: Done
09.639: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
09.639: mct_SendMrsCmd: Start
09.639: mct_SendMrsCmd: Done
09.639: DIMM 1 RttNom: 3
09.639: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.639: mct_SendMrsCmd: Start
09.639: mct_SendMrsCmd: Done
09.639: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401978
09.639: mct_SendMrsCmd: Start
09.639: mct_SendMrsCmd: Done
09.639: DIMM 1 RttWr: 1
09.639: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.639: mct_SendMrsCmd: Start
09.639: mct_SendMrsCmd: Done
09.639: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
09.639: mct_SendMrsCmd: Start
09.639: mct_SendMrsCmd: Done
09.639: DIMM 1 RttNom: 3
09.639: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.639: mct_SendMrsCmd: Start
09.639: mct_SendMrsCmd: Done
09.639: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601978
09.639: mct_SendMrsCmd: Start
09.639: mct_SendMrsCmd: Done
09.639: mct_DramInit_Sw_D: Done
09.639: AgesaHwWlPhase1: training nibble 0
09.639: DIMM 0 RttNom: 3
09.639: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.639: DIMM 0 RttWr: 1
09.639: DIMM 0 RttWr: 1
09.639: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.639: DIMM 0 RttWr: 1
09.639: DIMM 0 RttNom: 3
09.639: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.639: DIMM 0 RttNom: 3
09.639: DIMM 0 RttWr: 1
09.639: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.639: DIMM 0 RttWr: 1
09.639: DIMM 1 RttNom: 3
09.640: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.639: DIMM 0 RttNom: 3
09.639: DIMM 1 RttWr: 1
09.639: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.640: DIMM 0 RttWr: 1
09.640: DIMM 1 RttNom: 3
09.640: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.640: DIMM 0 RttNom: 3
09.640: DIMM 1 RttWr: 1
09.640: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.640: DIMM 0 RttWr: 1
09.640: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.640: <09>Lane 00 scaled delay: 004f
09.640: <09>Lane 00 new seed: 004f
09.640: <09>Lane 01 scaled delay: 004d
09.640: <09>Lane 01 new seed: 004d
09.640: <09>Lane 02 scaled delay: 004a
09.640: <09>Lane 02 new seed: 004a
09.640: <09>Lane 03 scaled delay: 0047
09.640: <09>Lane 03 new seed: 0047
09.640: <09>Lane 04 scaled delay: 0046
09.640: <09>Lane 04 new seed: 0046
09.640: <09>Lane 05 scaled delay: 0049
09.640: <09>Lane 05 new seed: 0049
09.640: <09>Lane 06 scaled delay: 004b
09.640: <09>Lane 06 new seed: 004b
09.640: <09>Lane 07 scaled delay: 004e
09.640: <09>Lane 07 new seed: 004e
09.640: <09>Lane 08 scaled delay: 0045
09.640: <09>Lane 08 new seed: 0045
09.640: <09>Lane 00 nibble 0 raw readback: 004d
09.640: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004d
09.640: <09>Lane 00 nibble 0 adjusted value (post nibble): 004d
09.640: <09>Lane 01 nibble 0 raw readback: 0047
09.640: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0047
09.640: <09>Lane 01 nibble 0 adjusted value (post nibble): 0047
09.640: <09>Lane 02 nibble 0 raw readback: 0043
09.640: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0043
09.640: <09>Lane 02 nibble 0 adjusted value (post nibble): 0043
09.640: <09>Lane 03 nibble 0 raw readback: 003e
09.640: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003e
09.640: <09>Lane 03 nibble 0 adjusted value (post nibble): 003e
09.640: <09>Lane 04 nibble 0 raw readback: 003b
09.640: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003b
09.640: <09>Lane 04 nibble 0 adjusted value (post nibble): 003b
09.640: <09>Lane 05 nibble 0 raw readback: 0041
09.640: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0041
09.640: <09>Lane 05 nibble 0 adjusted value (post nibble): 0041
09.640: <09>Lane 06 nibble 0 raw readback: 0045
09.640: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0045
09.640: <09>Lane 06 nibble 0 adjusted value (post nibble): 0045
09.640: <09>Lane 07 nibble 0 raw readback: 004a
09.640: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004a
09.640: <09>Lane 07 nibble 0 adjusted value (post nibble): 004a
09.640: <09>Lane 08 nibble 0 raw readback: 003a
09.640: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003a
09.640: <09>Lane 08 nibble 0 adjusted value (post nibble): 003a
09.640: AgesaHwWlPhase1: training nibble 1
09.640: DIMM 0 RttNom: 3
09.640: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.640: DIMM 0 RttWr: 1
09.640: DIMM 0 RttWr: 1
09.640: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.640: DIMM 0 RttWr: 1
09.641: DIMM 0 RttNom: 3
09.641: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.641: DIMM 0 RttNom: 3
09.641: DIMM 0 RttWr: 1
09.641: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.641: DIMM 0 RttWr: 1
09.641: DIMM 1 RttNom: 3
09.641: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.641: DIMM 0 RttNom: 3
09.641: DIMM 1 RttWr: 1
09.641: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.641: DIMM 0 RttWr: 1
09.641: DIMM 1 RttNom: 3
09.641: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.641: DIMM 0 RttNom: 3
09.641: DIMM 1 RttWr: 1
09.641: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.641: DIMM 0 RttWr: 1
09.641: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.641: <09>Lane 00 new seed: 004f
09.641: <09>Lane 01 new seed: 004d
09.641: <09>Lane 02 new seed: 004a
09.641: <09>Lane 03 new seed: 0047
09.641: <09>Lane 04 new seed: 0046
09.641: <09>Lane 05 new seed: 0049
09.641: <09>Lane 06 new seed: 004b
09.641: <09>Lane 07 new seed: 004e
09.641: <09>Lane 08 new seed: 0045
09.641: <09>Lane 00 nibble 1 raw readback: 004d
09.641: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004d
09.641: <09>Lane 00 nibble 1 adjusted value (post nibble): 004e
09.641: <09>Lane 01 nibble 1 raw readback: 0047
09.641: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0047
09.641: <09>Lane 01 nibble 1 adjusted value (post nibble): 004a
09.641: <09>Lane 02 nibble 1 raw readback: 0042
09.641: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0042
09.641: <09>Lane 02 nibble 1 adjusted value (post nibble): 0046
09.641: <09>Lane 03 nibble 1 raw readback: 003f
09.641: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003f
09.641: <09>Lane 03 nibble 1 adjusted value (post nibble): 0043
09.641: <09>Lane 04 nibble 1 raw readback: 003a
09.641: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003a
09.641: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
09.641: <09>Lane 05 nibble 1 raw readback: 0040
09.641: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0040
09.641: <09>Lane 05 nibble 1 adjusted value (post nibble): 0044
09.641: <09>Lane 06 nibble 1 raw readback: 0045
09.641: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0045
09.641: <09>Lane 06 nibble 1 adjusted value (post nibble): 0048
09.641: <09>Lane 07 nibble 1 raw readback: 004b
09.641: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004b
09.641: <09>Lane 07 nibble 1 adjusted value (post nibble): 004c
09.641: <09>Lane 08 nibble 1 raw readback: 0038
09.641: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0038
09.641: <09>Lane 08 nibble 1 adjusted value (post nibble): 003e
09.641: <09>original critical gross delay: 0
09.641: <09>new critical gross delay: 0
09.641: DIMM 0 RttNom: 3
09.641: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.641: DIMM 0 RttNom: 3
09.641: DIMM 0 RttWr: 1
09.641: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.641: DIMM 0 RttWr: 1
09.642: DIMM 0 RttNom: 3
09.642: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.642: DIMM 0 RttNom: 3
09.642: DIMM 0 RttWr: 1
09.642: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.642: DIMM 0 RttWr: 1
09.642: DIMM 1 RttNom: 3
09.642: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.642: DIMM 0 RttNom: 3
09.642: DIMM 1 RttWr: 1
09.642: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.642: DIMM 0 RttWr: 1
09.642: DIMM 1 RttNom: 3
09.642: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.642: DIMM 0 RttNom: 3
09.642: DIMM 1 RttWr: 1
09.642: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.642: DIMM 0 RttWr: 1
09.642: AgesaHwWlPhase1: training nibble 0
09.642: DIMM 1 RttNom: 3
09.642: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.642: DIMM 1 RttWr: 1
09.642: DIMM 1 RttWr: 1
09.642: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.642: DIMM 1 RttWr: 1
09.642: DIMM 1 RttNom: 3
09.642: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.642: DIMM 1 RttNom: 3
09.642: DIMM 1 RttWr: 1
09.642: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.642: DIMM 1 RttWr: 1
09.642: DIMM 0 RttNom: 3
09.642: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.642: DIMM 1 RttNom: 3
09.642: DIMM 0 RttWr: 1
09.642: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.642: DIMM 1 RttWr: 1
09.642: DIMM 0 RttNom: 3
09.642: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.642: DIMM 1 RttNom: 3
09.642: DIMM 0 RttWr: 1
09.642: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.642: DIMM 1 RttWr: 1
09.642: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.642: <09>Lane 00 scaled delay: 0053
09.642: <09>Lane 00 new seed: 0053
09.642: <09>Lane 01 scaled delay: 004f
09.642: <09>Lane 01 new seed: 004f
09.642: <09>Lane 02 scaled delay: 004d
09.642: <09>Lane 02 new seed: 004d
09.642: <09>Lane 03 scaled delay: 004b
09.642: <09>Lane 03 new seed: 004b
09.642: <09>Lane 04 scaled delay: 0049
09.642: <09>Lane 04 new seed: 0049
09.642: <09>Lane 05 scaled delay: 004b
09.642: <09>Lane 05 new seed: 004b
09.642: <09>Lane 06 scaled delay: 004e
09.642: <09>Lane 06 new seed: 004e
09.642: <09>Lane 07 scaled delay: 0052
09.642: <09>Lane 07 new seed: 0052
09.642: <09>Lane 08 scaled delay: 0049
09.642: <09>Lane 08 new seed: 0049
09.642: <09>Lane 00 nibble 0 raw readback: 0050
09.642: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0050
09.642: <09>Lane 00 nibble 0 adjusted value (post nibble): 0050
09.642: <09>Lane 01 nibble 0 raw readback: 004f
09.643: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004f
09.642: <09>Lane 01 nibble 0 adjusted value (post nibble): 004f
09.643: <09>Lane 02 nibble 0 raw readback: 0049
09.643: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0049
09.643: <09>Lane 02 nibble 0 adjusted value (post nibble): 0049
09.643: <09>Lane 03 nibble 0 raw readback: 0044
09.643: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
09.643: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
09.643: <09>Lane 04 nibble 0 raw readback: 0041
09.643: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0041
09.643: <09>Lane 04 nibble 0 adjusted value (post nibble): 0041
09.643: <09>Lane 05 nibble 0 raw readback: 0047
09.643: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0047
09.643: <09>Lane 05 nibble 0 adjusted value (post nibble): 0047
09.643: <09>Lane 06 nibble 0 raw readback: 004c
09.643: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004c
09.643: <09>Lane 06 nibble 0 adjusted value (post nibble): 004c
09.643: <09>Lane 07 nibble 0 raw readback: 0050
09.643: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0050
09.643: <09>Lane 07 nibble 0 adjusted value (post nibble): 0050
09.643: <09>Lane 08 nibble 0 raw readback: 003e
09.643: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003e
09.643: <09>Lane 08 nibble 0 adjusted value (post nibble): 003e
09.643: AgesaHwWlPhase1: training nibble 1
09.643: DIMM 1 RttNom: 3
09.643: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.643: DIMM 1 RttWr: 1
09.643: DIMM 1 RttWr: 1
09.643: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.643: DIMM 1 RttWr: 1
09.643: DIMM 1 RttNom: 3
09.643: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.643: DIMM 1 RttNom: 3
09.643: DIMM 1 RttWr: 1
09.643: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.643: DIMM 1 RttWr: 1
09.643: DIMM 0 RttNom: 3
09.643: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.643: DIMM 1 RttNom: 3
09.643: DIMM 0 RttWr: 1
09.643: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.643: DIMM 1 RttWr: 1
09.643: DIMM 0 RttNom: 3
09.643: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.643: DIMM 1 RttNom: 3
09.643: DIMM 0 RttWr: 1
09.643: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.643: DIMM 1 RttWr: 1
09.643: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.643: <09>Lane 00 new seed: 0053
09.643: <09>Lane 01 new seed: 004f
09.643: <09>Lane 02 new seed: 004d
09.643: <09>Lane 03 new seed: 004b
09.643: <09>Lane 04 new seed: 0049
09.643: <09>Lane 05 new seed: 004b
09.643: <09>Lane 06 new seed: 004e
09.643: <09>Lane 07 new seed: 0052
09.643: <09>Lane 08 new seed: 0049
09.643: <09>Lane 00 nibble 1 raw readback: 0053
09.643: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0053
09.643: <09>Lane 00 nibble 1 adjusted value (post nibble): 0053
09.643: <09>Lane 01 nibble 1 raw readback: 004e
09.643: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004e
09.643: <09>Lane 01 nibble 1 adjusted value (post nibble): 004e
09.643: <09>Lane 02 nibble 1 raw readback: 0049
09.643: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0049
09.643: <09>Lane 02 nibble 1 adjusted value (post nibble): 004b
09.643: <09>Lane 03 nibble 1 raw readback: 0045
09.643: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
09.643: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
09.643: <09>Lane 04 nibble 1 raw readback: 0040
09.643: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0040
09.643: <09>Lane 04 nibble 1 adjusted value (post nibble): 0044
09.643: <09>Lane 05 nibble 1 raw readback: 0045
09.643: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0045
09.643: <09>Lane 05 nibble 1 adjusted value (post nibble): 0048
09.644: <09>Lane 06 nibble 1 raw readback: 004b
09.644: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004b
09.644: <09>Lane 06 nibble 1 adjusted value (post nibble): 004c
09.644: <09>Lane 07 nibble 1 raw readback: 0050
09.644: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0050
09.644: <09>Lane 07 nibble 1 adjusted value (post nibble): 0051
09.644: <09>Lane 08 nibble 1 raw readback: 0040
09.644: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0040
09.644: <09>Lane 08 nibble 1 adjusted value (post nibble): 0044
09.644: <09>original critical gross delay: 0
09.644: <09>new critical gross delay: 0
09.644: DIMM 1 RttNom: 3
09.644: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.644: DIMM 1 RttNom: 3
09.644: DIMM 1 RttWr: 1
09.644: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.644: DIMM 1 RttWr: 1
09.644: DIMM 1 RttNom: 3
09.644: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.644: DIMM 1 RttNom: 3
09.644: DIMM 1 RttWr: 1
09.644: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.644: DIMM 1 RttWr: 1
09.644: DIMM 0 RttNom: 3
09.644: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.644: DIMM 1 RttNom: 3
09.644: DIMM 0 RttWr: 1
09.644: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.644: DIMM 1 RttWr: 1
09.644: DIMM 0 RttNom: 3
09.644: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.644: DIMM 1 RttNom: 3
09.644: DIMM 0 RttWr: 1
09.644: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.644: DIMM 1 RttWr: 1
09.644: SetTargetFreq: Start
09.644: SetTargetFreq: Node 1: New frequency code: 000e
09.644: ChangeMemClk: Start
09.644: set_2t_configuration: Start
09.644: set_2t_configuration: Done
09.644: mct_BeforePlatformSpec: Start
09.644: mct_BeforePlatformSpec: Done
09.645: mct_PlatformSpec: Start
09.645: Programmed DCT 0 timing/termination pattern 00383a38 30222222
09.645: mct_PlatformSpec: Done
09.645: set_2t_configuration: Start
09.645: set_2t_configuration: Done
09.645: mct_BeforePlatformSpec: Start
09.645: mct_BeforePlatformSpec: Done
09.645: mct_PlatformSpec: Start
09.645: Programmed DCT 1 timing/termination pattern 00383a38 30222222
09.645: mct_PlatformSpec: Done
09.645: ChangeMemClk: Done
09.645: phyAssistedMemFnceTraining: Start
09.645: phyAssistedMemFnceTraining: training node 1 DCT 0
09.645: phyAssistedMemFnceTraining: done training node 1 DCT 0
09.645: phyAssistedMemFnceTraining: training node 1 DCT 1
09.645: phyAssistedMemFnceTraining: done training node 1 DCT 1
09.645: phyAssistedMemFnceTraining: Done
09.645: InitPhyCompensation: DCT 0: Start
09.645: Waiting for predriver calibration to be applied...done!
09.645: InitPhyCompensation: DCT 0: Done
09.645: phyAssistedMemFnceTraining: Start
09.645: phyAssistedMemFnceTraining: training node 1 DCT 0
09.645: phyAssistedMemFnceTraining: done training node 1 DCT 0
09.645: phyAssistedMemFnceTraining: training node 1 DCT 1
09.645: phyAssistedMemFnceTraining: done training node 1 DCT 1
09.645: phyAssistedMemFnceTraining: Done
09.645: InitPhyCompensation: DCT 1: Start
09.646: Waiting for predriver calibration to be applied...done!
09.646: InitPhyCompensation: DCT 1: Done
09.646: Preparing to send DCT 0 DIMM 0 RC10: 02 (F2xA8: 02000300)
09.646: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.646: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
09.646: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.646: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
09.646: Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 02000c00)
09.646: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.646: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
09.646: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.646: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
09.646: Preparing to send DCT 1 DIMM 0 RC10: 02 (F2xA8: 02000300)
09.646: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.646: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
09.646: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.646: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
09.646: Preparing to send DCT 1 DIMM 1 RC10: 02 (F2xA8: 02000c00)
09.646: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.646: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
09.646: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.646: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
09.646: SetTargetFreq: Done
09.646: SPD2ndTiming: Start
09.647: SPD2ndTiming: Done
09.647: mct_BeforeDramInit_Prod_D: Start
09.647: mct_ProgramODT_D: Start
09.647: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
09.647: mct_ProgramODT_D: Done
09.647: mct_BeforeDramInit_Prod_D: Done
09.647: mct_DramInit_Sw_D: Start
09.647: DIMM 0 RttWr: 2
09.647: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.647: mct_SendMrsCmd: Start
09.647: mct_SendMrsCmd: Done
09.647: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
09.647: mct_SendMrsCmd: Start
09.647: mct_SendMrsCmd: Done
09.647: DIMM 0 RttNom: 5
09.647: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.647: mct_SendMrsCmd: Start
09.647: mct_SendMrsCmd: Done
09.647: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001b78
09.647: mct_SendMrsCmd: Start
09.647: mct_SendMrsCmd: Done
09.647: DIMM 0 RttWr: 2
09.647: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.647: mct_SendMrsCmd: Start
09.647: mct_SendMrsCmd: Done
09.647: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
09.647: mct_SendMrsCmd: Start
09.647: mct_SendMrsCmd: Done
09.647: DIMM 0 RttNom: 5
09.647: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.647: mct_SendMrsCmd: Start
09.647: mct_SendMrsCmd: Done
09.647: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201b78
09.647: mct_SendMrsCmd: Start
09.647: mct_SendMrsCmd: Done
09.647: DIMM 1 RttWr: 2
09.647: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.647: mct_SendMrsCmd: Start
09.647: mct_SendMrsCmd: Done
09.647: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
09.647: mct_SendMrsCmd: Start
09.647: mct_SendMrsCmd: Done
09.647: DIMM 1 RttNom: 5
09.647: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.647: mct_SendMrsCmd: Start
09.647: mct_SendMrsCmd: Done
09.647: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b78
09.647: mct_SendMrsCmd: Start
09.647: mct_SendMrsCmd: Done
09.647: DIMM 1 RttWr: 2
09.647: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.647: mct_SendMrsCmd: Start
09.647: mct_SendMrsCmd: Done
09.647: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
09.647: mct_SendMrsCmd: Start
09.647: mct_SendMrsCmd: Done
09.647: DIMM 1 RttNom: 5
09.647: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.647: mct_SendMrsCmd: Start
09.647: mct_SendMrsCmd: Done
09.647: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b78
09.647: mct_SendMrsCmd: Start
09.647: mct_SendMrsCmd: Done
09.647: mct_DramInit_Sw_D: Done
09.648: AgesaHwWlPhase1: training nibble 0
09.648: DIMM 0 RttNom: 5
09.648: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.648: DIMM 0 RttWr: 2
09.648: DIMM 0 RttWr: 2
09.648: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.648: DIMM 0 RttWr: 2
09.648: DIMM 0 RttNom: 5
09.648: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.648: DIMM 0 RttNom: 5
09.648: DIMM 0 RttWr: 2
09.648: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.648: DIMM 0 RttWr: 2
09.648: DIMM 1 RttNom: 5
09.648: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.648: DIMM 0 RttNom: 5
09.648: DIMM 1 RttWr: 2
09.648: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.648: DIMM 0 RttWr: 2
09.648: DIMM 1 RttNom: 5
09.648: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.648: DIMM 0 RttNom: 5
09.648: DIMM 1 RttWr: 2
09.648: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.648: DIMM 0 RttWr: 2
09.648: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.648: <09>Lane 00 scaled delay: 0055
09.648: <09>Lane 00 new seed: 0055
09.648: <09>Lane 01 scaled delay: 0050
09.648: <09>Lane 01 new seed: 0050
09.648: <09>Lane 02 scaled delay: 004d
09.648: <09>Lane 02 new seed: 004d
09.648: <09>Lane 03 scaled delay: 004d
09.648: <09>Lane 03 new seed: 004d
09.648: <09>Lane 04 scaled delay: 0046
09.648: <09>Lane 04 new seed: 0046
09.648: <09>Lane 05 scaled delay: 004b
09.648: <09>Lane 05 new seed: 004b
09.648: <09>Lane 06 scaled delay: 004e
09.648: <09>Lane 06 new seed: 004e
09.648: <09>Lane 07 scaled delay: 0053
09.649: <09>Lane 07 new seed: 0053
09.648: <09>Lane 08 scaled delay: 0045
09.649: <09>Lane 08 new seed: 0045
09.649: <09>Lane 00 nibble 0 raw readback: 0055
09.649: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0055
09.649: <09>Lane 00 nibble 0 adjusted value (post nibble): 0055
09.649: <09>Lane 01 nibble 0 raw readback: 004e
09.649: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004e
09.649: <09>Lane 01 nibble 0 adjusted value (post nibble): 004e
09.649: <09>Lane 02 nibble 0 raw readback: 0049
09.649: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0049
09.649: <09>Lane 02 nibble 0 adjusted value (post nibble): 0049
09.649: <09>Lane 03 nibble 0 raw readback: 0046
09.649: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0046
09.649: <09>Lane 03 nibble 0 adjusted value (post nibble): 0046
09.649: <09>Lane 04 nibble 0 raw readback: 0042
09.649: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0042
09.649: <09>Lane 04 nibble 0 adjusted value (post nibble): 0042
09.649: <09>Lane 05 nibble 0 raw readback: 0048
09.649: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0048
09.649: <09>Lane 05 nibble 0 adjusted value (post nibble): 0048
09.649: <09>Lane 06 nibble 0 raw readback: 004b
09.649: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004b
09.649: <09>Lane 06 nibble 0 adjusted value (post nibble): 004b
09.649: <09>Lane 07 nibble 0 raw readback: 0050
09.649: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0050
09.649: <09>Lane 07 nibble 0 adjusted value (post nibble): 0050
09.649: <09>Lane 08 nibble 0 raw readback: 003e
09.649: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003e
09.649: <09>Lane 08 nibble 0 adjusted value (post nibble): 003e
09.649: AgesaHwWlPhase1: training nibble 1
09.649: DIMM 0 RttNom: 5
09.649: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.649: DIMM 0 RttWr: 2
09.649: DIMM 0 RttWr: 2
09.649: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.649: DIMM 0 RttWr: 2
09.649: DIMM 0 RttNom: 5
09.649: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.649: DIMM 0 RttNom: 5
09.649: DIMM 0 RttWr: 2
09.649: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.649: DIMM 0 RttWr: 2
09.649: DIMM 1 RttNom: 5
09.649: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.649: DIMM 0 RttNom: 5
09.649: DIMM 1 RttWr: 2
09.649: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.649: DIMM 0 RttWr: 2
09.649: DIMM 1 RttNom: 5
09.649: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.649: DIMM 0 RttNom: 5
09.649: DIMM 1 RttWr: 2
09.649: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.649: DIMM 0 RttWr: 2
09.649: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.649: <09>Lane 00 new seed: 0055
09.649: <09>Lane 01 new seed: 0050
09.649: <09>Lane 02 new seed: 004d
09.649: <09>Lane 03 new seed: 004d
09.649: <09>Lane 04 new seed: 0046
09.650: <09>Lane 05 new seed: 004b
09.649: <09>Lane 06 new seed: 004e
09.649: <09>Lane 07 new seed: 0053
09.650: <09>Lane 08 new seed: 0045
09.650: <09>Lane 00 nibble 1 raw readback: 0055
09.650: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0055
09.650: <09>Lane 00 nibble 1 adjusted value (post nibble): 0055
09.650: <09>Lane 01 nibble 1 raw readback: 004f
09.650: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004f
09.650: <09>Lane 01 nibble 1 adjusted value (post nibble): 004f
09.650: <09>Lane 02 nibble 1 raw readback: 0049
09.650: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0049
09.650: <09>Lane 02 nibble 1 adjusted value (post nibble): 004b
09.650: <09>Lane 03 nibble 1 raw readback: 0047
09.650: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0047
09.650: <09>Lane 03 nibble 1 adjusted value (post nibble): 004a
09.650: <09>Lane 04 nibble 1 raw readback: 0040
09.650: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0040
09.650: <09>Lane 04 nibble 1 adjusted value (post nibble): 0043
09.650: <09>Lane 05 nibble 1 raw readback: 0047
09.650: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0047
09.650: <09>Lane 05 nibble 1 adjusted value (post nibble): 0049
09.650: <09>Lane 06 nibble 1 raw readback: 004b
09.650: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004b
09.650: <09>Lane 06 nibble 1 adjusted value (post nibble): 004c
09.650: <09>Lane 07 nibble 1 raw readback: 0050
09.650: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0050
09.650: <09>Lane 07 nibble 1 adjusted value (post nibble): 0051
09.650: <09>Lane 08 nibble 1 raw readback: 003d
09.650: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003d
09.650: <09>Lane 08 nibble 1 adjusted value (post nibble): 0041
09.650: <09>original critical gross delay: 0
09.650: <09>new critical gross delay: 0
09.650: DIMM 0 RttNom: 5
09.650: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.650: DIMM 0 RttNom: 5
09.650: DIMM 0 RttWr: 2
09.650: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.650: DIMM 0 RttWr: 2
09.650: DIMM 0 RttNom: 5
09.650: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.650: DIMM 0 RttNom: 5
09.650: DIMM 0 RttWr: 2
09.650: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.650: DIMM 0 RttWr: 2
09.650: DIMM 1 RttNom: 5
09.650: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.650: DIMM 0 RttNom: 5
09.650: DIMM 1 RttWr: 2
09.650: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.650: DIMM 0 RttWr: 2
09.650: DIMM 1 RttNom: 5
09.650: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.650: DIMM 0 RttNom: 5
09.650: DIMM 1 RttWr: 2
09.650: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.650: DIMM 0 RttWr: 2
09.650: AgesaHwWlPhase1: training nibble 0
09.650: DIMM 1 RttNom: 5
09.650: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.650: DIMM 1 RttWr: 2
09.650: DIMM 1 RttWr: 2
09.650: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.650: DIMM 1 RttWr: 2
09.651: DIMM 1 RttNom: 5
09.650: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.651: DIMM 1 RttNom: 5
09.651: DIMM 1 RttWr: 2
09.651: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.651: DIMM 1 RttWr: 2
09.651: DIMM 0 RttNom: 5
09.651: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.651: DIMM 1 RttNom: 5
09.651: DIMM 0 RttWr: 2
09.651: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.651: DIMM 1 RttWr: 2
09.651: DIMM 0 RttNom: 5
09.651: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.651: DIMM 1 RttNom: 5
09.651: DIMM 0 RttWr: 2
09.651: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.651: DIMM 1 RttWr: 2
09.651: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.651: <09>Lane 00 scaled delay: 005d
09.651: <09>Lane 00 new seed: 005d
09.651: <09>Lane 01 scaled delay: 0057
09.651: <09>Lane 01 new seed: 0057
09.651: <09>Lane 02 scaled delay: 0053
09.651: <09>Lane 02 new seed: 0053
09.651: <09>Lane 03 scaled delay: 0052
09.651: <09>Lane 03 new seed: 0052
09.651: <09>Lane 04 scaled delay: 004d
09.651: <09>Lane 04 new seed: 004d
09.651: <09>Lane 05 scaled delay: 0052
09.651: <09>Lane 05 new seed: 0052
09.651: <09>Lane 06 scaled delay: 0055
09.651: <09>Lane 06 new seed: 0055
09.651: <09>Lane 07 scaled delay: 0059
09.651: <09>Lane 07 new seed: 0059
09.651: <09>Lane 08 scaled delay: 004d
09.651: <09>Lane 08 new seed: 004d
09.651: <09>Lane 00 nibble 0 raw readback: 005f
09.651: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005f
09.651: <09>Lane 00 nibble 0 adjusted value (post nibble): 005f
09.651: <09>Lane 01 nibble 0 raw readback: 0055
09.651: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0055
09.651: <09>Lane 01 nibble 0 adjusted value (post nibble): 0055
09.651: <09>Lane 02 nibble 0 raw readback: 004f
09.651: <09>Lane 02 nibble 0 adjusted value (pre nibble): 004f
09.651: <09>Lane 02 nibble 0 adjusted value (post nibble): 004f
09.651: <09>Lane 03 nibble 0 raw readback: 004e
09.651: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004e
09.651: <09>Lane 03 nibble 0 adjusted value (post nibble): 004e
09.651: <09>Lane 04 nibble 0 raw readback: 0049
09.651: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0049
09.651: <09>Lane 04 nibble 0 adjusted value (post nibble): 0049
09.651: <09>Lane 05 nibble 0 raw readback: 0051
09.651: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0051
09.651: <09>Lane 05 nibble 0 adjusted value (post nibble): 0051
09.651: <09>Lane 06 nibble 0 raw readback: 0051
09.651: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0051
09.651: <09>Lane 06 nibble 0 adjusted value (post nibble): 0051
09.651: <09>Lane 07 nibble 0 raw readback: 0058
09.651: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0058
09.651: <09>Lane 07 nibble 0 adjusted value (post nibble): 0058
09.651: <09>Lane 08 nibble 0 raw readback: 0046
09.651: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0046
09.651: <09>Lane 08 nibble 0 adjusted value (post nibble): 0046
09.651: AgesaHwWlPhase1: training nibble 1
09.651: DIMM 1 RttNom: 5
09.651: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.651: DIMM 1 RttWr: 2
09.651: DIMM 1 RttWr: 2
09.651: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.651: DIMM 1 RttWr: 2
09.651: DIMM 1 RttNom: 5
09.652: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.651: DIMM 1 RttNom: 5
09.651: DIMM 1 RttWr: 2
09.652: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.652: DIMM 1 RttWr: 2
09.652: DIMM 0 RttNom: 5
09.652: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.652: DIMM 1 RttNom: 5
09.652: DIMM 0 RttWr: 2
09.652: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.652: DIMM 1 RttWr: 2
09.652: DIMM 0 RttNom: 5
09.652: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.652: DIMM 1 RttNom: 5
09.652: DIMM 0 RttWr: 2
09.652: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.652: DIMM 1 RttWr: 2
09.652: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.652: <09>Lane 00 new seed: 005d
09.652: <09>Lane 01 new seed: 0057
09.652: <09>Lane 02 new seed: 0053
09.652: <09>Lane 03 new seed: 0052
09.652: <09>Lane 04 new seed: 004d
09.652: <09>Lane 05 new seed: 0052
09.652: <09>Lane 06 new seed: 0055
09.652: <09>Lane 07 new seed: 0059
09.652: <09>Lane 08 new seed: 004d
09.652: <09>Lane 00 nibble 1 raw readback: 005e
09.652: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005e
09.652: <09>Lane 00 nibble 1 adjusted value (post nibble): 005d
09.652: <09>Lane 01 nibble 1 raw readback: 0055
09.652: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0055
09.652: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
09.652: <09>Lane 02 nibble 1 raw readback: 004f
09.652: <09>Lane 02 nibble 1 adjusted value (pre nibble): 004f
09.652: <09>Lane 02 nibble 1 adjusted value (post nibble): 0051
09.652: <09>Lane 03 nibble 1 raw readback: 004d
09.652: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004d
09.652: <09>Lane 03 nibble 1 adjusted value (post nibble): 004f
09.652: <09>Lane 04 nibble 1 raw readback: 0047
09.652: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0047
09.652: <09>Lane 04 nibble 1 adjusted value (post nibble): 004a
09.652: <09>Lane 05 nibble 1 raw readback: 004e
09.652: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004e
09.652: <09>Lane 05 nibble 1 adjusted value (post nibble): 0050
09.652: <09>Lane 06 nibble 1 raw readback: 0051
09.652: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0051
09.652: <09>Lane 06 nibble 1 adjusted value (post nibble): 0053
09.652: <09>Lane 07 nibble 1 raw readback: 0057
09.652: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0057
09.652: <09>Lane 07 nibble 1 adjusted value (post nibble): 0058
09.652: <09>Lane 08 nibble 1 raw readback: 0046
09.652: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0046
09.652: <09>Lane 08 nibble 1 adjusted value (post nibble): 0049
09.652: <09>original critical gross delay: 0
09.652: <09>new critical gross delay: 0
09.652: DIMM 1 RttNom: 5
09.652: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.652: DIMM 1 RttNom: 5
09.652: DIMM 1 RttWr: 2
09.652: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.652: DIMM 1 RttWr: 2
09.652: DIMM 1 RttNom: 5
09.652: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.652: DIMM 1 RttNom: 5
09.652: DIMM 1 RttWr: 2
09.652: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.653: DIMM 1 RttWr: 2
09.653: DIMM 0 RttNom: 5
09.653: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.653: DIMM 1 RttNom: 5
09.653: DIMM 0 RttWr: 2
09.653: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.653: DIMM 1 RttWr: 2
09.653: DIMM 0 RttNom: 5
09.653: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.653: DIMM 1 RttNom: 5
09.653: DIMM 0 RttWr: 2
09.653: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.653: DIMM 1 RttWr: 2
09.653: SPD2ndTiming: Start
09.653: SPD2ndTiming: Done
09.653: mct_BeforeDramInit_Prod_D: Start
09.653: mct_ProgramODT_D: Start
09.653: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
09.653: mct_ProgramODT_D: Done
09.653: mct_BeforeDramInit_Prod_D: Done
09.653: mct_DramInit_Sw_D: Start
09.653: DIMM 0 RttWr: 2
09.653: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.653: mct_SendMrsCmd: Start
09.653: mct_SendMrsCmd: Done
09.653: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
09.653: mct_SendMrsCmd: Start
09.653: mct_SendMrsCmd: Done
09.653: DIMM 0 RttNom: 5
09.653: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.653: mct_SendMrsCmd: Start
09.653: mct_SendMrsCmd: Done
09.653: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001b78
09.653: mct_SendMrsCmd: Start
09.653: mct_SendMrsCmd: Done
09.653: DIMM 0 RttWr: 2
09.653: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.654: mct_SendMrsCmd: Start
09.654: mct_SendMrsCmd: Done
09.654: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
09.654: mct_SendMrsCmd: Start
09.654: mct_SendMrsCmd: Done
09.654: DIMM 0 RttNom: 5
09.654: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.654: mct_SendMrsCmd: Start
09.654: mct_SendMrsCmd: Done
09.654: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201b78
09.654: mct_SendMrsCmd: Start
09.654: mct_SendMrsCmd: Done
09.654: DIMM 1 RttWr: 2
09.654: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.654: mct_SendMrsCmd: Start
09.654: mct_SendMrsCmd: Done
09.654: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
09.654: mct_SendMrsCmd: Start
09.654: mct_SendMrsCmd: Done
09.654: DIMM 1 RttNom: 5
09.654: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.654: mct_SendMrsCmd: Start
09.654: mct_SendMrsCmd: Done
09.654: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401b78
09.654: mct_SendMrsCmd: Start
09.654: mct_SendMrsCmd: Done
09.654: DIMM 1 RttWr: 2
09.654: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.654: mct_SendMrsCmd: Start
09.654: mct_SendMrsCmd: Done
09.654: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
09.654: mct_SendMrsCmd: Start
09.654: mct_SendMrsCmd: Done
09.654: DIMM 1 RttNom: 5
09.654: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.654: mct_SendMrsCmd: Start
09.654: mct_SendMrsCmd: Done
09.654: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601b78
09.654: mct_SendMrsCmd: Start
09.654: mct_SendMrsCmd: Done
09.654: mct_DramInit_Sw_D: Done
09.654: AgesaHwWlPhase1: training nibble 0
09.654: DIMM 0 RttNom: 5
09.654: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.654: DIMM 0 RttWr: 2
09.654: DIMM 0 RttWr: 2
09.654: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.654: DIMM 0 RttWr: 2
09.654: DIMM 0 RttNom: 5
09.654: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.654: DIMM 0 RttNom: 5
09.654: DIMM 0 RttWr: 2
09.654: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.654: DIMM 0 RttWr: 2
09.654: DIMM 1 RttNom: 5
09.654: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.654: DIMM 0 RttNom: 5
09.654: DIMM 1 RttWr: 2
09.654: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.654: DIMM 0 RttWr: 2
09.654: DIMM 1 RttNom: 5
09.654: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.654: DIMM 0 RttNom: 5
09.654: DIMM 1 RttWr: 2
09.654: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.654: DIMM 0 RttWr: 2
09.654: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.655: <09>Lane 00 scaled delay: 0059
09.655: <09>Lane 00 new seed: 0059
09.655: <09>Lane 01 scaled delay: 0054
09.655: <09>Lane 01 new seed: 0054
09.655: <09>Lane 02 scaled delay: 004f
09.655: <09>Lane 02 new seed: 004f
09.655: <09>Lane 03 scaled delay: 004b
09.655: <09>Lane 03 new seed: 004b
09.655: <09>Lane 04 scaled delay: 0048
09.655: <09>Lane 04 new seed: 0048
09.655: <09>Lane 05 scaled delay: 004d
09.655: <09>Lane 05 new seed: 004d
09.655: <09>Lane 06 scaled delay: 0052
09.655: <09>Lane 06 new seed: 0052
09.655: <09>Lane 07 scaled delay: 0057
09.655: <09>Lane 07 new seed: 0057
09.655: <09>Lane 08 scaled delay: 0045
09.655: <09>Lane 08 new seed: 0045
09.655: <09>Lane 00 nibble 0 raw readback: 0059
09.655: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0059
09.655: <09>Lane 00 nibble 0 adjusted value (post nibble): 0059
09.655: <09>Lane 01 nibble 0 raw readback: 0050
09.655: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0050
09.655: <09>Lane 01 nibble 0 adjusted value (post nibble): 0050
09.655: <09>Lane 02 nibble 0 raw readback: 004d
09.655: <09>Lane 02 nibble 0 adjusted value (pre nibble): 004d
09.655: <09>Lane 02 nibble 0 adjusted value (post nibble): 004d
09.655: <09>Lane 03 nibble 0 raw readback: 0047
09.655: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0047
09.655: <09>Lane 03 nibble 0 adjusted value (post nibble): 0047
09.655: <09>Lane 04 nibble 0 raw readback: 0044
09.655: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0044
09.655: <09>Lane 04 nibble 0 adjusted value (post nibble): 0044
09.655: <09>Lane 05 nibble 0 raw readback: 004b
09.655: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004b
09.655: <09>Lane 05 nibble 0 adjusted value (post nibble): 004b
09.655: <09>Lane 06 nibble 0 raw readback: 004e
09.655: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004e
09.655: <09>Lane 06 nibble 0 adjusted value (post nibble): 004e
09.655: <09>Lane 07 nibble 0 raw readback: 0055
09.655: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0055
09.655: <09>Lane 07 nibble 0 adjusted value (post nibble): 0055
09.655: <09>Lane 08 nibble 0 raw readback: 0042
09.655: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0042
09.655: <09>Lane 08 nibble 0 adjusted value (post nibble): 0042
09.655: AgesaHwWlPhase1: training nibble 1
09.655: DIMM 0 RttNom: 5
09.655: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.655: DIMM 0 RttWr: 2
09.655: DIMM 0 RttWr: 2
09.655: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.655: DIMM 0 RttWr: 2
09.655: DIMM 0 RttNom: 5
09.655: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.655: DIMM 0 RttNom: 5
09.655: DIMM 0 RttWr: 2
09.655: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.655: DIMM 0 RttWr: 2
09.655: DIMM 1 RttNom: 5
09.655: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.655: DIMM 0 RttNom: 5
09.655: DIMM 1 RttWr: 2
09.655: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.655: DIMM 0 RttWr: 2
09.656: DIMM 1 RttNom: 5
09.656: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.656: DIMM 0 RttNom: 5
09.656: DIMM 1 RttWr: 2
09.656: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.656: DIMM 0 RttWr: 2
09.656: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.656: <09>Lane 00 new seed: 0059
09.656: <09>Lane 01 new seed: 0054
09.656: <09>Lane 02 new seed: 004f
09.656: <09>Lane 03 new seed: 004b
09.656: <09>Lane 04 new seed: 0048
09.656: <09>Lane 05 new seed: 004d
09.656: <09>Lane 06 new seed: 0052
09.656: <09>Lane 07 new seed: 0057
09.656: <09>Lane 08 new seed: 0045
09.656: <09>Lane 00 nibble 1 raw readback: 0058
09.656: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0058
09.656: <09>Lane 00 nibble 1 adjusted value (post nibble): 0058
09.656: <09>Lane 01 nibble 1 raw readback: 0051
09.656: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0051
09.656: <09>Lane 01 nibble 1 adjusted value (post nibble): 0052
09.656: <09>Lane 02 nibble 1 raw readback: 004b
09.656: <09>Lane 02 nibble 1 adjusted value (pre nibble): 004b
09.656: <09>Lane 02 nibble 1 adjusted value (post nibble): 004d
09.656: <09>Lane 03 nibble 1 raw readback: 0047
09.656: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0047
09.656: <09>Lane 03 nibble 1 adjusted value (post nibble): 0049
09.656: <09>Lane 04 nibble 1 raw readback: 0042
09.656: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0042
09.656: <09>Lane 04 nibble 1 adjusted value (post nibble): 0045
09.656: <09>Lane 05 nibble 1 raw readback: 004a
09.656: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004a
09.656: <09>Lane 05 nibble 1 adjusted value (post nibble): 004b
09.656: <09>Lane 06 nibble 1 raw readback: 004f
09.656: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004f
09.656: <09>Lane 06 nibble 1 adjusted value (post nibble): 0050
09.656: <09>Lane 07 nibble 1 raw readback: 0057
09.656: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0057
09.656: <09>Lane 07 nibble 1 adjusted value (post nibble): 0057
09.656: <09>Lane 08 nibble 1 raw readback: 0040
09.656: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0040
09.656: <09>Lane 08 nibble 1 adjusted value (post nibble): 0042
09.656: <09>original critical gross delay: 0
09.656: <09>new critical gross delay: 0
09.656: DIMM 0 RttNom: 5
09.656: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.656: DIMM 0 RttNom: 5
09.656: DIMM 0 RttWr: 2
09.656: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.656: DIMM 0 RttWr: 2
09.656: DIMM 0 RttNom: 5
09.656: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.656: DIMM 0 RttNom: 5
09.656: DIMM 0 RttWr: 2
09.656: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.656: DIMM 0 RttWr: 2
09.656: DIMM 1 RttNom: 5
09.656: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.657: DIMM 0 RttNom: 5
09.656: DIMM 1 RttWr: 2
09.657: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.657: DIMM 0 RttWr: 2
09.657: DIMM 1 RttNom: 5
09.657: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.657: DIMM 0 RttNom: 5
09.657: DIMM 1 RttWr: 2
09.657: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.657: DIMM 0 RttWr: 2
09.657: AgesaHwWlPhase1: training nibble 0
09.657: DIMM 1 RttNom: 5
09.657: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.657: DIMM 1 RttWr: 2
09.657: DIMM 1 RttWr: 2
09.657: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.657: DIMM 1 RttWr: 2
09.657: DIMM 1 RttNom: 5
09.657: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.657: DIMM 1 RttNom: 5
09.657: DIMM 1 RttWr: 2
09.657: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.657: DIMM 1 RttWr: 2
09.657: DIMM 0 RttNom: 5
09.657: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.657: DIMM 1 RttNom: 5
09.657: DIMM 0 RttWr: 2
09.657: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.657: DIMM 1 RttWr: 2
09.657: DIMM 0 RttNom: 5
09.657: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.657: DIMM 1 RttNom: 5
09.657: DIMM 0 RttWr: 2
09.657: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.657: DIMM 1 RttWr: 2
09.657: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.657: <09>Lane 00 scaled delay: 005f
09.657: <09>Lane 00 new seed: 005f
09.657: <09>Lane 01 scaled delay: 0059
09.657: <09>Lane 01 new seed: 0059
09.657: <09>Lane 02 scaled delay: 0055
09.657: <09>Lane 02 new seed: 0055
09.657: <09>Lane 03 scaled delay: 0052
09.657: <09>Lane 03 new seed: 0052
09.657: <09>Lane 04 scaled delay: 004d
09.657: <09>Lane 04 new seed: 004d
09.657: <09>Lane 05 scaled delay: 0052
09.657: <09>Lane 05 new seed: 0052
09.657: <09>Lane 06 scaled delay: 0057
09.657: <09>Lane 06 new seed: 0057
09.657: <09>Lane 07 scaled delay: 005d
09.657: <09>Lane 07 new seed: 005d
09.657: <09>Lane 08 scaled delay: 004d
09.657: <09>Lane 08 new seed: 004d
09.657: <09>Lane 00 nibble 0 raw readback: 005c
09.657: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005c
09.657: <09>Lane 00 nibble 0 adjusted value (post nibble): 005c
09.657: <09>Lane 01 nibble 0 raw readback: 005a
09.657: <09>Lane 01 nibble 0 adjusted value (pre nibble): 005a
09.657: <09>Lane 01 nibble 0 adjusted value (post nibble): 005a
09.657: <09>Lane 02 nibble 0 raw readback: 0053
09.657: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0053
09.657: <09>Lane 02 nibble 0 adjusted value (post nibble): 0053
09.657: <09>Lane 03 nibble 0 raw readback: 004d
09.657: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004d
09.657: <09>Lane 03 nibble 0 adjusted value (post nibble): 004d
09.657: <09>Lane 04 nibble 0 raw readback: 004a
09.657: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004a
09.657: <09>Lane 04 nibble 0 adjusted value (post nibble): 004a
09.657: <09>Lane 05 nibble 0 raw readback: 0051
09.657: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0051
09.658: <09>Lane 05 nibble 0 adjusted value (post nibble): 0051
09.658: <09>Lane 06 nibble 0 raw readback: 0058
09.658: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0058
09.658: <09>Lane 06 nibble 0 adjusted value (post nibble): 0058
09.658: <09>Lane 07 nibble 0 raw readback: 005b
09.658: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005b
09.658: <09>Lane 07 nibble 0 adjusted value (post nibble): 005b
09.658: <09>Lane 08 nibble 0 raw readback: 0047
09.658: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0047
09.658: <09>Lane 08 nibble 0 adjusted value (post nibble): 0047
09.658: AgesaHwWlPhase1: training nibble 1
09.658: DIMM 1 RttNom: 5
09.658: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.658: DIMM 1 RttWr: 2
09.658: DIMM 1 RttWr: 2
09.658: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.658: DIMM 1 RttWr: 2
09.658: DIMM 1 RttNom: 5
09.658: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.658: DIMM 1 RttNom: 5
09.658: DIMM 1 RttWr: 2
09.658: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.658: DIMM 1 RttWr: 2
09.658: DIMM 0 RttNom: 5
09.658: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.658: DIMM 1 RttNom: 5
09.658: DIMM 0 RttWr: 2
09.658: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.658: DIMM 1 RttWr: 2
09.658: DIMM 0 RttNom: 5
09.658: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.658: DIMM 1 RttNom: 5
09.658: DIMM 0 RttWr: 2
09.658: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.658: DIMM 1 RttWr: 2
09.658: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.658: <09>Lane 00 new seed: 005f
09.658: <09>Lane 01 new seed: 0059
09.658: <09>Lane 02 new seed: 0055
09.658: <09>Lane 03 new seed: 0052
09.658: <09>Lane 04 new seed: 004d
09.658: <09>Lane 05 new seed: 0052
09.658: <09>Lane 06 new seed: 0057
09.658: <09>Lane 07 new seed: 005d
09.658: <09>Lane 08 new seed: 004d
09.658: <09>Lane 00 nibble 1 raw readback: 0060
09.658: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0060
09.658: <09>Lane 00 nibble 1 adjusted value (post nibble): 005f
09.658: <09>Lane 01 nibble 1 raw readback: 0059
09.658: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0059
09.658: <09>Lane 01 nibble 1 adjusted value (post nibble): 0059
09.658: <09>Lane 02 nibble 1 raw readback: 0053
09.658: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0053
09.658: <09>Lane 02 nibble 1 adjusted value (post nibble): 0054
09.658: <09>Lane 03 nibble 1 raw readback: 004e
09.658: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004e
09.658: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
09.658: <09>Lane 04 nibble 1 raw readback: 0049
09.658: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0049
09.658: <09>Lane 04 nibble 1 adjusted value (post nibble): 004b
09.658: <09>Lane 05 nibble 1 raw readback: 004f
09.658: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004f
09.658: <09>Lane 05 nibble 1 adjusted value (post nibble): 0050
09.658: <09>Lane 06 nibble 1 raw readback: 0056
09.658: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0056
09.658: <09>Lane 06 nibble 1 adjusted value (post nibble): 0056
09.658: <09>Lane 07 nibble 1 raw readback: 005d
09.658: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005d
09.658: <09>Lane 07 nibble 1 adjusted value (post nibble): 005d
09.658: <09>Lane 08 nibble 1 raw readback: 0048
09.658: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0048
09.658: <09>Lane 08 nibble 1 adjusted value (post nibble): 004a
09.658: <09>original critical gross delay: 0
09.658: <09>new critical gross delay: 0
09.659: DIMM 1 RttNom: 5
09.659: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.659: DIMM 1 RttNom: 5
09.659: DIMM 1 RttWr: 2
09.659: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.659: DIMM 1 RttWr: 2
09.659: DIMM 1 RttNom: 5
09.659: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.659: DIMM 1 RttNom: 5
09.659: DIMM 1 RttWr: 2
09.659: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.659: DIMM 1 RttWr: 2
09.659: DIMM 0 RttNom: 5
09.659: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.659: DIMM 1 RttNom: 5
09.659: DIMM 0 RttWr: 2
09.659: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.659: DIMM 1 RttWr: 2
09.659: DIMM 0 RttNom: 5
09.659: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.659: DIMM 1 RttNom: 5
09.659: DIMM 0 RttWr: 2
09.659: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.659: DIMM 1 RttWr: 2
09.659: SetTargetFreq: Start
09.659: SetTargetFreq: Node 1: New frequency code: 0012
09.659: ChangeMemClk: Start
09.659: set_2t_configuration: Start
09.659: set_2t_configuration: Done
09.659: mct_BeforePlatformSpec: Start
09.659: mct_BeforePlatformSpec: Done
09.659: mct_PlatformSpec: Start
09.659: Programmed DCT 0 timing/termination pattern 00353935 30222222
09.659: mct_PlatformSpec: Done
09.659: set_2t_configuration: Start
09.659: set_2t_configuration: Done
09.659: mct_BeforePlatformSpec: Start
09.659: mct_BeforePlatformSpec: Done
09.659: mct_PlatformSpec: Start
09.659: Programmed DCT 1 timing/termination pattern 00353935 30222222
09.659: mct_PlatformSpec: Done
09.660: ChangeMemClk: Done
09.660: phyAssistedMemFnceTraining: Start
09.660: phyAssistedMemFnceTraining: training node 1 DCT 0
09.660: phyAssistedMemFnceTraining: done training node 1 DCT 0
09.660: phyAssistedMemFnceTraining: training node 1 DCT 1
09.660: phyAssistedMemFnceTraining: done training node 1 DCT 1
09.660: phyAssistedMemFnceTraining: Done
09.660: InitPhyCompensation: DCT 0: Start
09.660: Waiting for predriver calibration to be applied...done!
09.660: InitPhyCompensation: DCT 0: Done
09.660: phyAssistedMemFnceTraining: Start
09.660: phyAssistedMemFnceTraining: training node 1 DCT 0
09.660: phyAssistedMemFnceTraining: done training node 1 DCT 0
09.660: phyAssistedMemFnceTraining: training node 1 DCT 1
09.660: phyAssistedMemFnceTraining: done training node 1 DCT 1
09.660: phyAssistedMemFnceTraining: Done
09.660: InitPhyCompensation: DCT 1: Start
09.660: Waiting for predriver calibration to be applied...done!
09.660: InitPhyCompensation: DCT 1: Done
09.660: Preparing to send DCT 0 DIMM 0 RC10: 03 (F2xA8: 02000300)
09.661: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.661: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
09.661: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.661: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
09.661: Preparing to send DCT 0 DIMM 1 RC10: 03 (F2xA8: 02000c00)
09.661: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.661: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
09.661: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.661: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
09.661: Preparing to send DCT 1 DIMM 0 RC10: 03 (F2xA8: 02000300)
09.661: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.661: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
09.661: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.661: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
09.661: Preparing to send DCT 1 DIMM 1 RC10: 03 (F2xA8: 02000c00)
09.661: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.661: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
09.661: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.661: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
09.661: SetTargetFreq: Done
09.661: SPD2ndTiming: Start
09.661: SPD2ndTiming: Done
09.661: mct_BeforeDramInit_Prod_D: Start
09.661: mct_ProgramODT_D: Start
09.661: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
09.661: mct_ProgramODT_D: Done
09.661: mct_BeforeDramInit_Prod_D: Done
09.661: mct_DramInit_Sw_D: Start
09.661: DIMM 0 RttWr: 1
09.661: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.661: mct_SendMrsCmd: Start
09.661: mct_SendMrsCmd: Done
09.661: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
09.661: mct_SendMrsCmd: Start
09.661: mct_SendMrsCmd: Done
09.662: DIMM 0 RttNom: 4
09.662: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.662: mct_SendMrsCmd: Start
09.662: mct_SendMrsCmd: Done
09.662: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001d78
09.662: mct_SendMrsCmd: Start
09.662: mct_SendMrsCmd: Done
09.662: DIMM 0 RttWr: 1
09.662: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.662: mct_SendMrsCmd: Start
09.662: mct_SendMrsCmd: Done
09.662: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
09.662: mct_SendMrsCmd: Start
09.662: mct_SendMrsCmd: Done
09.662: DIMM 0 RttNom: 4
09.662: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.662: mct_SendMrsCmd: Start
09.662: mct_SendMrsCmd: Done
09.662: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201d78
09.662: mct_SendMrsCmd: Start
09.662: mct_SendMrsCmd: Done
09.662: DIMM 1 RttWr: 1
09.662: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.662: mct_SendMrsCmd: Start
09.662: mct_SendMrsCmd: Done
09.662: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
09.662: mct_SendMrsCmd: Start
09.662: mct_SendMrsCmd: Done
09.662: DIMM 1 RttNom: 4
09.662: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.662: mct_SendMrsCmd: Start
09.662: mct_SendMrsCmd: Done
09.662: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401d78
09.662: mct_SendMrsCmd: Start
09.662: mct_SendMrsCmd: Done
09.662: DIMM 1 RttWr: 1
09.662: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.662: mct_SendMrsCmd: Start
09.662: mct_SendMrsCmd: Done
09.662: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
09.662: mct_SendMrsCmd: Start
09.662: mct_SendMrsCmd: Done
09.662: DIMM 1 RttNom: 4
09.662: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.662: mct_SendMrsCmd: Start
09.662: mct_SendMrsCmd: Done
09.662: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601d78
09.662: mct_SendMrsCmd: Start
09.662: mct_SendMrsCmd: Done
09.662: mct_DramInit_Sw_D: Done
09.662: AgesaHwWlPhase1: training nibble 0
09.662: DIMM 0 RttNom: 4
09.662: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.663: DIMM 0 RttWr: 1
09.663: DIMM 0 RttWr: 1
09.663: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.663: DIMM 0 RttWr: 1
09.663: DIMM 0 RttNom: 4
09.663: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.663: DIMM 0 RttNom: 4
09.663: DIMM 0 RttWr: 1
09.663: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.663: DIMM 0 RttWr: 1
09.663: DIMM 1 RttNom: 4
09.663: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.663: DIMM 0 RttNom: 4
09.663: DIMM 1 RttWr: 1
09.663: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.663: DIMM 0 RttWr: 1
09.663: DIMM 1 RttNom: 4
09.663: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.663: DIMM 0 RttNom: 4
09.663: DIMM 1 RttWr: 1
09.663: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.663: DIMM 0 RttWr: 1
09.663: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.663: <09>Lane 00 scaled delay: 005f
09.663: <09>Lane 00 new seed: 005f
09.663: <09>Lane 01 scaled delay: 0058
09.663: <09>Lane 01 new seed: 0058
09.663: <09>Lane 02 scaled delay: 0053
09.663: <09>Lane 02 new seed: 0053
09.663: <09>Lane 03 scaled delay: 0052
09.663: <09>Lane 03 new seed: 0052
09.663: <09>Lane 04 scaled delay: 0049
09.663: <09>Lane 04 new seed: 0049
09.663: <09>Lane 05 scaled delay: 0051
09.663: <09>Lane 05 new seed: 0051
09.663: <09>Lane 06 scaled delay: 0054
09.663: <09>Lane 06 new seed: 0054
09.663: <09>Lane 07 scaled delay: 005a
09.663: <09>Lane 07 new seed: 005a
09.663: <09>Lane 08 scaled delay: 0047
09.663: <09>Lane 08 new seed: 0047
09.663: <09>Lane 00 nibble 0 raw readback: 0065
09.663: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0065
09.663: <09>Lane 00 nibble 0 adjusted value (post nibble): 0065
09.663: <09>Lane 01 nibble 0 raw readback: 005c
09.663: <09>Lane 01 nibble 0 adjusted value (pre nibble): 005c
09.663: <09>Lane 01 nibble 0 adjusted value (post nibble): 005c
09.663: <09>Lane 02 nibble 0 raw readback: 0055
09.663: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0055
09.663: <09>Lane 02 nibble 0 adjusted value (post nibble): 0055
09.664: <09>Lane 03 nibble 0 raw readback: 0051
09.664: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0051
09.664: <09>Lane 03 nibble 0 adjusted value (post nibble): 0051
09.664: <09>Lane 04 nibble 0 raw readback: 004c
09.664: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004c
09.664: <09>Lane 04 nibble 0 adjusted value (post nibble): 004c
09.664: <09>Lane 05 nibble 0 raw readback: 0053
09.664: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0053
09.664: <09>Lane 05 nibble 0 adjusted value (post nibble): 0053
09.664: <09>Lane 06 nibble 0 raw readback: 0057
09.664: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0057
09.664: <09>Lane 06 nibble 0 adjusted value (post nibble): 0057
09.664: <09>Lane 07 nibble 0 raw readback: 005e
09.664: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005e
09.664: <09>Lane 07 nibble 0 adjusted value (post nibble): 005e
09.664: <09>Lane 08 nibble 0 raw readback: 0048
09.664: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0048
09.664: <09>Lane 08 nibble 0 adjusted value (post nibble): 0048
09.664: AgesaHwWlPhase1: training nibble 1
09.664: DIMM 0 RttNom: 4
09.664: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.664: DIMM 0 RttWr: 1
09.664: DIMM 0 RttWr: 1
09.664: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.664: DIMM 0 RttWr: 1
09.664: DIMM 0 RttNom: 4
09.664: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.664: DIMM 0 RttNom: 4
09.664: DIMM 0 RttWr: 1
09.664: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.664: DIMM 0 RttWr: 1
09.664: DIMM 1 RttNom: 4
09.664: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.664: DIMM 0 RttNom: 4
09.664: DIMM 1 RttWr: 1
09.664: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.664: DIMM 0 RttWr: 1
09.664: DIMM 1 RttNom: 4
09.664: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.664: DIMM 0 RttNom: 4
09.664: DIMM 1 RttWr: 1
09.664: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.664: DIMM 0 RttWr: 1
09.664: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.664: <09>Lane 00 new seed: 005f
09.664: <09>Lane 01 new seed: 0058
09.664: <09>Lane 02 new seed: 0053
09.664: <09>Lane 03 new seed: 0052
09.664: <09>Lane 04 new seed: 0049
09.664: <09>Lane 05 new seed: 0051
09.664: <09>Lane 06 new seed: 0054
09.664: <09>Lane 07 new seed: 005a
09.664: <09>Lane 08 new seed: 0047
09.664: <09>Lane 00 nibble 1 raw readback: 0064
09.664: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0064
09.664: <09>Lane 00 nibble 1 adjusted value (post nibble): 0061
09.664: <09>Lane 01 nibble 1 raw readback: 005c
09.664: <09>Lane 01 nibble 1 adjusted value (pre nibble): 005c
09.664: <09>Lane 01 nibble 1 adjusted value (post nibble): 005a
09.664: <09>Lane 02 nibble 1 raw readback: 0056
09.664: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0056
09.664: <09>Lane 02 nibble 1 adjusted value (post nibble): 0054
09.664: <09>Lane 03 nibble 1 raw readback: 0051
09.664: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0051
09.664: <09>Lane 03 nibble 1 adjusted value (post nibble): 0051
09.664: <09>Lane 04 nibble 1 raw readback: 004b
09.664: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004b
09.664: <09>Lane 04 nibble 1 adjusted value (post nibble): 004a
09.665: <09>Lane 05 nibble 1 raw readback: 0052
09.664: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0052
09.665: <09>Lane 05 nibble 1 adjusted value (post nibble): 0051
09.665: <09>Lane 06 nibble 1 raw readback: 0058
09.665: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0058
09.665: <09>Lane 06 nibble 1 adjusted value (post nibble): 0056
09.665: <09>Lane 07 nibble 1 raw readback: 005e
09.665: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005e
09.665: <09>Lane 07 nibble 1 adjusted value (post nibble): 005c
09.665: <09>Lane 08 nibble 1 raw readback: 0048
09.665: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0048
09.665: <09>Lane 08 nibble 1 adjusted value (post nibble): 0047
09.665: <09>original critical gross delay: 0
09.665: <09>new critical gross delay: 0
09.665: DIMM 0 RttNom: 4
09.665: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.665: DIMM 0 RttNom: 4
09.665: DIMM 0 RttWr: 1
09.665: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.665: DIMM 0 RttWr: 1
09.665: DIMM 0 RttNom: 4
09.665: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.665: DIMM 0 RttNom: 4
09.665: DIMM 0 RttWr: 1
09.665: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.665: DIMM 0 RttWr: 1
09.665: DIMM 1 RttNom: 4
09.665: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.665: DIMM 0 RttNom: 4
09.665: DIMM 1 RttWr: 1
09.665: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.665: DIMM 0 RttWr: 1
09.665: DIMM 1 RttNom: 4
09.665: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.665: DIMM 0 RttNom: 4
09.665: DIMM 1 RttWr: 1
09.665: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.665: DIMM 0 RttWr: 1
09.665: AgesaHwWlPhase1: training nibble 0
09.665: DIMM 1 RttNom: 4
09.665: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.665: DIMM 1 RttWr: 1
09.665: DIMM 1 RttWr: 1
09.665: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.665: DIMM 1 RttWr: 1
09.665: DIMM 1 RttNom: 4
09.665: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.665: DIMM 1 RttNom: 4
09.665: DIMM 1 RttWr: 1
09.665: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.665: DIMM 1 RttWr: 1
09.665: DIMM 0 RttNom: 4
09.665: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.665: DIMM 1 RttNom: 4
09.665: DIMM 0 RttWr: 1
09.665: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.665: DIMM 1 RttWr: 1
09.665: DIMM 0 RttNom: 4
09.665: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.665: DIMM 1 RttNom: 4
09.666: DIMM 0 RttWr: 1
09.666: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.666: DIMM 1 RttWr: 1
09.666: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.666: <09>Lane 00 scaled delay: 0069
09.666: <09>Lane 00 new seed: 0069
09.666: <09>Lane 01 scaled delay: 0060
09.666: <09>Lane 01 new seed: 0060
09.666: <09>Lane 02 scaled delay: 005a
09.666: <09>Lane 02 new seed: 005a
09.666: <09>Lane 03 scaled delay: 0058
09.666: <09>Lane 03 new seed: 0058
09.666: <09>Lane 04 scaled delay: 0052
09.666: <09>Lane 04 new seed: 0052
09.666: <09>Lane 05 scaled delay: 0059
09.666: <09>Lane 05 new seed: 0059
09.666: <09>Lane 06 scaled delay: 005d
09.666: <09>Lane 06 new seed: 005d
09.666: <09>Lane 07 scaled delay: 0063
09.666: <09>Lane 07 new seed: 0063
09.666: <09>Lane 08 scaled delay: 0051
09.666: <09>Lane 08 new seed: 0051
09.666: <09>Lane 00 nibble 0 raw readback: 0030
09.666: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0070
09.666: <09>Lane 00 nibble 0 adjusted value (post nibble): 0070
09.666: <09>Lane 01 nibble 0 raw readback: 0026
09.666: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0066
09.666: <09>Lane 01 nibble 0 adjusted value (post nibble): 0066
09.666: <09>Lane 02 nibble 0 raw readback: 005d
09.666: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005d
09.666: <09>Lane 02 nibble 0 adjusted value (post nibble): 005d
09.666: <09>Lane 03 nibble 0 raw readback: 005c
09.666: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005c
09.666: <09>Lane 03 nibble 0 adjusted value (post nibble): 005c
09.666: <09>Lane 04 nibble 0 raw readback: 0057
09.666: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0057
09.666: <09>Lane 04 nibble 0 adjusted value (post nibble): 0057
09.666: <09>Lane 05 nibble 0 raw readback: 005f
09.666: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005f
09.666: <09>Lane 05 nibble 0 adjusted value (post nibble): 005f
09.666: <09>Lane 06 nibble 0 raw readback: 0060
09.666: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0060
09.666: <09>Lane 06 nibble 0 adjusted value (post nibble): 0060
09.666: <09>Lane 07 nibble 0 raw readback: 0029
09.666: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0069
09.666: <09>Lane 07 nibble 0 adjusted value (post nibble): 0069
09.666: <09>Lane 08 nibble 0 raw readback: 0052
09.666: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0052
09.666: <09>Lane 08 nibble 0 adjusted value (post nibble): 0052
09.666: AgesaHwWlPhase1: training nibble 1
09.666: DIMM 1 RttNom: 4
09.666: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.666: DIMM 1 RttWr: 1
09.666: DIMM 1 RttWr: 1
09.666: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.666: DIMM 1 RttWr: 1
09.666: DIMM 1 RttNom: 4
09.666: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.666: DIMM 1 RttNom: 4
09.666: DIMM 1 RttWr: 1
09.666: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.666: DIMM 1 RttWr: 1
09.666: DIMM 0 RttNom: 4
09.666: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.666: DIMM 1 RttNom: 4
09.666: DIMM 0 RttWr: 1
09.666: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.666: DIMM 1 RttWr: 1
09.666: DIMM 0 RttNom: 4
09.666: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.666: DIMM 1 RttNom: 4
09.666: DIMM 0 RttWr: 1
09.666: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.667: DIMM 1 RttWr: 1
09.667: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.667: <09>Lane 00 new seed: 0069
09.667: <09>Lane 01 new seed: 0060
09.667: <09>Lane 02 new seed: 005a
09.667: <09>Lane 03 new seed: 0058
09.667: <09>Lane 04 new seed: 0052
09.667: <09>Lane 05 new seed: 0059
09.667: <09>Lane 06 new seed: 005d
09.667: <09>Lane 07 new seed: 0063
09.667: <09>Lane 08 new seed: 0051
09.667: <09>Lane 00 nibble 1 raw readback: 0030
09.667: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0070
09.667: <09>Lane 00 nibble 1 adjusted value (post nibble): 006c
09.667: <09>Lane 01 nibble 1 raw readback: 0025
09.667: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0065
09.667: <09>Lane 01 nibble 1 adjusted value (post nibble): 0062
09.667: <09>Lane 02 nibble 1 raw readback: 005d
09.667: <09>Lane 02 nibble 1 adjusted value (pre nibble): 005d
09.667: <09>Lane 02 nibble 1 adjusted value (post nibble): 005b
09.667: <09>Lane 03 nibble 1 raw readback: 005b
09.667: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005b
09.667: <09>Lane 03 nibble 1 adjusted value (post nibble): 0059
09.667: <09>Lane 04 nibble 1 raw readback: 0054
09.667: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0054
09.667: <09>Lane 04 nibble 1 adjusted value (post nibble): 0053
09.667: <09>Lane 05 nibble 1 raw readback: 005c
09.667: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005c
09.667: <09>Lane 05 nibble 1 adjusted value (post nibble): 005a
09.667: <09>Lane 06 nibble 1 raw readback: 0061
09.667: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0061
09.667: <09>Lane 06 nibble 1 adjusted value (post nibble): 005f
09.667: <09>Lane 07 nibble 1 raw readback: 0028
09.667: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0068
09.667: <09>Lane 07 nibble 1 adjusted value (post nibble): 0065
09.667: <09>Lane 08 nibble 1 raw readback: 0054
09.667: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0054
09.667: <09>Lane 08 nibble 1 adjusted value (post nibble): 0052
09.667: <09>original critical gross delay: 0
09.667: <09>new critical gross delay: 0
09.667: DIMM 1 RttNom: 4
09.667: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.667: DIMM 1 RttNom: 4
09.667: DIMM 1 RttWr: 1
09.667: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.667: DIMM 1 RttWr: 1
09.667: DIMM 1 RttNom: 4
09.667: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.667: DIMM 1 RttNom: 4
09.667: DIMM 1 RttWr: 1
09.667: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.667: DIMM 1 RttWr: 1
09.667: DIMM 0 RttNom: 4
09.667: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.667: DIMM 1 RttNom: 4
09.667: DIMM 0 RttWr: 1
09.667: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.667: DIMM 1 RttWr: 1
09.667: DIMM 0 RttNom: 4
09.667: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.667: DIMM 1 RttNom: 4
09.668: DIMM 0 RttWr: 1
09.667: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.667: DIMM 1 RttWr: 1
09.668: SPD2ndTiming: Start
09.668: SPD2ndTiming: Done
09.668: mct_BeforeDramInit_Prod_D: Start
09.668: mct_ProgramODT_D: Start
09.668: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
09.668: mct_ProgramODT_D: Done
09.668: mct_BeforeDramInit_Prod_D: Done
09.668: mct_DramInit_Sw_D: Start
09.668: DIMM 0 RttWr: 1
09.668: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.668: mct_SendMrsCmd: Start
09.668: mct_SendMrsCmd: Done
09.668: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
09.668: mct_SendMrsCmd: Start
09.668: mct_SendMrsCmd: Done
09.668: DIMM 0 RttNom: 4
09.668: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.668: mct_SendMrsCmd: Start
09.668: mct_SendMrsCmd: Done
09.668: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001d78
09.668: mct_SendMrsCmd: Start
09.668: mct_SendMrsCmd: Done
09.668: DIMM 0 RttWr: 1
09.668: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.668: mct_SendMrsCmd: Start
09.668: mct_SendMrsCmd: Done
09.668: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
09.668: mct_SendMrsCmd: Start
09.668: mct_SendMrsCmd: Done
09.668: DIMM 0 RttNom: 4
09.668: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.668: mct_SendMrsCmd: Start
09.668: mct_SendMrsCmd: Done
09.668: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201d78
09.668: mct_SendMrsCmd: Start
09.668: mct_SendMrsCmd: Done
09.668: DIMM 1 RttWr: 1
09.669: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.668: mct_SendMrsCmd: Start
09.669: mct_SendMrsCmd: Done
09.669: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
09.669: mct_SendMrsCmd: Start
09.669: mct_SendMrsCmd: Done
09.669: DIMM 1 RttNom: 4
09.669: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.669: mct_SendMrsCmd: Start
09.669: mct_SendMrsCmd: Done
09.669: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401d78
09.669: mct_SendMrsCmd: Start
09.669: mct_SendMrsCmd: Done
09.669: DIMM 1 RttWr: 1
09.669: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.669: mct_SendMrsCmd: Start
09.669: mct_SendMrsCmd: Done
09.669: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
09.669: mct_SendMrsCmd: Start
09.669: mct_SendMrsCmd: Done
09.669: DIMM 1 RttNom: 4
09.669: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.669: mct_SendMrsCmd: Start
09.669: mct_SendMrsCmd: Done
09.669: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601d78
09.669: mct_SendMrsCmd: Start
09.669: mct_SendMrsCmd: Done
09.669: mct_DramInit_Sw_D: Done
09.669: AgesaHwWlPhase1: training nibble 0
09.669: DIMM 0 RttNom: 4
09.669: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.669: DIMM 0 RttWr: 1
09.669: DIMM 0 RttWr: 1
09.669: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.669: DIMM 0 RttWr: 1
09.669: DIMM 0 RttNom: 4
09.669: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.669: DIMM 0 RttNom: 4
09.669: DIMM 0 RttWr: 1
09.669: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.669: DIMM 0 RttWr: 1
09.669: DIMM 1 RttNom: 4
09.669: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.669: DIMM 0 RttNom: 4
09.669: DIMM 1 RttWr: 1
09.669: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.669: DIMM 0 RttWr: 1
09.669: DIMM 1 RttNom: 4
09.669: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.669: DIMM 0 RttNom: 4
09.669: DIMM 1 RttWr: 1
09.669: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.669: DIMM 0 RttWr: 1
09.669: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.669: <09>Lane 00 scaled delay: 0063
09.669: <09>Lane 00 new seed: 0063
09.669: <09>Lane 01 scaled delay: 005b
09.669: <09>Lane 01 new seed: 005b
09.669: <09>Lane 02 scaled delay: 0055
09.669: <09>Lane 02 new seed: 0055
09.669: <09>Lane 03 scaled delay: 0051
09.670: <09>Lane 03 new seed: 0051
09.670: <09>Lane 04 scaled delay: 004c
09.670: <09>Lane 04 new seed: 004c
09.670: <09>Lane 05 scaled delay: 0053
09.670: <09>Lane 05 new seed: 0053
09.670: <09>Lane 06 scaled delay: 0059
09.670: <09>Lane 06 new seed: 0059
09.670: <09>Lane 07 scaled delay: 0061
09.670: <09>Lane 07 new seed: 0061
09.670: <09>Lane 08 scaled delay: 0048
09.670: <09>Lane 08 new seed: 0048
09.670: <09>Lane 00 nibble 0 raw readback: 0027
09.670: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0067
09.670: <09>Lane 00 nibble 0 adjusted value (post nibble): 0067
09.670: <09>Lane 01 nibble 0 raw readback: 005d
09.670: <09>Lane 01 nibble 0 adjusted value (pre nibble): 005d
09.670: <09>Lane 01 nibble 0 adjusted value (post nibble): 005d
09.670: <09>Lane 02 nibble 0 raw readback: 0056
09.670: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0056
09.670: <09>Lane 02 nibble 0 adjusted value (post nibble): 0056
09.670: <09>Lane 03 nibble 0 raw readback: 004f
09.670: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004f
09.670: <09>Lane 03 nibble 0 adjusted value (post nibble): 004f
09.670: <09>Lane 04 nibble 0 raw readback: 004c
09.670: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004c
09.670: <09>Lane 04 nibble 0 adjusted value (post nibble): 004c
09.670: <09>Lane 05 nibble 0 raw readback: 0056
09.670: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0056
09.670: <09>Lane 05 nibble 0 adjusted value (post nibble): 0056
09.670: <09>Lane 06 nibble 0 raw readback: 005a
09.670: <09>Lane 06 nibble 0 adjusted value (pre nibble): 005a
09.670: <09>Lane 06 nibble 0 adjusted value (post nibble): 005a
09.670: <09>Lane 07 nibble 0 raw readback: 0021
09.670: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0061
09.670: <09>Lane 07 nibble 0 adjusted value (post nibble): 0061
09.670: <09>Lane 08 nibble 0 raw readback: 004a
09.670: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004a
09.670: <09>Lane 08 nibble 0 adjusted value (post nibble): 004a
09.670: AgesaHwWlPhase1: training nibble 1
09.670: DIMM 0 RttNom: 4
09.670: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.670: DIMM 0 RttWr: 1
09.670: DIMM 0 RttWr: 1
09.670: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.670: DIMM 0 RttWr: 1
09.670: DIMM 0 RttNom: 4
09.670: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.670: DIMM 0 RttNom: 4
09.670: DIMM 0 RttWr: 1
09.670: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.670: DIMM 0 RttWr: 1
09.670: DIMM 1 RttNom: 4
09.670: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.670: DIMM 0 RttNom: 4
09.670: DIMM 1 RttWr: 1
09.670: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.670: DIMM 0 RttWr: 1
09.670: DIMM 1 RttNom: 4
09.670: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.670: DIMM 0 RttNom: 4
09.670: DIMM 1 RttWr: 1
09.670: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.670: DIMM 0 RttWr: 1
09.670: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.671: <09>Lane 00 new seed: 0063
09.671: <09>Lane 01 new seed: 005b
09.671: <09>Lane 02 new seed: 0055
09.671: <09>Lane 03 new seed: 0051
09.671: <09>Lane 04 new seed: 004c
09.671: <09>Lane 05 new seed: 0053
09.671: <09>Lane 06 new seed: 0059
09.671: <09>Lane 07 new seed: 0061
09.671: <09>Lane 08 new seed: 0048
09.671: <09>Lane 00 nibble 1 raw readback: 0026
09.671: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0066
09.671: <09>Lane 00 nibble 1 adjusted value (post nibble): 0064
09.671: <09>Lane 01 nibble 1 raw readback: 005e
09.671: <09>Lane 01 nibble 1 adjusted value (pre nibble): 005e
09.671: <09>Lane 01 nibble 1 adjusted value (post nibble): 005c
09.671: <09>Lane 02 nibble 1 raw readback: 0056
09.671: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0056
09.671: <09>Lane 02 nibble 1 adjusted value (post nibble): 0055
09.671: <09>Lane 03 nibble 1 raw readback: 0050
09.671: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0050
09.671: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
09.671: <09>Lane 04 nibble 1 raw readback: 004c
09.671: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004c
09.671: <09>Lane 04 nibble 1 adjusted value (post nibble): 004c
09.671: <09>Lane 05 nibble 1 raw readback: 0054
09.671: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0054
09.671: <09>Lane 05 nibble 1 adjusted value (post nibble): 0053
09.671: <09>Lane 06 nibble 1 raw readback: 005b
09.671: <09>Lane 06 nibble 1 adjusted value (pre nibble): 005b
09.671: <09>Lane 06 nibble 1 adjusted value (post nibble): 005a
09.671: <09>Lane 07 nibble 1 raw readback: 0024
09.671: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0064
09.671: <09>Lane 07 nibble 1 adjusted value (post nibble): 0062
09.671: <09>Lane 08 nibble 1 raw readback: 0049
09.671: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0049
09.671: <09>Lane 08 nibble 1 adjusted value (post nibble): 0048
09.671: <09>original critical gross delay: 0
09.671: <09>new critical gross delay: 0
09.671: DIMM 0 RttNom: 4
09.671: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.671: DIMM 0 RttNom: 4
09.671: DIMM 0 RttWr: 1
09.671: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.671: DIMM 0 RttWr: 1
09.671: DIMM 0 RttNom: 4
09.671: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.671: DIMM 0 RttNom: 4
09.671: DIMM 0 RttWr: 1
09.671: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.671: DIMM 0 RttWr: 1
09.671: DIMM 1 RttNom: 4
09.671: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.671: DIMM 0 RttNom: 4
09.671: DIMM 1 RttWr: 1
09.671: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.671: DIMM 0 RttWr: 1
09.671: DIMM 1 RttNom: 4
09.671: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.671: DIMM 0 RttNom: 4
09.671: DIMM 1 RttWr: 1
09.671: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.671: DIMM 0 RttWr: 1
09.671: AgesaHwWlPhase1: training nibble 0
09.672: DIMM 1 RttNom: 4
09.672: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.672: DIMM 1 RttWr: 1
09.672: DIMM 1 RttWr: 1
09.672: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.672: DIMM 1 RttWr: 1
09.672: DIMM 1 RttNom: 4
09.672: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.672: DIMM 1 RttNom: 4
09.672: DIMM 1 RttWr: 1
09.672: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.672: DIMM 1 RttWr: 1
09.672: DIMM 0 RttNom: 4
09.672: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.672: DIMM 1 RttNom: 4
09.672: DIMM 0 RttWr: 1
09.672: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.672: DIMM 1 RttWr: 1
09.672: DIMM 0 RttNom: 4
09.672: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.672: DIMM 1 RttNom: 4
09.672: DIMM 0 RttWr: 1
09.672: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.672: DIMM 1 RttWr: 1
09.672: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.672: <09>Lane 00 scaled delay: 006b
09.672: <09>Lane 00 new seed: 006b
09.672: <09>Lane 01 scaled delay: 0064
09.672: <09>Lane 01 new seed: 0064
09.672: <09>Lane 02 scaled delay: 005e
09.672: <09>Lane 02 new seed: 005e
09.672: <09>Lane 03 scaled delay: 0059
09.672: <09>Lane 03 new seed: 0059
09.672: <09>Lane 04 scaled delay: 0053
09.672: <09>Lane 04 new seed: 0053
09.672: <09>Lane 05 scaled delay: 0059
09.672: <09>Lane 05 new seed: 0059
09.672: <09>Lane 06 scaled delay: 0060
09.672: <09>Lane 06 new seed: 0060
09.672: <09>Lane 07 scaled delay: 0069
09.672: <09>Lane 07 new seed: 0069
09.672: <09>Lane 08 scaled delay: 0052
09.672: <09>Lane 08 new seed: 0052
09.672: <09>Lane 00 nibble 0 raw readback: 0029
09.672: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0069
09.672: <09>Lane 00 nibble 0 adjusted value (post nibble): 0069
09.672: <09>Lane 01 nibble 0 raw readback: 0027
09.672: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0067
09.672: <09>Lane 01 nibble 0 adjusted value (post nibble): 0067
09.672: <09>Lane 02 nibble 0 raw readback: 005e
09.672: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005e
09.672: <09>Lane 02 nibble 0 adjusted value (post nibble): 005e
09.672: <09>Lane 03 nibble 0 raw readback: 0057
09.672: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0057
09.672: <09>Lane 03 nibble 0 adjusted value (post nibble): 0057
09.672: <09>Lane 04 nibble 0 raw readback: 0055
09.672: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0055
09.672: <09>Lane 04 nibble 0 adjusted value (post nibble): 0055
09.672: <09>Lane 05 nibble 0 raw readback: 005d
09.672: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005d
09.672: <09>Lane 05 nibble 0 adjusted value (post nibble): 005d
09.672: <09>Lane 06 nibble 0 raw readback: 0024
09.672: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0064
09.672: <09>Lane 06 nibble 0 adjusted value (post nibble): 0064
09.672: <09>Lane 07 nibble 0 raw readback: 0028
09.672: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0068
09.672: <09>Lane 07 nibble 0 adjusted value (post nibble): 0068
09.672: <09>Lane 08 nibble 0 raw readback: 0050
09.672: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0050
09.672: <09>Lane 08 nibble 0 adjusted value (post nibble): 0050
09.672: AgesaHwWlPhase1: training nibble 1
09.672: DIMM 1 RttNom: 4
09.673: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.673: DIMM 1 RttWr: 1
09.673: DIMM 1 RttWr: 1
09.673: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.673: DIMM 1 RttWr: 1
09.673: DIMM 1 RttNom: 4
09.673: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.673: DIMM 1 RttNom: 4
09.673: DIMM 1 RttWr: 1
09.673: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.673: DIMM 1 RttWr: 1
09.673: DIMM 0 RttNom: 4
09.673: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.673: DIMM 1 RttNom: 4
09.673: DIMM 0 RttWr: 1
09.673: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.673: DIMM 1 RttWr: 1
09.673: DIMM 0 RttNom: 4
09.673: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.673: DIMM 1 RttNom: 4
09.673: DIMM 0 RttWr: 1
09.673: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.673: DIMM 1 RttWr: 1
09.673: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.673: <09>Lane 00 new seed: 006b
09.673: <09>Lane 01 new seed: 0064
09.673: <09>Lane 02 new seed: 005e
09.673: <09>Lane 03 new seed: 0059
09.673: <09>Lane 04 new seed: 0053
09.673: <09>Lane 05 new seed: 0059
09.673: <09>Lane 06 new seed: 0060
09.673: <09>Lane 07 new seed: 0069
09.673: <09>Lane 08 new seed: 0052
09.673: <09>Lane 00 nibble 1 raw readback: 002f
09.673: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006f
09.673: <09>Lane 00 nibble 1 adjusted value (post nibble): 006d
09.673: <09>Lane 01 nibble 1 raw readback: 0027
09.673: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0067
09.673: <09>Lane 01 nibble 1 adjusted value (post nibble): 0065
09.673: <09>Lane 02 nibble 1 raw readback: 005e
09.673: <09>Lane 02 nibble 1 adjusted value (pre nibble): 005e
09.673: <09>Lane 02 nibble 1 adjusted value (post nibble): 005e
09.673: <09>Lane 03 nibble 1 raw readback: 0059
09.673: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0059
09.673: <09>Lane 03 nibble 1 adjusted value (post nibble): 0059
09.673: <09>Lane 04 nibble 1 raw readback: 0053
09.673: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0053
09.673: <09>Lane 04 nibble 1 adjusted value (post nibble): 0053
09.673: <09>Lane 05 nibble 1 raw readback: 005a
09.673: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005a
09.673: <09>Lane 05 nibble 1 adjusted value (post nibble): 0059
09.673: <09>Lane 06 nibble 1 raw readback: 0022
09.673: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0062
09.673: <09>Lane 06 nibble 1 adjusted value (post nibble): 0061
09.673: <09>Lane 07 nibble 1 raw readback: 002b
09.673: <09>Lane 07 nibble 1 adjusted value (pre nibble): 006b
09.673: <09>Lane 07 nibble 1 adjusted value (post nibble): 006a
09.673: <09>Lane 08 nibble 1 raw readback: 0052
09.673: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0052
09.673: <09>Lane 08 nibble 1 adjusted value (post nibble): 0052
09.673: <09>original critical gross delay: 0
09.673: <09>new critical gross delay: 0
09.674: DIMM 1 RttNom: 4
09.673: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.673: DIMM 1 RttNom: 4
09.674: DIMM 1 RttWr: 1
09.673: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.674: DIMM 1 RttWr: 1
09.674: DIMM 1 RttNom: 4
09.674: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.674: DIMM 1 RttNom: 4
09.674: DIMM 1 RttWr: 1
09.674: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.674: DIMM 1 RttWr: 1
09.674: DIMM 0 RttNom: 4
09.674: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.674: DIMM 1 RttNom: 4
09.674: DIMM 0 RttWr: 1
09.674: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.674: DIMM 1 RttWr: 1
09.674: DIMM 0 RttNom: 4
09.674: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.674: DIMM 1 RttNom: 4
09.674: DIMM 0 RttWr: 1
09.674: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.674: DIMM 1 RttWr: 1
09.674: activate_spd_rom() for node 02
09.674: enable_spd_node2()
09.674: SetTargetFreq: Start
09.674: SetTargetFreq: Node 2: New frequency code: 0006
09.674: ChangeMemClk: Start
09.674: set_2t_configuration: Start
09.674: set_2t_configuration: Done
09.675: mct_BeforePlatformSpec: Start
09.675: mct_BeforePlatformSpec: Done
09.675: mct_PlatformSpec: Start
09.675: Programmed DCT 0 timing/termination pattern 00000000 20222222
09.675: mct_PlatformSpec: Done
09.675: set_2t_configuration: Start
09.675: set_2t_configuration: Done
09.675: mct_BeforePlatformSpec: Start
09.675: mct_BeforePlatformSpec: Done
09.675: mct_PlatformSpec: Start
09.675: Programmed DCT 1 timing/termination pattern 00000000 20222222
09.675: mct_PlatformSpec: Done
09.675: ChangeMemClk: Done
09.675: phyAssistedMemFnceTraining: Start
09.675: phyAssistedMemFnceTraining: training node 2 DCT 0
09.675: phyAssistedMemFnceTraining: done training node 2 DCT 0
09.675: phyAssistedMemFnceTraining: training node 2 DCT 1
09.675: phyAssistedMemFnceTraining: done training node 2 DCT 1
09.675: phyAssistedMemFnceTraining: Done
09.675: InitPhyCompensation: DCT 0: Start
09.675: Waiting for predriver calibration to be applied...done!
09.675: InitPhyCompensation: DCT 0: Done
09.675: phyAssistedMemFnceTraining: Start
09.675: phyAssistedMemFnceTraining: training node 2 DCT 0
09.676: phyAssistedMemFnceTraining: done training node 2 DCT 0
09.676: phyAssistedMemFnceTraining: training node 2 DCT 1
09.676: phyAssistedMemFnceTraining: done training node 2 DCT 1
09.676: phyAssistedMemFnceTraining: Done
09.676: InitPhyCompensation: DCT 1: Start
09.676: Waiting for predriver calibration to be applied...done!
09.676: InitPhyCompensation: DCT 1: Done
09.676: Preparing to send DCT 0 DIMM 0 RC10: 00 (F2xA8: 02000300)
09.676: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.676: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
09.676: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.676: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
09.676: Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 02000c00)
09.676: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.676: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
09.676: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.676: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
09.676: Preparing to send DCT 1 DIMM 0 RC10: 00 (F2xA8: 02000300)
09.676: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.676: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
09.676: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.676: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
09.676: Preparing to send DCT 1 DIMM 1 RC10: 00 (F2xA8: 02000c00)
09.676: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.676: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
09.676: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.676: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
09.676: SetTargetFreq: Done
09.676: SPD2ndTiming: Start
09.677: SPD2ndTiming: Done
09.677: mct_BeforeDramInit_Prod_D: Start
09.677: mct_ProgramODT_D: Start
09.677: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
09.677: mct_ProgramODT_D: Done
09.677: mct_BeforeDramInit_Prod_D: Done
09.677: mct_DramInit_Sw_D: Start
09.677: DIMM 0 RttWr: 2
09.677: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.677: mct_SendMrsCmd: Start
09.677: mct_SendMrsCmd: Done
09.677: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
09.677: mct_SendMrsCmd: Start
09.677: mct_SendMrsCmd: Done
09.677: DIMM 0 RttNom: 3
09.677: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.677: mct_SendMrsCmd: Start
09.677: mct_SendMrsCmd: Done
09.677: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001578
09.677: mct_SendMrsCmd: Start
09.677: mct_SendMrsCmd: Done
09.677: DIMM 0 RttWr: 2
09.677: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.677: mct_SendMrsCmd: Start
09.677: mct_SendMrsCmd: Done
09.677: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
09.677: mct_SendMrsCmd: Start
09.677: mct_SendMrsCmd: Done
09.677: DIMM 0 RttNom: 3
09.677: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.677: mct_SendMrsCmd: Start
09.677: mct_SendMrsCmd: Done
09.677: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201578
09.677: mct_SendMrsCmd: Start
09.677: mct_SendMrsCmd: Done
09.677: DIMM 1 RttWr: 2
09.677: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.677: mct_SendMrsCmd: Start
09.677: mct_SendMrsCmd: Done
09.677: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
09.677: mct_SendMrsCmd: Start
09.677: mct_SendMrsCmd: Done
09.677: DIMM 1 RttNom: 3
09.677: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.677: mct_SendMrsCmd: Start
09.678: mct_SendMrsCmd: Done
09.678: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401578
09.678: mct_SendMrsCmd: Start
09.678: mct_SendMrsCmd: Done
09.678: DIMM 1 RttWr: 2
09.678: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.678: mct_SendMrsCmd: Start
09.678: mct_SendMrsCmd: Done
09.678: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
09.678: mct_SendMrsCmd: Start
09.678: mct_SendMrsCmd: Done
09.678: DIMM 1 RttNom: 3
09.678: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.678: mct_SendMrsCmd: Start
09.678: mct_SendMrsCmd: Done
09.678: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601578
09.678: mct_SendMrsCmd: Start
09.678: mct_SendMrsCmd: Done
09.678: mct_DramInit_Sw_D: Done
09.678: AgesaHwWlPhase1: training nibble 0
09.678: DIMM 0 RttNom: 3
09.678: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.678: DIMM 0 RttWr: 2
09.678: DIMM 0 RttWr: 2
09.678: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.678: DIMM 0 RttWr: 2
09.678: DIMM 0 RttNom: 3
09.678: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.678: DIMM 0 RttNom: 3
09.678: DIMM 0 RttWr: 2
09.678: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.678: DIMM 0 RttWr: 2
09.678: DIMM 1 RttNom: 3
09.678: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.678: DIMM 0 RttNom: 3
09.678: DIMM 1 RttWr: 2
09.678: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.678: DIMM 0 RttWr: 2
09.678: DIMM 1 RttNom: 3
09.678: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.678: DIMM 0 RttNom: 3
09.678: DIMM 1 RttWr: 2
09.678: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.678: DIMM 0 RttWr: 2
09.678: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.678: <09>Lane 00 scaled delay: 0047
09.679: <09>Lane 00 new seed: 0047
09.679: <09>Lane 01 scaled delay: 0047
09.679: <09>Lane 01 new seed: 0047
09.679: <09>Lane 02 scaled delay: 0047
09.679: <09>Lane 02 new seed: 0047
09.679: <09>Lane 03 scaled delay: 0047
09.679: <09>Lane 03 new seed: 0047
09.679: <09>Lane 04 scaled delay: 0047
09.679: <09>Lane 04 new seed: 0047
09.679: <09>Lane 05 scaled delay: 0047
09.679: <09>Lane 05 new seed: 0047
09.679: <09>Lane 06 scaled delay: 0047
09.679: <09>Lane 06 new seed: 0047
09.679: <09>Lane 07 scaled delay: 0047
09.679: <09>Lane 07 new seed: 0047
09.679: <09>Lane 08 scaled delay: 0047
09.679: <09>Lane 08 new seed: 0047
09.679: <09>Lane 00 nibble 0 raw readback: 004f
09.679: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004f
09.679: <09>Lane 00 nibble 0 adjusted value (post nibble): 004f
09.679: <09>Lane 01 nibble 0 raw readback: 0048
09.679: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0048
09.679: <09>Lane 01 nibble 0 adjusted value (post nibble): 0048
09.679: <09>Lane 02 nibble 0 raw readback: 0047
09.679: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0047
09.679: <09>Lane 02 nibble 0 adjusted value (post nibble): 0047
09.679: <09>Lane 03 nibble 0 raw readback: 0044
09.679: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
09.679: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
09.679: <09>Lane 04 nibble 0 raw readback: 003b
09.679: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003b
09.679: <09>Lane 04 nibble 0 adjusted value (post nibble): 003b
09.679: <09>Lane 05 nibble 0 raw readback: 003e
09.679: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003e
09.679: <09>Lane 05 nibble 0 adjusted value (post nibble): 003e
09.679: <09>Lane 06 nibble 0 raw readback: 0040
09.679: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
09.679: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
09.679: <09>Lane 07 nibble 0 raw readback: 0043
09.679: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0043
09.679: <09>Lane 07 nibble 0 adjusted value (post nibble): 0043
09.679: <09>Lane 08 nibble 0 raw readback: 003c
09.679: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003c
09.679: <09>Lane 08 nibble 0 adjusted value (post nibble): 003c
09.679: AgesaHwWlPhase1: training nibble 1
09.679: DIMM 0 RttNom: 3
09.679: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.679: DIMM 0 RttWr: 2
09.679: DIMM 0 RttWr: 2
09.679: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.679: DIMM 0 RttWr: 2
09.679: DIMM 0 RttNom: 3
09.679: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.679: DIMM 0 RttNom: 3
09.679: DIMM 0 RttWr: 2
09.679: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.679: DIMM 0 RttWr: 2
09.679: DIMM 1 RttNom: 3
09.679: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.679: DIMM 0 RttNom: 3
09.680: DIMM 1 RttWr: 2
09.680: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.680: DIMM 0 RttWr: 2
09.680: DIMM 1 RttNom: 3
09.680: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.680: DIMM 0 RttNom: 3
09.680: DIMM 1 RttWr: 2
09.680: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.680: DIMM 0 RttWr: 2
09.680: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.680: <09>Lane 00 new seed: 0047
09.680: <09>Lane 01 new seed: 0047
09.680: <09>Lane 02 new seed: 0047
09.680: <09>Lane 03 new seed: 0047
09.680: <09>Lane 04 new seed: 0047
09.680: <09>Lane 05 new seed: 0047
09.680: <09>Lane 06 new seed: 0047
09.680: <09>Lane 07 new seed: 0047
09.680: <09>Lane 08 new seed: 0047
09.680: <09>Lane 00 nibble 1 raw readback: 004f
09.680: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004f
09.680: <09>Lane 00 nibble 1 adjusted value (post nibble): 004b
09.680: <09>Lane 01 nibble 1 raw readback: 004a
09.680: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004a
09.680: <09>Lane 01 nibble 1 adjusted value (post nibble): 0048
09.680: <09>Lane 02 nibble 1 raw readback: 0048
09.680: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0048
09.680: <09>Lane 02 nibble 1 adjusted value (post nibble): 0047
09.680: <09>Lane 03 nibble 1 raw readback: 0045
09.680: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
09.680: <09>Lane 03 nibble 1 adjusted value (post nibble): 0046
09.680: <09>Lane 04 nibble 1 raw readback: 0039
09.680: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
09.680: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
09.680: <09>Lane 05 nibble 1 raw readback: 003e
09.680: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003e
09.680: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
09.680: <09>Lane 06 nibble 1 raw readback: 0041
09.680: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0041
09.680: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
09.680: <09>Lane 07 nibble 1 raw readback: 0043
09.680: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0043
09.680: <09>Lane 07 nibble 1 adjusted value (post nibble): 0045
09.680: <09>Lane 08 nibble 1 raw readback: 003b
09.680: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003b
09.680: <09>Lane 08 nibble 1 adjusted value (post nibble): 0041
09.680: <09>original critical gross delay: 0
09.680: <09>new critical gross delay: 0
09.680: DIMM 0 RttNom: 3
09.680: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.680: DIMM 0 RttNom: 3
09.680: DIMM 0 RttWr: 2
09.680: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.680: DIMM 0 RttWr: 2
09.680: DIMM 0 RttNom: 3
09.680: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.680: DIMM 0 RttNom: 3
09.680: DIMM 0 RttWr: 2
09.680: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.680: DIMM 0 RttWr: 2
09.680: DIMM 1 RttNom: 3
09.681: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.680: DIMM 0 RttNom: 3
09.681: DIMM 1 RttWr: 2
09.681: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.681: DIMM 0 RttWr: 2
09.681: DIMM 1 RttNom: 3
09.681: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.681: DIMM 0 RttNom: 3
09.681: DIMM 1 RttWr: 2
09.681: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.681: DIMM 0 RttWr: 2
09.681: AgesaHwWlPhase1: training nibble 0
09.681: DIMM 1 RttNom: 3
09.681: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.681: DIMM 1 RttWr: 2
09.681: DIMM 1 RttWr: 2
09.681: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.681: DIMM 1 RttWr: 2
09.681: DIMM 1 RttNom: 3
09.681: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.681: DIMM 1 RttNom: 3
09.681: DIMM 1 RttWr: 2
09.681: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.681: DIMM 1 RttWr: 2
09.681: DIMM 0 RttNom: 3
09.681: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.681: DIMM 1 RttNom: 3
09.681: DIMM 0 RttWr: 2
09.681: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.681: DIMM 1 RttWr: 2
09.681: DIMM 0 RttNom: 3
09.681: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.681: DIMM 1 RttNom: 3
09.681: DIMM 0 RttWr: 2
09.681: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.681: DIMM 1 RttWr: 2
09.681: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.681: <09>Lane 00 scaled delay: 0047
09.681: <09>Lane 00 new seed: 0047
09.681: <09>Lane 01 scaled delay: 0047
09.681: <09>Lane 01 new seed: 0047
09.681: <09>Lane 02 scaled delay: 0047
09.681: <09>Lane 02 new seed: 0047
09.681: <09>Lane 03 scaled delay: 0047
09.681: <09>Lane 03 new seed: 0047
09.681: <09>Lane 04 scaled delay: 0047
09.681: <09>Lane 04 new seed: 0047
09.681: <09>Lane 05 scaled delay: 0047
09.681: <09>Lane 05 new seed: 0047
09.681: <09>Lane 06 scaled delay: 0047
09.681: <09>Lane 06 new seed: 0047
09.681: <09>Lane 07 scaled delay: 0047
09.681: <09>Lane 07 new seed: 0047
09.681: <09>Lane 08 scaled delay: 0047
09.681: <09>Lane 08 new seed: 0047
09.681: <09>Lane 00 nibble 0 raw readback: 0046
09.681: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0046
09.681: <09>Lane 00 nibble 0 adjusted value (post nibble): 0046
09.681: <09>Lane 01 nibble 0 raw readback: 003f
09.681: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003f
09.681: <09>Lane 01 nibble 0 adjusted value (post nibble): 003f
09.681: <09>Lane 02 nibble 0 raw readback: 003e
09.681: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003e
09.681: <09>Lane 02 nibble 0 adjusted value (post nibble): 003e
09.681: <09>Lane 03 nibble 0 raw readback: 003b
09.681: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
09.681: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
09.681: <09>Lane 04 nibble 0 raw readback: 002f
09.681: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002f
09.682: <09>Lane 04 nibble 0 adjusted value (post nibble): 002f
09.682: <09>Lane 05 nibble 0 raw readback: 0035
09.682: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0035
09.682: <09>Lane 05 nibble 0 adjusted value (post nibble): 0035
09.682: <09>Lane 06 nibble 0 raw readback: 0038
09.682: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0038
09.682: <09>Lane 06 nibble 0 adjusted value (post nibble): 0038
09.682: <09>Lane 07 nibble 0 raw readback: 003a
09.682: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003a
09.682: <09>Lane 07 nibble 0 adjusted value (post nibble): 003a
09.682: <09>Lane 08 nibble 0 raw readback: 0034
09.682: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0034
09.682: <09>Lane 08 nibble 0 adjusted value (post nibble): 0034
09.682: AgesaHwWlPhase1: training nibble 1
09.682: DIMM 1 RttNom: 3
09.682: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.682: DIMM 1 RttWr: 2
09.682: DIMM 1 RttWr: 2
09.682: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.682: DIMM 1 RttWr: 2
09.682: DIMM 1 RttNom: 3
09.682: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.682: DIMM 1 RttNom: 3
09.682: DIMM 1 RttWr: 2
09.682: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.682: DIMM 1 RttWr: 2
09.682: DIMM 0 RttNom: 3
09.682: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.682: DIMM 1 RttNom: 3
09.682: DIMM 0 RttWr: 2
09.682: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.682: DIMM 1 RttWr: 2
09.682: DIMM 0 RttNom: 3
09.682: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.682: DIMM 1 RttNom: 3
09.682: DIMM 0 RttWr: 2
09.682: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.682: DIMM 1 RttWr: 2
09.682: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.682: <09>Lane 00 new seed: 0047
09.682: <09>Lane 01 new seed: 0047
09.682: <09>Lane 02 new seed: 0047
09.682: <09>Lane 03 new seed: 0047
09.682: <09>Lane 04 new seed: 0047
09.682: <09>Lane 05 new seed: 0047
09.682: <09>Lane 06 new seed: 0047
09.682: <09>Lane 07 new seed: 0047
09.682: <09>Lane 08 new seed: 0047
09.682: <09>Lane 00 nibble 1 raw readback: 0045
09.682: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0045
09.682: <09>Lane 00 nibble 1 adjusted value (post nibble): 0046
09.682: <09>Lane 01 nibble 1 raw readback: 003f
09.682: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003f
09.682: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
09.682: <09>Lane 02 nibble 1 raw readback: 003f
09.682: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003f
09.682: <09>Lane 02 nibble 1 adjusted value (post nibble): 0043
09.682: <09>Lane 03 nibble 1 raw readback: 003c
09.682: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003c
09.682: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
09.682: <09>Lane 04 nibble 1 raw readback: 0031
09.682: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0031
09.682: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
09.682: <09>Lane 05 nibble 1 raw readback: 0035
09.682: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0035
09.682: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
09.682: <09>Lane 06 nibble 1 raw readback: 0038
09.682: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0038
09.682: <09>Lane 06 nibble 1 adjusted value (post nibble): 003f
09.682: <09>Lane 07 nibble 1 raw readback: 003a
09.682: <09>Lane 07 nibble 1 adjusted value (pre nibble): 003a
09.682: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
09.682: <09>Lane 08 nibble 1 raw readback: 0033
09.682: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0033
09.682: <09>Lane 08 nibble 1 adjusted value (post nibble): 003d
09.682: <09>original critical gross delay: 0
09.683: <09>new critical gross delay: 0
09.683: DIMM 1 RttNom: 3
09.683: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.683: DIMM 1 RttNom: 3
09.683: DIMM 1 RttWr: 2
09.683: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.683: DIMM 1 RttWr: 2
09.683: DIMM 1 RttNom: 3
09.683: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.683: DIMM 1 RttNom: 3
09.683: DIMM 1 RttWr: 2
09.683: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.683: DIMM 1 RttWr: 2
09.683: DIMM 0 RttNom: 3
09.683: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.683: DIMM 1 RttNom: 3
09.683: DIMM 0 RttWr: 2
09.683: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.683: DIMM 1 RttWr: 2
09.683: DIMM 0 RttNom: 3
09.683: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.683: DIMM 1 RttNom: 3
09.683: DIMM 0 RttWr: 2
09.683: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.683: DIMM 1 RttWr: 2
09.683: SPD2ndTiming: Start
09.684: SPD2ndTiming: Done
09.684: mct_BeforeDramInit_Prod_D: Start
09.684: mct_ProgramODT_D: Start
09.684: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
09.684: mct_ProgramODT_D: Done
09.684: mct_BeforeDramInit_Prod_D: Done
09.684: mct_DramInit_Sw_D: Start
09.684: DIMM 0 RttWr: 2
09.684: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.684: mct_SendMrsCmd: Start
09.684: mct_SendMrsCmd: Done
09.684: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
09.684: mct_SendMrsCmd: Start
09.684: mct_SendMrsCmd: Done
09.684: DIMM 0 RttNom: 3
09.684: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.684: mct_SendMrsCmd: Start
09.684: mct_SendMrsCmd: Done
09.684: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001578
09.684: mct_SendMrsCmd: Start
09.684: mct_SendMrsCmd: Done
09.684: DIMM 0 RttWr: 2
09.684: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.684: mct_SendMrsCmd: Start
09.684: mct_SendMrsCmd: Done
09.684: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
09.684: mct_SendMrsCmd: Start
09.684: mct_SendMrsCmd: Done
09.684: DIMM 0 RttNom: 3
09.684: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.684: mct_SendMrsCmd: Start
09.684: mct_SendMrsCmd: Done
09.684: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201578
09.684: mct_SendMrsCmd: Start
09.684: mct_SendMrsCmd: Done
09.684: DIMM 1 RttWr: 2
09.684: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.684: mct_SendMrsCmd: Start
09.684: mct_SendMrsCmd: Done
09.684: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
09.684: mct_SendMrsCmd: Start
09.684: mct_SendMrsCmd: Done
09.684: DIMM 1 RttNom: 3
09.684: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.684: mct_SendMrsCmd: Start
09.684: mct_SendMrsCmd: Done
09.684: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401578
09.684: mct_SendMrsCmd: Start
09.684: mct_SendMrsCmd: Done
09.684: DIMM 1 RttWr: 2
09.684: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.684: mct_SendMrsCmd: Start
09.684: mct_SendMrsCmd: Done
09.684: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
09.684: mct_SendMrsCmd: Start
09.684: mct_SendMrsCmd: Done
09.684: DIMM 1 RttNom: 3
09.684: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.684: mct_SendMrsCmd: Start
09.684: mct_SendMrsCmd: Done
09.684: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601578
09.684: mct_SendMrsCmd: Start
09.684: mct_SendMrsCmd: Done
09.684: mct_DramInit_Sw_D: Done
09.684: AgesaHwWlPhase1: training nibble 0
09.684: DIMM 0 RttNom: 3
09.684: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.684: DIMM 0 RttWr: 2
09.685: DIMM 0 RttWr: 2
09.685: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.685: DIMM 0 RttWr: 2
09.685: DIMM 0 RttNom: 3
09.685: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.685: DIMM 0 RttNom: 3
09.685: DIMM 0 RttWr: 2
09.685: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.685: DIMM 0 RttWr: 2
09.685: DIMM 1 RttNom: 3
09.685: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.685: DIMM 0 RttNom: 3
09.685: DIMM 1 RttWr: 2
09.685: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.685: DIMM 0 RttWr: 2
09.685: DIMM 1 RttNom: 3
09.685: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.685: DIMM 0 RttNom: 3
09.685: DIMM 1 RttWr: 2
09.685: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.685: DIMM 0 RttWr: 2
09.685: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.685: <09>Lane 00 scaled delay: 0047
09.685: <09>Lane 00 new seed: 0047
09.685: <09>Lane 01 scaled delay: 0047
09.685: <09>Lane 01 new seed: 0047
09.685: <09>Lane 02 scaled delay: 0047
09.685: <09>Lane 02 new seed: 0047
09.685: <09>Lane 03 scaled delay: 0047
09.685: <09>Lane 03 new seed: 0047
09.685: <09>Lane 04 scaled delay: 0047
09.685: <09>Lane 04 new seed: 0047
09.685: <09>Lane 05 scaled delay: 0047
09.685: <09>Lane 05 new seed: 0047
09.685: <09>Lane 06 scaled delay: 0047
09.685: <09>Lane 06 new seed: 0047
09.685: <09>Lane 07 scaled delay: 0047
09.685: <09>Lane 07 new seed: 0047
09.685: <09>Lane 08 scaled delay: 0047
09.685: <09>Lane 08 new seed: 0047
09.685: <09>Lane 00 nibble 0 raw readback: 004e
09.685: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004e
09.685: <09>Lane 00 nibble 0 adjusted value (post nibble): 004e
09.685: <09>Lane 01 nibble 0 raw readback: 004a
09.685: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004a
09.685: <09>Lane 01 nibble 0 adjusted value (post nibble): 004a
09.685: <09>Lane 02 nibble 0 raw readback: 0046
09.685: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0046
09.685: <09>Lane 02 nibble 0 adjusted value (post nibble): 0046
09.685: <09>Lane 03 nibble 0 raw readback: 0044
09.685: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
09.685: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
09.685: <09>Lane 04 nibble 0 raw readback: 0039
09.686: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
09.686: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
09.686: <09>Lane 05 nibble 0 raw readback: 003d
09.686: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
09.686: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
09.686: <09>Lane 06 nibble 0 raw readback: 0040
09.686: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
09.686: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
09.686: <09>Lane 07 nibble 0 raw readback: 0042
09.686: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0042
09.686: <09>Lane 07 nibble 0 adjusted value (post nibble): 0042
09.686: <09>Lane 08 nibble 0 raw readback: 003b
09.686: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003b
09.686: <09>Lane 08 nibble 0 adjusted value (post nibble): 003b
09.686: AgesaHwWlPhase1: training nibble 1
09.686: DIMM 0 RttNom: 3
09.686: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.686: DIMM 0 RttWr: 2
09.686: DIMM 0 RttWr: 2
09.686: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.686: DIMM 0 RttWr: 2
09.686: DIMM 0 RttNom: 3
09.686: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.686: DIMM 0 RttNom: 3
09.686: DIMM 0 RttWr: 2
09.686: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.686: DIMM 0 RttWr: 2
09.686: DIMM 1 RttNom: 3
09.686: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.686: DIMM 0 RttNom: 3
09.686: DIMM 1 RttWr: 2
09.686: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.686: DIMM 0 RttWr: 2
09.686: DIMM 1 RttNom: 3
09.686: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.686: DIMM 0 RttNom: 3
09.686: DIMM 1 RttWr: 2
09.686: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.686: DIMM 0 RttWr: 2
09.686: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.686: <09>Lane 00 new seed: 0047
09.686: <09>Lane 01 new seed: 0047
09.686: <09>Lane 02 new seed: 0047
09.686: <09>Lane 03 new seed: 0047
09.686: <09>Lane 04 new seed: 0047
09.686: <09>Lane 05 new seed: 0047
09.686: <09>Lane 06 new seed: 0047
09.686: <09>Lane 07 new seed: 0047
09.686: <09>Lane 08 new seed: 0047
09.686: <09>Lane 00 nibble 1 raw readback: 004e
09.686: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004e
09.686: <09>Lane 00 nibble 1 adjusted value (post nibble): 004a
09.686: <09>Lane 01 nibble 1 raw readback: 004a
09.686: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004a
09.686: <09>Lane 01 nibble 1 adjusted value (post nibble): 0048
09.686: <09>Lane 02 nibble 1 raw readback: 0047
09.686: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0047
09.686: <09>Lane 02 nibble 1 adjusted value (post nibble): 0047
09.686: <09>Lane 03 nibble 1 raw readback: 0044
09.686: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0044
09.686: <09>Lane 03 nibble 1 adjusted value (post nibble): 0045
09.686: <09>Lane 04 nibble 1 raw readback: 0039
09.686: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
09.686: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
09.686: <09>Lane 05 nibble 1 raw readback: 003e
09.686: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003e
09.686: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
09.686: <09>Lane 06 nibble 1 raw readback: 0040
09.686: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0040
09.686: <09>Lane 06 nibble 1 adjusted value (post nibble): 0043
09.686: <09>Lane 07 nibble 1 raw readback: 0041
09.687: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
09.687: <09>Lane 07 nibble 1 adjusted value (post nibble): 0044
09.687: <09>Lane 08 nibble 1 raw readback: 003c
09.687: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003c
09.687: <09>Lane 08 nibble 1 adjusted value (post nibble): 0041
09.687: <09>original critical gross delay: 0
09.687: <09>new critical gross delay: 0
09.687: DIMM 0 RttNom: 3
09.687: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.687: DIMM 0 RttNom: 3
09.687: DIMM 0 RttWr: 2
09.687: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.687: DIMM 0 RttWr: 2
09.687: DIMM 0 RttNom: 3
09.687: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.687: DIMM 0 RttNom: 3
09.687: DIMM 0 RttWr: 2
09.687: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.687: DIMM 0 RttWr: 2
09.687: DIMM 1 RttNom: 3
09.687: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.687: DIMM 0 RttNom: 3
09.687: DIMM 1 RttWr: 2
09.687: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.687: DIMM 0 RttWr: 2
09.687: DIMM 1 RttNom: 3
09.687: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.687: DIMM 0 RttNom: 3
09.687: DIMM 1 RttWr: 2
09.687: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.687: DIMM 0 RttWr: 2
09.687: AgesaHwWlPhase1: training nibble 0
09.687: DIMM 1 RttNom: 3
09.687: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.687: DIMM 1 RttWr: 2
09.687: DIMM 1 RttWr: 2
09.687: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.687: DIMM 1 RttWr: 2
09.687: DIMM 1 RttNom: 3
09.687: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.687: DIMM 1 RttNom: 3
09.687: DIMM 1 RttWr: 2
09.687: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.687: DIMM 1 RttWr: 2
09.687: DIMM 0 RttNom: 3
09.687: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.687: DIMM 1 RttNom: 3
09.687: DIMM 0 RttWr: 2
09.687: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.687: DIMM 1 RttWr: 2
09.687: DIMM 0 RttNom: 3
09.687: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.687: DIMM 1 RttNom: 3
09.687: DIMM 0 RttWr: 2
09.687: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.687: DIMM 1 RttWr: 2
09.687: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.688: <09>Lane 00 scaled delay: 0047
09.688: <09>Lane 00 new seed: 0047
09.688: <09>Lane 01 scaled delay: 0047
09.688: <09>Lane 01 new seed: 0047
09.688: <09>Lane 02 scaled delay: 0047
09.688: <09>Lane 02 new seed: 0047
09.688: <09>Lane 03 scaled delay: 0047
09.688: <09>Lane 03 new seed: 0047
09.688: <09>Lane 04 scaled delay: 0047
09.688: <09>Lane 04 new seed: 0047
09.688: <09>Lane 05 scaled delay: 0047
09.688: <09>Lane 05 new seed: 0047
09.688: <09>Lane 06 scaled delay: 0047
09.688: <09>Lane 06 new seed: 0047
09.688: <09>Lane 07 scaled delay: 0047
09.688: <09>Lane 07 new seed: 0047
09.688: <09>Lane 08 scaled delay: 0047
09.688: <09>Lane 08 new seed: 0047
09.688: <09>Lane 00 nibble 0 raw readback: 0044
09.688: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0044
09.688: <09>Lane 00 nibble 0 adjusted value (post nibble): 0044
09.688: <09>Lane 01 nibble 0 raw readback: 003f
09.688: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003f
09.688: <09>Lane 01 nibble 0 adjusted value (post nibble): 003f
09.688: <09>Lane 02 nibble 0 raw readback: 003c
09.688: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003c
09.688: <09>Lane 02 nibble 0 adjusted value (post nibble): 003c
09.688: <09>Lane 03 nibble 0 raw readback: 003a
09.688: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003a
09.688: <09>Lane 03 nibble 0 adjusted value (post nibble): 003a
09.688: <09>Lane 04 nibble 0 raw readback: 002f
09.688: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002f
09.688: <09>Lane 04 nibble 0 adjusted value (post nibble): 002f
09.688: <09>Lane 05 nibble 0 raw readback: 0033
09.688: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0033
09.688: <09>Lane 05 nibble 0 adjusted value (post nibble): 0033
09.688: <09>Lane 06 nibble 0 raw readback: 0035
09.688: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0035
09.688: <09>Lane 06 nibble 0 adjusted value (post nibble): 0035
09.688: <09>Lane 07 nibble 0 raw readback: 0039
09.688: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0039
09.688: <09>Lane 07 nibble 0 adjusted value (post nibble): 0039
09.688: <09>Lane 08 nibble 0 raw readback: 0032
09.688: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0032
09.688: <09>Lane 08 nibble 0 adjusted value (post nibble): 0032
09.688: AgesaHwWlPhase1: training nibble 1
09.688: DIMM 1 RttNom: 3
09.688: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.688: DIMM 1 RttWr: 2
09.688: DIMM 1 RttWr: 2
09.688: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.688: DIMM 1 RttWr: 2
09.688: DIMM 1 RttNom: 3
09.688: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.688: DIMM 1 RttNom: 3
09.688: DIMM 1 RttWr: 2
09.688: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.688: DIMM 1 RttWr: 2
09.688: DIMM 0 RttNom: 3
09.688: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.688: DIMM 1 RttNom: 3
09.688: DIMM 0 RttWr: 2
09.688: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.688: DIMM 1 RttWr: 2
09.688: DIMM 0 RttNom: 3
09.688: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.688: DIMM 1 RttNom: 3
09.688: DIMM 0 RttWr: 2
09.688: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.688: DIMM 1 RttWr: 2
09.689: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.689: <09>Lane 00 new seed: 0047
09.689: <09>Lane 01 new seed: 0047
09.689: <09>Lane 02 new seed: 0047
09.689: <09>Lane 03 new seed: 0047
09.689: <09>Lane 04 new seed: 0047
09.689: <09>Lane 05 new seed: 0047
09.689: <09>Lane 06 new seed: 0047
09.689: <09>Lane 07 new seed: 0047
09.689: <09>Lane 08 new seed: 0047
09.689: <09>Lane 00 nibble 1 raw readback: 0043
09.689: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0043
09.689: <09>Lane 00 nibble 1 adjusted value (post nibble): 0045
09.689: <09>Lane 01 nibble 1 raw readback: 003f
09.689: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003f
09.689: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
09.689: <09>Lane 02 nibble 1 raw readback: 003c
09.689: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003c
09.689: <09>Lane 02 nibble 1 adjusted value (post nibble): 0041
09.689: <09>Lane 03 nibble 1 raw readback: 003b
09.689: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
09.689: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
09.689: <09>Lane 04 nibble 1 raw readback: 0030
09.689: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0030
09.689: <09>Lane 04 nibble 1 adjusted value (post nibble): 003b
09.689: <09>Lane 05 nibble 1 raw readback: 0033
09.689: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0033
09.689: <09>Lane 05 nibble 1 adjusted value (post nibble): 003d
09.689: <09>Lane 06 nibble 1 raw readback: 0036
09.689: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0036
09.689: <09>Lane 06 nibble 1 adjusted value (post nibble): 003e
09.689: <09>Lane 07 nibble 1 raw readback: 0039
09.689: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0039
09.689: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
09.689: <09>Lane 08 nibble 1 raw readback: 0032
09.689: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0032
09.689: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
09.689: <09>original critical gross delay: 0
09.689: <09>new critical gross delay: 0
09.689: DIMM 1 RttNom: 3
09.689: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.689: DIMM 1 RttNom: 3
09.689: DIMM 1 RttWr: 2
09.689: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.689: DIMM 1 RttWr: 2
09.689: DIMM 1 RttNom: 3
09.689: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.689: DIMM 1 RttNom: 3
09.689: DIMM 1 RttWr: 2
09.689: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.689: DIMM 1 RttWr: 2
09.689: DIMM 0 RttNom: 3
09.689: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.689: DIMM 1 RttNom: 3
09.689: DIMM 0 RttWr: 2
09.689: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.689: DIMM 1 RttWr: 2
09.689: DIMM 0 RttNom: 3
09.689: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.689: DIMM 1 RttNom: 3
09.689: DIMM 0 RttWr: 2
09.689: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.689: DIMM 1 RttWr: 2
09.690: SetTargetFreq: Start
09.690: SetTargetFreq: Node 2: New frequency code: 000a
09.690: ChangeMemClk: Start
09.690: set_2t_configuration: Start
09.690: set_2t_configuration: Done
09.690: mct_BeforePlatformSpec: Start
09.690: mct_BeforePlatformSpec: Done
09.690: mct_PlatformSpec: Start
09.690: Programmed DCT 0 timing/termination pattern 003a3c3a 30222222
09.690: mct_PlatformSpec: Done
09.690: set_2t_configuration: Start
09.690: set_2t_configuration: Done
09.690: mct_BeforePlatformSpec: Start
09.690: mct_BeforePlatformSpec: Done
09.690: mct_PlatformSpec: Start
09.690: Programmed DCT 1 timing/termination pattern 003a3c3a 30222222
09.690: mct_PlatformSpec: Done
09.690: ChangeMemClk: Done
09.690: phyAssistedMemFnceTraining: Start
09.690: phyAssistedMemFnceTraining: training node 2 DCT 0
09.690: phyAssistedMemFnceTraining: done training node 2 DCT 0
09.690: phyAssistedMemFnceTraining: training node 2 DCT 1
09.690: phyAssistedMemFnceTraining: done training node 2 DCT 1
09.690: phyAssistedMemFnceTraining: Done
09.690: InitPhyCompensation: DCT 0: Start
09.690: Waiting for predriver calibration to be applied...done!
09.691: InitPhyCompensation: DCT 0: Done
09.691: phyAssistedMemFnceTraining: Start
09.691: phyAssistedMemFnceTraining: training node 2 DCT 0
09.691: phyAssistedMemFnceTraining: done training node 2 DCT 0
09.691: phyAssistedMemFnceTraining: training node 2 DCT 1
09.691: phyAssistedMemFnceTraining: done training node 2 DCT 1
09.691: phyAssistedMemFnceTraining: Done
09.691: InitPhyCompensation: DCT 1: Start
09.691: Waiting for predriver calibration to be applied...done!
09.691: InitPhyCompensation: DCT 1: Done
09.691: Preparing to send DCT 0 DIMM 0 RC10: 01 (F2xA8: 02000300)
09.691: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.691: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
09.691: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.691: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
09.691: Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 02000c00)
09.691: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.691: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
09.691: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.691: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
09.691: Preparing to send DCT 1 DIMM 0 RC10: 01 (F2xA8: 02000300)
09.691: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.691: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
09.691: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.691: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
09.691: Preparing to send DCT 1 DIMM 1 RC10: 01 (F2xA8: 02000c00)
09.691: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.692: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
09.692: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.692: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
09.692: SetTargetFreq: Done
09.692: SPD2ndTiming: Start
09.692: SPD2ndTiming: Done
09.692: mct_BeforeDramInit_Prod_D: Start
09.692: mct_ProgramODT_D: Start
09.692: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
09.692: mct_ProgramODT_D: Done
09.692: mct_BeforeDramInit_Prod_D: Done
09.692: mct_DramInit_Sw_D: Start
09.692: DIMM 0 RttWr: 1
09.692: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.692: mct_SendMrsCmd: Start
09.692: mct_SendMrsCmd: Done
09.692: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
09.692: mct_SendMrsCmd: Start
09.692: mct_SendMrsCmd: Done
09.692: DIMM 0 RttNom: 3
09.692: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.692: mct_SendMrsCmd: Start
09.692: mct_SendMrsCmd: Done
09.692: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001978
09.692: mct_SendMrsCmd: Start
09.692: mct_SendMrsCmd: Done
09.692: DIMM 0 RttWr: 1
09.692: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.692: mct_SendMrsCmd: Start
09.692: mct_SendMrsCmd: Done
09.692: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
09.692: mct_SendMrsCmd: Start
09.692: mct_SendMrsCmd: Done
09.692: DIMM 0 RttNom: 3
09.692: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.692: mct_SendMrsCmd: Start
09.692: mct_SendMrsCmd: Done
09.692: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201978
09.692: mct_SendMrsCmd: Start
09.692: mct_SendMrsCmd: Done
09.692: DIMM 1 RttWr: 1
09.692: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.692: mct_SendMrsCmd: Start
09.692: mct_SendMrsCmd: Done
09.693: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
09.693: mct_SendMrsCmd: Start
09.693: mct_SendMrsCmd: Done
09.693: DIMM 1 RttNom: 3
09.693: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.693: mct_SendMrsCmd: Start
09.693: mct_SendMrsCmd: Done
09.693: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401978
09.693: mct_SendMrsCmd: Start
09.693: mct_SendMrsCmd: Done
09.693: DIMM 1 RttWr: 1
09.693: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.693: mct_SendMrsCmd: Start
09.693: mct_SendMrsCmd: Done
09.693: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
09.693: mct_SendMrsCmd: Start
09.693: mct_SendMrsCmd: Done
09.693: DIMM 1 RttNom: 3
09.693: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.693: mct_SendMrsCmd: Start
09.693: mct_SendMrsCmd: Done
09.693: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601978
09.693: mct_SendMrsCmd: Start
09.693: mct_SendMrsCmd: Done
09.693: mct_DramInit_Sw_D: Done
09.693: AgesaHwWlPhase1: training nibble 0
09.693: DIMM 0 RttNom: 3
09.693: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.693: DIMM 0 RttWr: 1
09.693: DIMM 0 RttWr: 1
09.693: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.693: DIMM 0 RttWr: 1
09.693: DIMM 0 RttNom: 3
09.693: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.693: DIMM 0 RttNom: 3
09.693: DIMM 0 RttWr: 1
09.693: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.693: DIMM 0 RttWr: 1
09.693: DIMM 1 RttNom: 3
09.693: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.693: DIMM 0 RttNom: 3
09.693: DIMM 1 RttWr: 1
09.693: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.693: DIMM 0 RttWr: 1
09.693: DIMM 1 RttNom: 3
09.693: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.693: DIMM 0 RttNom: 3
09.693: DIMM 1 RttWr: 1
09.693: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.693: DIMM 0 RttWr: 1
09.693: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.694: <09>Lane 00 scaled delay: 0059
09.694: <09>Lane 00 new seed: 0059
09.694: <09>Lane 01 scaled delay: 0055
09.694: <09>Lane 01 new seed: 0055
09.694: <09>Lane 02 scaled delay: 0053
09.694: <09>Lane 02 new seed: 0053
09.694: <09>Lane 03 scaled delay: 0052
09.694: <09>Lane 03 new seed: 0052
09.694: <09>Lane 04 scaled delay: 004a
09.694: <09>Lane 04 new seed: 004a
09.694: <09>Lane 05 scaled delay: 004d
09.694: <09>Lane 05 new seed: 004d
09.694: <09>Lane 06 scaled delay: 004f
09.694: <09>Lane 06 new seed: 004f
09.694: <09>Lane 07 scaled delay: 0051
09.694: <09>Lane 07 new seed: 0051
09.694: <09>Lane 08 scaled delay: 004b
09.694: <09>Lane 08 new seed: 004b
09.694: <09>Lane 00 nibble 0 raw readback: 0060
09.694: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0060
09.694: <09>Lane 00 nibble 0 adjusted value (post nibble): 0060
09.694: <09>Lane 01 nibble 0 raw readback: 0057
09.694: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0057
09.694: <09>Lane 01 nibble 0 adjusted value (post nibble): 0057
09.694: <09>Lane 02 nibble 0 raw readback: 0055
09.694: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0055
09.694: <09>Lane 02 nibble 0 adjusted value (post nibble): 0055
09.694: <09>Lane 03 nibble 0 raw readback: 0052
09.694: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0052
09.694: <09>Lane 03 nibble 0 adjusted value (post nibble): 0052
09.694: <09>Lane 04 nibble 0 raw readback: 0044
09.694: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0044
09.694: <09>Lane 04 nibble 0 adjusted value (post nibble): 0044
09.694: <09>Lane 05 nibble 0 raw readback: 004a
09.694: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004a
09.694: <09>Lane 05 nibble 0 adjusted value (post nibble): 004a
09.694: <09>Lane 06 nibble 0 raw readback: 004e
09.694: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004e
09.694: <09>Lane 06 nibble 0 adjusted value (post nibble): 004e
09.694: <09>Lane 07 nibble 0 raw readback: 0051
09.694: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0051
09.694: <09>Lane 07 nibble 0 adjusted value (post nibble): 0051
09.694: <09>Lane 08 nibble 0 raw readback: 0047
09.694: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0047
09.694: <09>Lane 08 nibble 0 adjusted value (post nibble): 0047
09.694: AgesaHwWlPhase1: training nibble 1
09.694: DIMM 0 RttNom: 3
09.694: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.694: DIMM 0 RttWr: 1
09.694: DIMM 0 RttWr: 1
09.694: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.694: DIMM 0 RttWr: 1
09.694: DIMM 0 RttNom: 3
09.694: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.694: DIMM 0 RttNom: 3
09.694: DIMM 0 RttWr: 1
09.694: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.694: DIMM 0 RttWr: 1
09.694: DIMM 1 RttNom: 3
09.695: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.695: DIMM 0 RttNom: 3
09.695: DIMM 1 RttWr: 1
09.695: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.695: DIMM 0 RttWr: 1
09.695: DIMM 1 RttNom: 3
09.695: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.695: DIMM 0 RttNom: 3
09.695: DIMM 1 RttWr: 1
09.695: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.695: DIMM 0 RttWr: 1
09.695: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.695: <09>Lane 00 new seed: 0059
09.695: <09>Lane 01 new seed: 0055
09.695: <09>Lane 02 new seed: 0053
09.695: <09>Lane 03 new seed: 0052
09.695: <09>Lane 04 new seed: 004a
09.695: <09>Lane 05 new seed: 004d
09.695: <09>Lane 06 new seed: 004f
09.695: <09>Lane 07 new seed: 0051
09.695: <09>Lane 08 new seed: 004b
09.695: <09>Lane 00 nibble 1 raw readback: 005f
09.695: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005f
09.695: <09>Lane 00 nibble 1 adjusted value (post nibble): 005c
09.695: <09>Lane 01 nibble 1 raw readback: 0059
09.695: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0059
09.695: <09>Lane 01 nibble 1 adjusted value (post nibble): 0057
09.695: <09>Lane 02 nibble 1 raw readback: 0056
09.695: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0056
09.695: <09>Lane 02 nibble 1 adjusted value (post nibble): 0054
09.695: <09>Lane 03 nibble 1 raw readback: 0052
09.695: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0052
09.695: <09>Lane 03 nibble 1 adjusted value (post nibble): 0052
09.695: <09>Lane 04 nibble 1 raw readback: 0043
09.695: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0043
09.695: <09>Lane 04 nibble 1 adjusted value (post nibble): 0046
09.695: <09>Lane 05 nibble 1 raw readback: 0048
09.695: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0048
09.695: <09>Lane 05 nibble 1 adjusted value (post nibble): 004a
09.695: <09>Lane 06 nibble 1 raw readback: 004e
09.695: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004e
09.695: <09>Lane 06 nibble 1 adjusted value (post nibble): 004e
09.695: <09>Lane 07 nibble 1 raw readback: 0050
09.695: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0050
09.695: <09>Lane 07 nibble 1 adjusted value (post nibble): 0050
09.695: <09>Lane 08 nibble 1 raw readback: 0045
09.695: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0045
09.695: <09>Lane 08 nibble 1 adjusted value (post nibble): 0048
09.695: <09>original critical gross delay: 0
09.695: <09>new critical gross delay: 0
09.695: DIMM 0 RttNom: 3
09.695: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.695: DIMM 0 RttNom: 3
09.695: DIMM 0 RttWr: 1
09.695: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.695: DIMM 0 RttWr: 1
09.695: DIMM 0 RttNom: 3
09.695: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.695: DIMM 0 RttNom: 3
09.695: DIMM 0 RttWr: 1
09.695: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.695: DIMM 0 RttWr: 1
09.696: DIMM 1 RttNom: 3
09.696: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.696: DIMM 0 RttNom: 3
09.696: DIMM 1 RttWr: 1
09.696: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.696: DIMM 0 RttWr: 1
09.696: DIMM 1 RttNom: 3
09.696: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.696: DIMM 0 RttNom: 3
09.696: DIMM 1 RttWr: 1
09.696: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.696: DIMM 0 RttWr: 1
09.696: AgesaHwWlPhase1: training nibble 0
09.696: DIMM 1 RttNom: 3
09.696: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.696: DIMM 1 RttWr: 1
09.696: DIMM 1 RttWr: 1
09.696: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.696: DIMM 1 RttWr: 1
09.696: DIMM 1 RttNom: 3
09.696: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.696: DIMM 1 RttNom: 3
09.696: DIMM 1 RttWr: 1
09.696: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.696: DIMM 1 RttWr: 1
09.696: DIMM 0 RttNom: 3
09.696: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.696: DIMM 1 RttNom: 3
09.696: DIMM 0 RttWr: 1
09.696: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.696: DIMM 1 RttWr: 1
09.696: DIMM 0 RttNom: 3
09.696: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.696: DIMM 1 RttNom: 3
09.696: DIMM 0 RttWr: 1
09.696: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.696: DIMM 1 RttWr: 1
09.696: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.696: <09>Lane 00 scaled delay: 0052
09.696: <09>Lane 00 new seed: 0052
09.696: <09>Lane 01 scaled delay: 004e
09.696: <09>Lane 01 new seed: 004e
09.696: <09>Lane 02 scaled delay: 004e
09.696: <09>Lane 02 new seed: 004e
09.696: <09>Lane 03 scaled delay: 004b
09.696: <09>Lane 03 new seed: 004b
09.696: <09>Lane 04 scaled delay: 0045
09.696: <09>Lane 04 new seed: 0045
09.696: <09>Lane 05 scaled delay: 0047
09.696: <09>Lane 05 new seed: 0047
09.696: <09>Lane 06 scaled delay: 0049
09.696: <09>Lane 06 new seed: 0049
09.696: <09>Lane 07 scaled delay: 004a
09.696: <09>Lane 07 new seed: 004a
09.696: <09>Lane 08 scaled delay: 0046
09.696: <09>Lane 08 new seed: 0046
09.696: <09>Lane 00 nibble 0 raw readback: 0053
09.696: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0053
09.696: <09>Lane 00 nibble 0 adjusted value (post nibble): 0053
09.696: <09>Lane 01 nibble 0 raw readback: 004a
09.696: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004a
09.696: <09>Lane 01 nibble 0 adjusted value (post nibble): 004a
09.696: <09>Lane 02 nibble 0 raw readback: 0048
09.696: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0048
09.697: <09>Lane 02 nibble 0 adjusted value (post nibble): 0048
09.697: <09>Lane 03 nibble 0 raw readback: 0043
09.697: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0043
09.697: <09>Lane 03 nibble 0 adjusted value (post nibble): 0043
09.697: <09>Lane 04 nibble 0 raw readback: 0036
09.697: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0036
09.697: <09>Lane 04 nibble 0 adjusted value (post nibble): 0036
09.697: <09>Lane 05 nibble 0 raw readback: 003c
09.697: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003c
09.697: <09>Lane 05 nibble 0 adjusted value (post nibble): 003c
09.697: <09>Lane 06 nibble 0 raw readback: 0040
09.697: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
09.697: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
09.697: <09>Lane 07 nibble 0 raw readback: 0044
09.697: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0044
09.697: <09>Lane 07 nibble 0 adjusted value (post nibble): 0044
09.697: <09>Lane 08 nibble 0 raw readback: 0039
09.697: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0039
09.697: <09>Lane 08 nibble 0 adjusted value (post nibble): 0039
09.697: AgesaHwWlPhase1: training nibble 1
09.697: DIMM 1 RttNom: 3
09.697: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.697: DIMM 1 RttWr: 1
09.697: DIMM 1 RttWr: 1
09.697: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.697: DIMM 1 RttWr: 1
09.697: DIMM 1 RttNom: 3
09.697: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.697: DIMM 1 RttNom: 3
09.697: DIMM 1 RttWr: 1
09.697: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.697: DIMM 1 RttWr: 1
09.697: DIMM 0 RttNom: 3
09.697: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.697: DIMM 1 RttNom: 3
09.697: DIMM 0 RttWr: 1
09.697: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.697: DIMM 1 RttWr: 1
09.697: DIMM 0 RttNom: 3
09.697: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.697: DIMM 1 RttNom: 3
09.697: DIMM 0 RttWr: 1
09.697: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.697: DIMM 1 RttWr: 1
09.697: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.697: <09>Lane 00 new seed: 0052
09.697: <09>Lane 01 new seed: 004e
09.697: <09>Lane 02 new seed: 004e
09.697: <09>Lane 03 new seed: 004b
09.697: <09>Lane 04 new seed: 0045
09.697: <09>Lane 05 new seed: 0047
09.697: <09>Lane 06 new seed: 0049
09.697: <09>Lane 07 new seed: 004a
09.697: <09>Lane 08 new seed: 0046
09.697: <09>Lane 00 nibble 1 raw readback: 0051
09.697: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0051
09.697: <09>Lane 00 nibble 1 adjusted value (post nibble): 0051
09.697: <09>Lane 01 nibble 1 raw readback: 004a
09.697: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004a
09.697: <09>Lane 01 nibble 1 adjusted value (post nibble): 004c
09.697: <09>Lane 02 nibble 1 raw readback: 004a
09.697: <09>Lane 02 nibble 1 adjusted value (pre nibble): 004a
09.697: <09>Lane 02 nibble 1 adjusted value (post nibble): 004c
09.697: <09>Lane 03 nibble 1 raw readback: 0045
09.697: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
09.697: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
09.697: <09>Lane 04 nibble 1 raw readback: 0037
09.697: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0037
09.697: <09>Lane 04 nibble 1 adjusted value (post nibble): 003e
09.697: <09>Lane 05 nibble 1 raw readback: 003c
09.697: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
09.697: <09>Lane 05 nibble 1 adjusted value (post nibble): 0041
09.697: <09>Lane 06 nibble 1 raw readback: 0040
09.697: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0040
09.697: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
09.697: <09>Lane 07 nibble 1 raw readback: 0045
09.698: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0045
09.698: <09>Lane 07 nibble 1 adjusted value (post nibble): 0047
09.698: <09>Lane 08 nibble 1 raw readback: 0039
09.698: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0039
09.698: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
09.698: <09>original critical gross delay: 0
09.698: <09>new critical gross delay: 0
09.698: DIMM 1 RttNom: 3
09.698: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.698: DIMM 1 RttNom: 3
09.698: DIMM 1 RttWr: 1
09.698: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.698: DIMM 1 RttWr: 1
09.698: DIMM 1 RttNom: 3
09.698: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.698: DIMM 1 RttNom: 3
09.698: DIMM 1 RttWr: 1
09.698: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.698: DIMM 1 RttWr: 1
09.698: DIMM 0 RttNom: 3
09.698: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.698: DIMM 1 RttNom: 3
09.698: DIMM 0 RttWr: 1
09.698: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.698: DIMM 1 RttWr: 1
09.698: DIMM 0 RttNom: 3
09.698: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.698: DIMM 1 RttNom: 3
09.698: DIMM 0 RttWr: 1
09.698: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.698: DIMM 1 RttWr: 1
09.698: SPD2ndTiming: Start
09.699: SPD2ndTiming: Done
09.699: mct_BeforeDramInit_Prod_D: Start
09.699: mct_ProgramODT_D: Start
09.699: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
09.699: mct_ProgramODT_D: Done
09.699: mct_BeforeDramInit_Prod_D: Done
09.699: mct_DramInit_Sw_D: Start
09.699: DIMM 0 RttWr: 1
09.699: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.699: mct_SendMrsCmd: Start
09.699: mct_SendMrsCmd: Done
09.699: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
09.699: mct_SendMrsCmd: Start
09.699: mct_SendMrsCmd: Done
09.699: DIMM 0 RttNom: 3
09.699: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.699: mct_SendMrsCmd: Start
09.699: mct_SendMrsCmd: Done
09.699: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001978
09.699: mct_SendMrsCmd: Start
09.699: mct_SendMrsCmd: Done
09.699: DIMM 0 RttWr: 1
09.699: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.699: mct_SendMrsCmd: Start
09.699: mct_SendMrsCmd: Done
09.699: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
09.699: mct_SendMrsCmd: Start
09.699: mct_SendMrsCmd: Done
09.699: DIMM 0 RttNom: 3
09.699: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.699: mct_SendMrsCmd: Start
09.699: mct_SendMrsCmd: Done
09.699: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201978
09.699: mct_SendMrsCmd: Start
09.699: mct_SendMrsCmd: Done
09.699: DIMM 1 RttWr: 1
09.699: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.699: mct_SendMrsCmd: Start
09.699: mct_SendMrsCmd: Done
09.699: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
09.699: mct_SendMrsCmd: Start
09.699: mct_SendMrsCmd: Done
09.699: DIMM 1 RttNom: 3
09.699: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.699: mct_SendMrsCmd: Start
09.699: mct_SendMrsCmd: Done
09.699: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401978
09.699: mct_SendMrsCmd: Start
09.699: mct_SendMrsCmd: Done
09.699: DIMM 1 RttWr: 1
09.699: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.699: mct_SendMrsCmd: Start
09.699: mct_SendMrsCmd: Done
09.699: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
09.699: mct_SendMrsCmd: Start
09.699: mct_SendMrsCmd: Done
09.699: DIMM 1 RttNom: 3
09.699: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.699: mct_SendMrsCmd: Start
09.699: mct_SendMrsCmd: Done
09.699: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601978
09.699: mct_SendMrsCmd: Start
09.699: mct_SendMrsCmd: Done
09.699: mct_DramInit_Sw_D: Done
09.699: AgesaHwWlPhase1: training nibble 0
09.700: DIMM 0 RttNom: 3
09.699: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.699: DIMM 0 RttWr: 1
09.700: DIMM 0 RttWr: 1
09.700: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.700: DIMM 0 RttWr: 1
09.700: DIMM 0 RttNom: 3
09.700: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.700: DIMM 0 RttNom: 3
09.700: DIMM 0 RttWr: 1
09.700: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.700: DIMM 0 RttWr: 1
09.700: DIMM 1 RttNom: 3
09.700: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.700: DIMM 0 RttNom: 3
09.700: DIMM 1 RttWr: 1
09.700: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.700: DIMM 0 RttWr: 1
09.700: DIMM 1 RttNom: 3
09.700: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.700: DIMM 0 RttNom: 3
09.700: DIMM 1 RttWr: 1
09.700: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.700: DIMM 0 RttWr: 1
09.700: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.700: <09>Lane 00 scaled delay: 0057
09.700: <09>Lane 00 new seed: 0057
09.700: <09>Lane 01 scaled delay: 0055
09.700: <09>Lane 01 new seed: 0055
09.700: <09>Lane 02 scaled delay: 0053
09.700: <09>Lane 02 new seed: 0053
09.700: <09>Lane 03 scaled delay: 0051
09.700: <09>Lane 03 new seed: 0051
09.700: <09>Lane 04 scaled delay: 004a
09.700: <09>Lane 04 new seed: 004a
09.700: <09>Lane 05 scaled delay: 004d
09.700: <09>Lane 05 new seed: 004d
09.700: <09>Lane 06 scaled delay: 004e
09.700: <09>Lane 06 new seed: 004e
09.700: <09>Lane 07 scaled delay: 004f
09.700: <09>Lane 07 new seed: 004f
09.700: <09>Lane 08 scaled delay: 004b
09.700: <09>Lane 08 new seed: 004b
09.700: <09>Lane 00 nibble 0 raw readback: 005d
09.700: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005d
09.700: <09>Lane 00 nibble 0 adjusted value (post nibble): 005d
09.700: <09>Lane 01 nibble 0 raw readback: 0059
09.700: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0059
09.700: <09>Lane 01 nibble 0 adjusted value (post nibble): 0059
09.700: <09>Lane 02 nibble 0 raw readback: 0054
09.700: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0054
09.700: <09>Lane 02 nibble 0 adjusted value (post nibble): 0054
09.700: <09>Lane 03 nibble 0 raw readback: 0050
09.700: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0050
09.700: <09>Lane 03 nibble 0 adjusted value (post nibble): 0050
09.700: <09>Lane 04 nibble 0 raw readback: 0042
09.700: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0042
09.700: <09>Lane 04 nibble 0 adjusted value (post nibble): 0042
09.700: <09>Lane 05 nibble 0 raw readback: 0047
09.700: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0047
09.700: <09>Lane 05 nibble 0 adjusted value (post nibble): 0047
09.701: <09>Lane 06 nibble 0 raw readback: 004b
09.701: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004b
09.701: <09>Lane 06 nibble 0 adjusted value (post nibble): 004b
09.701: <09>Lane 07 nibble 0 raw readback: 004e
09.701: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004e
09.701: <09>Lane 07 nibble 0 adjusted value (post nibble): 004e
09.701: <09>Lane 08 nibble 0 raw readback: 0045
09.701: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0045
09.701: <09>Lane 08 nibble 0 adjusted value (post nibble): 0045
09.701: AgesaHwWlPhase1: training nibble 1
09.701: DIMM 0 RttNom: 3
09.701: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.701: DIMM 0 RttWr: 1
09.701: DIMM 0 RttWr: 1
09.701: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.701: DIMM 0 RttWr: 1
09.701: DIMM 0 RttNom: 3
09.701: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.701: DIMM 0 RttNom: 3
09.701: DIMM 0 RttWr: 1
09.701: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.701: DIMM 0 RttWr: 1
09.701: DIMM 1 RttNom: 3
09.701: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.701: DIMM 0 RttNom: 3
09.701: DIMM 1 RttWr: 1
09.701: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.701: DIMM 0 RttWr: 1
09.701: DIMM 1 RttNom: 3
09.701: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.701: DIMM 0 RttNom: 3
09.701: DIMM 1 RttWr: 1
09.701: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.701: DIMM 0 RttWr: 1
09.701: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.701: <09>Lane 00 new seed: 0057
09.701: <09>Lane 01 new seed: 0055
09.701: <09>Lane 02 new seed: 0053
09.701: <09>Lane 03 new seed: 0051
09.701: <09>Lane 04 new seed: 004a
09.701: <09>Lane 05 new seed: 004d
09.701: <09>Lane 06 new seed: 004e
09.701: <09>Lane 07 new seed: 004f
09.701: <09>Lane 08 new seed: 004b
09.701: <09>Lane 00 nibble 1 raw readback: 005d
09.701: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005d
09.701: <09>Lane 00 nibble 1 adjusted value (post nibble): 005a
09.701: <09>Lane 01 nibble 1 raw readback: 0058
09.701: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0058
09.701: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
09.701: <09>Lane 02 nibble 1 raw readback: 0055
09.701: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0055
09.701: <09>Lane 02 nibble 1 adjusted value (post nibble): 0054
09.701: <09>Lane 03 nibble 1 raw readback: 0051
09.701: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0051
09.701: <09>Lane 03 nibble 1 adjusted value (post nibble): 0051
09.701: <09>Lane 04 nibble 1 raw readback: 0041
09.701: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0041
09.701: <09>Lane 04 nibble 1 adjusted value (post nibble): 0045
09.701: <09>Lane 05 nibble 1 raw readback: 0047
09.701: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0047
09.701: <09>Lane 05 nibble 1 adjusted value (post nibble): 004a
09.701: <09>Lane 06 nibble 1 raw readback: 004a
09.701: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004a
09.701: <09>Lane 06 nibble 1 adjusted value (post nibble): 004c
09.701: <09>Lane 07 nibble 1 raw readback: 004d
09.701: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004d
09.701: <09>Lane 07 nibble 1 adjusted value (post nibble): 004e
09.701: <09>Lane 08 nibble 1 raw readback: 0045
09.701: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0045
09.701: <09>Lane 08 nibble 1 adjusted value (post nibble): 0048
09.701: <09>original critical gross delay: 0
09.702: <09>new critical gross delay: 0
09.702: DIMM 0 RttNom: 3
09.702: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.702: DIMM 0 RttNom: 3
09.702: DIMM 0 RttWr: 1
09.702: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.702: DIMM 0 RttWr: 1
09.702: DIMM 0 RttNom: 3
09.702: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.702: DIMM 0 RttNom: 3
09.702: DIMM 0 RttWr: 1
09.702: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.702: DIMM 0 RttWr: 1
09.702: DIMM 1 RttNom: 3
09.702: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.702: DIMM 0 RttNom: 3
09.702: DIMM 1 RttWr: 1
09.702: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.702: DIMM 0 RttWr: 1
09.702: DIMM 1 RttNom: 3
09.702: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.702: DIMM 0 RttNom: 3
09.702: DIMM 1 RttWr: 1
09.702: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.702: DIMM 0 RttWr: 1
09.702: AgesaHwWlPhase1: training nibble 0
09.702: DIMM 1 RttNom: 3
09.702: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.702: DIMM 1 RttWr: 1
09.702: DIMM 1 RttWr: 1
09.702: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.702: DIMM 1 RttWr: 1
09.702: DIMM 1 RttNom: 3
09.702: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.702: DIMM 1 RttNom: 3
09.702: DIMM 1 RttWr: 1
09.702: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.702: DIMM 1 RttWr: 1
09.702: DIMM 0 RttNom: 3
09.702: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.702: DIMM 1 RttNom: 3
09.702: DIMM 0 RttWr: 1
09.702: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.702: DIMM 1 RttWr: 1
09.702: DIMM 0 RttNom: 3
09.702: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.702: DIMM 1 RttNom: 3
09.702: DIMM 0 RttWr: 1
09.702: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.702: DIMM 1 RttWr: 1
09.702: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.702: <09>Lane 00 scaled delay: 0051
09.702: <09>Lane 00 new seed: 0051
09.702: <09>Lane 01 scaled delay: 004e
09.702: <09>Lane 01 new seed: 004e
09.702: <09>Lane 02 scaled delay: 004b
09.703: <09>Lane 02 new seed: 004b
09.703: <09>Lane 03 scaled delay: 004b
09.703: <09>Lane 03 new seed: 004b
09.703: <09>Lane 04 scaled delay: 0043
09.703: <09>Lane 04 new seed: 0043
09.703: <09>Lane 05 scaled delay: 0046
09.703: <09>Lane 05 new seed: 0046
09.703: <09>Lane 06 scaled delay: 0047
09.703: <09>Lane 06 new seed: 0047
09.703: <09>Lane 07 scaled delay: 004a
09.703: <09>Lane 07 new seed: 004a
09.703: <09>Lane 08 scaled delay: 0045
09.703: <09>Lane 08 new seed: 0045
09.703: <09>Lane 00 nibble 0 raw readback: 0050
09.703: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0050
09.703: <09>Lane 00 nibble 0 adjusted value (post nibble): 0050
09.703: <09>Lane 01 nibble 0 raw readback: 004b
09.703: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004b
09.703: <09>Lane 01 nibble 0 adjusted value (post nibble): 004b
09.703: <09>Lane 02 nibble 0 raw readback: 0048
09.703: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0048
09.703: <09>Lane 02 nibble 0 adjusted value (post nibble): 0048
09.703: <09>Lane 03 nibble 0 raw readback: 0044
09.703: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
09.703: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
09.703: <09>Lane 04 nibble 0 raw readback: 0035
09.703: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0035
09.703: <09>Lane 04 nibble 0 adjusted value (post nibble): 0035
09.703: <09>Lane 05 nibble 0 raw readback: 003a
09.703: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003a
09.703: <09>Lane 05 nibble 0 adjusted value (post nibble): 003a
09.703: <09>Lane 06 nibble 0 raw readback: 003d
09.703: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003d
09.703: <09>Lane 06 nibble 0 adjusted value (post nibble): 003d
09.703: <09>Lane 07 nibble 0 raw readback: 0042
09.703: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0042
09.703: <09>Lane 07 nibble 0 adjusted value (post nibble): 0042
09.703: <09>Lane 08 nibble 0 raw readback: 0039
09.703: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0039
09.703: <09>Lane 08 nibble 0 adjusted value (post nibble): 0039
09.703: AgesaHwWlPhase1: training nibble 1
09.703: DIMM 1 RttNom: 3
09.703: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.703: DIMM 1 RttWr: 1
09.703: DIMM 1 RttWr: 1
09.703: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.703: DIMM 1 RttWr: 1
09.703: DIMM 1 RttNom: 3
09.703: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.703: DIMM 1 RttNom: 3
09.703: DIMM 1 RttWr: 1
09.703: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.703: DIMM 1 RttWr: 1
09.703: DIMM 0 RttNom: 3
09.703: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.703: DIMM 1 RttNom: 3
09.703: DIMM 0 RttWr: 1
09.703: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.703: DIMM 1 RttWr: 1
09.703: DIMM 0 RttNom: 3
09.703: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.703: DIMM 1 RttNom: 3
09.703: DIMM 0 RttWr: 1
09.703: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.703: DIMM 1 RttWr: 1
09.704: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.703: <09>Lane 00 new seed: 0051
09.703: <09>Lane 01 new seed: 004e
09.703: <09>Lane 02 new seed: 004b
09.703: <09>Lane 03 new seed: 004b
09.703: <09>Lane 04 new seed: 0043
09.703: <09>Lane 05 new seed: 0046
09.703: <09>Lane 06 new seed: 0047
09.704: <09>Lane 07 new seed: 004a
09.703: <09>Lane 08 new seed: 0045
09.704: <09>Lane 00 nibble 1 raw readback: 004f
09.704: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004f
09.704: <09>Lane 00 nibble 1 adjusted value (post nibble): 0050
09.704: <09>Lane 01 nibble 1 raw readback: 004a
09.704: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004a
09.704: <09>Lane 01 nibble 1 adjusted value (post nibble): 004c
09.704: <09>Lane 02 nibble 1 raw readback: 0047
09.704: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0047
09.704: <09>Lane 02 nibble 1 adjusted value (post nibble): 0049
09.704: <09>Lane 03 nibble 1 raw readback: 0045
09.704: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
09.704: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
09.704: <09>Lane 04 nibble 1 raw readback: 0035
09.704: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0035
09.704: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
09.704: <09>Lane 05 nibble 1 raw readback: 003a
09.704: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003a
09.704: <09>Lane 05 nibble 1 adjusted value (post nibble): 0040
09.704: <09>Lane 06 nibble 1 raw readback: 003d
09.704: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003d
09.704: <09>Lane 06 nibble 1 adjusted value (post nibble): 0042
09.704: <09>Lane 07 nibble 1 raw readback: 0041
09.704: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
09.704: <09>Lane 07 nibble 1 adjusted value (post nibble): 0045
09.704: <09>Lane 08 nibble 1 raw readback: 003a
09.704: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003a
09.704: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
09.704: <09>original critical gross delay: 0
09.704: <09>new critical gross delay: 0
09.704: DIMM 1 RttNom: 3
09.704: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.704: DIMM 1 RttNom: 3
09.704: DIMM 1 RttWr: 1
09.704: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.704: DIMM 1 RttWr: 1
09.704: DIMM 1 RttNom: 3
09.704: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.704: DIMM 1 RttNom: 3
09.704: DIMM 1 RttWr: 1
09.704: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.704: DIMM 1 RttWr: 1
09.704: DIMM 0 RttNom: 3
09.704: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.704: DIMM 1 RttNom: 3
09.704: DIMM 0 RttWr: 1
09.704: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.704: DIMM 1 RttWr: 1
09.704: DIMM 0 RttNom: 3
09.704: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.704: DIMM 1 RttNom: 3
09.704: DIMM 0 RttWr: 1
09.704: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.704: DIMM 1 RttWr: 1
09.704: SetTargetFreq: Start
09.704: SetTargetFreq: Node 2: New frequency code: 000e
09.705: ChangeMemClk: Start
09.705: set_2t_configuration: Start
09.705: set_2t_configuration: Done
09.705: mct_BeforePlatformSpec: Start
09.705: mct_BeforePlatformSpec: Done
09.705: mct_PlatformSpec: Start
09.705: Programmed DCT 0 timing/termination pattern 00383a38 30222222
09.705: mct_PlatformSpec: Done
09.705: set_2t_configuration: Start
09.705: set_2t_configuration: Done
09.705: mct_BeforePlatformSpec: Start
09.705: mct_BeforePlatformSpec: Done
09.705: mct_PlatformSpec: Start
09.705: Programmed DCT 1 timing/termination pattern 00383a38 30222222
09.705: mct_PlatformSpec: Done
09.705: ChangeMemClk: Done
09.705: phyAssistedMemFnceTraining: Start
09.705: phyAssistedMemFnceTraining: training node 2 DCT 0
09.705: phyAssistedMemFnceTraining: done training node 2 DCT 0
09.705: phyAssistedMemFnceTraining: training node 2 DCT 1
09.705: phyAssistedMemFnceTraining: done training node 2 DCT 1
09.705: phyAssistedMemFnceTraining: Done
09.705: InitPhyCompensation: DCT 0: Start
09.705: Waiting for predriver calibration to be applied...done!
09.705: InitPhyCompensation: DCT 0: Done
09.706: phyAssistedMemFnceTraining: Start
09.706: phyAssistedMemFnceTraining: training node 2 DCT 0
09.706: phyAssistedMemFnceTraining: done training node 2 DCT 0
09.706: phyAssistedMemFnceTraining: training node 2 DCT 1
09.706: phyAssistedMemFnceTraining: done training node 2 DCT 1
09.706: phyAssistedMemFnceTraining: Done
09.706: InitPhyCompensation: DCT 1: Start
09.706: Waiting for predriver calibration to be applied...done!
09.706: InitPhyCompensation: DCT 1: Done
09.706: Preparing to send DCT 0 DIMM 0 RC10: 02 (F2xA8: 02000300)
09.706: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.706: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
09.706: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.706: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
09.706: Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 02000c00)
09.706: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.706: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
09.706: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.706: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
09.706: Preparing to send DCT 1 DIMM 0 RC10: 02 (F2xA8: 02000300)
09.706: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.706: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
09.706: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.706: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
09.706: Preparing to send DCT 1 DIMM 1 RC10: 02 (F2xA8: 02000c00)
09.706: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.706: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
09.706: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.706: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
09.706: SetTargetFreq: Done
09.707: SPD2ndTiming: Start
09.707: SPD2ndTiming: Done
09.707: mct_BeforeDramInit_Prod_D: Start
09.707: mct_ProgramODT_D: Start
09.707: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
09.707: mct_ProgramODT_D: Done
09.707: mct_BeforeDramInit_Prod_D: Done
09.707: mct_DramInit_Sw_D: Start
09.707: DIMM 0 RttWr: 2
09.707: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.707: mct_SendMrsCmd: Start
09.707: mct_SendMrsCmd: Done
09.707: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
09.707: mct_SendMrsCmd: Start
09.707: mct_SendMrsCmd: Done
09.707: DIMM 0 RttNom: 5
09.707: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.707: mct_SendMrsCmd: Start
09.707: mct_SendMrsCmd: Done
09.707: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001b78
09.707: mct_SendMrsCmd: Start
09.707: mct_SendMrsCmd: Done
09.707: DIMM 0 RttWr: 2
09.707: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.707: mct_SendMrsCmd: Start
09.707: mct_SendMrsCmd: Done
09.707: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
09.707: mct_SendMrsCmd: Start
09.707: mct_SendMrsCmd: Done
09.707: DIMM 0 RttNom: 5
09.707: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.707: mct_SendMrsCmd: Start
09.707: mct_SendMrsCmd: Done
09.707: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201b78
09.707: mct_SendMrsCmd: Start
09.707: mct_SendMrsCmd: Done
09.707: DIMM 1 RttWr: 2
09.707: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.707: mct_SendMrsCmd: Start
09.707: mct_SendMrsCmd: Done
09.707: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
09.707: mct_SendMrsCmd: Start
09.707: mct_SendMrsCmd: Done
09.707: DIMM 1 RttNom: 5
09.708: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.708: mct_SendMrsCmd: Start
09.708: mct_SendMrsCmd: Done
09.708: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b78
09.708: mct_SendMrsCmd: Start
09.708: mct_SendMrsCmd: Done
09.708: DIMM 1 RttWr: 2
09.708: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.708: mct_SendMrsCmd: Start
09.708: mct_SendMrsCmd: Done
09.708: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
09.708: mct_SendMrsCmd: Start
09.708: mct_SendMrsCmd: Done
09.708: DIMM 1 RttNom: 5
09.708: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.708: mct_SendMrsCmd: Start
09.708: mct_SendMrsCmd: Done
09.708: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b78
09.708: mct_SendMrsCmd: Start
09.708: mct_SendMrsCmd: Done
09.708: mct_DramInit_Sw_D: Done
09.708: AgesaHwWlPhase1: training nibble 0
09.708: DIMM 0 RttNom: 5
09.708: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.708: DIMM 0 RttWr: 2
09.708: DIMM 0 RttWr: 2
09.708: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.708: DIMM 0 RttWr: 2
09.708: DIMM 0 RttNom: 5
09.708: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.708: DIMM 0 RttNom: 5
09.708: DIMM 0 RttWr: 2
09.708: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.708: DIMM 0 RttWr: 2
09.708: DIMM 1 RttNom: 5
09.708: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.708: DIMM 0 RttNom: 5
09.708: DIMM 1 RttWr: 2
09.708: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.708: DIMM 0 RttWr: 2
09.708: DIMM 1 RttNom: 5
09.708: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.708: DIMM 0 RttNom: 5
09.708: DIMM 1 RttWr: 2
09.708: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.708: DIMM 0 RttWr: 2
09.708: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.709: <09>Lane 00 scaled delay: 006b
09.709: <09>Lane 00 new seed: 006b
09.709: <09>Lane 01 scaled delay: 0064
09.709: <09>Lane 01 new seed: 0064
09.709: <09>Lane 02 scaled delay: 0061
09.709: <09>Lane 02 new seed: 0061
09.709: <09>Lane 03 scaled delay: 005e
09.709: <09>Lane 03 new seed: 005e
09.709: <09>Lane 04 scaled delay: 004f
09.709: <09>Lane 04 new seed: 004f
09.709: <09>Lane 05 scaled delay: 0054
09.709: <09>Lane 05 new seed: 0054
09.709: <09>Lane 06 scaled delay: 0059
09.709: <09>Lane 06 new seed: 0059
09.709: <09>Lane 07 scaled delay: 005c
09.709: <09>Lane 07 new seed: 005c
09.709: <09>Lane 08 scaled delay: 0052
09.709: <09>Lane 08 new seed: 0052
09.709: <09>Lane 00 nibble 0 raw readback: 0030
09.709: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0070
09.709: <09>Lane 00 nibble 0 adjusted value (post nibble): 0070
09.709: <09>Lane 01 nibble 0 raw readback: 0025
09.709: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0065
09.709: <09>Lane 01 nibble 0 adjusted value (post nibble): 0065
09.709: <09>Lane 02 nibble 0 raw readback: 0022
09.709: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0062
09.709: <09>Lane 02 nibble 0 adjusted value (post nibble): 0062
09.709: <09>Lane 03 nibble 0 raw readback: 005c
09.709: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005c
09.709: <09>Lane 03 nibble 0 adjusted value (post nibble): 005c
09.709: <09>Lane 04 nibble 0 raw readback: 004c
09.709: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004c
09.709: <09>Lane 04 nibble 0 adjusted value (post nibble): 004c
09.709: <09>Lane 05 nibble 0 raw readback: 0054
09.709: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0054
09.709: <09>Lane 05 nibble 0 adjusted value (post nibble): 0054
09.709: <09>Lane 06 nibble 0 raw readback: 0059
09.709: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0059
09.709: <09>Lane 06 nibble 0 adjusted value (post nibble): 0059
09.709: <09>Lane 07 nibble 0 raw readback: 005d
09.709: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005d
09.709: <09>Lane 07 nibble 0 adjusted value (post nibble): 005d
09.709: <09>Lane 08 nibble 0 raw readback: 004f
09.709: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004f
09.709: <09>Lane 08 nibble 0 adjusted value (post nibble): 004f
09.709: AgesaHwWlPhase1: training nibble 1
09.709: DIMM 0 RttNom: 5
09.709: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.709: DIMM 0 RttWr: 2
09.709: DIMM 0 RttWr: 2
09.709: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.709: DIMM 0 RttWr: 2
09.709: DIMM 0 RttNom: 5
09.709: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.709: DIMM 0 RttNom: 5
09.709: DIMM 0 RttWr: 2
09.709: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.709: DIMM 0 RttWr: 2
09.710: DIMM 1 RttNom: 5
09.710: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.710: DIMM 0 RttNom: 5
09.710: DIMM 1 RttWr: 2
09.710: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.710: DIMM 0 RttWr: 2
09.710: DIMM 1 RttNom: 5
09.710: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.710: DIMM 0 RttNom: 5
09.710: DIMM 1 RttWr: 2
09.710: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.710: DIMM 0 RttWr: 2
09.710: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.710: <09>Lane 00 new seed: 006b
09.710: <09>Lane 01 new seed: 0064
09.710: <09>Lane 02 new seed: 0061
09.710: <09>Lane 03 new seed: 005e
09.710: <09>Lane 04 new seed: 004f
09.710: <09>Lane 05 new seed: 0054
09.710: <09>Lane 06 new seed: 0059
09.710: <09>Lane 07 new seed: 005c
09.710: <09>Lane 08 new seed: 0052
09.710: <09>Lane 00 nibble 1 raw readback: 002f
09.710: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006f
09.710: <09>Lane 00 nibble 1 adjusted value (post nibble): 006d
09.710: <09>Lane 01 nibble 1 raw readback: 0027
09.710: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0067
09.710: <09>Lane 01 nibble 1 adjusted value (post nibble): 0065
09.710: <09>Lane 02 nibble 1 raw readback: 0023
09.710: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0063
09.710: <09>Lane 02 nibble 1 adjusted value (post nibble): 0062
09.710: <09>Lane 03 nibble 1 raw readback: 005e
09.710: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005e
09.710: <09>Lane 03 nibble 1 adjusted value (post nibble): 005e
09.710: <09>Lane 04 nibble 1 raw readback: 004b
09.710: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004b
09.710: <09>Lane 04 nibble 1 adjusted value (post nibble): 004d
09.710: <09>Lane 05 nibble 1 raw readback: 0052
09.710: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0052
09.710: <09>Lane 05 nibble 1 adjusted value (post nibble): 0053
09.710: <09>Lane 06 nibble 1 raw readback: 0058
09.710: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0058
09.710: <09>Lane 06 nibble 1 adjusted value (post nibble): 0058
09.710: <09>Lane 07 nibble 1 raw readback: 005b
09.710: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005b
09.710: <09>Lane 07 nibble 1 adjusted value (post nibble): 005b
09.710: <09>Lane 08 nibble 1 raw readback: 004c
09.710: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004c
09.710: <09>Lane 08 nibble 1 adjusted value (post nibble): 004f
09.710: <09>original critical gross delay: 0
09.710: <09>new critical gross delay: 0
09.710: DIMM 0 RttNom: 5
09.710: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.710: DIMM 0 RttNom: 5
09.710: DIMM 0 RttWr: 2
09.710: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.710: DIMM 0 RttWr: 2
09.710: DIMM 0 RttNom: 5
09.710: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.710: DIMM 0 RttNom: 5
09.710: DIMM 0 RttWr: 2
09.710: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.711: DIMM 0 RttWr: 2
09.711: DIMM 1 RttNom: 5
09.711: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.711: DIMM 0 RttNom: 5
09.711: DIMM 1 RttWr: 2
09.711: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.711: DIMM 0 RttWr: 2
09.711: DIMM 1 RttNom: 5
09.711: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.711: DIMM 0 RttNom: 5
09.711: DIMM 1 RttWr: 2
09.711: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.711: DIMM 0 RttWr: 2
09.711: AgesaHwWlPhase1: training nibble 0
09.711: DIMM 1 RttNom: 5
09.711: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.711: DIMM 1 RttWr: 2
09.711: DIMM 1 RttWr: 2
09.711: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.711: DIMM 1 RttWr: 2
09.711: DIMM 1 RttNom: 5
09.711: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.711: DIMM 1 RttNom: 5
09.711: DIMM 1 RttWr: 2
09.711: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.711: DIMM 1 RttWr: 2
09.711: DIMM 0 RttNom: 5
09.711: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.711: DIMM 1 RttNom: 5
09.711: DIMM 0 RttWr: 2
09.711: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.711: DIMM 1 RttWr: 2
09.711: DIMM 0 RttNom: 5
09.711: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.711: DIMM 1 RttNom: 5
09.711: DIMM 0 RttWr: 2
09.711: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.711: DIMM 1 RttWr: 2
09.711: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.711: <09>Lane 00 scaled delay: 005d
09.711: <09>Lane 00 new seed: 005d
09.711: <09>Lane 01 scaled delay: 0057
09.711: <09>Lane 01 new seed: 0057
09.711: <09>Lane 02 scaled delay: 0057
09.711: <09>Lane 02 new seed: 0057
09.711: <09>Lane 03 scaled delay: 0052
09.711: <09>Lane 03 new seed: 0052
09.711: <09>Lane 04 scaled delay: 0045
09.711: <09>Lane 04 new seed: 0045
09.711: <09>Lane 05 scaled delay: 0049
09.711: <09>Lane 05 new seed: 0049
09.711: <09>Lane 06 scaled delay: 004d
09.711: <09>Lane 06 new seed: 004d
09.711: <09>Lane 07 scaled delay: 0050
09.711: <09>Lane 07 new seed: 0050
09.711: <09>Lane 08 scaled delay: 0046
09.711: <09>Lane 08 new seed: 0046
09.711: <09>Lane 00 nibble 0 raw readback: 0061
09.711: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0061
09.711: <09>Lane 00 nibble 0 adjusted value (post nibble): 0061
09.711: <09>Lane 01 nibble 0 raw readback: 0056
09.711: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0056
09.711: <09>Lane 01 nibble 0 adjusted value (post nibble): 0056
09.712: <09>Lane 02 nibble 0 raw readback: 0053
09.711: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0053
09.712: <09>Lane 02 nibble 0 adjusted value (post nibble): 0053
09.712: <09>Lane 03 nibble 0 raw readback: 004d
09.712: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004d
09.712: <09>Lane 03 nibble 0 adjusted value (post nibble): 004d
09.712: <09>Lane 04 nibble 0 raw readback: 003b
09.712: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003b
09.712: <09>Lane 04 nibble 0 adjusted value (post nibble): 003b
09.712: <09>Lane 05 nibble 0 raw readback: 0044
09.712: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0044
09.712: <09>Lane 05 nibble 0 adjusted value (post nibble): 0044
09.712: <09>Lane 06 nibble 0 raw readback: 0049
09.712: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0049
09.712: <09>Lane 06 nibble 0 adjusted value (post nibble): 0049
09.712: <09>Lane 07 nibble 0 raw readback: 004d
09.712: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004d
09.712: <09>Lane 07 nibble 0 adjusted value (post nibble): 004d
09.712: <09>Lane 08 nibble 0 raw readback: 0040
09.712: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0040
09.712: <09>Lane 08 nibble 0 adjusted value (post nibble): 0040
09.712: AgesaHwWlPhase1: training nibble 1
09.712: DIMM 1 RttNom: 5
09.712: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.712: DIMM 1 RttWr: 2
09.712: DIMM 1 RttWr: 2
09.712: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.712: DIMM 1 RttWr: 2
09.712: DIMM 1 RttNom: 5
09.712: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.712: DIMM 1 RttNom: 5
09.712: DIMM 1 RttWr: 2
09.712: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.712: DIMM 1 RttWr: 2
09.712: DIMM 0 RttNom: 5
09.712: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.712: DIMM 1 RttNom: 5
09.712: DIMM 0 RttWr: 2
09.712: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.712: DIMM 1 RttWr: 2
09.712: DIMM 0 RttNom: 5
09.712: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.712: DIMM 1 RttNom: 5
09.712: DIMM 0 RttWr: 2
09.712: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.712: DIMM 1 RttWr: 2
09.712: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.712: <09>Lane 00 new seed: 005d
09.712: <09>Lane 01 new seed: 0057
09.712: <09>Lane 02 new seed: 0057
09.712: <09>Lane 03 new seed: 0052
09.712: <09>Lane 04 new seed: 0045
09.712: <09>Lane 05 new seed: 0049
09.712: <09>Lane 06 new seed: 004d
09.712: <09>Lane 07 new seed: 0050
09.712: <09>Lane 08 new seed: 0046
09.712: <09>Lane 00 nibble 1 raw readback: 005f
09.712: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005f
09.712: <09>Lane 00 nibble 1 adjusted value (post nibble): 005e
09.712: <09>Lane 01 nibble 1 raw readback: 0055
09.712: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0055
09.712: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
09.712: <09>Lane 02 nibble 1 raw readback: 0056
09.712: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0056
09.712: <09>Lane 02 nibble 1 adjusted value (post nibble): 0056
09.712: <09>Lane 03 nibble 1 raw readback: 004f
09.712: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004f
09.712: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
09.712: <09>Lane 04 nibble 1 raw readback: 003d
09.712: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003d
09.712: <09>Lane 04 nibble 1 adjusted value (post nibble): 0041
09.712: <09>Lane 05 nibble 1 raw readback: 0045
09.712: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0045
09.712: <09>Lane 05 nibble 1 adjusted value (post nibble): 0047
09.712: <09>Lane 06 nibble 1 raw readback: 0049
09.712: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0049
09.712: <09>Lane 06 nibble 1 adjusted value (post nibble): 004b
09.712: <09>Lane 07 nibble 1 raw readback: 004e
09.713: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004e
09.712: <09>Lane 07 nibble 1 adjusted value (post nibble): 004f
09.713: <09>Lane 08 nibble 1 raw readback: 0040
09.713: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0040
09.713: <09>Lane 08 nibble 1 adjusted value (post nibble): 0043
09.713: <09>original critical gross delay: 0
09.713: <09>new critical gross delay: 0
09.713: DIMM 1 RttNom: 5
09.713: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.713: DIMM 1 RttNom: 5
09.713: DIMM 1 RttWr: 2
09.713: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.713: DIMM 1 RttWr: 2
09.713: DIMM 1 RttNom: 5
09.713: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.713: DIMM 1 RttNom: 5
09.713: DIMM 1 RttWr: 2
09.713: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.713: DIMM 1 RttWr: 2
09.713: DIMM 0 RttNom: 5
09.713: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.713: DIMM 1 RttNom: 5
09.713: DIMM 0 RttWr: 2
09.713: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.713: DIMM 1 RttWr: 2
09.713: DIMM 0 RttNom: 5
09.713: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.713: DIMM 1 RttNom: 5
09.713: DIMM 0 RttWr: 2
09.713: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.713: DIMM 1 RttWr: 2
09.713: SPD2ndTiming: Start
09.714: SPD2ndTiming: Done
09.714: mct_BeforeDramInit_Prod_D: Start
09.714: mct_ProgramODT_D: Start
09.714: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
09.714: mct_ProgramODT_D: Done
09.714: mct_BeforeDramInit_Prod_D: Done
09.714: mct_DramInit_Sw_D: Start
09.714: DIMM 0 RttWr: 2
09.714: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.714: mct_SendMrsCmd: Start
09.714: mct_SendMrsCmd: Done
09.714: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
09.714: mct_SendMrsCmd: Start
09.714: mct_SendMrsCmd: Done
09.714: DIMM 0 RttNom: 5
09.714: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.714: mct_SendMrsCmd: Start
09.714: mct_SendMrsCmd: Done
09.714: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001b78
09.714: mct_SendMrsCmd: Start
09.714: mct_SendMrsCmd: Done
09.714: DIMM 0 RttWr: 2
09.714: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.714: mct_SendMrsCmd: Start
09.714: mct_SendMrsCmd: Done
09.714: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
09.714: mct_SendMrsCmd: Start
09.714: mct_SendMrsCmd: Done
09.714: DIMM 0 RttNom: 5
09.714: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.714: mct_SendMrsCmd: Start
09.714: mct_SendMrsCmd: Done
09.714: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201b78
09.714: mct_SendMrsCmd: Start
09.714: mct_SendMrsCmd: Done
09.714: DIMM 1 RttWr: 2
09.714: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.714: mct_SendMrsCmd: Start
09.714: mct_SendMrsCmd: Done
09.714: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
09.714: mct_SendMrsCmd: Start
09.714: mct_SendMrsCmd: Done
09.714: DIMM 1 RttNom: 5
09.714: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.714: mct_SendMrsCmd: Start
09.714: mct_SendMrsCmd: Done
09.714: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401b78
09.714: mct_SendMrsCmd: Start
09.714: mct_SendMrsCmd: Done
09.714: DIMM 1 RttWr: 2
09.714: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.714: mct_SendMrsCmd: Start
09.714: mct_SendMrsCmd: Done
09.714: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
09.714: mct_SendMrsCmd: Start
09.714: mct_SendMrsCmd: Done
09.714: DIMM 1 RttNom: 5
09.714: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.714: mct_SendMrsCmd: Start
09.714: mct_SendMrsCmd: Done
09.714: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601b78
09.714: mct_SendMrsCmd: Start
09.714: mct_SendMrsCmd: Done
09.714: mct_DramInit_Sw_D: Done
09.714: AgesaHwWlPhase1: training nibble 0
09.714: DIMM 0 RttNom: 5
09.714: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.714: DIMM 0 RttWr: 2
09.715: DIMM 0 RttWr: 2
09.715: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.715: DIMM 0 RttWr: 2
09.715: DIMM 0 RttNom: 5
09.715: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.715: DIMM 0 RttNom: 5
09.715: DIMM 0 RttWr: 2
09.715: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.715: DIMM 0 RttWr: 2
09.715: DIMM 1 RttNom: 5
09.715: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.715: DIMM 0 RttNom: 5
09.715: DIMM 1 RttWr: 2
09.715: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.715: DIMM 0 RttWr: 2
09.715: DIMM 1 RttNom: 5
09.715: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.715: DIMM 0 RttNom: 5
09.715: DIMM 1 RttWr: 2
09.715: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.715: DIMM 0 RttWr: 2
09.715: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.715: <09>Lane 00 scaled delay: 0068
09.715: <09>Lane 00 new seed: 0068
09.715: <09>Lane 01 scaled delay: 0063
09.715: <09>Lane 01 new seed: 0063
09.715: <09>Lane 02 scaled delay: 0061
09.715: <09>Lane 02 new seed: 0061
09.715: <09>Lane 03 scaled delay: 005d
09.715: <09>Lane 03 new seed: 005d
09.715: <09>Lane 04 scaled delay: 004e
09.715: <09>Lane 04 new seed: 004e
09.715: <09>Lane 05 scaled delay: 0054
09.715: <09>Lane 05 new seed: 0054
09.715: <09>Lane 06 scaled delay: 0057
09.715: <09>Lane 06 new seed: 0057
09.715: <09>Lane 07 scaled delay: 0059
09.715: <09>Lane 07 new seed: 0059
09.715: <09>Lane 08 scaled delay: 0052
09.715: <09>Lane 08 new seed: 0052
09.715: <09>Lane 00 nibble 0 raw readback: 002c
09.715: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006c
09.715: <09>Lane 00 nibble 0 adjusted value (post nibble): 006c
09.715: <09>Lane 01 nibble 0 raw readback: 0028
09.715: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0068
09.715: <09>Lane 01 nibble 0 adjusted value (post nibble): 0068
09.715: <09>Lane 02 nibble 0 raw readback: 0021
09.715: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0061
09.715: <09>Lane 02 nibble 0 adjusted value (post nibble): 0061
09.715: <09>Lane 03 nibble 0 raw readback: 005c
09.715: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005c
09.715: <09>Lane 03 nibble 0 adjusted value (post nibble): 005c
09.715: <09>Lane 04 nibble 0 raw readback: 004a
09.715: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004a
09.715: <09>Lane 04 nibble 0 adjusted value (post nibble): 004a
09.716: <09>Lane 05 nibble 0 raw readback: 0051
09.716: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0051
09.716: <09>Lane 05 nibble 0 adjusted value (post nibble): 0051
09.716: <09>Lane 06 nibble 0 raw readback: 0057
09.716: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0057
09.716: <09>Lane 06 nibble 0 adjusted value (post nibble): 0057
09.716: <09>Lane 07 nibble 0 raw readback: 005b
09.716: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005b
09.716: <09>Lane 07 nibble 0 adjusted value (post nibble): 005b
09.716: <09>Lane 08 nibble 0 raw readback: 004e
09.716: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004e
09.716: <09>Lane 08 nibble 0 adjusted value (post nibble): 004e
09.716: AgesaHwWlPhase1: training nibble 1
09.716: DIMM 0 RttNom: 5
09.716: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.716: DIMM 0 RttWr: 2
09.716: DIMM 0 RttWr: 2
09.716: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.716: DIMM 0 RttWr: 2
09.716: DIMM 0 RttNom: 5
09.716: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.716: DIMM 0 RttNom: 5
09.716: DIMM 0 RttWr: 2
09.716: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.716: DIMM 0 RttWr: 2
09.716: DIMM 1 RttNom: 5
09.716: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.716: DIMM 0 RttNom: 5
09.716: DIMM 1 RttWr: 2
09.716: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.716: DIMM 0 RttWr: 2
09.716: DIMM 1 RttNom: 5
09.716: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.716: DIMM 0 RttNom: 5
09.716: DIMM 1 RttWr: 2
09.716: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.716: DIMM 0 RttWr: 2
09.716: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.716: <09>Lane 00 new seed: 0068
09.716: <09>Lane 01 new seed: 0063
09.716: <09>Lane 02 new seed: 0061
09.716: <09>Lane 03 new seed: 005d
09.716: <09>Lane 04 new seed: 004e
09.716: <09>Lane 05 new seed: 0054
09.716: <09>Lane 06 new seed: 0057
09.716: <09>Lane 07 new seed: 0059
09.716: <09>Lane 08 new seed: 0052
09.716: <09>Lane 00 nibble 1 raw readback: 002c
09.716: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006c
09.716: <09>Lane 00 nibble 1 adjusted value (post nibble): 006a
09.716: <09>Lane 01 nibble 1 raw readback: 0026
09.716: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0066
09.716: <09>Lane 01 nibble 1 adjusted value (post nibble): 0064
09.716: <09>Lane 02 nibble 1 raw readback: 0021
09.716: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0061
09.716: <09>Lane 02 nibble 1 adjusted value (post nibble): 0061
09.716: <09>Lane 03 nibble 1 raw readback: 005d
09.716: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005d
09.716: <09>Lane 03 nibble 1 adjusted value (post nibble): 005d
09.716: <09>Lane 04 nibble 1 raw readback: 0049
09.716: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0049
09.716: <09>Lane 04 nibble 1 adjusted value (post nibble): 004b
09.716: <09>Lane 05 nibble 1 raw readback: 0051
09.716: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0051
09.716: <09>Lane 05 nibble 1 adjusted value (post nibble): 0052
09.716: <09>Lane 06 nibble 1 raw readback: 0056
09.716: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0056
09.716: <09>Lane 06 nibble 1 adjusted value (post nibble): 0056
09.716: <09>Lane 07 nibble 1 raw readback: 0059
09.716: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0059
09.717: <09>Lane 07 nibble 1 adjusted value (post nibble): 0059
09.717: <09>Lane 08 nibble 1 raw readback: 004e
09.717: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004e
09.717: <09>Lane 08 nibble 1 adjusted value (post nibble): 0050
09.717: <09>original critical gross delay: 0
09.717: <09>new critical gross delay: 0
09.717: DIMM 0 RttNom: 5
09.717: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.717: DIMM 0 RttNom: 5
09.717: DIMM 0 RttWr: 2
09.717: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.717: DIMM 0 RttWr: 2
09.717: DIMM 0 RttNom: 5
09.717: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.717: DIMM 0 RttNom: 5
09.717: DIMM 0 RttWr: 2
09.717: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.717: DIMM 0 RttWr: 2
09.717: DIMM 1 RttNom: 5
09.717: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.717: DIMM 0 RttNom: 5
09.717: DIMM 1 RttWr: 2
09.717: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.717: DIMM 0 RttWr: 2
09.717: DIMM 1 RttNom: 5
09.717: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.717: DIMM 0 RttNom: 5
09.717: DIMM 1 RttWr: 2
09.717: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.717: DIMM 0 RttWr: 2
09.717: AgesaHwWlPhase1: training nibble 0
09.717: DIMM 1 RttNom: 5
09.717: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.717: DIMM 1 RttWr: 2
09.717: DIMM 1 RttWr: 2
09.717: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.717: DIMM 1 RttWr: 2
09.717: DIMM 1 RttNom: 5
09.717: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.717: DIMM 1 RttNom: 5
09.717: DIMM 1 RttWr: 2
09.717: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.717: DIMM 1 RttWr: 2
09.717: DIMM 0 RttNom: 5
09.717: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.717: DIMM 1 RttNom: 5
09.717: DIMM 0 RttWr: 2
09.717: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.717: DIMM 1 RttWr: 2
09.717: DIMM 0 RttNom: 5
09.717: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.717: DIMM 1 RttNom: 5
09.717: DIMM 0 RttWr: 2
09.717: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.717: DIMM 1 RttWr: 2
09.717: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.717: <09>Lane 00 scaled delay: 005c
09.718: <09>Lane 00 new seed: 005c
09.718: <09>Lane 01 scaled delay: 0057
09.718: <09>Lane 01 new seed: 0057
09.718: <09>Lane 02 scaled delay: 0053
09.718: <09>Lane 02 new seed: 0053
09.718: <09>Lane 03 scaled delay: 0052
09.718: <09>Lane 03 new seed: 0052
09.718: <09>Lane 04 scaled delay: 0043
09.718: <09>Lane 04 new seed: 0043
09.718: <09>Lane 05 scaled delay: 0048
09.718: <09>Lane 05 new seed: 0048
09.718: <09>Lane 06 scaled delay: 004a
09.718: <09>Lane 06 new seed: 004a
09.718: <09>Lane 07 scaled delay: 004e
09.718: <09>Lane 07 new seed: 004e
09.718: <09>Lane 08 scaled delay: 0046
09.718: <09>Lane 08 new seed: 0046
09.718: <09>Lane 00 nibble 0 raw readback: 005c
09.718: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005c
09.718: <09>Lane 00 nibble 0 adjusted value (post nibble): 005c
09.718: <09>Lane 01 nibble 0 raw readback: 0056
09.718: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0056
09.718: <09>Lane 01 nibble 0 adjusted value (post nibble): 0056
09.718: <09>Lane 02 nibble 0 raw readback: 0050
09.718: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0050
09.718: <09>Lane 02 nibble 0 adjusted value (post nibble): 0050
09.718: <09>Lane 03 nibble 0 raw readback: 004b
09.718: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004b
09.718: <09>Lane 03 nibble 0 adjusted value (post nibble): 004b
09.718: <09>Lane 04 nibble 0 raw readback: 0039
09.718: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
09.718: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
09.718: <09>Lane 05 nibble 0 raw readback: 0041
09.718: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0041
09.718: <09>Lane 05 nibble 0 adjusted value (post nibble): 0041
09.718: <09>Lane 06 nibble 0 raw readback: 0045
09.718: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0045
09.718: <09>Lane 06 nibble 0 adjusted value (post nibble): 0045
09.718: <09>Lane 07 nibble 0 raw readback: 004b
09.718: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004b
09.718: <09>Lane 07 nibble 0 adjusted value (post nibble): 004b
09.718: <09>Lane 08 nibble 0 raw readback: 003e
09.718: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003e
09.718: <09>Lane 08 nibble 0 adjusted value (post nibble): 003e
09.718: AgesaHwWlPhase1: training nibble 1
09.718: DIMM 1 RttNom: 5
09.718: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.718: DIMM 1 RttWr: 2
09.718: DIMM 1 RttWr: 2
09.718: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.718: DIMM 1 RttWr: 2
09.718: DIMM 1 RttNom: 5
09.718: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.718: DIMM 1 RttNom: 5
09.718: DIMM 1 RttWr: 2
09.718: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.718: DIMM 1 RttWr: 2
09.718: DIMM 0 RttNom: 5
09.718: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.718: DIMM 1 RttNom: 5
09.718: DIMM 0 RttWr: 2
09.718: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.718: DIMM 1 RttWr: 2
09.718: DIMM 0 RttNom: 5
09.718: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.718: DIMM 1 RttNom: 5
09.718: DIMM 0 RttWr: 2
09.718: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.718: DIMM 1 RttWr: 2
09.719: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.718: <09>Lane 00 new seed: 005c
09.718: <09>Lane 01 new seed: 0057
09.718: <09>Lane 02 new seed: 0053
09.718: <09>Lane 03 new seed: 0052
09.719: <09>Lane 04 new seed: 0043
09.719: <09>Lane 05 new seed: 0048
09.719: <09>Lane 06 new seed: 004a
09.719: <09>Lane 07 new seed: 004e
09.719: <09>Lane 08 new seed: 0046
09.719: <09>Lane 00 nibble 1 raw readback: 005b
09.719: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005b
09.719: <09>Lane 00 nibble 1 adjusted value (post nibble): 005b
09.719: <09>Lane 01 nibble 1 raw readback: 0055
09.719: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0055
09.719: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
09.719: <09>Lane 02 nibble 1 raw readback: 0050
09.719: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0050
09.719: <09>Lane 02 nibble 1 adjusted value (post nibble): 0051
09.719: <09>Lane 03 nibble 1 raw readback: 004d
09.719: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004d
09.719: <09>Lane 03 nibble 1 adjusted value (post nibble): 004f
09.719: <09>Lane 04 nibble 1 raw readback: 003a
09.719: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003a
09.719: <09>Lane 04 nibble 1 adjusted value (post nibble): 003e
09.719: <09>Lane 05 nibble 1 raw readback: 0041
09.719: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0041
09.719: <09>Lane 05 nibble 1 adjusted value (post nibble): 0044
09.719: <09>Lane 06 nibble 1 raw readback: 0046
09.719: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0046
09.719: <09>Lane 06 nibble 1 adjusted value (post nibble): 0048
09.719: <09>Lane 07 nibble 1 raw readback: 004b
09.719: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004b
09.719: <09>Lane 07 nibble 1 adjusted value (post nibble): 004c
09.719: <09>Lane 08 nibble 1 raw readback: 003f
09.719: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003f
09.719: <09>Lane 08 nibble 1 adjusted value (post nibble): 0042
09.719: <09>original critical gross delay: 0
09.719: <09>new critical gross delay: 0
09.719: DIMM 1 RttNom: 5
09.719: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.719: DIMM 1 RttNom: 5
09.719: DIMM 1 RttWr: 2
09.719: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.719: DIMM 1 RttWr: 2
09.719: DIMM 1 RttNom: 5
09.719: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.719: DIMM 1 RttNom: 5
09.719: DIMM 1 RttWr: 2
09.719: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.719: DIMM 1 RttWr: 2
09.719: DIMM 0 RttNom: 5
09.719: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.719: DIMM 1 RttNom: 5
09.719: DIMM 0 RttWr: 2
09.719: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.719: DIMM 1 RttWr: 2
09.719: DIMM 0 RttNom: 5
09.719: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.719: DIMM 1 RttNom: 5
09.719: DIMM 0 RttWr: 2
09.719: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.719: DIMM 1 RttWr: 2
09.720: SetTargetFreq: Start
09.720: SetTargetFreq: Node 2: New frequency code: 0012
09.720: ChangeMemClk: Start
09.720: set_2t_configuration: Start
09.720: set_2t_configuration: Done
09.720: mct_BeforePlatformSpec: Start
09.720: mct_BeforePlatformSpec: Done
09.720: mct_PlatformSpec: Start
09.720: Programmed DCT 0 timing/termination pattern 00353935 30222222
09.720: mct_PlatformSpec: Done
09.720: set_2t_configuration: Start
09.720: set_2t_configuration: Done
09.720: mct_BeforePlatformSpec: Start
09.720: mct_BeforePlatformSpec: Done
09.720: mct_PlatformSpec: Start
09.720: Programmed DCT 1 timing/termination pattern 00353935 30222222
09.720: mct_PlatformSpec: Done
09.720: ChangeMemClk: Done
09.720: phyAssistedMemFnceTraining: Start
09.720: phyAssistedMemFnceTraining: training node 2 DCT 0
09.720: phyAssistedMemFnceTraining: done training node 2 DCT 0
09.720: phyAssistedMemFnceTraining: training node 2 DCT 1
09.720: phyAssistedMemFnceTraining: done training node 2 DCT 1
09.720: phyAssistedMemFnceTraining: Done
09.720: InitPhyCompensation: DCT 0: Start
09.720: Waiting for predriver calibration to be applied...done!
09.721: InitPhyCompensation: DCT 0: Done
09.721: phyAssistedMemFnceTraining: Start
09.721: phyAssistedMemFnceTraining: training node 2 DCT 0
09.721: phyAssistedMemFnceTraining: done training node 2 DCT 0
09.721: phyAssistedMemFnceTraining: training node 2 DCT 1
09.721: phyAssistedMemFnceTraining: done training node 2 DCT 1
09.721: phyAssistedMemFnceTraining: Done
09.721: InitPhyCompensation: DCT 1: Start
09.721: Waiting for predriver calibration to be applied...done!
09.721: InitPhyCompensation: DCT 1: Done
09.721: Preparing to send DCT 0 DIMM 0 RC10: 03 (F2xA8: 02000300)
09.721: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.721: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
09.721: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.721: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
09.721: Preparing to send DCT 0 DIMM 1 RC10: 03 (F2xA8: 02000c00)
09.721: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.721: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
09.721: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.721: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
09.721: Preparing to send DCT 1 DIMM 0 RC10: 03 (F2xA8: 02000300)
09.721: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.721: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
09.721: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.721: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
09.722: Preparing to send DCT 1 DIMM 1 RC10: 03 (F2xA8: 02000c00)
09.721: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.721: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
09.721: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.722: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
09.722: SetTargetFreq: Done
09.722: SPD2ndTiming: Start
09.722: SPD2ndTiming: Done
09.722: mct_BeforeDramInit_Prod_D: Start
09.722: mct_ProgramODT_D: Start
09.722: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
09.722: mct_ProgramODT_D: Done
09.722: mct_BeforeDramInit_Prod_D: Done
09.722: mct_DramInit_Sw_D: Start
09.722: DIMM 0 RttWr: 1
09.722: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.722: mct_SendMrsCmd: Start
09.722: mct_SendMrsCmd: Done
09.722: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
09.722: mct_SendMrsCmd: Start
09.722: mct_SendMrsCmd: Done
09.722: DIMM 0 RttNom: 4
09.722: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.722: mct_SendMrsCmd: Start
09.722: mct_SendMrsCmd: Done
09.722: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001d78
09.722: mct_SendMrsCmd: Start
09.722: mct_SendMrsCmd: Done
09.722: DIMM 0 RttWr: 1
09.722: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.722: mct_SendMrsCmd: Start
09.722: mct_SendMrsCmd: Done
09.722: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
09.722: mct_SendMrsCmd: Start
09.722: mct_SendMrsCmd: Done
09.722: DIMM 0 RttNom: 4
09.722: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.722: mct_SendMrsCmd: Start
09.722: mct_SendMrsCmd: Done
09.722: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201d78
09.722: mct_SendMrsCmd: Start
09.722: mct_SendMrsCmd: Done
09.722: DIMM 1 RttWr: 1
09.722: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.722: mct_SendMrsCmd: Start
09.722: mct_SendMrsCmd: Done
09.722: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
09.722: mct_SendMrsCmd: Start
09.723: mct_SendMrsCmd: Done
09.723: DIMM 1 RttNom: 4
09.723: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.723: mct_SendMrsCmd: Start
09.723: mct_SendMrsCmd: Done
09.723: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401d78
09.723: mct_SendMrsCmd: Start
09.723: mct_SendMrsCmd: Done
09.723: DIMM 1 RttWr: 1
09.723: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.723: mct_SendMrsCmd: Start
09.723: mct_SendMrsCmd: Done
09.723: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
09.723: mct_SendMrsCmd: Start
09.723: mct_SendMrsCmd: Done
09.723: DIMM 1 RttNom: 4
09.723: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.723: mct_SendMrsCmd: Start
09.723: mct_SendMrsCmd: Done
09.723: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601d78
09.723: mct_SendMrsCmd: Start
09.723: mct_SendMrsCmd: Done
09.723: mct_DramInit_Sw_D: Done
09.723: AgesaHwWlPhase1: training nibble 0
09.723: DIMM 0 RttNom: 4
09.723: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.723: DIMM 0 RttWr: 1
09.723: DIMM 0 RttWr: 1
09.723: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.723: DIMM 0 RttWr: 1
09.723: DIMM 0 RttNom: 4
09.723: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.723: DIMM 0 RttNom: 4
09.723: DIMM 0 RttWr: 1
09.723: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.723: DIMM 0 RttWr: 1
09.723: DIMM 1 RttNom: 4
09.723: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.723: DIMM 0 RttNom: 4
09.723: DIMM 1 RttWr: 1
09.723: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.723: DIMM 0 RttWr: 1
09.723: DIMM 1 RttNom: 4
09.723: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.723: DIMM 0 RttNom: 4
09.723: DIMM 1 RttWr: 1
09.723: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.723: DIMM 0 RttWr: 1
09.723: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.724: <09>Lane 00 scaled delay: 007c
09.724: <09>Lane 00 new seed: 007c
09.724: <09>Lane 01 scaled delay: 0072
09.724: <09>Lane 01 new seed: 0072
09.724: <09>Lane 02 scaled delay: 006f
09.724: <09>Lane 02 new seed: 006f
09.724: <09>Lane 03 scaled delay: 006a
09.724: <09>Lane 03 new seed: 006a
09.724: <09>Lane 04 scaled delay: 0055
09.724: <09>Lane 04 new seed: 0055
09.724: <09>Lane 05 scaled delay: 005d
09.724: <09>Lane 05 new seed: 005d
09.724: <09>Lane 06 scaled delay: 0063
09.724: <09>Lane 06 new seed: 0063
09.724: <09>Lane 07 scaled delay: 0066
09.724: <09>Lane 07 new seed: 0066
09.724: <09>Lane 08 scaled delay: 0058
09.724: <09>Lane 08 new seed: 0058
09.724: <09>Lane 00 nibble 0 raw readback: 0042
09.724: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0082
09.724: <09>Lane 00 nibble 0 adjusted value (post nibble): 0082
09.724: <09>Lane 01 nibble 0 raw readback: 0034
09.724: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0074
09.724: <09>Lane 01 nibble 0 adjusted value (post nibble): 0074
09.724: <09>Lane 02 nibble 0 raw readback: 0032
09.724: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0072
09.724: <09>Lane 02 nibble 0 adjusted value (post nibble): 0072
09.724: <09>Lane 03 nibble 0 raw readback: 002c
09.724: <09>Lane 03 nibble 0 adjusted value (pre nibble): 006c
09.724: <09>Lane 03 nibble 0 adjusted value (post nibble): 006c
09.724: <09>Lane 04 nibble 0 raw readback: 0059
09.724: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0059
09.724: <09>Lane 04 nibble 0 adjusted value (post nibble): 0059
09.724: <09>Lane 05 nibble 0 raw readback: 0060
09.724: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0060
09.724: <09>Lane 05 nibble 0 adjusted value (post nibble): 0060
09.724: <09>Lane 06 nibble 0 raw readback: 0026
09.724: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0066
09.724: <09>Lane 06 nibble 0 adjusted value (post nibble): 0066
09.724: <09>Lane 07 nibble 0 raw readback: 002b
09.724: <09>Lane 07 nibble 0 adjusted value (pre nibble): 006b
09.724: <09>Lane 07 nibble 0 adjusted value (post nibble): 006b
09.724: <09>Lane 08 nibble 0 raw readback: 005c
09.724: <09>Lane 08 nibble 0 adjusted value (pre nibble): 005c
09.724: <09>Lane 08 nibble 0 adjusted value (post nibble): 005c
09.724: AgesaHwWlPhase1: training nibble 1
09.724: DIMM 0 RttNom: 4
09.724: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.724: DIMM 0 RttWr: 1
09.724: DIMM 0 RttWr: 1
09.724: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.724: DIMM 0 RttWr: 1
09.724: DIMM 0 RttNom: 4
09.724: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.724: DIMM 0 RttNom: 4
09.725: DIMM 0 RttWr: 1
09.725: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.725: DIMM 0 RttWr: 1
09.725: DIMM 1 RttNom: 4
09.725: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.725: DIMM 0 RttNom: 4
09.725: DIMM 1 RttWr: 1
09.725: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.725: DIMM 0 RttWr: 1
09.725: DIMM 1 RttNom: 4
09.725: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.725: DIMM 0 RttNom: 4
09.725: DIMM 1 RttWr: 1
09.725: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.725: DIMM 0 RttWr: 1
09.725: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.725: <09>Lane 00 new seed: 007c
09.725: <09>Lane 01 new seed: 0072
09.725: <09>Lane 02 new seed: 006f
09.725: <09>Lane 03 new seed: 006a
09.725: <09>Lane 04 new seed: 0055
09.725: <09>Lane 05 new seed: 005d
09.725: <09>Lane 06 new seed: 0063
09.725: <09>Lane 07 new seed: 0066
09.725: <09>Lane 08 new seed: 0058
09.725: <09>Lane 00 nibble 1 raw readback: 0041
09.725: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0081
09.725: <09>Lane 00 nibble 1 adjusted value (post nibble): 007e
09.725: <09>Lane 01 nibble 1 raw readback: 0038
09.725: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0078
09.725: <09>Lane 01 nibble 1 adjusted value (post nibble): 0075
09.725: <09>Lane 02 nibble 1 raw readback: 0032
09.725: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0072
09.725: <09>Lane 02 nibble 1 adjusted value (post nibble): 0070
09.725: <09>Lane 03 nibble 1 raw readback: 002c
09.725: <09>Lane 03 nibble 1 adjusted value (pre nibble): 006c
09.725: <09>Lane 03 nibble 1 adjusted value (post nibble): 006b
09.725: <09>Lane 04 nibble 1 raw readback: 0057
09.725: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0057
09.725: <09>Lane 04 nibble 1 adjusted value (post nibble): 0056
09.725: <09>Lane 05 nibble 1 raw readback: 0060
09.725: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0060
09.725: <09>Lane 05 nibble 1 adjusted value (post nibble): 005e
09.725: <09>Lane 06 nibble 1 raw readback: 0026
09.725: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0066
09.725: <09>Lane 06 nibble 1 adjusted value (post nibble): 0064
09.725: <09>Lane 07 nibble 1 raw readback: 002a
09.725: <09>Lane 07 nibble 1 adjusted value (pre nibble): 006a
09.725: <09>Lane 07 nibble 1 adjusted value (post nibble): 0068
09.725: <09>Lane 08 nibble 1 raw readback: 0059
09.725: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0059
09.725: <09>Lane 08 nibble 1 adjusted value (post nibble): 0058
09.725: <09>original critical gross delay: 0
09.725: <09>new critical gross delay: 0
09.725: DIMM 0 RttNom: 4
09.725: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.725: DIMM 0 RttNom: 4
09.725: DIMM 0 RttWr: 1
09.725: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.725: DIMM 0 RttWr: 1
09.725: DIMM 0 RttNom: 4
09.725: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.725: DIMM 0 RttNom: 4
09.726: DIMM 0 RttWr: 1
09.726: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.726: DIMM 0 RttWr: 1
09.726: DIMM 1 RttNom: 4
09.726: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.726: DIMM 0 RttNom: 4
09.726: DIMM 1 RttWr: 1
09.726: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.726: DIMM 0 RttWr: 1
09.726: DIMM 1 RttNom: 4
09.726: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.726: DIMM 0 RttNom: 4
09.726: DIMM 1 RttWr: 1
09.726: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.726: DIMM 0 RttWr: 1
09.726: AgesaHwWlPhase1: training nibble 0
09.726: DIMM 1 RttNom: 4
09.726: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.726: DIMM 1 RttWr: 1
09.726: DIMM 1 RttWr: 1
09.726: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.726: DIMM 1 RttWr: 1
09.726: DIMM 1 RttNom: 4
09.726: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.726: DIMM 1 RttNom: 4
09.726: DIMM 1 RttWr: 1
09.726: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.726: DIMM 1 RttWr: 1
09.726: DIMM 0 RttNom: 4
09.726: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.726: DIMM 1 RttNom: 4
09.726: DIMM 0 RttWr: 1
09.726: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.726: DIMM 1 RttWr: 1
09.726: DIMM 0 RttNom: 4
09.726: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.726: DIMM 1 RttNom: 4
09.726: DIMM 0 RttWr: 1
09.726: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.726: DIMM 1 RttWr: 1
09.726: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.726: <09>Lane 00 scaled delay: 006a
09.726: <09>Lane 00 new seed: 006a
09.726: <09>Lane 01 scaled delay: 0060
09.726: <09>Lane 01 new seed: 0060
09.726: <09>Lane 02 scaled delay: 0060
09.726: <09>Lane 02 new seed: 0060
09.726: <09>Lane 03 scaled delay: 0059
09.726: <09>Lane 03 new seed: 0059
09.726: <09>Lane 04 scaled delay: 0047
09.726: <09>Lane 04 new seed: 0047
09.726: <09>Lane 05 scaled delay: 004e
09.726: <09>Lane 05 new seed: 004e
09.726: <09>Lane 06 scaled delay: 0053
09.726: <09>Lane 06 new seed: 0053
09.726: <09>Lane 07 scaled delay: 0058
09.726: <09>Lane 07 new seed: 0058
09.726: <09>Lane 08 scaled delay: 0049
09.726: <09>Lane 08 new seed: 0049
09.726: <09>Lane 00 nibble 0 raw readback: 0031
09.726: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0071
09.726: <09>Lane 00 nibble 0 adjusted value (post nibble): 0071
09.726: <09>Lane 01 nibble 0 raw readback: 0024
09.727: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0064
09.727: <09>Lane 01 nibble 0 adjusted value (post nibble): 0064
09.727: <09>Lane 02 nibble 0 raw readback: 0021
09.727: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0061
09.727: <09>Lane 02 nibble 0 adjusted value (post nibble): 0061
09.727: <09>Lane 03 nibble 0 raw readback: 0059
09.727: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0059
09.727: <09>Lane 03 nibble 0 adjusted value (post nibble): 0059
09.727: <09>Lane 04 nibble 0 raw readback: 0045
09.727: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0045
09.727: <09>Lane 04 nibble 0 adjusted value (post nibble): 0045
09.727: <09>Lane 05 nibble 0 raw readback: 004f
09.727: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004f
09.727: <09>Lane 05 nibble 0 adjusted value (post nibble): 004f
09.727: <09>Lane 06 nibble 0 raw readback: 0055
09.727: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0055
09.727: <09>Lane 06 nibble 0 adjusted value (post nibble): 0055
09.727: <09>Lane 07 nibble 0 raw readback: 005a
09.727: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005a
09.727: <09>Lane 07 nibble 0 adjusted value (post nibble): 005a
09.727: <09>Lane 08 nibble 0 raw readback: 004b
09.727: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004b
09.727: <09>Lane 08 nibble 0 adjusted value (post nibble): 004b
09.727: AgesaHwWlPhase1: training nibble 1
09.727: DIMM 1 RttNom: 4
09.727: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.727: DIMM 1 RttWr: 1
09.727: DIMM 1 RttWr: 1
09.727: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.727: DIMM 1 RttWr: 1
09.727: DIMM 1 RttNom: 4
09.727: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.727: DIMM 1 RttNom: 4
09.727: DIMM 1 RttWr: 1
09.727: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.727: DIMM 1 RttWr: 1
09.727: DIMM 0 RttNom: 4
09.727: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.727: DIMM 1 RttNom: 4
09.727: DIMM 0 RttWr: 1
09.727: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.727: DIMM 1 RttWr: 1
09.727: DIMM 0 RttNom: 4
09.727: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.727: DIMM 1 RttNom: 4
09.727: DIMM 0 RttWr: 1
09.727: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.727: DIMM 1 RttWr: 1
09.727: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.727: <09>Lane 00 new seed: 006a
09.727: <09>Lane 01 new seed: 0060
09.727: <09>Lane 02 new seed: 0060
09.727: <09>Lane 03 new seed: 0059
09.727: <09>Lane 04 new seed: 0047
09.727: <09>Lane 05 new seed: 004e
09.727: <09>Lane 06 new seed: 0053
09.727: <09>Lane 07 new seed: 0058
09.727: <09>Lane 08 new seed: 0049
09.727: <09>Lane 00 nibble 1 raw readback: 0030
09.727: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0070
09.727: <09>Lane 00 nibble 1 adjusted value (post nibble): 006d
09.727: <09>Lane 01 nibble 1 raw readback: 0025
09.727: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0065
09.727: <09>Lane 01 nibble 1 adjusted value (post nibble): 0062
09.727: <09>Lane 02 nibble 1 raw readback: 0025
09.727: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0065
09.727: <09>Lane 02 nibble 1 adjusted value (post nibble): 0062
09.727: <09>Lane 03 nibble 1 raw readback: 005d
09.727: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005d
09.727: <09>Lane 03 nibble 1 adjusted value (post nibble): 005b
09.727: <09>Lane 04 nibble 1 raw readback: 0048
09.727: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0048
09.727: <09>Lane 04 nibble 1 adjusted value (post nibble): 0047
09.727: <09>Lane 05 nibble 1 raw readback: 004f
09.727: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004f
09.727: <09>Lane 05 nibble 1 adjusted value (post nibble): 004e
09.727: <09>Lane 06 nibble 1 raw readback: 0055
09.727: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0055
09.728: <09>Lane 06 nibble 1 adjusted value (post nibble): 0054
09.728: <09>Lane 07 nibble 1 raw readback: 005c
09.728: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005c
09.728: <09>Lane 07 nibble 1 adjusted value (post nibble): 005a
09.728: <09>Lane 08 nibble 1 raw readback: 004b
09.728: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004b
09.728: <09>Lane 08 nibble 1 adjusted value (post nibble): 004a
09.728: <09>original critical gross delay: 0
09.728: <09>new critical gross delay: 0
09.728: DIMM 1 RttNom: 4
09.728: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.728: DIMM 1 RttNom: 4
09.728: DIMM 1 RttWr: 1
09.728: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.728: DIMM 1 RttWr: 1
09.728: DIMM 1 RttNom: 4
09.728: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.728: DIMM 1 RttNom: 4
09.728: DIMM 1 RttWr: 1
09.728: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.728: DIMM 1 RttWr: 1
09.728: DIMM 0 RttNom: 4
09.728: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.728: DIMM 1 RttNom: 4
09.728: DIMM 0 RttWr: 1
09.728: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.728: DIMM 1 RttWr: 1
09.728: DIMM 0 RttNom: 4
09.728: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.728: DIMM 1 RttNom: 4
09.728: DIMM 0 RttWr: 1
09.728: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.728: DIMM 1 RttWr: 1
09.728: SPD2ndTiming: Start
09.729: SPD2ndTiming: Done
09.729: mct_BeforeDramInit_Prod_D: Start
09.729: mct_ProgramODT_D: Start
09.729: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
09.729: mct_ProgramODT_D: Done
09.729: mct_BeforeDramInit_Prod_D: Done
09.729: mct_DramInit_Sw_D: Start
09.729: DIMM 0 RttWr: 1
09.729: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.729: mct_SendMrsCmd: Start
09.729: mct_SendMrsCmd: Done
09.729: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
09.729: mct_SendMrsCmd: Start
09.729: mct_SendMrsCmd: Done
09.729: DIMM 0 RttNom: 4
09.729: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.729: mct_SendMrsCmd: Start
09.729: mct_SendMrsCmd: Done
09.729: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001d78
09.729: mct_SendMrsCmd: Start
09.729: mct_SendMrsCmd: Done
09.729: DIMM 0 RttWr: 1
09.729: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.729: mct_SendMrsCmd: Start
09.729: mct_SendMrsCmd: Done
09.729: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
09.729: mct_SendMrsCmd: Start
09.729: mct_SendMrsCmd: Done
09.729: DIMM 0 RttNom: 4
09.729: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.729: mct_SendMrsCmd: Start
09.729: mct_SendMrsCmd: Done
09.729: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201d78
09.729: mct_SendMrsCmd: Start
09.729: mct_SendMrsCmd: Done
09.729: DIMM 1 RttWr: 1
09.729: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.729: mct_SendMrsCmd: Start
09.729: mct_SendMrsCmd: Done
09.729: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
09.729: mct_SendMrsCmd: Start
09.729: mct_SendMrsCmd: Done
09.729: DIMM 1 RttNom: 4
09.729: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.729: mct_SendMrsCmd: Start
09.729: mct_SendMrsCmd: Done
09.729: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401d78
09.729: mct_SendMrsCmd: Start
09.729: mct_SendMrsCmd: Done
09.729: DIMM 1 RttWr: 1
09.729: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.729: mct_SendMrsCmd: Start
09.729: mct_SendMrsCmd: Done
09.729: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
09.729: mct_SendMrsCmd: Start
09.729: mct_SendMrsCmd: Done
09.729: DIMM 1 RttNom: 4
09.729: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.729: mct_SendMrsCmd: Start
09.729: mct_SendMrsCmd: Done
09.729: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601d78
09.729: mct_SendMrsCmd: Start
09.729: mct_SendMrsCmd: Done
09.729: mct_DramInit_Sw_D: Done
09.729: AgesaHwWlPhase1: training nibble 0
09.730: DIMM 0 RttNom: 4
09.730: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.730: DIMM 0 RttWr: 1
09.730: DIMM 0 RttWr: 1
09.730: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.730: DIMM 0 RttWr: 1
09.730: DIMM 0 RttNom: 4
09.730: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.730: DIMM 0 RttNom: 4
09.730: DIMM 0 RttWr: 1
09.730: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.730: DIMM 0 RttWr: 1
09.730: DIMM 1 RttNom: 4
09.730: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.730: DIMM 0 RttNom: 4
09.730: DIMM 1 RttWr: 1
09.730: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.730: DIMM 0 RttWr: 1
09.730: DIMM 1 RttNom: 4
09.730: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.730: DIMM 0 RttNom: 4
09.730: DIMM 1 RttWr: 1
09.730: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.730: DIMM 0 RttWr: 1
09.730: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.730: <09>Lane 00 scaled delay: 0078
09.730: <09>Lane 00 new seed: 0078
09.730: <09>Lane 01 scaled delay: 0071
09.730: <09>Lane 01 new seed: 0071
09.730: <09>Lane 02 scaled delay: 006d
09.730: <09>Lane 02 new seed: 006d
09.730: <09>Lane 03 scaled delay: 0069
09.730: <09>Lane 03 new seed: 0069
09.730: <09>Lane 04 scaled delay: 0053
09.730: <09>Lane 04 new seed: 0053
09.730: <09>Lane 05 scaled delay: 005b
09.730: <09>Lane 05 new seed: 005b
09.730: <09>Lane 06 scaled delay: 0060
09.730: <09>Lane 06 new seed: 0060
09.730: <09>Lane 07 scaled delay: 0064
09.730: <09>Lane 07 new seed: 0064
09.730: <09>Lane 08 scaled delay: 0059
09.730: <09>Lane 08 new seed: 0059
09.730: <09>Lane 00 nibble 0 raw readback: 003e
09.730: <09>Lane 00 nibble 0 adjusted value (pre nibble): 007e
09.730: <09>Lane 00 nibble 0 adjusted value (post nibble): 007e
09.730: <09>Lane 01 nibble 0 raw readback: 0038
09.730: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0078
09.730: <09>Lane 01 nibble 0 adjusted value (post nibble): 0078
09.730: <09>Lane 02 nibble 0 raw readback: 002f
09.730: <09>Lane 02 nibble 0 adjusted value (pre nibble): 006f
09.730: <09>Lane 02 nibble 0 adjusted value (post nibble): 006f
09.730: <09>Lane 03 nibble 0 raw readback: 002a
09.731: <09>Lane 03 nibble 0 adjusted value (pre nibble): 006a
09.731: <09>Lane 03 nibble 0 adjusted value (post nibble): 006a
09.731: <09>Lane 04 nibble 0 raw readback: 0055
09.731: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0055
09.731: <09>Lane 04 nibble 0 adjusted value (post nibble): 0055
09.731: <09>Lane 05 nibble 0 raw readback: 005e
09.731: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005e
09.731: <09>Lane 05 nibble 0 adjusted value (post nibble): 005e
09.731: <09>Lane 06 nibble 0 raw readback: 0024
09.731: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0064
09.731: <09>Lane 06 nibble 0 adjusted value (post nibble): 0064
09.731: <09>Lane 07 nibble 0 raw readback: 0026
09.731: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0066
09.731: <09>Lane 07 nibble 0 adjusted value (post nibble): 0066
09.731: <09>Lane 08 nibble 0 raw readback: 005a
09.731: <09>Lane 08 nibble 0 adjusted value (pre nibble): 005a
09.731: <09>Lane 08 nibble 0 adjusted value (post nibble): 005a
09.731: AgesaHwWlPhase1: training nibble 1
09.731: DIMM 0 RttNom: 4
09.731: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.731: DIMM 0 RttWr: 1
09.731: DIMM 0 RttWr: 1
09.731: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.731: DIMM 0 RttWr: 1
09.731: DIMM 0 RttNom: 4
09.731: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.731: DIMM 0 RttNom: 4
09.731: DIMM 0 RttWr: 1
09.731: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.731: DIMM 0 RttWr: 1
09.731: DIMM 1 RttNom: 4
09.731: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.731: DIMM 0 RttNom: 4
09.731: DIMM 1 RttWr: 1
09.731: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.731: DIMM 0 RttWr: 1
09.731: DIMM 1 RttNom: 4
09.731: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.731: DIMM 0 RttNom: 4
09.731: DIMM 1 RttWr: 1
09.731: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.731: DIMM 0 RttWr: 1
09.731: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.731: <09>Lane 00 new seed: 0078
09.731: <09>Lane 01 new seed: 0071
09.731: <09>Lane 02 new seed: 006d
09.731: <09>Lane 03 new seed: 0069
09.731: <09>Lane 04 new seed: 0053
09.731: <09>Lane 05 new seed: 005b
09.731: <09>Lane 06 new seed: 0060
09.731: <09>Lane 07 new seed: 0064
09.731: <09>Lane 08 new seed: 0059
09.731: <09>Lane 00 nibble 1 raw readback: 003d
09.731: <09>Lane 00 nibble 1 adjusted value (pre nibble): 007d
09.731: <09>Lane 00 nibble 1 adjusted value (post nibble): 007a
09.731: <09>Lane 01 nibble 1 raw readback: 0037
09.731: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0077
09.731: <09>Lane 01 nibble 1 adjusted value (post nibble): 0074
09.731: <09>Lane 02 nibble 1 raw readback: 002f
09.731: <09>Lane 02 nibble 1 adjusted value (pre nibble): 006f
09.731: <09>Lane 02 nibble 1 adjusted value (post nibble): 006e
09.731: <09>Lane 03 nibble 1 raw readback: 002b
09.731: <09>Lane 03 nibble 1 adjusted value (pre nibble): 006b
09.731: <09>Lane 03 nibble 1 adjusted value (post nibble): 006a
09.731: <09>Lane 04 nibble 1 raw readback: 0055
09.731: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0055
09.732: <09>Lane 04 nibble 1 adjusted value (post nibble): 0054
09.731: <09>Lane 05 nibble 1 raw readback: 005e
09.732: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005e
09.732: <09>Lane 05 nibble 1 adjusted value (post nibble): 005c
09.732: <09>Lane 06 nibble 1 raw readback: 0023
09.732: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0063
09.732: <09>Lane 06 nibble 1 adjusted value (post nibble): 0061
09.732: <09>Lane 07 nibble 1 raw readback: 0026
09.732: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0066
09.732: <09>Lane 07 nibble 1 adjusted value (post nibble): 0065
09.732: <09>Lane 08 nibble 1 raw readback: 0059
09.732: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0059
09.732: <09>Lane 08 nibble 1 adjusted value (post nibble): 0059
09.732: <09>original critical gross delay: 0
09.732: <09>new critical gross delay: 0
09.732: DIMM 0 RttNom: 4
09.732: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.732: DIMM 0 RttNom: 4
09.732: DIMM 0 RttWr: 1
09.732: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.732: DIMM 0 RttWr: 1
09.732: DIMM 0 RttNom: 4
09.732: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.732: DIMM 0 RttNom: 4
09.732: DIMM 0 RttWr: 1
09.732: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.732: DIMM 0 RttWr: 1
09.732: DIMM 1 RttNom: 4
09.732: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.732: DIMM 0 RttNom: 4
09.732: DIMM 1 RttWr: 1
09.732: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.732: DIMM 0 RttWr: 1
09.732: DIMM 1 RttNom: 4
09.732: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.732: DIMM 0 RttNom: 4
09.732: DIMM 1 RttWr: 1
09.732: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.732: DIMM 0 RttWr: 1
09.732: AgesaHwWlPhase1: training nibble 0
09.732: DIMM 1 RttNom: 4
09.732: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.732: DIMM 1 RttWr: 1
09.732: DIMM 1 RttWr: 1
09.732: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.732: DIMM 1 RttWr: 1
09.732: DIMM 1 RttNom: 4
09.732: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.732: DIMM 1 RttNom: 4
09.732: DIMM 1 RttWr: 1
09.732: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.732: DIMM 1 RttWr: 1
09.732: DIMM 0 RttNom: 4
09.732: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.732: DIMM 1 RttNom: 4
09.732: DIMM 0 RttWr: 1
09.732: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.732: DIMM 1 RttWr: 1
09.732: DIMM 0 RttNom: 4
09.732: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.732: DIMM 1 RttNom: 4
09.732: DIMM 0 RttWr: 1
09.733: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.733: DIMM 1 RttWr: 1
09.733: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.733: <09>Lane 00 scaled delay: 0066
09.733: <09>Lane 00 new seed: 0066
09.733: <09>Lane 01 scaled delay: 0060
09.733: <09>Lane 01 new seed: 0060
09.733: <09>Lane 02 scaled delay: 005a
09.733: <09>Lane 02 new seed: 005a
09.733: <09>Lane 03 scaled delay: 0058
09.733: <09>Lane 03 new seed: 0058
09.733: <09>Lane 04 scaled delay: 0043
09.733: <09>Lane 04 new seed: 0043
09.733: <09>Lane 05 scaled delay: 004b
09.733: <09>Lane 05 new seed: 004b
09.733: <09>Lane 06 scaled delay: 004f
09.733: <09>Lane 06 new seed: 004f
09.733: <09>Lane 07 scaled delay: 0054
09.733: <09>Lane 07 new seed: 0054
09.733: <09>Lane 08 scaled delay: 0048
09.733: <09>Lane 08 new seed: 0048
09.733: <09>Lane 00 nibble 0 raw readback: 002e
09.733: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006e
09.733: <09>Lane 00 nibble 0 adjusted value (post nibble): 006e
09.733: <09>Lane 01 nibble 0 raw readback: 0026
09.733: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0066
09.733: <09>Lane 01 nibble 0 adjusted value (post nibble): 0066
09.733: <09>Lane 02 nibble 0 raw readback: 005f
09.733: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005f
09.733: <09>Lane 02 nibble 0 adjusted value (post nibble): 005f
09.733: <09>Lane 03 nibble 0 raw readback: 0059
09.733: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0059
09.733: <09>Lane 03 nibble 0 adjusted value (post nibble): 0059
09.733: <09>Lane 04 nibble 0 raw readback: 0044
09.733: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0044
09.733: <09>Lane 04 nibble 0 adjusted value (post nibble): 0044
09.733: <09>Lane 05 nibble 0 raw readback: 004d
09.733: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004d
09.733: <09>Lane 05 nibble 0 adjusted value (post nibble): 004d
09.733: <09>Lane 06 nibble 0 raw readback: 0051
09.733: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0051
09.733: <09>Lane 06 nibble 0 adjusted value (post nibble): 0051
09.733: <09>Lane 07 nibble 0 raw readback: 0058
09.733: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0058
09.733: <09>Lane 07 nibble 0 adjusted value (post nibble): 0058
09.733: <09>Lane 08 nibble 0 raw readback: 004a
09.733: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004a
09.733: <09>Lane 08 nibble 0 adjusted value (post nibble): 004a
09.733: AgesaHwWlPhase1: training nibble 1
09.733: DIMM 1 RttNom: 4
09.733: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.733: DIMM 1 RttWr: 1
09.733: DIMM 1 RttWr: 1
09.733: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.733: DIMM 1 RttWr: 1
09.733: DIMM 1 RttNom: 4
09.733: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.733: DIMM 1 RttNom: 4
09.733: DIMM 1 RttWr: 1
09.733: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.733: DIMM 1 RttWr: 1
09.733: DIMM 0 RttNom: 4
09.733: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.733: DIMM 1 RttNom: 4
09.733: DIMM 0 RttWr: 1
09.733: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.733: DIMM 1 RttWr: 1
09.733: DIMM 0 RttNom: 4
09.733: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.733: DIMM 1 RttNom: 4
09.733: DIMM 0 RttWr: 1
09.733: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.734: DIMM 1 RttWr: 1
09.734: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.734: <09>Lane 00 new seed: 0066
09.734: <09>Lane 01 new seed: 0060
09.734: <09>Lane 02 new seed: 005a
09.734: <09>Lane 03 new seed: 0058
09.734: <09>Lane 04 new seed: 0043
09.734: <09>Lane 05 new seed: 004b
09.734: <09>Lane 06 new seed: 004f
09.734: <09>Lane 07 new seed: 0054
09.734: <09>Lane 08 new seed: 0048
09.734: <09>Lane 00 nibble 1 raw readback: 002c
09.734: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006c
09.734: <09>Lane 00 nibble 1 adjusted value (post nibble): 0069
09.734: <09>Lane 01 nibble 1 raw readback: 0025
09.734: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0065
09.734: <09>Lane 01 nibble 1 adjusted value (post nibble): 0062
09.734: <09>Lane 02 nibble 1 raw readback: 005e
09.734: <09>Lane 02 nibble 1 adjusted value (pre nibble): 005e
09.734: <09>Lane 02 nibble 1 adjusted value (post nibble): 005c
09.734: <09>Lane 03 nibble 1 raw readback: 005a
09.734: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005a
09.734: <09>Lane 03 nibble 1 adjusted value (post nibble): 0059
09.734: <09>Lane 04 nibble 1 raw readback: 0046
09.734: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0046
09.734: <09>Lane 04 nibble 1 adjusted value (post nibble): 0044
09.734: <09>Lane 05 nibble 1 raw readback: 004d
09.734: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004d
09.734: <09>Lane 05 nibble 1 adjusted value (post nibble): 004c
09.734: <09>Lane 06 nibble 1 raw readback: 0052
09.734: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0052
09.734: <09>Lane 06 nibble 1 adjusted value (post nibble): 0050
09.734: <09>Lane 07 nibble 1 raw readback: 0057
09.734: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0057
09.734: <09>Lane 07 nibble 1 adjusted value (post nibble): 0055
09.734: <09>Lane 08 nibble 1 raw readback: 004a
09.734: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004a
09.734: <09>Lane 08 nibble 1 adjusted value (post nibble): 0049
09.734: <09>original critical gross delay: 0
09.734: <09>new critical gross delay: 0
09.734: DIMM 1 RttNom: 4
09.734: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.734: DIMM 1 RttNom: 4
09.734: DIMM 1 RttWr: 1
09.734: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.734: DIMM 1 RttWr: 1
09.734: DIMM 1 RttNom: 4
09.734: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.734: DIMM 1 RttNom: 4
09.734: DIMM 1 RttWr: 1
09.734: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.734: DIMM 1 RttWr: 1
09.734: DIMM 0 RttNom: 4
09.734: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.734: DIMM 1 RttNom: 4
09.734: DIMM 0 RttWr: 1
09.734: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.734: DIMM 1 RttWr: 1
09.734: DIMM 0 RttNom: 4
09.734: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.734: DIMM 1 RttNom: 4
09.734: DIMM 0 RttWr: 1
09.734: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.734: DIMM 1 RttWr: 1
09.735: activate_spd_rom() for node 03
09.735: enable_spd_node3()
09.735: SetTargetFreq: Start
09.735: SetTargetFreq: Node 3: New frequency code: 0006
09.735: ChangeMemClk: Start
09.735: set_2t_configuration: Start
09.735: set_2t_configuration: Done
09.735: mct_BeforePlatformSpec: Start
09.735: mct_BeforePlatformSpec: Done
09.735: mct_PlatformSpec: Start
09.735: Programmed DCT 0 timing/termination pattern 00000000 20222222
09.735: mct_PlatformSpec: Done
09.735: set_2t_configuration: Start
09.735: set_2t_configuration: Done
09.735: mct_BeforePlatformSpec: Start
09.735: mct_BeforePlatformSpec: Done
09.735: mct_PlatformSpec: Start
09.735: Programmed DCT 1 timing/termination pattern 00000000 20222222
09.735: mct_PlatformSpec: Done
09.735: ChangeMemClk: Done
09.735: phyAssistedMemFnceTraining: Start
09.735: phyAssistedMemFnceTraining: training node 3 DCT 0
09.736: phyAssistedMemFnceTraining: done training node 3 DCT 0
09.736: phyAssistedMemFnceTraining: training node 3 DCT 1
09.736: phyAssistedMemFnceTraining: done training node 3 DCT 1
09.736: phyAssistedMemFnceTraining: Done
09.736: InitPhyCompensation: DCT 0: Start
09.736: Waiting for predriver calibration to be applied...done!
09.736: InitPhyCompensation: DCT 0: Done
09.736: phyAssistedMemFnceTraining: Start
09.736: phyAssistedMemFnceTraining: training node 3 DCT 0
09.736: phyAssistedMemFnceTraining: done training node 3 DCT 0
09.736: phyAssistedMemFnceTraining: training node 3 DCT 1
09.736: phyAssistedMemFnceTraining: done training node 3 DCT 1
09.736: phyAssistedMemFnceTraining: Done
09.736: InitPhyCompensation: DCT 1: Start
09.736: Waiting for predriver calibration to be applied...done!
09.736: InitPhyCompensation: DCT 1: Done
09.736: Preparing to send DCT 0 DIMM 0 RC10: 00 (F2xA8: 02000300)
09.737: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.737: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
09.737: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.737: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
09.737: Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 02000c00)
09.737: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.737: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
09.737: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.737: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
09.737: Preparing to send DCT 1 DIMM 0 RC10: 00 (F2xA8: 02000300)
09.737: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.737: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
09.737: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.737: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
09.737: Preparing to send DCT 1 DIMM 1 RC10: 00 (F2xA8: 02000c00)
09.737: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.737: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
09.737: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.737: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
09.737: SetTargetFreq: Done
09.737: SPD2ndTiming: Start
09.737: SPD2ndTiming: Done
09.737: mct_BeforeDramInit_Prod_D: Start
09.737: mct_ProgramODT_D: Start
09.737: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
09.737: mct_ProgramODT_D: Done
09.738: mct_BeforeDramInit_Prod_D: Done
09.738: mct_DramInit_Sw_D: Start
09.738: DIMM 0 RttWr: 2
09.738: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.738: mct_SendMrsCmd: Start
09.738: mct_SendMrsCmd: Done
09.738: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
09.738: mct_SendMrsCmd: Start
09.738: mct_SendMrsCmd: Done
09.738: DIMM 0 RttNom: 3
09.738: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.738: mct_SendMrsCmd: Start
09.738: mct_SendMrsCmd: Done
09.738: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001578
09.738: mct_SendMrsCmd: Start
09.738: mct_SendMrsCmd: Done
09.738: DIMM 0 RttWr: 2
09.738: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.738: mct_SendMrsCmd: Start
09.738: mct_SendMrsCmd: Done
09.738: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
09.738: mct_SendMrsCmd: Start
09.738: mct_SendMrsCmd: Done
09.738: DIMM 0 RttNom: 3
09.738: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.738: mct_SendMrsCmd: Start
09.738: mct_SendMrsCmd: Done
09.738: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201578
09.738: mct_SendMrsCmd: Start
09.738: mct_SendMrsCmd: Done
09.738: DIMM 1 RttWr: 2
09.738: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.738: mct_SendMrsCmd: Start
09.738: mct_SendMrsCmd: Done
09.738: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
09.738: mct_SendMrsCmd: Start
09.738: mct_SendMrsCmd: Done
09.738: DIMM 1 RttNom: 3
09.738: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.738: mct_SendMrsCmd: Start
09.738: mct_SendMrsCmd: Done
09.738: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401578
09.738: mct_SendMrsCmd: Start
09.738: mct_SendMrsCmd: Done
09.738: DIMM 1 RttWr: 2
09.738: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.738: mct_SendMrsCmd: Start
09.738: mct_SendMrsCmd: Done
09.738: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
09.738: mct_SendMrsCmd: Start
09.738: mct_SendMrsCmd: Done
09.738: DIMM 1 RttNom: 3
09.738: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.738: mct_SendMrsCmd: Start
09.738: mct_SendMrsCmd: Done
09.738: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601578
09.738: mct_SendMrsCmd: Start
09.738: mct_SendMrsCmd: Done
09.738: mct_DramInit_Sw_D: Done
09.739: AgesaHwWlPhase1: training nibble 0
09.739: DIMM 0 RttNom: 3
09.739: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.739: DIMM 0 RttWr: 2
09.739: DIMM 0 RttWr: 2
09.739: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.739: DIMM 0 RttWr: 2
09.739: DIMM 0 RttNom: 3
09.739: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.739: DIMM 0 RttNom: 3
09.739: DIMM 0 RttWr: 2
09.739: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.739: DIMM 0 RttWr: 2
09.739: DIMM 1 RttNom: 3
09.739: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.739: DIMM 0 RttNom: 3
09.739: DIMM 1 RttWr: 2
09.739: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.739: DIMM 0 RttWr: 2
09.739: DIMM 1 RttNom: 3
09.739: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.739: DIMM 0 RttNom: 3
09.739: DIMM 1 RttWr: 2
09.739: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.739: DIMM 0 RttWr: 2
09.739: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.739: <09>Lane 00 scaled delay: 0047
09.739: <09>Lane 00 new seed: 0047
09.739: <09>Lane 01 scaled delay: 0047
09.739: <09>Lane 01 new seed: 0047
09.739: <09>Lane 02 scaled delay: 0047
09.739: <09>Lane 02 new seed: 0047
09.739: <09>Lane 03 scaled delay: 0047
09.739: <09>Lane 03 new seed: 0047
09.739: <09>Lane 04 scaled delay: 0047
09.739: <09>Lane 04 new seed: 0047
09.739: <09>Lane 05 scaled delay: 0047
09.739: <09>Lane 05 new seed: 0047
09.739: <09>Lane 06 scaled delay: 0047
09.739: <09>Lane 06 new seed: 0047
09.739: <09>Lane 07 scaled delay: 0047
09.739: <09>Lane 07 new seed: 0047
09.739: <09>Lane 08 scaled delay: 0047
09.739: <09>Lane 08 new seed: 0047
09.740: <09>Lane 00 nibble 0 raw readback: 0046
09.740: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0046
09.740: <09>Lane 00 nibble 0 adjusted value (post nibble): 0046
09.740: <09>Lane 01 nibble 0 raw readback: 003f
09.740: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003f
09.740: <09>Lane 01 nibble 0 adjusted value (post nibble): 003f
09.740: <09>Lane 02 nibble 0 raw readback: 003c
09.740: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003c
09.740: <09>Lane 02 nibble 0 adjusted value (post nibble): 003c
09.740: <09>Lane 03 nibble 0 raw readback: 003e
09.740: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003e
09.740: <09>Lane 03 nibble 0 adjusted value (post nibble): 003e
09.740: <09>Lane 04 nibble 0 raw readback: 003a
09.740: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
09.740: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
09.740: <09>Lane 05 nibble 0 raw readback: 003e
09.740: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003e
09.740: <09>Lane 05 nibble 0 adjusted value (post nibble): 003e
09.740: <09>Lane 06 nibble 0 raw readback: 003f
09.740: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003f
09.740: <09>Lane 06 nibble 0 adjusted value (post nibble): 003f
09.740: <09>Lane 07 nibble 0 raw readback: 0043
09.740: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0043
09.740: <09>Lane 07 nibble 0 adjusted value (post nibble): 0043
09.740: <09>Lane 08 nibble 0 raw readback: 0037
09.740: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0037
09.740: <09>Lane 08 nibble 0 adjusted value (post nibble): 0037
09.740: AgesaHwWlPhase1: training nibble 1
09.740: DIMM 0 RttNom: 3
09.740: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.740: DIMM 0 RttWr: 2
09.740: DIMM 0 RttWr: 2
09.740: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.740: DIMM 0 RttWr: 2
09.740: DIMM 0 RttNom: 3
09.740: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.740: DIMM 0 RttNom: 3
09.740: DIMM 0 RttWr: 2
09.740: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.740: DIMM 0 RttWr: 2
09.740: DIMM 1 RttNom: 3
09.740: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.740: DIMM 0 RttNom: 3
09.740: DIMM 1 RttWr: 2
09.740: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.740: DIMM 0 RttWr: 2
09.740: DIMM 1 RttNom: 3
09.740: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.740: DIMM 0 RttNom: 3
09.740: DIMM 1 RttWr: 2
09.740: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.740: DIMM 0 RttWr: 2
09.740: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.740: <09>Lane 00 new seed: 0047
09.740: <09>Lane 01 new seed: 0047
09.740: <09>Lane 02 new seed: 0047
09.740: <09>Lane 03 new seed: 0047
09.740: <09>Lane 04 new seed: 0047
09.740: <09>Lane 05 new seed: 0047
09.740: <09>Lane 06 new seed: 0047
09.740: <09>Lane 07 new seed: 0047
09.740: <09>Lane 08 new seed: 0047
09.741: <09>Lane 00 nibble 1 raw readback: 0047
09.741: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0047
09.741: <09>Lane 00 nibble 1 adjusted value (post nibble): 0047
09.741: <09>Lane 01 nibble 1 raw readback: 0042
09.741: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0042
09.741: <09>Lane 01 nibble 1 adjusted value (post nibble): 0044
09.741: <09>Lane 02 nibble 1 raw readback: 003f
09.741: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003f
09.741: <09>Lane 02 nibble 1 adjusted value (post nibble): 0043
09.741: <09>Lane 03 nibble 1 raw readback: 003c
09.741: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003c
09.741: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
09.741: <09>Lane 04 nibble 1 raw readback: 003a
09.741: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003a
09.741: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
09.741: <09>Lane 05 nibble 1 raw readback: 003d
09.741: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003d
09.741: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
09.741: <09>Lane 06 nibble 1 raw readback: 0041
09.741: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0041
09.741: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
09.741: <09>Lane 07 nibble 1 raw readback: 0045
09.741: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0045
09.741: <09>Lane 07 nibble 1 adjusted value (post nibble): 0046
09.741: <09>Lane 08 nibble 1 raw readback: 0038
09.741: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0038
09.741: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
09.741: <09>original critical gross delay: 0
09.741: <09>new critical gross delay: 0
09.741: DIMM 0 RttNom: 3
09.741: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.741: DIMM 0 RttNom: 3
09.741: DIMM 0 RttWr: 2
09.741: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.741: DIMM 0 RttWr: 2
09.741: DIMM 0 RttNom: 3
09.741: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.741: DIMM 0 RttNom: 3
09.741: DIMM 0 RttWr: 2
09.741: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.741: DIMM 0 RttWr: 2
09.741: DIMM 1 RttNom: 3
09.741: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.741: DIMM 0 RttNom: 3
09.741: DIMM 1 RttWr: 2
09.741: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.741: DIMM 0 RttWr: 2
09.741: DIMM 1 RttNom: 3
09.741: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.741: DIMM 0 RttNom: 3
09.741: DIMM 1 RttWr: 2
09.741: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.741: DIMM 0 RttWr: 2
09.741: AgesaHwWlPhase1: training nibble 0
09.741: DIMM 1 RttNom: 3
09.741: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.741: DIMM 1 RttWr: 2
09.741: DIMM 1 RttWr: 2
09.741: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.741: DIMM 1 RttWr: 2
09.741: DIMM 1 RttNom: 3
09.741: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.741: DIMM 1 RttNom: 3
09.742: DIMM 1 RttWr: 2
09.742: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.742: DIMM 1 RttWr: 2
09.742: DIMM 0 RttNom: 3
09.742: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.742: DIMM 1 RttNom: 3
09.742: DIMM 0 RttWr: 2
09.742: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.742: DIMM 1 RttWr: 2
09.742: DIMM 0 RttNom: 3
09.742: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.742: DIMM 1 RttNom: 3
09.742: DIMM 0 RttWr: 2
09.742: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.742: DIMM 1 RttWr: 2
09.742: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.742: <09>Lane 00 scaled delay: 0047
09.742: <09>Lane 00 new seed: 0047
09.742: <09>Lane 01 scaled delay: 0047
09.742: <09>Lane 01 new seed: 0047
09.742: <09>Lane 02 scaled delay: 0047
09.742: <09>Lane 02 new seed: 0047
09.742: <09>Lane 03 scaled delay: 0047
09.742: <09>Lane 03 new seed: 0047
09.742: <09>Lane 04 scaled delay: 0047
09.742: <09>Lane 04 new seed: 0047
09.742: <09>Lane 05 scaled delay: 0047
09.742: <09>Lane 05 new seed: 0047
09.742: <09>Lane 06 scaled delay: 0047
09.742: <09>Lane 06 new seed: 0047
09.742: <09>Lane 07 scaled delay: 0047
09.742: <09>Lane 07 new seed: 0047
09.742: <09>Lane 08 scaled delay: 0047
09.742: <09>Lane 08 new seed: 0047
09.742: <09>Lane 00 nibble 0 raw readback: 0044
09.742: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0044
09.742: <09>Lane 00 nibble 0 adjusted value (post nibble): 0044
09.742: <09>Lane 01 nibble 0 raw readback: 0040
09.742: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0040
09.742: <09>Lane 01 nibble 0 adjusted value (post nibble): 0040
09.742: <09>Lane 02 nibble 0 raw readback: 003c
09.742: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003c
09.742: <09>Lane 02 nibble 0 adjusted value (post nibble): 003c
09.742: <09>Lane 03 nibble 0 raw readback: 003c
09.742: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003c
09.742: <09>Lane 03 nibble 0 adjusted value (post nibble): 003c
09.742: <09>Lane 04 nibble 0 raw readback: 0039
09.742: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
09.742: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
09.742: <09>Lane 05 nibble 0 raw readback: 003c
09.742: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003c
09.742: <09>Lane 05 nibble 0 adjusted value (post nibble): 003c
09.742: <09>Lane 06 nibble 0 raw readback: 003e
09.742: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003e
09.742: <09>Lane 06 nibble 0 adjusted value (post nibble): 003e
09.742: <09>Lane 07 nibble 0 raw readback: 0042
09.742: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0042
09.742: <09>Lane 07 nibble 0 adjusted value (post nibble): 0042
09.742: <09>Lane 08 nibble 0 raw readback: 0036
09.742: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
09.742: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
09.742: AgesaHwWlPhase1: training nibble 1
09.742: DIMM 1 RttNom: 3
09.742: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.742: DIMM 1 RttWr: 2
09.742: DIMM 1 RttWr: 2
09.742: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.742: DIMM 1 RttWr: 2
09.742: DIMM 1 RttNom: 3
09.742: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.742: DIMM 1 RttNom: 3
09.742: DIMM 1 RttWr: 2
09.742: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.742: DIMM 1 RttWr: 2
09.743: DIMM 0 RttNom: 3
09.743: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.743: DIMM 1 RttNom: 3
09.743: DIMM 0 RttWr: 2
09.743: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.743: DIMM 1 RttWr: 2
09.743: DIMM 0 RttNom: 3
09.743: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.743: DIMM 1 RttNom: 3
09.743: DIMM 0 RttWr: 2
09.743: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.743: DIMM 1 RttWr: 2
09.743: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.743: <09>Lane 00 new seed: 0047
09.743: <09>Lane 01 new seed: 0047
09.743: <09>Lane 02 new seed: 0047
09.743: <09>Lane 03 new seed: 0047
09.743: <09>Lane 04 new seed: 0047
09.743: <09>Lane 05 new seed: 0047
09.743: <09>Lane 06 new seed: 0047
09.743: <09>Lane 07 new seed: 0047
09.743: <09>Lane 08 new seed: 0047
09.743: <09>Lane 00 nibble 1 raw readback: 0045
09.743: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0045
09.743: <09>Lane 00 nibble 1 adjusted value (post nibble): 0046
09.743: <09>Lane 01 nibble 1 raw readback: 0040
09.743: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0040
09.743: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
09.743: <09>Lane 02 nibble 1 raw readback: 003d
09.743: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003d
09.743: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
09.743: <09>Lane 03 nibble 1 raw readback: 003c
09.743: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003c
09.743: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
09.743: <09>Lane 04 nibble 1 raw readback: 0038
09.743: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
09.743: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
09.743: <09>Lane 05 nibble 1 raw readback: 003c
09.743: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
09.743: <09>Lane 05 nibble 1 adjusted value (post nibble): 0041
09.743: <09>Lane 06 nibble 1 raw readback: 003d
09.743: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003d
09.743: <09>Lane 06 nibble 1 adjusted value (post nibble): 0042
09.743: <09>Lane 07 nibble 1 raw readback: 0042
09.743: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
09.743: <09>Lane 07 nibble 1 adjusted value (post nibble): 0044
09.743: <09>Lane 08 nibble 1 raw readback: 0036
09.743: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0036
09.743: <09>Lane 08 nibble 1 adjusted value (post nibble): 003e
09.743: <09>original critical gross delay: 0
09.743: <09>new critical gross delay: 0
09.743: DIMM 1 RttNom: 3
09.743: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.743: DIMM 1 RttNom: 3
09.743: DIMM 1 RttWr: 2
09.743: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
09.743: DIMM 1 RttWr: 2
09.743: DIMM 1 RttNom: 3
09.743: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.743: DIMM 1 RttNom: 3
09.743: DIMM 1 RttWr: 2
09.743: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
09.744: DIMM 1 RttWr: 2
09.744: DIMM 0 RttNom: 3
09.744: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.744: DIMM 1 RttNom: 3
09.744: DIMM 0 RttWr: 2
09.744: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
09.744: DIMM 1 RttWr: 2
09.744: DIMM 0 RttNom: 3
09.744: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.744: DIMM 1 RttNom: 3
09.744: DIMM 0 RttWr: 2
09.744: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
09.744: DIMM 1 RttWr: 2
09.744: SPD2ndTiming: Start
09.744: SPD2ndTiming: Done
09.744: mct_BeforeDramInit_Prod_D: Start
09.744: mct_ProgramODT_D: Start
09.744: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
09.744: mct_ProgramODT_D: Done
09.744: mct_BeforeDramInit_Prod_D: Done
09.744: mct_DramInit_Sw_D: Start
09.744: DIMM 0 RttWr: 2
09.744: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.744: mct_SendMrsCmd: Start
09.744: mct_SendMrsCmd: Done
09.744: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
09.744: mct_SendMrsCmd: Start
09.744: mct_SendMrsCmd: Done
09.744: DIMM 0 RttNom: 3
09.744: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.744: mct_SendMrsCmd: Start
09.745: mct_SendMrsCmd: Done
09.745: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001578
09.744: mct_SendMrsCmd: Start
09.745: mct_SendMrsCmd: Done
09.745: DIMM 0 RttWr: 2
09.745: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.745: mct_SendMrsCmd: Start
09.745: mct_SendMrsCmd: Done
09.745: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
09.745: mct_SendMrsCmd: Start
09.745: mct_SendMrsCmd: Done
09.745: DIMM 0 RttNom: 3
09.745: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.745: mct_SendMrsCmd: Start
09.745: mct_SendMrsCmd: Done
09.745: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201578
09.745: mct_SendMrsCmd: Start
09.745: mct_SendMrsCmd: Done
09.745: DIMM 1 RttWr: 2
09.745: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.745: mct_SendMrsCmd: Start
09.745: mct_SendMrsCmd: Done
09.745: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
09.745: mct_SendMrsCmd: Start
09.745: mct_SendMrsCmd: Done
09.745: DIMM 1 RttNom: 3
09.745: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.745: mct_SendMrsCmd: Start
09.745: mct_SendMrsCmd: Done
09.745: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401578
09.745: mct_SendMrsCmd: Start
09.745: mct_SendMrsCmd: Done
09.745: DIMM 1 RttWr: 2
09.745: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.745: mct_SendMrsCmd: Start
09.745: mct_SendMrsCmd: Done
09.745: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
09.745: mct_SendMrsCmd: Start
09.745: mct_SendMrsCmd: Done
09.745: DIMM 1 RttNom: 3
09.745: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.745: mct_SendMrsCmd: Start
09.745: mct_SendMrsCmd: Done
09.745: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601578
09.745: mct_SendMrsCmd: Start
09.745: mct_SendMrsCmd: Done
09.745: mct_DramInit_Sw_D: Done
09.745: AgesaHwWlPhase1: training nibble 0
09.745: DIMM 0 RttNom: 3
09.745: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.745: DIMM 0 RttWr: 2
09.745: DIMM 0 RttWr: 2
09.745: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.745: DIMM 0 RttWr: 2
09.745: DIMM 0 RttNom: 3
09.745: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.745: DIMM 0 RttNom: 3
09.745: DIMM 0 RttWr: 2
09.745: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.745: DIMM 0 RttWr: 2
09.745: DIMM 1 RttNom: 3
09.745: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.745: DIMM 0 RttNom: 3
09.745: DIMM 1 RttWr: 2
09.745: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.745: DIMM 0 RttWr: 2
09.745: DIMM 1 RttNom: 3
09.745: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.745: DIMM 0 RttNom: 3
09.745: DIMM 1 RttWr: 2
09.745: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.745: DIMM 0 RttWr: 2
09.746: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.746: <09>Lane 00 scaled delay: 0047
09.746: <09>Lane 00 new seed: 0047
09.746: <09>Lane 01 scaled delay: 0047
09.746: <09>Lane 01 new seed: 0047
09.746: <09>Lane 02 scaled delay: 0047
09.746: <09>Lane 02 new seed: 0047
09.746: <09>Lane 03 scaled delay: 0047
09.746: <09>Lane 03 new seed: 0047
09.746: <09>Lane 04 scaled delay: 0047
09.746: <09>Lane 04 new seed: 0047
09.746: <09>Lane 05 scaled delay: 0047
09.746: <09>Lane 05 new seed: 0047
09.746: <09>Lane 06 scaled delay: 0047
09.746: <09>Lane 06 new seed: 0047
09.746: <09>Lane 07 scaled delay: 0047
09.746: <09>Lane 07 new seed: 0047
09.746: <09>Lane 08 scaled delay: 0047
09.746: <09>Lane 08 new seed: 0047
09.746: <09>Lane 00 nibble 0 raw readback: 0046
09.746: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0046
09.746: <09>Lane 00 nibble 0 adjusted value (post nibble): 0046
09.746: <09>Lane 01 nibble 0 raw readback: 0042
09.746: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0042
09.746: <09>Lane 01 nibble 0 adjusted value (post nibble): 0042
09.746: <09>Lane 02 nibble 0 raw readback: 003e
09.746: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003e
09.746: <09>Lane 02 nibble 0 adjusted value (post nibble): 003e
09.746: <09>Lane 03 nibble 0 raw readback: 003b
09.746: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
09.746: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
09.746: <09>Lane 04 nibble 0 raw readback: 003a
09.746: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
09.746: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
09.746: <09>Lane 05 nibble 0 raw readback: 003e
09.746: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003e
09.746: <09>Lane 05 nibble 0 adjusted value (post nibble): 003e
09.746: <09>Lane 06 nibble 0 raw readback: 0041
09.746: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0041
09.746: <09>Lane 06 nibble 0 adjusted value (post nibble): 0041
09.746: <09>Lane 07 nibble 0 raw readback: 0045
09.746: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0045
09.746: <09>Lane 07 nibble 0 adjusted value (post nibble): 0045
09.746: <09>Lane 08 nibble 0 raw readback: 0037
09.746: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0037
09.746: <09>Lane 08 nibble 0 adjusted value (post nibble): 0037
09.746: AgesaHwWlPhase1: training nibble 1
09.746: DIMM 0 RttNom: 3
09.746: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.746: DIMM 0 RttWr: 2
09.746: DIMM 0 RttWr: 2
09.746: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.746: DIMM 0 RttWr: 2
09.746: DIMM 0 RttNom: 3
09.746: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.746: DIMM 0 RttNom: 3
09.746: DIMM 0 RttWr: 2
09.746: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.746: DIMM 0 RttWr: 2
09.746: DIMM 1 RttNom: 3
09.746: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.746: DIMM 0 RttNom: 3
09.746: DIMM 1 RttWr: 2
09.746: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.747: DIMM 0 RttWr: 2
09.747: DIMM 1 RttNom: 3
09.747: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.747: DIMM 0 RttNom: 3
09.747: DIMM 1 RttWr: 2
09.747: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.747: DIMM 0 RttWr: 2
09.747: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.747: <09>Lane 00 new seed: 0047
09.747: <09>Lane 01 new seed: 0047
09.747: <09>Lane 02 new seed: 0047
09.747: <09>Lane 03 new seed: 0047
09.747: <09>Lane 04 new seed: 0047
09.747: <09>Lane 05 new seed: 0047
09.747: <09>Lane 06 new seed: 0047
09.747: <09>Lane 07 new seed: 0047
09.747: <09>Lane 08 new seed: 0047
09.747: <09>Lane 00 nibble 1 raw readback: 0047
09.747: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0047
09.747: <09>Lane 00 nibble 1 adjusted value (post nibble): 0047
09.747: <09>Lane 01 nibble 1 raw readback: 0044
09.747: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0044
09.747: <09>Lane 01 nibble 1 adjusted value (post nibble): 0045
09.747: <09>Lane 02 nibble 1 raw readback: 0040
09.747: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0040
09.747: <09>Lane 02 nibble 1 adjusted value (post nibble): 0043
09.747: <09>Lane 03 nibble 1 raw readback: 003c
09.747: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003c
09.747: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
09.747: <09>Lane 04 nibble 1 raw readback: 003a
09.747: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003a
09.747: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
09.747: <09>Lane 05 nibble 1 raw readback: 003d
09.747: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003d
09.747: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
09.747: <09>Lane 06 nibble 1 raw readback: 0041
09.747: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0041
09.747: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
09.747: <09>Lane 07 nibble 1 raw readback: 0046
09.747: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0046
09.747: <09>Lane 07 nibble 1 adjusted value (post nibble): 0046
09.747: <09>Lane 08 nibble 1 raw readback: 0038
09.747: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0038
09.747: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
09.747: <09>original critical gross delay: 0
09.747: <09>new critical gross delay: 0
09.747: DIMM 0 RttNom: 3
09.747: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.747: DIMM 0 RttNom: 3
09.747: DIMM 0 RttWr: 2
09.747: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.747: DIMM 0 RttWr: 2
09.747: DIMM 0 RttNom: 3
09.747: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.747: DIMM 0 RttNom: 3
09.747: DIMM 0 RttWr: 2
09.747: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.747: DIMM 0 RttWr: 2
09.748: DIMM 1 RttNom: 3
09.747: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.748: DIMM 0 RttNom: 3
09.748: DIMM 1 RttWr: 2
09.748: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.748: DIMM 0 RttWr: 2
09.748: DIMM 1 RttNom: 3
09.748: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.748: DIMM 0 RttNom: 3
09.748: DIMM 1 RttWr: 2
09.748: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.748: DIMM 0 RttWr: 2
09.748: AgesaHwWlPhase1: training nibble 0
09.748: DIMM 1 RttNom: 3
09.748: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.748: DIMM 1 RttWr: 2
09.748: DIMM 1 RttWr: 2
09.748: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.748: DIMM 1 RttWr: 2
09.748: DIMM 1 RttNom: 3
09.748: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.748: DIMM 1 RttNom: 3
09.748: DIMM 1 RttWr: 2
09.748: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.748: DIMM 1 RttWr: 2
09.748: DIMM 0 RttNom: 3
09.748: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.748: DIMM 1 RttNom: 3
09.748: DIMM 0 RttWr: 2
09.748: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.748: DIMM 1 RttWr: 2
09.748: DIMM 0 RttNom: 3
09.748: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.748: DIMM 1 RttNom: 3
09.748: DIMM 0 RttWr: 2
09.748: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.748: DIMM 1 RttWr: 2
09.748: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.748: <09>Lane 00 scaled delay: 0047
09.748: <09>Lane 00 new seed: 0047
09.748: <09>Lane 01 scaled delay: 0047
09.748: <09>Lane 01 new seed: 0047
09.748: <09>Lane 02 scaled delay: 0047
09.748: <09>Lane 02 new seed: 0047
09.748: <09>Lane 03 scaled delay: 0047
09.748: <09>Lane 03 new seed: 0047
09.748: <09>Lane 04 scaled delay: 0047
09.748: <09>Lane 04 new seed: 0047
09.748: <09>Lane 05 scaled delay: 0047
09.748: <09>Lane 05 new seed: 0047
09.748: <09>Lane 06 scaled delay: 0047
09.748: <09>Lane 06 new seed: 0047
09.748: <09>Lane 07 scaled delay: 0047
09.748: <09>Lane 07 new seed: 0047
09.748: <09>Lane 08 scaled delay: 0047
09.748: <09>Lane 08 new seed: 0047
09.748: <09>Lane 00 nibble 0 raw readback: 0046
09.748: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0046
09.748: <09>Lane 00 nibble 0 adjusted value (post nibble): 0046
09.748: <09>Lane 01 nibble 0 raw readback: 0042
09.748: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0042
09.748: <09>Lane 01 nibble 0 adjusted value (post nibble): 0042
09.748: <09>Lane 02 nibble 0 raw readback: 003d
09.748: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003d
09.748: <09>Lane 02 nibble 0 adjusted value (post nibble): 003d
09.748: <09>Lane 03 nibble 0 raw readback: 003b
09.748: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
09.748: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
09.748: <09>Lane 04 nibble 0 raw readback: 0039
09.749: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
09.748: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
09.749: <09>Lane 05 nibble 0 raw readback: 003e
09.749: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003e
09.749: <09>Lane 05 nibble 0 adjusted value (post nibble): 003e
09.749: <09>Lane 06 nibble 0 raw readback: 0041
09.749: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0041
09.749: <09>Lane 06 nibble 0 adjusted value (post nibble): 0041
09.749: <09>Lane 07 nibble 0 raw readback: 0044
09.749: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0044
09.749: <09>Lane 07 nibble 0 adjusted value (post nibble): 0044
09.749: <09>Lane 08 nibble 0 raw readback: 0038
09.749: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0038
09.749: <09>Lane 08 nibble 0 adjusted value (post nibble): 0038
09.749: AgesaHwWlPhase1: training nibble 1
09.749: DIMM 1 RttNom: 3
09.749: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.749: DIMM 1 RttWr: 2
09.749: DIMM 1 RttWr: 2
09.749: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.749: DIMM 1 RttWr: 2
09.749: DIMM 1 RttNom: 3
09.749: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.749: DIMM 1 RttNom: 3
09.749: DIMM 1 RttWr: 2
09.749: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.749: DIMM 1 RttWr: 2
09.749: DIMM 0 RttNom: 3
09.749: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.749: DIMM 1 RttNom: 3
09.749: DIMM 0 RttWr: 2
09.749: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.749: DIMM 1 RttWr: 2
09.749: DIMM 0 RttNom: 3
09.749: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.749: DIMM 1 RttNom: 3
09.749: DIMM 0 RttWr: 2
09.749: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.749: DIMM 1 RttWr: 2
09.749: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.749: <09>Lane 00 new seed: 0047
09.749: <09>Lane 01 new seed: 0047
09.749: <09>Lane 02 new seed: 0047
09.749: <09>Lane 03 new seed: 0047
09.749: <09>Lane 04 new seed: 0047
09.749: <09>Lane 05 new seed: 0047
09.749: <09>Lane 06 new seed: 0047
09.749: <09>Lane 07 new seed: 0047
09.749: <09>Lane 08 new seed: 0047
09.749: <09>Lane 00 nibble 1 raw readback: 0047
09.749: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0047
09.749: <09>Lane 00 nibble 1 adjusted value (post nibble): 0047
09.749: <09>Lane 01 nibble 1 raw readback: 0044
09.749: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0044
09.749: <09>Lane 01 nibble 1 adjusted value (post nibble): 0045
09.749: <09>Lane 02 nibble 1 raw readback: 003e
09.749: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003e
09.749: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
09.749: <09>Lane 03 nibble 1 raw readback: 003c
09.749: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003c
09.749: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
09.749: <09>Lane 04 nibble 1 raw readback: 003a
09.749: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003a
09.749: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
09.749: <09>Lane 05 nibble 1 raw readback: 003d
09.749: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003d
09.749: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
09.749: <09>Lane 06 nibble 1 raw readback: 0042
09.749: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0042
09.749: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
09.749: <09>Lane 07 nibble 1 raw readback: 0046
09.749: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0046
09.749: <09>Lane 07 nibble 1 adjusted value (post nibble): 0046
09.749: <09>Lane 08 nibble 1 raw readback: 0037
09.749: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
09.749: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
09.750: <09>original critical gross delay: 0
09.750: <09>new critical gross delay: 0
09.750: DIMM 1 RttNom: 3
09.750: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.750: DIMM 1 RttNom: 3
09.750: DIMM 1 RttWr: 2
09.750: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
09.750: DIMM 1 RttWr: 2
09.750: DIMM 1 RttNom: 3
09.750: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.750: DIMM 1 RttNom: 3
09.750: DIMM 1 RttWr: 2
09.750: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
09.750: DIMM 1 RttWr: 2
09.750: DIMM 0 RttNom: 3
09.750: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.750: DIMM 1 RttNom: 3
09.750: DIMM 0 RttWr: 2
09.750: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
09.750: DIMM 1 RttWr: 2
09.750: DIMM 0 RttNom: 3
09.750: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.750: DIMM 1 RttNom: 3
09.750: DIMM 0 RttWr: 2
09.750: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
09.750: DIMM 1 RttWr: 2
09.750: SetTargetFreq: Start
09.750: SetTargetFreq: Node 3: New frequency code: 000a
09.750: ChangeMemClk: Start
09.750: set_2t_configuration: Start
09.750: set_2t_configuration: Done
09.750: mct_BeforePlatformSpec: Start
09.750: mct_BeforePlatformSpec: Done
09.750: mct_PlatformSpec: Start
09.751: Programmed DCT 0 timing/termination pattern 003a3c3a 30222222
09.751: mct_PlatformSpec: Done
09.751: set_2t_configuration: Start
09.751: set_2t_configuration: Done
09.751: mct_BeforePlatformSpec: Start
09.751: mct_BeforePlatformSpec: Done
09.751: mct_PlatformSpec: Start
09.751: Programmed DCT 1 timing/termination pattern 003a3c3a 30222222
09.751: mct_PlatformSpec: Done
09.751: ChangeMemClk: Done
09.751: phyAssistedMemFnceTraining: Start
09.751: phyAssistedMemFnceTraining: training node 3 DCT 0
09.751: phyAssistedMemFnceTraining: done training node 3 DCT 0
09.751: phyAssistedMemFnceTraining: training node 3 DCT 1
09.751: phyAssistedMemFnceTraining: done training node 3 DCT 1
09.751: phyAssistedMemFnceTraining: Done
09.751: InitPhyCompensation: DCT 0: Start
09.751: Waiting for predriver calibration to be applied...done!
09.751: InitPhyCompensation: DCT 0: Done
09.751: phyAssistedMemFnceTraining: Start
09.751: phyAssistedMemFnceTraining: training node 3 DCT 0
09.751: phyAssistedMemFnceTraining: done training node 3 DCT 0
09.751: phyAssistedMemFnceTraining: training node 3 DCT 1
09.751: phyAssistedMemFnceTraining: done training node 3 DCT 1
09.751: phyAssistedMemFnceTraining: Done
09.751: InitPhyCompensation: DCT 1: Start
09.751: Waiting for predriver calibration to be applied...done!
09.751: InitPhyCompensation: DCT 1: Done
09.752: Preparing to send DCT 0 DIMM 0 RC10: 01 (F2xA8: 02000300)
09.752: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.752: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
09.752: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.752: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
09.752: Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 02000c00)
09.752: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.752: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
09.752: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.752: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
09.752: Preparing to send DCT 1 DIMM 0 RC10: 01 (F2xA8: 02000300)
09.752: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.752: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
09.752: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.752: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
09.752: Preparing to send DCT 1 DIMM 1 RC10: 01 (F2xA8: 02000c00)
09.752: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.752: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
09.752: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.752: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
09.752: SetTargetFreq: Done
09.752: SPD2ndTiming: Start
09.752: SPD2ndTiming: Done
09.752: mct_BeforeDramInit_Prod_D: Start
09.752: mct_ProgramODT_D: Start
09.752: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
09.752: mct_ProgramODT_D: Done
09.752: mct_BeforeDramInit_Prod_D: Done
09.753: mct_DramInit_Sw_D: Start
09.753: DIMM 0 RttWr: 1
09.753: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.753: mct_SendMrsCmd: Start
09.753: mct_SendMrsCmd: Done
09.753: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
09.753: mct_SendMrsCmd: Start
09.753: mct_SendMrsCmd: Done
09.753: DIMM 0 RttNom: 3
09.753: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.753: mct_SendMrsCmd: Start
09.753: mct_SendMrsCmd: Done
09.753: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001978
09.753: mct_SendMrsCmd: Start
09.753: mct_SendMrsCmd: Done
09.753: DIMM 0 RttWr: 1
09.753: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.753: mct_SendMrsCmd: Start
09.753: mct_SendMrsCmd: Done
09.753: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
09.753: mct_SendMrsCmd: Start
09.753: mct_SendMrsCmd: Done
09.753: DIMM 0 RttNom: 3
09.753: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.753: mct_SendMrsCmd: Start
09.753: mct_SendMrsCmd: Done
09.753: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201978
09.753: mct_SendMrsCmd: Start
09.753: mct_SendMrsCmd: Done
09.753: DIMM 1 RttWr: 1
09.753: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.753: mct_SendMrsCmd: Start
09.753: mct_SendMrsCmd: Done
09.753: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
09.753: mct_SendMrsCmd: Start
09.753: mct_SendMrsCmd: Done
09.753: DIMM 1 RttNom: 3
09.753: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.753: mct_SendMrsCmd: Start
09.753: mct_SendMrsCmd: Done
09.753: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401978
09.753: mct_SendMrsCmd: Start
09.753: mct_SendMrsCmd: Done
09.753: DIMM 1 RttWr: 1
09.753: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.753: mct_SendMrsCmd: Start
09.753: mct_SendMrsCmd: Done
09.753: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
09.753: mct_SendMrsCmd: Start
09.753: mct_SendMrsCmd: Done
09.753: DIMM 1 RttNom: 3
09.753: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.753: mct_SendMrsCmd: Start
09.753: mct_SendMrsCmd: Done
09.753: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601978
09.753: mct_SendMrsCmd: Start
09.753: mct_SendMrsCmd: Done
09.753: mct_DramInit_Sw_D: Done
09.754: AgesaHwWlPhase1: training nibble 0
09.754: DIMM 0 RttNom: 3
09.754: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.754: DIMM 0 RttWr: 1
09.754: DIMM 0 RttWr: 1
09.754: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.754: DIMM 0 RttWr: 1
09.754: DIMM 0 RttNom: 3
09.754: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.754: DIMM 0 RttNom: 3
09.754: DIMM 0 RttWr: 1
09.754: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.754: DIMM 0 RttWr: 1
09.754: DIMM 1 RttNom: 3
09.754: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.754: DIMM 0 RttNom: 3
09.754: DIMM 1 RttWr: 1
09.754: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.754: DIMM 0 RttWr: 1
09.754: DIMM 1 RttNom: 3
09.754: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.754: DIMM 0 RttNom: 3
09.754: DIMM 1 RttWr: 1
09.754: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.754: DIMM 0 RttWr: 1
09.754: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.754: <09>Lane 00 scaled delay: 0053
09.754: <09>Lane 00 new seed: 0053
09.754: <09>Lane 01 scaled delay: 004f
09.754: <09>Lane 01 new seed: 004f
09.754: <09>Lane 02 scaled delay: 004e
09.754: <09>Lane 02 new seed: 004e
09.754: <09>Lane 03 scaled delay: 004b
09.754: <09>Lane 03 new seed: 004b
09.754: <09>Lane 04 scaled delay: 004a
09.754: <09>Lane 04 new seed: 004a
09.754: <09>Lane 05 scaled delay: 004d
09.754: <09>Lane 05 new seed: 004d
09.754: <09>Lane 06 scaled delay: 004f
09.754: <09>Lane 06 new seed: 004f
09.754: <09>Lane 07 scaled delay: 0052
09.754: <09>Lane 07 new seed: 0052
09.754: <09>Lane 08 scaled delay: 0049
09.754: <09>Lane 08 new seed: 0049
09.754: <09>Lane 00 nibble 0 raw readback: 0052
09.755: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0052
09.755: <09>Lane 00 nibble 0 adjusted value (post nibble): 0052
09.755: <09>Lane 01 nibble 0 raw readback: 0049
09.755: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0049
09.755: <09>Lane 01 nibble 0 adjusted value (post nibble): 0049
09.755: <09>Lane 02 nibble 0 raw readback: 0047
09.755: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0047
09.755: <09>Lane 02 nibble 0 adjusted value (post nibble): 0047
09.755: <09>Lane 03 nibble 0 raw readback: 0047
09.755: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0047
09.755: <09>Lane 03 nibble 0 adjusted value (post nibble): 0047
09.755: <09>Lane 04 nibble 0 raw readback: 0044
09.755: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0044
09.755: <09>Lane 04 nibble 0 adjusted value (post nibble): 0044
09.755: <09>Lane 05 nibble 0 raw readback: 0049
09.755: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0049
09.755: <09>Lane 05 nibble 0 adjusted value (post nibble): 0049
09.755: <09>Lane 06 nibble 0 raw readback: 004b
09.755: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004b
09.755: <09>Lane 06 nibble 0 adjusted value (post nibble): 004b
09.755: <09>Lane 07 nibble 0 raw readback: 004e
09.755: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004e
09.755: <09>Lane 07 nibble 0 adjusted value (post nibble): 004e
09.755: <09>Lane 08 nibble 0 raw readback: 003e
09.755: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003e
09.755: <09>Lane 08 nibble 0 adjusted value (post nibble): 003e
09.755: AgesaHwWlPhase1: training nibble 1
09.755: DIMM 0 RttNom: 3
09.755: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.755: DIMM 0 RttWr: 1
09.755: DIMM 0 RttWr: 1
09.755: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.755: DIMM 0 RttWr: 1
09.755: DIMM 0 RttNom: 3
09.755: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.755: DIMM 0 RttNom: 3
09.755: DIMM 0 RttWr: 1
09.755: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.755: DIMM 0 RttWr: 1
09.755: DIMM 1 RttNom: 3
09.755: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.755: DIMM 0 RttNom: 3
09.755: DIMM 1 RttWr: 1
09.755: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.755: DIMM 0 RttWr: 1
09.755: DIMM 1 RttNom: 3
09.755: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.755: DIMM 0 RttNom: 3
09.755: DIMM 1 RttWr: 1
09.755: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.755: DIMM 0 RttWr: 1
09.755: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.755: <09>Lane 00 new seed: 0053
09.755: <09>Lane 01 new seed: 004f
09.755: <09>Lane 02 new seed: 004e
09.755: <09>Lane 03 new seed: 004b
09.755: <09>Lane 04 new seed: 004a
09.755: <09>Lane 05 new seed: 004d
09.755: <09>Lane 06 new seed: 004f
09.755: <09>Lane 07 new seed: 0052
09.755: <09>Lane 08 new seed: 0049
09.755: <09>Lane 00 nibble 1 raw readback: 0054
09.755: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0054
09.755: <09>Lane 00 nibble 1 adjusted value (post nibble): 0053
09.755: <09>Lane 01 nibble 1 raw readback: 004d
09.755: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004d
09.755: <09>Lane 01 nibble 1 adjusted value (post nibble): 004e
09.755: <09>Lane 02 nibble 1 raw readback: 0049
09.755: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0049
09.755: <09>Lane 02 nibble 1 adjusted value (post nibble): 004b
09.755: <09>Lane 03 nibble 1 raw readback: 0046
09.755: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0046
09.755: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
09.756: <09>Lane 04 nibble 1 raw readback: 0043
09.756: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0043
09.756: <09>Lane 04 nibble 1 adjusted value (post nibble): 0046
09.756: <09>Lane 05 nibble 1 raw readback: 0048
09.756: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0048
09.756: <09>Lane 05 nibble 1 adjusted value (post nibble): 004a
09.756: <09>Lane 06 nibble 1 raw readback: 004d
09.756: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004d
09.756: <09>Lane 06 nibble 1 adjusted value (post nibble): 004e
09.756: <09>Lane 07 nibble 1 raw readback: 0050
09.756: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0050
09.756: <09>Lane 07 nibble 1 adjusted value (post nibble): 0051
09.756: <09>Lane 08 nibble 1 raw readback: 0040
09.756: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0040
09.756: <09>Lane 08 nibble 1 adjusted value (post nibble): 0044
09.756: <09>original critical gross delay: 0
09.756: <09>new critical gross delay: 0
09.756: DIMM 0 RttNom: 3
09.756: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.756: DIMM 0 RttNom: 3
09.756: DIMM 0 RttWr: 1
09.756: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.756: DIMM 0 RttWr: 1
09.756: DIMM 0 RttNom: 3
09.756: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.756: DIMM 0 RttNom: 3
09.756: DIMM 0 RttWr: 1
09.756: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.756: DIMM 0 RttWr: 1
09.756: DIMM 1 RttNom: 3
09.756: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.756: DIMM 0 RttNom: 3
09.756: DIMM 1 RttWr: 1
09.756: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.756: DIMM 0 RttWr: 1
09.756: DIMM 1 RttNom: 3
09.756: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.756: DIMM 0 RttNom: 3
09.756: DIMM 1 RttWr: 1
09.756: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.756: DIMM 0 RttWr: 1
09.756: AgesaHwWlPhase1: training nibble 0
09.756: DIMM 1 RttNom: 3
09.756: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.756: DIMM 1 RttWr: 1
09.756: DIMM 1 RttWr: 1
09.756: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.756: DIMM 1 RttWr: 1
09.756: DIMM 1 RttNom: 3
09.756: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.756: DIMM 1 RttNom: 3
09.756: DIMM 1 RttWr: 1
09.756: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.756: DIMM 1 RttWr: 1
09.756: DIMM 0 RttNom: 3
09.756: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.756: DIMM 1 RttNom: 3
09.756: DIMM 0 RttWr: 1
09.756: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.756: DIMM 1 RttWr: 1
09.756: DIMM 0 RttNom: 3
09.757: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.757: DIMM 1 RttNom: 3
09.757: DIMM 0 RttWr: 1
09.757: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.757: DIMM 1 RttWr: 1
09.757: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.757: <09>Lane 00 scaled delay: 0052
09.757: <09>Lane 00 new seed: 0052
09.757: <09>Lane 01 scaled delay: 004e
09.757: <09>Lane 01 new seed: 004e
09.757: <09>Lane 02 scaled delay: 004d
09.757: <09>Lane 02 new seed: 004d
09.757: <09>Lane 03 scaled delay: 004b
09.757: <09>Lane 03 new seed: 004b
09.757: <09>Lane 04 scaled delay: 0049
09.757: <09>Lane 04 new seed: 0049
09.757: <09>Lane 05 scaled delay: 004b
09.757: <09>Lane 05 new seed: 004b
09.757: <09>Lane 06 scaled delay: 004d
09.757: <09>Lane 06 new seed: 004d
09.757: <09>Lane 07 scaled delay: 004f
09.757: <09>Lane 07 new seed: 004f
09.757: <09>Lane 08 scaled delay: 0047
09.757: <09>Lane 08 new seed: 0047
09.757: <09>Lane 00 nibble 0 raw readback: 004f
09.757: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004f
09.757: <09>Lane 00 nibble 0 adjusted value (post nibble): 004f
09.757: <09>Lane 01 nibble 0 raw readback: 004a
09.757: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004a
09.757: <09>Lane 01 nibble 0 adjusted value (post nibble): 004a
09.757: <09>Lane 02 nibble 0 raw readback: 0046
09.757: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0046
09.757: <09>Lane 02 nibble 0 adjusted value (post nibble): 0046
09.757: <09>Lane 03 nibble 0 raw readback: 0044
09.757: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
09.757: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
09.757: <09>Lane 04 nibble 0 raw readback: 0041
09.757: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0041
09.757: <09>Lane 04 nibble 0 adjusted value (post nibble): 0041
09.757: <09>Lane 05 nibble 0 raw readback: 0045
09.757: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0045
09.757: <09>Lane 05 nibble 0 adjusted value (post nibble): 0045
09.757: <09>Lane 06 nibble 0 raw readback: 0047
09.757: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0047
09.757: <09>Lane 06 nibble 0 adjusted value (post nibble): 0047
09.757: <09>Lane 07 nibble 0 raw readback: 004d
09.757: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004d
09.757: <09>Lane 07 nibble 0 adjusted value (post nibble): 004d
09.757: <09>Lane 08 nibble 0 raw readback: 003d
09.757: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003d
09.757: <09>Lane 08 nibble 0 adjusted value (post nibble): 003d
09.757: AgesaHwWlPhase1: training nibble 1
09.757: DIMM 1 RttNom: 3
09.757: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.757: DIMM 1 RttWr: 1
09.757: DIMM 1 RttWr: 1
09.757: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.757: DIMM 1 RttWr: 1
09.757: DIMM 1 RttNom: 3
09.757: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.757: DIMM 1 RttNom: 3
09.757: DIMM 1 RttWr: 1
09.757: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.757: DIMM 1 RttWr: 1
09.757: DIMM 0 RttNom: 3
09.757: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.757: DIMM 1 RttNom: 3
09.757: DIMM 0 RttWr: 1
09.757: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.757: DIMM 1 RttWr: 1
09.757: DIMM 0 RttNom: 3
09.758: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.758: DIMM 1 RttNom: 3
09.758: DIMM 0 RttWr: 1
09.758: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.758: DIMM 1 RttWr: 1
09.758: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.758: <09>Lane 00 new seed: 0052
09.758: <09>Lane 01 new seed: 004e
09.758: <09>Lane 02 new seed: 004d
09.758: <09>Lane 03 new seed: 004b
09.758: <09>Lane 04 new seed: 0049
09.758: <09>Lane 05 new seed: 004b
09.758: <09>Lane 06 new seed: 004d
09.758: <09>Lane 07 new seed: 004f
09.758: <09>Lane 08 new seed: 0047
09.758: <09>Lane 00 nibble 1 raw readback: 0050
09.758: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0050
09.758: <09>Lane 00 nibble 1 adjusted value (post nibble): 0051
09.758: <09>Lane 01 nibble 1 raw readback: 004a
09.758: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004a
09.758: <09>Lane 01 nibble 1 adjusted value (post nibble): 004c
09.758: <09>Lane 02 nibble 1 raw readback: 0046
09.758: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0046
09.758: <09>Lane 02 nibble 1 adjusted value (post nibble): 0049
09.758: <09>Lane 03 nibble 1 raw readback: 0045
09.758: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
09.758: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
09.758: <09>Lane 04 nibble 1 raw readback: 0040
09.758: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0040
09.758: <09>Lane 04 nibble 1 adjusted value (post nibble): 0044
09.758: <09>Lane 05 nibble 1 raw readback: 0045
09.758: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0045
09.758: <09>Lane 05 nibble 1 adjusted value (post nibble): 0048
09.758: <09>Lane 06 nibble 1 raw readback: 0046
09.758: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0046
09.758: <09>Lane 06 nibble 1 adjusted value (post nibble): 0049
09.758: <09>Lane 07 nibble 1 raw readback: 004d
09.758: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004d
09.758: <09>Lane 07 nibble 1 adjusted value (post nibble): 004e
09.758: <09>Lane 08 nibble 1 raw readback: 003d
09.758: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003d
09.758: <09>Lane 08 nibble 1 adjusted value (post nibble): 0042
09.758: <09>original critical gross delay: 0
09.758: <09>new critical gross delay: 0
09.758: DIMM 1 RttNom: 3
09.758: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
09.758: DIMM 1 RttNom: 3
09.758: DIMM 1 RttWr: 1
09.758: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
09.758: DIMM 1 RttWr: 1
09.758: DIMM 1 RttNom: 3
09.758: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
09.758: DIMM 1 RttNom: 3
09.758: DIMM 1 RttWr: 1
09.758: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
09.758: DIMM 1 RttWr: 1
09.758: DIMM 0 RttNom: 3
09.758: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
09.758: DIMM 1 RttNom: 3
09.758: DIMM 0 RttWr: 1
09.758: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
09.758: DIMM 1 RttWr: 1
09.758: DIMM 0 RttNom: 3
09.758: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
09.758: DIMM 1 RttNom: 3
09.758: DIMM 0 RttWr: 1
09.758: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
09.759: DIMM 1 RttWr: 1
09.759: SPD2ndTiming: Start
09.759: SPD2ndTiming: Done
09.759: mct_BeforeDramInit_Prod_D: Start
09.759: mct_ProgramODT_D: Start
09.759: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
09.759: mct_ProgramODT_D: Done
09.759: mct_BeforeDramInit_Prod_D: Done
09.759: mct_DramInit_Sw_D: Start
09.759: DIMM 0 RttWr: 1
09.759: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.759: mct_SendMrsCmd: Start
09.759: mct_SendMrsCmd: Done
09.759: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
09.759: mct_SendMrsCmd: Start
09.759: mct_SendMrsCmd: Done
09.759: DIMM 0 RttNom: 3
09.759: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.759: mct_SendMrsCmd: Start
09.759: mct_SendMrsCmd: Done
09.759: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001978
09.759: mct_SendMrsCmd: Start
09.759: mct_SendMrsCmd: Done
09.759: DIMM 0 RttWr: 1
09.759: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.759: mct_SendMrsCmd: Start
09.759: mct_SendMrsCmd: Done
09.759: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
09.759: mct_SendMrsCmd: Start
09.759: mct_SendMrsCmd: Done
09.759: DIMM 0 RttNom: 3
09.759: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.759: mct_SendMrsCmd: Start
09.759: mct_SendMrsCmd: Done
09.759: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201978
09.759: mct_SendMrsCmd: Start
09.759: mct_SendMrsCmd: Done
09.759: DIMM 1 RttWr: 1
09.759: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.759: mct_SendMrsCmd: Start
09.760: mct_SendMrsCmd: Done
09.760: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
09.760: mct_SendMrsCmd: Start
09.760: mct_SendMrsCmd: Done
09.760: DIMM 1 RttNom: 3
09.760: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.760: mct_SendMrsCmd: Start
09.760: mct_SendMrsCmd: Done
09.760: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401978
09.760: mct_SendMrsCmd: Start
09.760: mct_SendMrsCmd: Done
09.760: DIMM 1 RttWr: 1
09.760: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.760: mct_SendMrsCmd: Start
09.760: mct_SendMrsCmd: Done
09.760: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
09.760: mct_SendMrsCmd: Start
09.760: mct_SendMrsCmd: Done
09.760: DIMM 1 RttNom: 3
09.760: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.760: mct_SendMrsCmd: Start
09.760: mct_SendMrsCmd: Done
09.760: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601978
09.760: mct_SendMrsCmd: Start
09.760: mct_SendMrsCmd: Done
09.760: mct_DramInit_Sw_D: Done
09.760: AgesaHwWlPhase1: training nibble 0
09.760: DIMM 0 RttNom: 3
09.760: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.760: DIMM 0 RttWr: 1
09.760: DIMM 0 RttWr: 1
09.760: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.760: DIMM 0 RttWr: 1
09.760: DIMM 0 RttNom: 3
09.760: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.760: DIMM 0 RttNom: 3
09.760: DIMM 0 RttWr: 1
09.760: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.760: DIMM 0 RttWr: 1
09.760: DIMM 1 RttNom: 3
09.760: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.760: DIMM 0 RttNom: 3
09.760: DIMM 1 RttWr: 1
09.760: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.760: DIMM 0 RttWr: 1
09.760: DIMM 1 RttNom: 3
09.760: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.760: DIMM 0 RttNom: 3
09.760: DIMM 1 RttWr: 1
09.760: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.760: DIMM 0 RttWr: 1
09.760: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.760: <09>Lane 00 scaled delay: 0053
09.760: <09>Lane 00 new seed: 0053
09.760: <09>Lane 01 scaled delay: 0051
09.760: <09>Lane 01 new seed: 0051
09.760: <09>Lane 02 scaled delay: 004e
09.760: <09>Lane 02 new seed: 004e
09.760: <09>Lane 03 scaled delay: 004b
09.760: <09>Lane 03 new seed: 004b
09.761: <09>Lane 04 scaled delay: 004a
09.760: <09>Lane 04 new seed: 004a
09.761: <09>Lane 05 scaled delay: 004d
09.761: <09>Lane 05 new seed: 004d
09.761: <09>Lane 06 scaled delay: 004f
09.761: <09>Lane 06 new seed: 004f
09.761: <09>Lane 07 scaled delay: 0052
09.761: <09>Lane 07 new seed: 0052
09.761: <09>Lane 08 scaled delay: 0049
09.761: <09>Lane 08 new seed: 0049
09.761: <09>Lane 00 nibble 0 raw readback: 0054
09.761: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0054
09.761: <09>Lane 00 nibble 0 adjusted value (post nibble): 0054
09.761: <09>Lane 01 nibble 0 raw readback: 004e
09.761: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004e
09.761: <09>Lane 01 nibble 0 adjusted value (post nibble): 004e
09.761: <09>Lane 02 nibble 0 raw readback: 004a
09.761: <09>Lane 02 nibble 0 adjusted value (pre nibble): 004a
09.761: <09>Lane 02 nibble 0 adjusted value (post nibble): 004a
09.761: <09>Lane 03 nibble 0 raw readback: 0045
09.761: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0045
09.761: <09>Lane 03 nibble 0 adjusted value (post nibble): 0045
09.761: <09>Lane 04 nibble 0 raw readback: 0044
09.761: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0044
09.761: <09>Lane 04 nibble 0 adjusted value (post nibble): 0044
09.761: <09>Lane 05 nibble 0 raw readback: 004a
09.761: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004a
09.761: <09>Lane 05 nibble 0 adjusted value (post nibble): 004a
09.761: <09>Lane 06 nibble 0 raw readback: 004e
09.761: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004e
09.761: <09>Lane 06 nibble 0 adjusted value (post nibble): 004e
09.761: <09>Lane 07 nibble 0 raw readback: 0053
09.761: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0053
09.761: <09>Lane 07 nibble 0 adjusted value (post nibble): 0053
09.761: <09>Lane 08 nibble 0 raw readback: 0040
09.761: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0040
09.761: <09>Lane 08 nibble 0 adjusted value (post nibble): 0040
09.761: AgesaHwWlPhase1: training nibble 1
09.761: DIMM 0 RttNom: 3
09.761: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.761: DIMM 0 RttWr: 1
09.761: DIMM 0 RttWr: 1
09.761: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.761: DIMM 0 RttWr: 1
09.761: DIMM 0 RttNom: 3
09.761: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.761: DIMM 0 RttNom: 3
09.761: DIMM 0 RttWr: 1
09.761: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.761: DIMM 0 RttWr: 1
09.761: DIMM 1 RttNom: 3
09.761: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.761: DIMM 0 RttNom: 3
09.761: DIMM 1 RttWr: 1
09.761: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.761: DIMM 0 RttWr: 1
09.761: DIMM 1 RttNom: 3
09.761: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.761: DIMM 0 RttNom: 3
09.761: DIMM 1 RttWr: 1
09.761: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.761: DIMM 0 RttWr: 1
09.761: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.761: <09>Lane 00 new seed: 0053
09.761: <09>Lane 01 new seed: 0051
09.762: <09>Lane 02 new seed: 004e
09.762: <09>Lane 03 new seed: 004b
09.762: <09>Lane 04 new seed: 004a
09.762: <09>Lane 05 new seed: 004d
09.762: <09>Lane 06 new seed: 004f
09.762: <09>Lane 07 new seed: 0052
09.762: <09>Lane 08 new seed: 0049
09.762: <09>Lane 00 nibble 1 raw readback: 0055
09.762: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0055
09.762: <09>Lane 00 nibble 1 adjusted value (post nibble): 0054
09.762: <09>Lane 01 nibble 1 raw readback: 0050
09.762: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0050
09.762: <09>Lane 01 nibble 1 adjusted value (post nibble): 0050
09.762: <09>Lane 02 nibble 1 raw readback: 004c
09.762: <09>Lane 02 nibble 1 adjusted value (pre nibble): 004c
09.762: <09>Lane 02 nibble 1 adjusted value (post nibble): 004d
09.762: <09>Lane 03 nibble 1 raw readback: 0046
09.762: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0046
09.762: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
09.762: <09>Lane 04 nibble 1 raw readback: 0043
09.762: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0043
09.762: <09>Lane 04 nibble 1 adjusted value (post nibble): 0046
09.762: <09>Lane 05 nibble 1 raw readback: 0049
09.762: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0049
09.762: <09>Lane 05 nibble 1 adjusted value (post nibble): 004b
09.762: <09>Lane 06 nibble 1 raw readback: 004e
09.762: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004e
09.762: <09>Lane 06 nibble 1 adjusted value (post nibble): 004e
09.762: <09>Lane 07 nibble 1 raw readback: 0053
09.762: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0053
09.762: <09>Lane 07 nibble 1 adjusted value (post nibble): 0052
09.762: <09>Lane 08 nibble 1 raw readback: 0041
09.762: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0041
09.762: <09>Lane 08 nibble 1 adjusted value (post nibble): 0045
09.762: <09>original critical gross delay: 0
09.762: <09>new critical gross delay: 0
09.762: DIMM 0 RttNom: 3
09.762: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.762: DIMM 0 RttNom: 3
09.762: DIMM 0 RttWr: 1
09.762: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.762: DIMM 0 RttWr: 1
09.762: DIMM 0 RttNom: 3
09.762: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.762: DIMM 0 RttNom: 3
09.762: DIMM 0 RttWr: 1
09.762: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.762: DIMM 0 RttWr: 1
09.762: DIMM 1 RttNom: 3
09.762: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.762: DIMM 0 RttNom: 3
09.762: DIMM 1 RttWr: 1
09.762: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.762: DIMM 0 RttWr: 1
09.762: DIMM 1 RttNom: 3
09.762: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.762: DIMM 0 RttNom: 3
09.762: DIMM 1 RttWr: 1
09.762: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.762: DIMM 0 RttWr: 1
09.762: AgesaHwWlPhase1: training nibble 0
09.762: DIMM 1 RttNom: 3
09.762: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.763: DIMM 1 RttWr: 1
09.763: DIMM 1 RttWr: 1
09.763: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.763: DIMM 1 RttWr: 1
09.763: DIMM 1 RttNom: 3
09.763: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.763: DIMM 1 RttNom: 3
09.763: DIMM 1 RttWr: 1
09.763: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.763: DIMM 1 RttWr: 1
09.763: DIMM 0 RttNom: 3
09.763: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.763: DIMM 1 RttNom: 3
09.763: DIMM 0 RttWr: 1
09.763: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.763: DIMM 1 RttWr: 1
09.763: DIMM 0 RttNom: 3
09.763: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.763: DIMM 1 RttNom: 3
09.763: DIMM 0 RttWr: 1
09.763: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.763: DIMM 1 RttWr: 1
09.763: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.763: <09>Lane 00 scaled delay: 0053
09.763: <09>Lane 00 new seed: 0053
09.763: <09>Lane 01 scaled delay: 0051
09.763: <09>Lane 01 new seed: 0051
09.763: <09>Lane 02 scaled delay: 004d
09.763: <09>Lane 02 new seed: 004d
09.763: <09>Lane 03 scaled delay: 004b
09.763: <09>Lane 03 new seed: 004b
09.763: <09>Lane 04 scaled delay: 004a
09.763: <09>Lane 04 new seed: 004a
09.763: <09>Lane 05 scaled delay: 004d
09.763: <09>Lane 05 new seed: 004d
09.763: <09>Lane 06 scaled delay: 004f
09.763: <09>Lane 06 new seed: 004f
09.763: <09>Lane 07 scaled delay: 0052
09.763: <09>Lane 07 new seed: 0052
09.763: <09>Lane 08 scaled delay: 0049
09.763: <09>Lane 08 new seed: 0049
09.763: <09>Lane 00 nibble 0 raw readback: 0053
09.763: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0053
09.763: <09>Lane 00 nibble 0 adjusted value (post nibble): 0053
09.763: <09>Lane 01 nibble 0 raw readback: 004d
09.763: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004d
09.763: <09>Lane 01 nibble 0 adjusted value (post nibble): 004d
09.763: <09>Lane 02 nibble 0 raw readback: 0048
09.763: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0048
09.763: <09>Lane 02 nibble 0 adjusted value (post nibble): 0048
09.763: <09>Lane 03 nibble 0 raw readback: 0044
09.763: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
09.763: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
09.763: <09>Lane 04 nibble 0 raw readback: 0041
09.763: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0041
09.763: <09>Lane 04 nibble 0 adjusted value (post nibble): 0041
09.763: <09>Lane 05 nibble 0 raw readback: 0048
09.763: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0048
09.763: <09>Lane 05 nibble 0 adjusted value (post nibble): 0048
09.763: <09>Lane 06 nibble 0 raw readback: 004e
09.763: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004e
09.763: <09>Lane 06 nibble 0 adjusted value (post nibble): 004e
09.763: <09>Lane 07 nibble 0 raw readback: 0052
09.763: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0052
09.763: <09>Lane 07 nibble 0 adjusted value (post nibble): 0052
09.763: <09>Lane 08 nibble 0 raw readback: 0041
09.763: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0041
09.763: <09>Lane 08 nibble 0 adjusted value (post nibble): 0041
09.763: AgesaHwWlPhase1: training nibble 1
09.763: DIMM 1 RttNom: 3
09.763: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.763: DIMM 1 RttWr: 1
09.764: DIMM 1 RttWr: 1
09.764: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.764: DIMM 1 RttWr: 1
09.764: DIMM 1 RttNom: 3
09.764: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.764: DIMM 1 RttNom: 3
09.764: DIMM 1 RttWr: 1
09.764: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.764: DIMM 1 RttWr: 1
09.764: DIMM 0 RttNom: 3
09.764: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.764: DIMM 1 RttNom: 3
09.764: DIMM 0 RttWr: 1
09.764: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.764: DIMM 1 RttWr: 1
09.764: DIMM 0 RttNom: 3
09.764: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.764: DIMM 1 RttNom: 3
09.764: DIMM 0 RttWr: 1
09.764: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.764: DIMM 1 RttWr: 1
09.764: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.764: <09>Lane 00 new seed: 0053
09.764: <09>Lane 01 new seed: 0051
09.764: <09>Lane 02 new seed: 004d
09.764: <09>Lane 03 new seed: 004b
09.764: <09>Lane 04 new seed: 004a
09.764: <09>Lane 05 new seed: 004d
09.764: <09>Lane 06 new seed: 004f
09.764: <09>Lane 07 new seed: 0052
09.764: <09>Lane 08 new seed: 0049
09.764: <09>Lane 00 nibble 1 raw readback: 0053
09.764: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0053
09.764: <09>Lane 00 nibble 1 adjusted value (post nibble): 0053
09.764: <09>Lane 01 nibble 1 raw readback: 004e
09.764: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004e
09.764: <09>Lane 01 nibble 1 adjusted value (post nibble): 004f
09.764: <09>Lane 02 nibble 1 raw readback: 0047
09.764: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0047
09.764: <09>Lane 02 nibble 1 adjusted value (post nibble): 004a
09.764: <09>Lane 03 nibble 1 raw readback: 0045
09.764: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
09.764: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
09.764: <09>Lane 04 nibble 1 raw readback: 0040
09.764: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0040
09.764: <09>Lane 04 nibble 1 adjusted value (post nibble): 0045
09.764: <09>Lane 05 nibble 1 raw readback: 0047
09.764: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0047
09.764: <09>Lane 05 nibble 1 adjusted value (post nibble): 004a
09.764: <09>Lane 06 nibble 1 raw readback: 004d
09.764: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004d
09.764: <09>Lane 06 nibble 1 adjusted value (post nibble): 004e
09.764: <09>Lane 07 nibble 1 raw readback: 0051
09.764: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0051
09.764: <09>Lane 07 nibble 1 adjusted value (post nibble): 0051
09.764: <09>Lane 08 nibble 1 raw readback: 003e
09.764: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003e
09.764: <09>Lane 08 nibble 1 adjusted value (post nibble): 0043
09.764: <09>original critical gross delay: 0
09.764: <09>new critical gross delay: 0
09.764: DIMM 1 RttNom: 3
09.764: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
09.764: DIMM 1 RttNom: 3
09.764: DIMM 1 RttWr: 1
09.764: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
09.765: DIMM 1 RttWr: 1
09.765: DIMM 1 RttNom: 3
09.765: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
09.765: DIMM 1 RttNom: 3
09.765: DIMM 1 RttWr: 1
09.765: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
09.765: DIMM 1 RttWr: 1
09.765: DIMM 0 RttNom: 3
09.765: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
09.765: DIMM 1 RttNom: 3
09.765: DIMM 0 RttWr: 1
09.765: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
09.765: DIMM 1 RttWr: 1
09.765: DIMM 0 RttNom: 3
09.765: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
09.765: DIMM 1 RttNom: 3
09.765: DIMM 0 RttWr: 1
09.765: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
09.765: DIMM 1 RttWr: 1
09.765: SetTargetFreq: Start
09.765: SetTargetFreq: Node 3: New frequency code: 000e
09.765: ChangeMemClk: Start
09.765: set_2t_configuration: Start
09.765: set_2t_configuration: Done
09.765: mct_BeforePlatformSpec: Start
09.765: mct_BeforePlatformSpec: Done
09.765: mct_PlatformSpec: Start
09.765: Programmed DCT 0 timing/termination pattern 00383a38 30222222
09.765: mct_PlatformSpec: Done
09.765: set_2t_configuration: Start
09.765: set_2t_configuration: Done
09.765: mct_BeforePlatformSpec: Start
09.765: mct_BeforePlatformSpec: Done
09.765: mct_PlatformSpec: Start
09.765: Programmed DCT 1 timing/termination pattern 00383a38 30222222
09.765: mct_PlatformSpec: Done
09.765: ChangeMemClk: Done
09.765: phyAssistedMemFnceTraining: Start
09.765: phyAssistedMemFnceTraining: training node 3 DCT 0
09.766: phyAssistedMemFnceTraining: done training node 3 DCT 0
09.766: phyAssistedMemFnceTraining: training node 3 DCT 1
09.766: phyAssistedMemFnceTraining: done training node 3 DCT 1
09.766: phyAssistedMemFnceTraining: Done
09.766: InitPhyCompensation: DCT 0: Start
09.766: Waiting for predriver calibration to be applied...done!
09.766: InitPhyCompensation: DCT 0: Done
09.766: phyAssistedMemFnceTraining: Start
09.766: phyAssistedMemFnceTraining: training node 3 DCT 0
09.766: phyAssistedMemFnceTraining: done training node 3 DCT 0
09.766: phyAssistedMemFnceTraining: training node 3 DCT 1
09.766: phyAssistedMemFnceTraining: done training node 3 DCT 1
09.766: phyAssistedMemFnceTraining: Done
09.766: InitPhyCompensation: DCT 1: Start
09.766: Waiting for predriver calibration to be applied...done!
09.766: InitPhyCompensation: DCT 1: Done
09.766: Preparing to send DCT 0 DIMM 0 RC10: 02 (F2xA8: 02000300)
09.767: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.767: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
09.767: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.767: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
09.767: Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 02000c00)
09.767: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.767: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
09.767: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.767: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
09.767: Preparing to send DCT 1 DIMM 0 RC10: 02 (F2xA8: 02000300)
09.767: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.767: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
09.767: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.767: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
09.767: Preparing to send DCT 1 DIMM 1 RC10: 02 (F2xA8: 02000c00)
09.767: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.767: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
09.767: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.767: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
09.767: SetTargetFreq: Done
09.767: SPD2ndTiming: Start
09.767: SPD2ndTiming: Done
09.767: mct_BeforeDramInit_Prod_D: Start
09.767: mct_ProgramODT_D: Start
09.767: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
09.767: mct_ProgramODT_D: Done
09.767: mct_BeforeDramInit_Prod_D: Done
09.767: mct_DramInit_Sw_D: Start
09.767: DIMM 0 RttWr: 2
09.767: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.767: mct_SendMrsCmd: Start
09.767: mct_SendMrsCmd: Done
09.767: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
09.767: mct_SendMrsCmd: Start
09.767: mct_SendMrsCmd: Done
09.767: DIMM 0 RttNom: 5
09.767: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.767: mct_SendMrsCmd: Start
09.767: mct_SendMrsCmd: Done
09.768: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001b78
09.768: mct_SendMrsCmd: Start
09.768: mct_SendMrsCmd: Done
09.768: DIMM 0 RttWr: 2
09.768: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.768: mct_SendMrsCmd: Start
09.768: mct_SendMrsCmd: Done
09.768: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
09.768: mct_SendMrsCmd: Start
09.768: mct_SendMrsCmd: Done
09.768: DIMM 0 RttNom: 5
09.768: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.768: mct_SendMrsCmd: Start
09.768: mct_SendMrsCmd: Done
09.768: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201b78
09.768: mct_SendMrsCmd: Start
09.768: mct_SendMrsCmd: Done
09.768: DIMM 1 RttWr: 2
09.768: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.768: mct_SendMrsCmd: Start
09.768: mct_SendMrsCmd: Done
09.768: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
09.768: mct_SendMrsCmd: Start
09.768: mct_SendMrsCmd: Done
09.768: DIMM 1 RttNom: 5
09.768: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.768: mct_SendMrsCmd: Start
09.768: mct_SendMrsCmd: Done
09.768: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b78
09.768: mct_SendMrsCmd: Start
09.768: mct_SendMrsCmd: Done
09.768: DIMM 1 RttWr: 2
09.768: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.768: mct_SendMrsCmd: Start
09.768: mct_SendMrsCmd: Done
09.768: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
09.768: mct_SendMrsCmd: Start
09.768: mct_SendMrsCmd: Done
09.768: DIMM 1 RttNom: 5
09.768: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.768: mct_SendMrsCmd: Start
09.768: mct_SendMrsCmd: Done
09.768: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b78
09.768: mct_SendMrsCmd: Start
09.768: mct_SendMrsCmd: Done
09.768: mct_DramInit_Sw_D: Done
09.768: AgesaHwWlPhase1: training nibble 0
09.768: DIMM 0 RttNom: 5
09.768: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.768: DIMM 0 RttWr: 2
09.768: DIMM 0 RttWr: 2
09.768: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.768: DIMM 0 RttWr: 2
09.768: DIMM 0 RttNom: 5
09.768: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.768: DIMM 0 RttNom: 5
09.768: DIMM 0 RttWr: 2
09.769: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.769: DIMM 0 RttWr: 2
09.769: DIMM 1 RttNom: 5
09.769: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.769: DIMM 0 RttNom: 5
09.769: DIMM 1 RttWr: 2
09.769: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.769: DIMM 0 RttWr: 2
09.769: DIMM 1 RttNom: 5
09.769: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.769: DIMM 0 RttNom: 5
09.769: DIMM 1 RttWr: 2
09.769: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.769: DIMM 0 RttWr: 2
09.769: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.769: <09>Lane 00 scaled delay: 005f
09.769: <09>Lane 00 new seed: 005f
09.769: <09>Lane 01 scaled delay: 0059
09.769: <09>Lane 01 new seed: 0059
09.769: <09>Lane 02 scaled delay: 0055
09.769: <09>Lane 02 new seed: 0055
09.769: <09>Lane 03 scaled delay: 0052
09.769: <09>Lane 03 new seed: 0052
09.769: <09>Lane 04 scaled delay: 004f
09.769: <09>Lane 04 new seed: 004f
09.769: <09>Lane 05 scaled delay: 0054
09.769: <09>Lane 05 new seed: 0054
09.769: <09>Lane 06 scaled delay: 0059
09.769: <09>Lane 06 new seed: 0059
09.769: <09>Lane 07 scaled delay: 005d
09.769: <09>Lane 07 new seed: 005d
09.769: <09>Lane 08 scaled delay: 004d
09.769: <09>Lane 08 new seed: 004d
09.769: <09>Lane 00 nibble 0 raw readback: 005f
09.769: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005f
09.769: <09>Lane 00 nibble 0 adjusted value (post nibble): 005f
09.769: <09>Lane 01 nibble 0 raw readback: 0054
09.769: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0054
09.769: <09>Lane 01 nibble 0 adjusted value (post nibble): 0054
09.769: <09>Lane 02 nibble 0 raw readback: 0050
09.769: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0050
09.769: <09>Lane 02 nibble 0 adjusted value (post nibble): 0050
09.769: <09>Lane 03 nibble 0 raw readback: 0051
09.769: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0051
09.769: <09>Lane 03 nibble 0 adjusted value (post nibble): 0051
09.769: <09>Lane 04 nibble 0 raw readback: 004d
09.769: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004d
09.769: <09>Lane 04 nibble 0 adjusted value (post nibble): 004d
09.769: <09>Lane 05 nibble 0 raw readback: 0053
09.769: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0053
09.769: <09>Lane 05 nibble 0 adjusted value (post nibble): 0053
09.769: <09>Lane 06 nibble 0 raw readback: 0054
09.769: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0054
09.769: <09>Lane 06 nibble 0 adjusted value (post nibble): 0054
09.769: <09>Lane 07 nibble 0 raw readback: 0059
09.769: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0059
09.770: <09>Lane 07 nibble 0 adjusted value (post nibble): 0059
09.770: <09>Lane 08 nibble 0 raw readback: 0047
09.770: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0047
09.770: <09>Lane 08 nibble 0 adjusted value (post nibble): 0047
09.770: AgesaHwWlPhase1: training nibble 1
09.770: DIMM 0 RttNom: 5
09.770: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.770: DIMM 0 RttWr: 2
09.770: DIMM 0 RttWr: 2
09.770: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.770: DIMM 0 RttWr: 2
09.770: DIMM 0 RttNom: 5
09.770: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.770: DIMM 0 RttNom: 5
09.770: DIMM 0 RttWr: 2
09.770: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.770: DIMM 0 RttWr: 2
09.770: DIMM 1 RttNom: 5
09.770: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.770: DIMM 0 RttNom: 5
09.770: DIMM 1 RttWr: 2
09.770: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.770: DIMM 0 RttWr: 2
09.770: DIMM 1 RttNom: 5
09.770: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.770: DIMM 0 RttNom: 5
09.770: DIMM 1 RttWr: 2
09.770: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.770: DIMM 0 RttWr: 2
09.770: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.770: <09>Lane 00 new seed: 005f
09.770: <09>Lane 01 new seed: 0059
09.770: <09>Lane 02 new seed: 0055
09.770: <09>Lane 03 new seed: 0052
09.770: <09>Lane 04 new seed: 004f
09.770: <09>Lane 05 new seed: 0054
09.770: <09>Lane 06 new seed: 0059
09.770: <09>Lane 07 new seed: 005d
09.770: <09>Lane 08 new seed: 004d
09.770: <09>Lane 00 nibble 1 raw readback: 0061
09.770: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0061
09.770: <09>Lane 00 nibble 1 adjusted value (post nibble): 0060
09.770: <09>Lane 01 nibble 1 raw readback: 0059
09.770: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0059
09.770: <09>Lane 01 nibble 1 adjusted value (post nibble): 0059
09.770: <09>Lane 02 nibble 1 raw readback: 0054
09.770: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0054
09.770: <09>Lane 02 nibble 1 adjusted value (post nibble): 0054
09.770: <09>Lane 03 nibble 1 raw readback: 004f
09.770: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004f
09.770: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
09.770: <09>Lane 04 nibble 1 raw readback: 004b
09.770: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004b
09.770: <09>Lane 04 nibble 1 adjusted value (post nibble): 004d
09.770: <09>Lane 05 nibble 1 raw readback: 0050
09.770: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0050
09.770: <09>Lane 05 nibble 1 adjusted value (post nibble): 0052
09.770: <09>Lane 06 nibble 1 raw readback: 0055
09.770: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0055
09.770: <09>Lane 06 nibble 1 adjusted value (post nibble): 0057
09.770: <09>Lane 07 nibble 1 raw readback: 005c
09.770: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005c
09.770: <09>Lane 07 nibble 1 adjusted value (post nibble): 005c
09.770: <09>Lane 08 nibble 1 raw readback: 0049
09.770: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0049
09.770: <09>Lane 08 nibble 1 adjusted value (post nibble): 004b
09.770: <09>original critical gross delay: 0
09.770: <09>new critical gross delay: 0
09.771: DIMM 0 RttNom: 5
09.771: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.771: DIMM 0 RttNom: 5
09.771: DIMM 0 RttWr: 2
09.771: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.771: DIMM 0 RttWr: 2
09.771: DIMM 0 RttNom: 5
09.771: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.771: DIMM 0 RttNom: 5
09.771: DIMM 0 RttWr: 2
09.771: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.771: DIMM 0 RttWr: 2
09.771: DIMM 1 RttNom: 5
09.771: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.771: DIMM 0 RttNom: 5
09.771: DIMM 1 RttWr: 2
09.771: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.771: DIMM 0 RttWr: 2
09.771: DIMM 1 RttNom: 5
09.771: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.771: DIMM 0 RttNom: 5
09.771: DIMM 1 RttWr: 2
09.771: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.771: DIMM 0 RttWr: 2
09.771: AgesaHwWlPhase1: training nibble 0
09.771: DIMM 1 RttNom: 5
09.771: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.771: DIMM 1 RttWr: 2
09.771: DIMM 1 RttWr: 2
09.771: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.771: DIMM 1 RttWr: 2
09.771: DIMM 1 RttNom: 5
09.771: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.771: DIMM 1 RttNom: 5
09.771: DIMM 1 RttWr: 2
09.771: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.771: DIMM 1 RttWr: 2
09.771: DIMM 0 RttNom: 5
09.771: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.771: DIMM 1 RttNom: 5
09.771: DIMM 0 RttWr: 2
09.771: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.771: DIMM 1 RttWr: 2
09.771: DIMM 0 RttNom: 5
09.771: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.771: DIMM 1 RttNom: 5
09.771: DIMM 0 RttWr: 2
09.772: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.771: DIMM 1 RttWr: 2
09.771: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.771: <09>Lane 00 scaled delay: 005d
09.771: <09>Lane 00 new seed: 005d
09.771: <09>Lane 01 scaled delay: 0057
09.771: <09>Lane 01 new seed: 0057
09.771: <09>Lane 02 scaled delay: 0053
09.771: <09>Lane 02 new seed: 0053
09.772: <09>Lane 03 scaled delay: 0052
09.772: <09>Lane 03 new seed: 0052
09.772: <09>Lane 04 scaled delay: 004d
09.772: <09>Lane 04 new seed: 004d
09.772: <09>Lane 05 scaled delay: 0052
09.772: <09>Lane 05 new seed: 0052
09.772: <09>Lane 06 scaled delay: 0053
09.772: <09>Lane 06 new seed: 0053
09.772: <09>Lane 07 scaled delay: 0059
09.772: <09>Lane 07 new seed: 0059
09.772: <09>Lane 08 scaled delay: 004a
09.772: <09>Lane 08 new seed: 004a
09.772: <09>Lane 00 nibble 0 raw readback: 005d
09.772: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005d
09.772: <09>Lane 00 nibble 0 adjusted value (post nibble): 005d
09.772: <09>Lane 01 nibble 0 raw readback: 0054
09.772: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0054
09.772: <09>Lane 01 nibble 0 adjusted value (post nibble): 0054
09.772: <09>Lane 02 nibble 0 raw readback: 004f
09.772: <09>Lane 02 nibble 0 adjusted value (pre nibble): 004f
09.772: <09>Lane 02 nibble 0 adjusted value (post nibble): 004f
09.772: <09>Lane 03 nibble 0 raw readback: 004d
09.772: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004d
09.772: <09>Lane 03 nibble 0 adjusted value (post nibble): 004d
09.772: <09>Lane 04 nibble 0 raw readback: 0049
09.772: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0049
09.772: <09>Lane 04 nibble 0 adjusted value (post nibble): 0049
09.772: <09>Lane 05 nibble 0 raw readback: 004f
09.772: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004f
09.772: <09>Lane 05 nibble 0 adjusted value (post nibble): 004f
09.772: <09>Lane 06 nibble 0 raw readback: 004f
09.772: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004f
09.772: <09>Lane 06 nibble 0 adjusted value (post nibble): 004f
09.772: <09>Lane 07 nibble 0 raw readback: 0057
09.772: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0057
09.772: <09>Lane 07 nibble 0 adjusted value (post nibble): 0057
09.772: <09>Lane 08 nibble 0 raw readback: 0045
09.772: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0045
09.772: <09>Lane 08 nibble 0 adjusted value (post nibble): 0045
09.772: AgesaHwWlPhase1: training nibble 1
09.772: DIMM 1 RttNom: 5
09.772: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.772: DIMM 1 RttWr: 2
09.772: DIMM 1 RttWr: 2
09.772: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.772: DIMM 1 RttWr: 2
09.772: DIMM 1 RttNom: 5
09.772: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.772: DIMM 1 RttNom: 5
09.772: DIMM 1 RttWr: 2
09.772: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.772: DIMM 1 RttWr: 2
09.772: DIMM 0 RttNom: 5
09.772: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.772: DIMM 1 RttNom: 5
09.772: DIMM 0 RttWr: 2
09.772: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.772: DIMM 1 RttWr: 2
09.772: DIMM 0 RttNom: 5
09.772: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.772: DIMM 1 RttNom: 5
09.772: DIMM 0 RttWr: 2
09.772: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.772: DIMM 1 RttWr: 2
09.772: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.772: <09>Lane 00 new seed: 005d
09.772: <09>Lane 01 new seed: 0057
09.772: <09>Lane 02 new seed: 0053
09.772: <09>Lane 03 new seed: 0052
09.772: <09>Lane 04 new seed: 004d
09.772: <09>Lane 05 new seed: 0052
09.772: <09>Lane 06 new seed: 0053
09.773: <09>Lane 07 new seed: 0059
09.773: <09>Lane 08 new seed: 004a
09.773: <09>Lane 00 nibble 1 raw readback: 005d
09.773: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005d
09.773: <09>Lane 00 nibble 1 adjusted value (post nibble): 005d
09.773: <09>Lane 01 nibble 1 raw readback: 0056
09.773: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0056
09.773: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
09.773: <09>Lane 02 nibble 1 raw readback: 0050
09.773: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0050
09.773: <09>Lane 02 nibble 1 adjusted value (post nibble): 0051
09.773: <09>Lane 03 nibble 1 raw readback: 004e
09.773: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004e
09.773: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
09.773: <09>Lane 04 nibble 1 raw readback: 0048
09.773: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0048
09.773: <09>Lane 04 nibble 1 adjusted value (post nibble): 004a
09.773: <09>Lane 05 nibble 1 raw readback: 004e
09.773: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004e
09.773: <09>Lane 05 nibble 1 adjusted value (post nibble): 0050
09.773: <09>Lane 06 nibble 1 raw readback: 004f
09.773: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004f
09.773: <09>Lane 06 nibble 1 adjusted value (post nibble): 0051
09.773: <09>Lane 07 nibble 1 raw readback: 0058
09.773: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0058
09.773: <09>Lane 07 nibble 1 adjusted value (post nibble): 0058
09.773: <09>Lane 08 nibble 1 raw readback: 0044
09.773: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0044
09.773: <09>Lane 08 nibble 1 adjusted value (post nibble): 0047
09.773: <09>original critical gross delay: 0
09.773: <09>new critical gross delay: 0
09.773: DIMM 1 RttNom: 5
09.773: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
09.773: DIMM 1 RttNom: 5
09.773: DIMM 1 RttWr: 2
09.773: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
09.773: DIMM 1 RttWr: 2
09.773: DIMM 1 RttNom: 5
09.773: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
09.773: DIMM 1 RttNom: 5
09.773: DIMM 1 RttWr: 2
09.773: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
09.773: DIMM 1 RttWr: 2
09.773: DIMM 0 RttNom: 5
09.773: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
09.773: DIMM 1 RttNom: 5
09.773: DIMM 0 RttWr: 2
09.773: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
09.773: DIMM 1 RttWr: 2
09.773: DIMM 0 RttNom: 5
09.773: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
09.773: DIMM 1 RttNom: 5
09.773: DIMM 0 RttWr: 2
09.773: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
09.773: DIMM 1 RttWr: 2
09.773: SPD2ndTiming: Start
09.774: SPD2ndTiming: Done
09.774: mct_BeforeDramInit_Prod_D: Start
09.774: mct_ProgramODT_D: Start
09.774: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
09.774: mct_ProgramODT_D: Done
09.774: mct_BeforeDramInit_Prod_D: Done
09.774: mct_DramInit_Sw_D: Start
09.774: DIMM 0 RttWr: 2
09.774: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.774: mct_SendMrsCmd: Start
09.774: mct_SendMrsCmd: Done
09.774: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
09.774: mct_SendMrsCmd: Start
09.774: mct_SendMrsCmd: Done
09.774: DIMM 0 RttNom: 5
09.774: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.774: mct_SendMrsCmd: Start
09.774: mct_SendMrsCmd: Done
09.774: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001b78
09.774: mct_SendMrsCmd: Start
09.774: mct_SendMrsCmd: Done
09.774: DIMM 0 RttWr: 2
09.774: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.774: mct_SendMrsCmd: Start
09.774: mct_SendMrsCmd: Done
09.774: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
09.774: mct_SendMrsCmd: Start
09.774: mct_SendMrsCmd: Done
09.774: DIMM 0 RttNom: 5
09.774: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.774: mct_SendMrsCmd: Start
09.774: mct_SendMrsCmd: Done
09.774: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201b78
09.774: mct_SendMrsCmd: Start
09.774: mct_SendMrsCmd: Done
09.774: DIMM 1 RttWr: 2
09.774: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.774: mct_SendMrsCmd: Start
09.774: mct_SendMrsCmd: Done
09.774: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
09.774: mct_SendMrsCmd: Start
09.774: mct_SendMrsCmd: Done
09.774: DIMM 1 RttNom: 5
09.774: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.774: mct_SendMrsCmd: Start
09.774: mct_SendMrsCmd: Done
09.774: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401b78
09.774: mct_SendMrsCmd: Start
09.774: mct_SendMrsCmd: Done
09.775: DIMM 1 RttWr: 2
09.775: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.775: mct_SendMrsCmd: Start
09.775: mct_SendMrsCmd: Done
09.775: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
09.775: mct_SendMrsCmd: Start
09.775: mct_SendMrsCmd: Done
09.775: DIMM 1 RttNom: 5
09.775: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.775: mct_SendMrsCmd: Start
09.775: mct_SendMrsCmd: Done
09.775: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601b78
09.775: mct_SendMrsCmd: Start
09.775: mct_SendMrsCmd: Done
09.775: mct_DramInit_Sw_D: Done
09.775: AgesaHwWlPhase1: training nibble 0
09.775: DIMM 0 RttNom: 5
09.775: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.775: DIMM 0 RttWr: 2
09.775: DIMM 0 RttWr: 2
09.775: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.775: DIMM 0 RttWr: 2
09.775: DIMM 0 RttNom: 5
09.775: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.775: DIMM 0 RttNom: 5
09.775: DIMM 0 RttWr: 2
09.775: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.775: DIMM 0 RttWr: 2
09.775: DIMM 1 RttNom: 5
09.775: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.775: DIMM 0 RttNom: 5
09.775: DIMM 1 RttWr: 2
09.775: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.775: DIMM 0 RttWr: 2
09.775: DIMM 1 RttNom: 5
09.775: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.775: DIMM 0 RttNom: 5
09.775: DIMM 1 RttWr: 2
09.775: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.775: DIMM 0 RttWr: 2
09.775: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.775: <09>Lane 00 scaled delay: 0061
09.775: <09>Lane 00 new seed: 0061
09.775: <09>Lane 01 scaled delay: 005c
09.775: <09>Lane 01 new seed: 005c
09.775: <09>Lane 02 scaled delay: 0058
09.775: <09>Lane 02 new seed: 0058
09.775: <09>Lane 03 scaled delay: 0052
09.775: <09>Lane 03 new seed: 0052
09.775: <09>Lane 04 scaled delay: 004f
09.775: <09>Lane 04 new seed: 004f
09.775: <09>Lane 05 scaled delay: 0055
09.775: <09>Lane 05 new seed: 0055
09.775: <09>Lane 06 scaled delay: 0059
09.775: <09>Lane 06 new seed: 0059
09.775: <09>Lane 07 scaled delay: 005e
09.776: <09>Lane 07 new seed: 005e
09.775: <09>Lane 08 scaled delay: 004e
09.776: <09>Lane 08 new seed: 004e
09.776: <09>Lane 00 nibble 0 raw readback: 001f
09.776: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005f
09.776: <09>Lane 00 nibble 0 adjusted value (post nibble): 005f
09.776: <09>Lane 01 nibble 0 raw readback: 0059
09.776: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0059
09.776: <09>Lane 01 nibble 0 adjusted value (post nibble): 0059
09.776: <09>Lane 02 nibble 0 raw readback: 0054
09.776: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0054
09.776: <09>Lane 02 nibble 0 adjusted value (post nibble): 0054
09.776: <09>Lane 03 nibble 0 raw readback: 004e
09.776: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004e
09.776: <09>Lane 03 nibble 0 adjusted value (post nibble): 004e
09.776: <09>Lane 04 nibble 0 raw readback: 004c
09.776: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004c
09.776: <09>Lane 04 nibble 0 adjusted value (post nibble): 004c
09.776: <09>Lane 05 nibble 0 raw readback: 0054
09.776: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0054
09.776: <09>Lane 05 nibble 0 adjusted value (post nibble): 0054
09.776: <09>Lane 06 nibble 0 raw readback: 0059
09.776: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0059
09.776: <09>Lane 06 nibble 0 adjusted value (post nibble): 0059
09.776: <09>Lane 07 nibble 0 raw readback: 0060
09.776: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0060
09.776: <09>Lane 07 nibble 0 adjusted value (post nibble): 0060
09.776: <09>Lane 08 nibble 0 raw readback: 0049
09.776: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0049
09.776: <09>Lane 08 nibble 0 adjusted value (post nibble): 0049
09.776: AgesaHwWlPhase1: training nibble 1
09.776: DIMM 0 RttNom: 5
09.776: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.776: DIMM 0 RttWr: 2
09.776: DIMM 0 RttWr: 2
09.776: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.776: DIMM 0 RttWr: 2
09.776: DIMM 0 RttNom: 5
09.776: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.776: DIMM 0 RttNom: 5
09.776: DIMM 0 RttWr: 2
09.776: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.776: DIMM 0 RttWr: 2
09.776: DIMM 1 RttNom: 5
09.776: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.776: DIMM 0 RttNom: 5
09.776: DIMM 1 RttWr: 2
09.776: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.776: DIMM 0 RttWr: 2
09.776: DIMM 1 RttNom: 5
09.776: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.776: DIMM 0 RttNom: 5
09.776: DIMM 1 RttWr: 2
09.776: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.776: DIMM 0 RttWr: 2
09.776: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.776: <09>Lane 00 new seed: 0061
09.776: <09>Lane 01 new seed: 005c
09.776: <09>Lane 02 new seed: 0058
09.776: <09>Lane 03 new seed: 0052
09.776: <09>Lane 04 new seed: 004f
09.776: <09>Lane 05 new seed: 0055
09.776: <09>Lane 06 new seed: 0059
09.776: <09>Lane 07 new seed: 005e
09.776: <09>Lane 08 new seed: 004e
09.777: <09>Lane 00 nibble 1 raw readback: 0021
09.777: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0061
09.777: <09>Lane 00 nibble 1 adjusted value (post nibble): 0061
09.777: <09>Lane 01 nibble 1 raw readback: 005c
09.777: <09>Lane 01 nibble 1 adjusted value (pre nibble): 005c
09.777: <09>Lane 01 nibble 1 adjusted value (post nibble): 005c
09.777: <09>Lane 02 nibble 1 raw readback: 0056
09.777: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0056
09.777: <09>Lane 02 nibble 1 adjusted value (post nibble): 0057
09.777: <09>Lane 03 nibble 1 raw readback: 004f
09.777: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004f
09.777: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
09.777: <09>Lane 04 nibble 1 raw readback: 004c
09.777: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004c
09.777: <09>Lane 04 nibble 1 adjusted value (post nibble): 004d
09.777: <09>Lane 05 nibble 1 raw readback: 0053
09.777: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0053
09.777: <09>Lane 05 nibble 1 adjusted value (post nibble): 0054
09.777: <09>Lane 06 nibble 1 raw readback: 005a
09.777: <09>Lane 06 nibble 1 adjusted value (pre nibble): 005a
09.777: <09>Lane 06 nibble 1 adjusted value (post nibble): 0059
09.777: <09>Lane 07 nibble 1 raw readback: 005f
09.777: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005f
09.777: <09>Lane 07 nibble 1 adjusted value (post nibble): 005e
09.777: <09>Lane 08 nibble 1 raw readback: 004a
09.777: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004a
09.777: <09>Lane 08 nibble 1 adjusted value (post nibble): 004c
09.777: <09>original critical gross delay: 0
09.777: <09>new critical gross delay: 0
09.777: DIMM 0 RttNom: 5
09.777: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.777: DIMM 0 RttNom: 5
09.777: DIMM 0 RttWr: 2
09.777: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.777: DIMM 0 RttWr: 2
09.777: DIMM 0 RttNom: 5
09.777: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.777: DIMM 0 RttNom: 5
09.777: DIMM 0 RttWr: 2
09.777: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.777: DIMM 0 RttWr: 2
09.777: DIMM 1 RttNom: 5
09.777: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.777: DIMM 0 RttNom: 5
09.777: DIMM 1 RttWr: 2
09.777: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.777: DIMM 0 RttWr: 2
09.777: DIMM 1 RttNom: 5
09.777: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.777: DIMM 0 RttNom: 5
09.777: DIMM 1 RttWr: 2
09.777: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.777: DIMM 0 RttWr: 2
09.777: AgesaHwWlPhase1: training nibble 0
09.777: DIMM 1 RttNom: 5
09.777: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.777: DIMM 1 RttWr: 2
09.777: DIMM 1 RttWr: 2
09.777: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.777: DIMM 1 RttWr: 2
09.778: DIMM 1 RttNom: 5
09.777: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.777: DIMM 1 RttNom: 5
09.778: DIMM 1 RttWr: 2
09.778: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.778: DIMM 1 RttWr: 2
09.778: DIMM 0 RttNom: 5
09.778: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.778: DIMM 1 RttNom: 5
09.778: DIMM 0 RttWr: 2
09.778: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.778: DIMM 1 RttWr: 2
09.778: DIMM 0 RttNom: 5
09.778: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.778: DIMM 1 RttNom: 5
09.778: DIMM 0 RttWr: 2
09.778: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.778: DIMM 1 RttWr: 2
09.778: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.778: <09>Lane 00 scaled delay: 005f
09.778: <09>Lane 00 new seed: 005f
09.778: <09>Lane 01 scaled delay: 005a
09.778: <09>Lane 01 new seed: 005a
09.778: <09>Lane 02 scaled delay: 0054
09.778: <09>Lane 02 new seed: 0054
09.778: <09>Lane 03 scaled delay: 0052
09.778: <09>Lane 03 new seed: 0052
09.778: <09>Lane 04 scaled delay: 004e
09.778: <09>Lane 04 new seed: 004e
09.778: <09>Lane 05 scaled delay: 0054
09.778: <09>Lane 05 new seed: 0054
09.778: <09>Lane 06 scaled delay: 0059
09.778: <09>Lane 06 new seed: 0059
09.778: <09>Lane 07 scaled delay: 005d
09.778: <09>Lane 07 new seed: 005d
09.778: <09>Lane 08 scaled delay: 004b
09.778: <09>Lane 08 new seed: 004b
09.778: <09>Lane 00 nibble 0 raw readback: 005d
09.778: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005d
09.778: <09>Lane 00 nibble 0 adjusted value (post nibble): 005d
09.778: <09>Lane 01 nibble 0 raw readback: 0058
09.778: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0058
09.778: <09>Lane 01 nibble 0 adjusted value (post nibble): 0058
09.778: <09>Lane 02 nibble 0 raw readback: 0050
09.778: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0050
09.778: <09>Lane 02 nibble 0 adjusted value (post nibble): 0050
09.778: <09>Lane 03 nibble 0 raw readback: 004d
09.778: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004d
09.778: <09>Lane 03 nibble 0 adjusted value (post nibble): 004d
09.778: <09>Lane 04 nibble 0 raw readback: 0049
09.778: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0049
09.778: <09>Lane 04 nibble 0 adjusted value (post nibble): 0049
09.778: <09>Lane 05 nibble 0 raw readback: 0052
09.778: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0052
09.778: <09>Lane 05 nibble 0 adjusted value (post nibble): 0052
09.778: <09>Lane 06 nibble 0 raw readback: 0058
09.778: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0058
09.778: <09>Lane 06 nibble 0 adjusted value (post nibble): 0058
09.778: <09>Lane 07 nibble 0 raw readback: 005d
09.778: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005d
09.778: <09>Lane 07 nibble 0 adjusted value (post nibble): 005d
09.778: <09>Lane 08 nibble 0 raw readback: 0049
09.778: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0049
09.778: <09>Lane 08 nibble 0 adjusted value (post nibble): 0049
09.778: AgesaHwWlPhase1: training nibble 1
09.778: DIMM 1 RttNom: 5
09.778: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.778: DIMM 1 RttWr: 2
09.778: DIMM 1 RttWr: 2
09.778: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.778: DIMM 1 RttWr: 2
09.778: DIMM 1 RttNom: 5
09.778: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.778: DIMM 1 RttNom: 5
09.778: DIMM 1 RttWr: 2
09.779: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.778: DIMM 1 RttWr: 2
09.779: DIMM 0 RttNom: 5
09.779: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.779: DIMM 1 RttNom: 5
09.779: DIMM 0 RttWr: 2
09.779: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.779: DIMM 1 RttWr: 2
09.779: DIMM 0 RttNom: 5
09.779: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.779: DIMM 1 RttNom: 5
09.779: DIMM 0 RttWr: 2
09.779: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.779: DIMM 1 RttWr: 2
09.779: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.779: <09>Lane 00 new seed: 005f
09.779: <09>Lane 01 new seed: 005a
09.779: <09>Lane 02 new seed: 0054
09.779: <09>Lane 03 new seed: 0052
09.779: <09>Lane 04 new seed: 004e
09.779: <09>Lane 05 new seed: 0054
09.779: <09>Lane 06 new seed: 0059
09.779: <09>Lane 07 new seed: 005d
09.779: <09>Lane 08 new seed: 004b
09.779: <09>Lane 00 nibble 1 raw readback: 005f
09.779: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005f
09.779: <09>Lane 00 nibble 1 adjusted value (post nibble): 005f
09.779: <09>Lane 01 nibble 1 raw readback: 0059
09.779: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0059
09.779: <09>Lane 01 nibble 1 adjusted value (post nibble): 0059
09.779: <09>Lane 02 nibble 1 raw readback: 0051
09.779: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0051
09.779: <09>Lane 02 nibble 1 adjusted value (post nibble): 0052
09.779: <09>Lane 03 nibble 1 raw readback: 004e
09.779: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004e
09.779: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
09.779: <09>Lane 04 nibble 1 raw readback: 0049
09.779: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0049
09.779: <09>Lane 04 nibble 1 adjusted value (post nibble): 004b
09.779: <09>Lane 05 nibble 1 raw readback: 0050
09.779: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0050
09.779: <09>Lane 05 nibble 1 adjusted value (post nibble): 0052
09.779: <09>Lane 06 nibble 1 raw readback: 0058
09.779: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0058
09.779: <09>Lane 06 nibble 1 adjusted value (post nibble): 0058
09.779: <09>Lane 07 nibble 1 raw readback: 005d
09.779: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005d
09.779: <09>Lane 07 nibble 1 adjusted value (post nibble): 005d
09.779: <09>Lane 08 nibble 1 raw readback: 0046
09.779: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0046
09.779: <09>Lane 08 nibble 1 adjusted value (post nibble): 0048
09.779: <09>original critical gross delay: 0
09.779: <09>new critical gross delay: 0
09.779: DIMM 1 RttNom: 5
09.779: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
09.779: DIMM 1 RttNom: 5
09.779: DIMM 1 RttWr: 2
09.779: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
09.779: DIMM 1 RttWr: 2
09.779: DIMM 1 RttNom: 5
09.779: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
09.779: DIMM 1 RttNom: 5
09.779: DIMM 1 RttWr: 2
09.779: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
09.780: DIMM 1 RttWr: 2
09.780: DIMM 0 RttNom: 5
09.780: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
09.780: DIMM 1 RttNom: 5
09.780: DIMM 0 RttWr: 2
09.780: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
09.780: DIMM 1 RttWr: 2
09.780: DIMM 0 RttNom: 5
09.780: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
09.780: DIMM 1 RttNom: 5
09.780: DIMM 0 RttWr: 2
09.780: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
09.780: DIMM 1 RttWr: 2
09.780: SetTargetFreq: Start
09.780: SetTargetFreq: Node 3: New frequency code: 0012
09.780: ChangeMemClk: Start
09.780: set_2t_configuration: Start
09.780: set_2t_configuration: Done
09.780: mct_BeforePlatformSpec: Start
09.780: mct_BeforePlatformSpec: Done
09.780: mct_PlatformSpec: Start
09.780: Programmed DCT 0 timing/termination pattern 00353935 30222222
09.780: mct_PlatformSpec: Done
09.780: set_2t_configuration: Start
09.780: set_2t_configuration: Done
09.780: mct_BeforePlatformSpec: Start
09.780: mct_BeforePlatformSpec: Done
09.780: mct_PlatformSpec: Start
09.780: Programmed DCT 1 timing/termination pattern 00353935 30222222
09.780: mct_PlatformSpec: Done
09.780: ChangeMemClk: Done
09.780: phyAssistedMemFnceTraining: Start
09.780: phyAssistedMemFnceTraining: training node 3 DCT 0
09.781: phyAssistedMemFnceTraining: done training node 3 DCT 0
09.781: phyAssistedMemFnceTraining: training node 3 DCT 1
09.781: phyAssistedMemFnceTraining: done training node 3 DCT 1
09.781: phyAssistedMemFnceTraining: Done
09.781: InitPhyCompensation: DCT 0: Start
09.781: Waiting for predriver calibration to be applied...done!
09.781: InitPhyCompensation: DCT 0: Done
09.781: phyAssistedMemFnceTraining: Start
09.781: phyAssistedMemFnceTraining: training node 3 DCT 0
09.781: phyAssistedMemFnceTraining: done training node 3 DCT 0
09.781: phyAssistedMemFnceTraining: training node 3 DCT 1
09.781: phyAssistedMemFnceTraining: done training node 3 DCT 1
09.781: phyAssistedMemFnceTraining: Done
09.781: InitPhyCompensation: DCT 1: Start
09.781: Waiting for predriver calibration to be applied...done!
09.781: InitPhyCompensation: DCT 1: Done
09.781: Preparing to send DCT 0 DIMM 0 RC10: 03 (F2xA8: 02000300)
09.781: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.781: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
09.782: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.782: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
09.782: Preparing to send DCT 0 DIMM 1 RC10: 03 (F2xA8: 02000c00)
09.782: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.782: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
09.782: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
09.782: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
09.782: Preparing to send DCT 1 DIMM 0 RC10: 03 (F2xA8: 02000300)
09.782: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.782: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
09.782: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.782: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
09.782: Preparing to send DCT 1 DIMM 1 RC10: 03 (F2xA8: 02000c00)
09.782: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.782: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
09.782: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
09.782: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
09.782: SetTargetFreq: Done
09.782: SPD2ndTiming: Start
09.782: SPD2ndTiming: Done
09.782: mct_BeforeDramInit_Prod_D: Start
09.782: mct_ProgramODT_D: Start
09.782: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
09.782: mct_ProgramODT_D: Done
09.782: mct_BeforeDramInit_Prod_D: Done
09.782: mct_DramInit_Sw_D: Start
09.782: DIMM 0 RttWr: 1
09.782: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.782: mct_SendMrsCmd: Start
09.782: mct_SendMrsCmd: Done
09.782: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
09.782: mct_SendMrsCmd: Start
09.782: mct_SendMrsCmd: Done
09.782: DIMM 0 RttNom: 4
09.783: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.783: mct_SendMrsCmd: Start
09.783: mct_SendMrsCmd: Done
09.783: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001d78
09.783: mct_SendMrsCmd: Start
09.783: mct_SendMrsCmd: Done
09.783: DIMM 0 RttWr: 1
09.783: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.783: mct_SendMrsCmd: Start
09.783: mct_SendMrsCmd: Done
09.783: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
09.783: mct_SendMrsCmd: Start
09.783: mct_SendMrsCmd: Done
09.783: DIMM 0 RttNom: 4
09.783: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.783: mct_SendMrsCmd: Start
09.783: mct_SendMrsCmd: Done
09.783: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201d78
09.783: mct_SendMrsCmd: Start
09.783: mct_SendMrsCmd: Done
09.783: DIMM 1 RttWr: 1
09.783: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.783: mct_SendMrsCmd: Start
09.783: mct_SendMrsCmd: Done
09.783: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
09.783: mct_SendMrsCmd: Start
09.783: mct_SendMrsCmd: Done
09.783: DIMM 1 RttNom: 4
09.783: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.783: mct_SendMrsCmd: Start
09.783: mct_SendMrsCmd: Done
09.783: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401d78
09.783: mct_SendMrsCmd: Start
09.783: mct_SendMrsCmd: Done
09.783: DIMM 1 RttWr: 1
09.783: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.783: mct_SendMrsCmd: Start
09.783: mct_SendMrsCmd: Done
09.783: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
09.783: mct_SendMrsCmd: Start
09.783: mct_SendMrsCmd: Done
09.783: DIMM 1 RttNom: 4
09.783: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.783: mct_SendMrsCmd: Start
09.783: mct_SendMrsCmd: Done
09.783: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601d78
09.783: mct_SendMrsCmd: Start
09.783: mct_SendMrsCmd: Done
09.783: mct_DramInit_Sw_D: Done
09.783: AgesaHwWlPhase1: training nibble 0
09.783: DIMM 0 RttNom: 4
09.783: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.783: DIMM 0 RttWr: 1
09.783: DIMM 0 RttWr: 1
09.784: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.783: DIMM 0 RttWr: 1
09.783: DIMM 0 RttNom: 4
09.784: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.784: DIMM 0 RttNom: 4
09.784: DIMM 0 RttWr: 1
09.784: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.784: DIMM 0 RttWr: 1
09.784: DIMM 1 RttNom: 4
09.784: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.784: DIMM 0 RttNom: 4
09.784: DIMM 1 RttWr: 1
09.784: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.784: DIMM 0 RttWr: 1
09.784: DIMM 1 RttNom: 4
09.784: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.784: DIMM 0 RttNom: 4
09.784: DIMM 1 RttWr: 1
09.784: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.784: DIMM 0 RttWr: 1
09.784: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.784: <09>Lane 00 scaled delay: 006c
09.784: <09>Lane 00 new seed: 006c
09.784: <09>Lane 01 scaled delay: 0064
09.784: <09>Lane 01 new seed: 0064
09.784: <09>Lane 02 scaled delay: 005e
09.784: <09>Lane 02 new seed: 005e
09.784: <09>Lane 03 scaled delay: 0059
09.784: <09>Lane 03 new seed: 0059
09.784: <09>Lane 04 scaled delay: 0055
09.784: <09>Lane 04 new seed: 0055
09.784: <09>Lane 05 scaled delay: 005b
09.784: <09>Lane 05 new seed: 005b
09.784: <09>Lane 06 scaled delay: 0061
09.784: <09>Lane 06 new seed: 0061
09.784: <09>Lane 07 scaled delay: 0067
09.784: <09>Lane 07 new seed: 0067
09.784: <09>Lane 08 scaled delay: 0053
09.784: <09>Lane 08 new seed: 0053
09.784: <09>Lane 00 nibble 0 raw readback: 0030
09.784: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0070
09.784: <09>Lane 00 nibble 0 adjusted value (post nibble): 0070
09.784: <09>Lane 01 nibble 0 raw readback: 0023
09.784: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0063
09.784: <09>Lane 01 nibble 0 adjusted value (post nibble): 0063
09.784: <09>Lane 02 nibble 0 raw readback: 005c
09.784: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005c
09.784: <09>Lane 02 nibble 0 adjusted value (post nibble): 005c
09.784: <09>Lane 03 nibble 0 raw readback: 005e
09.784: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005e
09.784: <09>Lane 03 nibble 0 adjusted value (post nibble): 005e
09.784: <09>Lane 04 nibble 0 raw readback: 005a
09.784: <09>Lane 04 nibble 0 adjusted value (pre nibble): 005a
09.784: <09>Lane 04 nibble 0 adjusted value (post nibble): 005a
09.784: <09>Lane 05 nibble 0 raw readback: 0062
09.784: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0062
09.785: <09>Lane 05 nibble 0 adjusted value (post nibble): 0062
09.785: <09>Lane 06 nibble 0 raw readback: 0024
09.785: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0064
09.785: <09>Lane 06 nibble 0 adjusted value (post nibble): 0064
09.785: <09>Lane 07 nibble 0 raw readback: 0029
09.785: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0069
09.785: <09>Lane 07 nibble 0 adjusted value (post nibble): 0069
09.785: <09>Lane 08 nibble 0 raw readback: 0052
09.785: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0052
09.785: <09>Lane 08 nibble 0 adjusted value (post nibble): 0052
09.785: AgesaHwWlPhase1: training nibble 1
09.785: DIMM 0 RttNom: 4
09.785: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.785: DIMM 0 RttWr: 1
09.785: DIMM 0 RttWr: 1
09.785: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.785: DIMM 0 RttWr: 1
09.785: DIMM 0 RttNom: 4
09.785: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.785: DIMM 0 RttNom: 4
09.785: DIMM 0 RttWr: 1
09.785: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.785: DIMM 0 RttWr: 1
09.785: DIMM 1 RttNom: 4
09.785: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.785: DIMM 0 RttNom: 4
09.785: DIMM 1 RttWr: 1
09.785: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.785: DIMM 0 RttWr: 1
09.785: DIMM 1 RttNom: 4
09.785: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.785: DIMM 0 RttNom: 4
09.785: DIMM 1 RttWr: 1
09.785: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.785: DIMM 0 RttWr: 1
09.785: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
09.785: <09>Lane 00 new seed: 006c
09.785: <09>Lane 01 new seed: 0064
09.785: <09>Lane 02 new seed: 005e
09.785: <09>Lane 03 new seed: 0059
09.785: <09>Lane 04 new seed: 0055
09.785: <09>Lane 05 new seed: 005b
09.785: <09>Lane 06 new seed: 0061
09.785: <09>Lane 07 new seed: 0067
09.785: <09>Lane 08 new seed: 0053
09.785: <09>Lane 00 nibble 1 raw readback: 0033
09.785: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0073
09.785: <09>Lane 00 nibble 1 adjusted value (post nibble): 006f
09.785: <09>Lane 01 nibble 1 raw readback: 0029
09.785: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0069
09.785: <09>Lane 01 nibble 1 adjusted value (post nibble): 0066
09.785: <09>Lane 02 nibble 1 raw readback: 0061
09.785: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0061
09.785: <09>Lane 02 nibble 1 adjusted value (post nibble): 005f
09.785: <09>Lane 03 nibble 1 raw readback: 005b
09.785: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005b
09.785: <09>Lane 03 nibble 1 adjusted value (post nibble): 005a
09.785: <09>Lane 04 nibble 1 raw readback: 0059
09.785: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0059
09.785: <09>Lane 04 nibble 1 adjusted value (post nibble): 0057
09.785: <09>Lane 05 nibble 1 raw readback: 005e
09.785: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005e
09.785: <09>Lane 05 nibble 1 adjusted value (post nibble): 005c
09.785: <09>Lane 06 nibble 1 raw readback: 0027
09.785: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0067
09.785: <09>Lane 06 nibble 1 adjusted value (post nibble): 0064
09.785: <09>Lane 07 nibble 1 raw readback: 002e
09.785: <09>Lane 07 nibble 1 adjusted value (pre nibble): 006e
09.786: <09>Lane 07 nibble 1 adjusted value (post nibble): 006a
09.786: <09>Lane 08 nibble 1 raw readback: 0055
09.786: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0055
09.786: <09>Lane 08 nibble 1 adjusted value (post nibble): 0054
09.786: <09>original critical gross delay: 0
09.786: <09>new critical gross delay: 0
09.786: DIMM 0 RttNom: 4
09.786: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.786: DIMM 0 RttNom: 4
09.786: DIMM 0 RttWr: 1
09.786: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.786: DIMM 0 RttWr: 1
09.786: DIMM 0 RttNom: 4
09.786: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.786: DIMM 0 RttNom: 4
09.786: DIMM 0 RttWr: 1
09.786: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.786: DIMM 0 RttWr: 1
09.786: DIMM 1 RttNom: 4
09.786: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.786: DIMM 0 RttNom: 4
09.786: DIMM 1 RttWr: 1
09.786: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.786: DIMM 0 RttWr: 1
09.786: DIMM 1 RttNom: 4
09.786: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.786: DIMM 0 RttNom: 4
09.786: DIMM 1 RttWr: 1
09.786: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.786: DIMM 0 RttWr: 1
09.786: AgesaHwWlPhase1: training nibble 0
09.786: DIMM 1 RttNom: 4
09.786: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.786: DIMM 1 RttWr: 1
09.786: DIMM 1 RttWr: 1
09.786: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.786: DIMM 1 RttWr: 1
09.786: DIMM 1 RttNom: 4
09.786: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.786: DIMM 1 RttNom: 4
09.786: DIMM 1 RttWr: 1
09.786: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.786: DIMM 1 RttWr: 1
09.786: DIMM 0 RttNom: 4
09.786: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.786: DIMM 1 RttNom: 4
09.786: DIMM 0 RttWr: 1
09.786: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.786: DIMM 1 RttWr: 1
09.786: DIMM 0 RttNom: 4
09.786: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.786: DIMM 1 RttNom: 4
09.786: DIMM 0 RttWr: 1
09.787: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.786: DIMM 1 RttWr: 1
09.786: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.787: <09>Lane 00 scaled delay: 0069
09.786: <09>Lane 00 new seed: 0069
09.787: <09>Lane 01 scaled delay: 0060
09.787: <09>Lane 01 new seed: 0060
09.787: <09>Lane 02 scaled delay: 005a
09.787: <09>Lane 02 new seed: 005a
09.787: <09>Lane 03 scaled delay: 0059
09.787: <09>Lane 03 new seed: 0059
09.787: <09>Lane 04 scaled delay: 0052
09.787: <09>Lane 04 new seed: 0052
09.787: <09>Lane 05 scaled delay: 0059
09.787: <09>Lane 05 new seed: 0059
09.787: <09>Lane 06 scaled delay: 005a
09.787: <09>Lane 06 new seed: 005a
09.787: <09>Lane 07 scaled delay: 0063
09.787: <09>Lane 07 new seed: 0063
09.787: <09>Lane 08 scaled delay: 004e
09.787: <09>Lane 08 new seed: 004e
09.787: <09>Lane 00 nibble 0 raw readback: 002e
09.787: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006e
09.787: <09>Lane 00 nibble 0 adjusted value (post nibble): 006e
09.787: <09>Lane 01 nibble 0 raw readback: 0024
09.787: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0064
09.787: <09>Lane 01 nibble 0 adjusted value (post nibble): 0064
09.787: <09>Lane 02 nibble 0 raw readback: 005c
09.787: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005c
09.787: <09>Lane 02 nibble 0 adjusted value (post nibble): 005c
09.787: <09>Lane 03 nibble 0 raw readback: 005c
09.787: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005c
09.787: <09>Lane 03 nibble 0 adjusted value (post nibble): 005c
09.787: <09>Lane 04 nibble 0 raw readback: 0055
09.787: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0055
09.787: <09>Lane 04 nibble 0 adjusted value (post nibble): 0055
09.787: <09>Lane 05 nibble 0 raw readback: 005c
09.787: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005c
09.787: <09>Lane 05 nibble 0 adjusted value (post nibble): 005c
09.787: <09>Lane 06 nibble 0 raw readback: 005f
09.787: <09>Lane 06 nibble 0 adjusted value (pre nibble): 005f
09.787: <09>Lane 06 nibble 0 adjusted value (post nibble): 005f
09.787: <09>Lane 07 nibble 0 raw readback: 0028
09.787: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0068
09.787: <09>Lane 07 nibble 0 adjusted value (post nibble): 0068
09.787: <09>Lane 08 nibble 0 raw readback: 004f
09.787: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004f
09.787: <09>Lane 08 nibble 0 adjusted value (post nibble): 004f
09.787: AgesaHwWlPhase1: training nibble 1
09.787: DIMM 1 RttNom: 4
09.787: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.787: DIMM 1 RttWr: 1
09.787: DIMM 1 RttWr: 1
09.787: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.787: DIMM 1 RttWr: 1
09.787: DIMM 1 RttNom: 4
09.787: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.787: DIMM 1 RttNom: 4
09.787: DIMM 1 RttWr: 1
09.787: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.787: DIMM 1 RttWr: 1
09.787: DIMM 0 RttNom: 4
09.787: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.787: DIMM 1 RttNom: 4
09.787: DIMM 0 RttWr: 1
09.787: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.787: DIMM 1 RttWr: 1
09.787: DIMM 0 RttNom: 4
09.787: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.787: DIMM 1 RttNom: 4
09.787: DIMM 0 RttWr: 1
09.787: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.787: DIMM 1 RttWr: 1
09.787: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
09.787: <09>Lane 00 new seed: 0069
09.787: <09>Lane 01 new seed: 0060
09.787: <09>Lane 02 new seed: 005a
09.788: <09>Lane 03 new seed: 0059
09.788: <09>Lane 04 new seed: 0052
09.788: <09>Lane 05 new seed: 0059
09.788: <09>Lane 06 new seed: 005a
09.788: <09>Lane 07 new seed: 0063
09.788: <09>Lane 08 new seed: 004e
09.788: <09>Lane 00 nibble 1 raw readback: 002e
09.788: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006e
09.788: <09>Lane 00 nibble 1 adjusted value (post nibble): 006b
09.788: <09>Lane 01 nibble 1 raw readback: 0025
09.788: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0065
09.788: <09>Lane 01 nibble 1 adjusted value (post nibble): 0062
09.788: <09>Lane 02 nibble 1 raw readback: 005d
09.788: <09>Lane 02 nibble 1 adjusted value (pre nibble): 005d
09.788: <09>Lane 02 nibble 1 adjusted value (post nibble): 005b
09.788: <09>Lane 03 nibble 1 raw readback: 005b
09.788: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005b
09.788: <09>Lane 03 nibble 1 adjusted value (post nibble): 005a
09.788: <09>Lane 04 nibble 1 raw readback: 0054
09.788: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0054
09.788: <09>Lane 04 nibble 1 adjusted value (post nibble): 0053
09.788: <09>Lane 05 nibble 1 raw readback: 005c
09.788: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005c
09.788: <09>Lane 05 nibble 1 adjusted value (post nibble): 005a
09.788: <09>Lane 06 nibble 1 raw readback: 005d
09.788: <09>Lane 06 nibble 1 adjusted value (pre nibble): 005d
09.788: <09>Lane 06 nibble 1 adjusted value (post nibble): 005b
09.788: <09>Lane 07 nibble 1 raw readback: 0027
09.788: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0067
09.788: <09>Lane 07 nibble 1 adjusted value (post nibble): 0065
09.788: <09>Lane 08 nibble 1 raw readback: 0050
09.788: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0050
09.788: <09>Lane 08 nibble 1 adjusted value (post nibble): 004f
09.788: <09>original critical gross delay: 0
09.788: <09>new critical gross delay: 0
09.788: DIMM 1 RttNom: 4
09.788: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
09.788: DIMM 1 RttNom: 4
09.788: DIMM 1 RttWr: 1
09.788: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
09.788: DIMM 1 RttWr: 1
09.788: DIMM 1 RttNom: 4
09.788: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
09.788: DIMM 1 RttNom: 4
09.788: DIMM 1 RttWr: 1
09.788: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
09.788: DIMM 1 RttWr: 1
09.788: DIMM 0 RttNom: 4
09.788: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
09.788: DIMM 1 RttNom: 4
09.788: DIMM 0 RttWr: 1
09.788: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
09.788: DIMM 1 RttWr: 1
09.788: DIMM 0 RttNom: 4
09.788: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
09.788: DIMM 1 RttNom: 4
09.788: DIMM 0 RttWr: 1
09.788: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
09.788: DIMM 1 RttWr: 1
09.788: SPD2ndTiming: Start
09.789: SPD2ndTiming: Done
09.789: mct_BeforeDramInit_Prod_D: Start
09.789: mct_ProgramODT_D: Start
09.789: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
09.789: mct_ProgramODT_D: Done
09.789: mct_BeforeDramInit_Prod_D: Done
09.789: mct_DramInit_Sw_D: Start
09.789: DIMM 0 RttWr: 1
09.789: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.789: mct_SendMrsCmd: Start
09.789: mct_SendMrsCmd: Done
09.789: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
09.789: mct_SendMrsCmd: Start
09.789: mct_SendMrsCmd: Done
09.789: DIMM 0 RttNom: 4
09.789: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.789: mct_SendMrsCmd: Start
09.789: mct_SendMrsCmd: Done
09.789: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001d78
09.789: mct_SendMrsCmd: Start
09.789: mct_SendMrsCmd: Done
09.789: DIMM 0 RttWr: 1
09.789: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.789: mct_SendMrsCmd: Start
09.789: mct_SendMrsCmd: Done
09.789: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
09.789: mct_SendMrsCmd: Start
09.789: mct_SendMrsCmd: Done
09.789: DIMM 0 RttNom: 4
09.789: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.789: mct_SendMrsCmd: Start
09.789: mct_SendMrsCmd: Done
09.789: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201d78
09.789: mct_SendMrsCmd: Start
09.789: mct_SendMrsCmd: Done
09.789: DIMM 1 RttWr: 1
09.789: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.789: mct_SendMrsCmd: Start
09.789: mct_SendMrsCmd: Done
09.790: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
09.789: mct_SendMrsCmd: Start
09.790: mct_SendMrsCmd: Done
09.790: DIMM 1 RttNom: 4
09.790: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.790: mct_SendMrsCmd: Start
09.790: mct_SendMrsCmd: Done
09.790: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401d78
09.790: mct_SendMrsCmd: Start
09.790: mct_SendMrsCmd: Done
09.790: DIMM 1 RttWr: 1
09.790: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.790: mct_SendMrsCmd: Start
09.790: mct_SendMrsCmd: Done
09.790: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
09.790: mct_SendMrsCmd: Start
09.790: mct_SendMrsCmd: Done
09.790: DIMM 1 RttNom: 4
09.790: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.790: mct_SendMrsCmd: Start
09.790: mct_SendMrsCmd: Done
09.790: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601d78
09.790: mct_SendMrsCmd: Start
09.790: mct_SendMrsCmd: Done
09.790: mct_DramInit_Sw_D: Done
09.790: AgesaHwWlPhase1: training nibble 0
09.790: DIMM 0 RttNom: 4
09.790: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.790: DIMM 0 RttWr: 1
09.790: DIMM 0 RttWr: 1
09.790: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.790: DIMM 0 RttWr: 1
09.790: DIMM 0 RttNom: 4
09.790: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.790: DIMM 0 RttNom: 4
09.790: DIMM 0 RttWr: 1
09.790: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.790: DIMM 0 RttWr: 1
09.790: DIMM 1 RttNom: 4
09.790: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.790: DIMM 0 RttNom: 4
09.790: DIMM 1 RttWr: 1
09.790: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.790: DIMM 0 RttWr: 1
09.790: DIMM 1 RttNom: 4
09.790: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.790: DIMM 0 RttNom: 4
09.790: DIMM 1 RttWr: 1
09.790: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.790: DIMM 0 RttWr: 1
09.790: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.790: <09>Lane 00 scaled delay: 006d
09.790: <09>Lane 00 new seed: 006d
09.790: <09>Lane 01 scaled delay: 0067
09.790: <09>Lane 01 new seed: 0067
09.790: <09>Lane 02 scaled delay: 0061
09.790: <09>Lane 02 new seed: 0061
09.790: <09>Lane 03 scaled delay: 0059
09.790: <09>Lane 03 new seed: 0059
09.790: <09>Lane 04 scaled delay: 0055
09.790: <09>Lane 04 new seed: 0055
09.790: <09>Lane 05 scaled delay: 005e
09.790: <09>Lane 05 new seed: 005e
09.790: <09>Lane 06 scaled delay: 0064
09.791: <09>Lane 06 new seed: 0064
09.791: <09>Lane 07 scaled delay: 006a
09.791: <09>Lane 07 new seed: 006a
09.791: <09>Lane 08 scaled delay: 0054
09.791: <09>Lane 08 new seed: 0054
09.791: <09>Lane 00 nibble 0 raw readback: 002f
09.791: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006f
09.791: <09>Lane 00 nibble 0 adjusted value (post nibble): 006f
09.791: <09>Lane 01 nibble 0 raw readback: 0027
09.791: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0067
09.791: <09>Lane 01 nibble 0 adjusted value (post nibble): 0067
09.791: <09>Lane 02 nibble 0 raw readback: 0020
09.791: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0060
09.791: <09>Lane 02 nibble 0 adjusted value (post nibble): 0060
09.791: <09>Lane 03 nibble 0 raw readback: 0059
09.791: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0059
09.791: <09>Lane 03 nibble 0 adjusted value (post nibble): 0059
09.791: <09>Lane 04 nibble 0 raw readback: 0057
09.791: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0057
09.791: <09>Lane 04 nibble 0 adjusted value (post nibble): 0057
09.791: <09>Lane 05 nibble 0 raw readback: 0061
09.791: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0061
09.791: <09>Lane 05 nibble 0 adjusted value (post nibble): 0061
09.791: <09>Lane 06 nibble 0 raw readback: 0027
09.791: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0067
09.791: <09>Lane 06 nibble 0 adjusted value (post nibble): 0067
09.791: <09>Lane 07 nibble 0 raw readback: 002e
09.791: <09>Lane 07 nibble 0 adjusted value (pre nibble): 006e
09.791: <09>Lane 07 nibble 0 adjusted value (post nibble): 006e
09.791: <09>Lane 08 nibble 0 raw readback: 0053
09.791: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0053
09.791: <09>Lane 08 nibble 0 adjusted value (post nibble): 0053
09.791: AgesaHwWlPhase1: training nibble 1
09.791: DIMM 0 RttNom: 4
09.791: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.791: DIMM 0 RttWr: 1
09.791: DIMM 0 RttWr: 1
09.791: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.791: DIMM 0 RttWr: 1
09.791: DIMM 0 RttNom: 4
09.791: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.791: DIMM 0 RttNom: 4
09.791: DIMM 0 RttWr: 1
09.791: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.791: DIMM 0 RttWr: 1
09.791: DIMM 1 RttNom: 4
09.791: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.791: DIMM 0 RttNom: 4
09.791: DIMM 1 RttWr: 1
09.791: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.791: DIMM 0 RttWr: 1
09.791: DIMM 1 RttNom: 4
09.791: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.791: DIMM 0 RttNom: 4
09.791: DIMM 1 RttWr: 1
09.791: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.791: DIMM 0 RttWr: 1
09.791: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
09.791: <09>Lane 00 new seed: 006d
09.792: <09>Lane 01 new seed: 0067
09.792: <09>Lane 02 new seed: 0061
09.792: <09>Lane 03 new seed: 0059
09.792: <09>Lane 04 new seed: 0055
09.792: <09>Lane 05 new seed: 005e
09.792: <09>Lane 06 new seed: 0064
09.792: <09>Lane 07 new seed: 006a
09.792: <09>Lane 08 new seed: 0054
09.792: <09>Lane 00 nibble 1 raw readback: 0030
09.792: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0070
09.792: <09>Lane 00 nibble 1 adjusted value (post nibble): 006e
09.792: <09>Lane 01 nibble 1 raw readback: 002a
09.792: <09>Lane 01 nibble 1 adjusted value (pre nibble): 006a
09.792: <09>Lane 01 nibble 1 adjusted value (post nibble): 0068
09.792: <09>Lane 02 nibble 1 raw readback: 0022
09.792: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0062
09.792: <09>Lane 02 nibble 1 adjusted value (post nibble): 0061
09.792: <09>Lane 03 nibble 1 raw readback: 005b
09.792: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005b
09.792: <09>Lane 03 nibble 1 adjusted value (post nibble): 005a
09.792: <09>Lane 04 nibble 1 raw readback: 0056
09.792: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0056
09.792: <09>Lane 04 nibble 1 adjusted value (post nibble): 0055
09.792: <09>Lane 05 nibble 1 raw readback: 005f
09.792: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005f
09.792: <09>Lane 05 nibble 1 adjusted value (post nibble): 005e
09.792: <09>Lane 06 nibble 1 raw readback: 0026
09.792: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0066
09.792: <09>Lane 06 nibble 1 adjusted value (post nibble): 0065
09.792: <09>Lane 07 nibble 1 raw readback: 002e
09.792: <09>Lane 07 nibble 1 adjusted value (pre nibble): 006e
09.792: <09>Lane 07 nibble 1 adjusted value (post nibble): 006c
09.792: <09>Lane 08 nibble 1 raw readback: 0055
09.792: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0055
09.792: <09>Lane 08 nibble 1 adjusted value (post nibble): 0054
09.792: <09>original critical gross delay: 0
09.792: <09>new critical gross delay: 0
09.792: DIMM 0 RttNom: 4
09.792: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.792: DIMM 0 RttNom: 4
09.792: DIMM 0 RttWr: 1
09.792: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.792: DIMM 0 RttWr: 1
09.792: DIMM 0 RttNom: 4
09.792: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.792: DIMM 0 RttNom: 4
09.792: DIMM 0 RttWr: 1
09.792: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.792: DIMM 0 RttWr: 1
09.792: DIMM 1 RttNom: 4
09.792: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.792: DIMM 0 RttNom: 4
09.792: DIMM 1 RttWr: 1
09.792: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.792: DIMM 0 RttWr: 1
09.792: DIMM 1 RttNom: 4
09.792: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.792: DIMM 0 RttNom: 4
09.792: DIMM 1 RttWr: 1
09.792: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.792: DIMM 0 RttWr: 1
09.792: AgesaHwWlPhase1: training nibble 0
09.792: DIMM 1 RttNom: 4
09.793: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.793: DIMM 1 RttWr: 1
09.793: DIMM 1 RttWr: 1
09.793: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.793: DIMM 1 RttWr: 1
09.793: DIMM 1 RttNom: 4
09.793: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.793: DIMM 1 RttNom: 4
09.793: DIMM 1 RttWr: 1
09.793: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.793: DIMM 1 RttWr: 1
09.793: DIMM 0 RttNom: 4
09.793: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.793: DIMM 1 RttNom: 4
09.793: DIMM 0 RttWr: 1
09.793: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.793: DIMM 1 RttWr: 1
09.793: DIMM 0 RttNom: 4
09.793: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.793: DIMM 1 RttNom: 4
09.793: DIMM 0 RttWr: 1
09.793: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.793: DIMM 1 RttWr: 1
09.793: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.793: <09>Lane 00 scaled delay: 006b
09.793: <09>Lane 00 new seed: 006b
09.793: <09>Lane 01 scaled delay: 0064
09.793: <09>Lane 01 new seed: 0064
09.793: <09>Lane 02 scaled delay: 005b
09.793: <09>Lane 02 new seed: 005b
09.793: <09>Lane 03 scaled delay: 0059
09.793: <09>Lane 03 new seed: 0059
09.793: <09>Lane 04 scaled delay: 0053
09.793: <09>Lane 04 new seed: 0053
09.793: <09>Lane 05 scaled delay: 005b
09.793: <09>Lane 05 new seed: 005b
09.793: <09>Lane 06 scaled delay: 0063
09.793: <09>Lane 06 new seed: 0063
09.793: <09>Lane 07 scaled delay: 0069
09.793: <09>Lane 07 new seed: 0069
09.793: <09>Lane 08 scaled delay: 004f
09.793: <09>Lane 08 new seed: 004f
09.793: <09>Lane 00 nibble 0 raw readback: 002d
09.793: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006d
09.793: <09>Lane 00 nibble 0 adjusted value (post nibble): 006d
09.793: <09>Lane 01 nibble 0 raw readback: 0025
09.793: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0065
09.793: <09>Lane 01 nibble 0 adjusted value (post nibble): 0065
09.793: <09>Lane 02 nibble 0 raw readback: 005b
09.793: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005b
09.793: <09>Lane 02 nibble 0 adjusted value (post nibble): 005b
09.793: <09>Lane 03 nibble 0 raw readback: 0057
09.793: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0057
09.793: <09>Lane 03 nibble 0 adjusted value (post nibble): 0057
09.793: <09>Lane 04 nibble 0 raw readback: 0054
09.793: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0054
09.793: <09>Lane 04 nibble 0 adjusted value (post nibble): 0054
09.793: <09>Lane 05 nibble 0 raw readback: 005e
09.793: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005e
09.793: <09>Lane 05 nibble 0 adjusted value (post nibble): 005e
09.793: <09>Lane 06 nibble 0 raw readback: 0025
09.793: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0065
09.793: <09>Lane 06 nibble 0 adjusted value (post nibble): 0065
09.793: <09>Lane 07 nibble 0 raw readback: 002b
09.793: <09>Lane 07 nibble 0 adjusted value (pre nibble): 006b
09.793: <09>Lane 07 nibble 0 adjusted value (post nibble): 006b
09.793: <09>Lane 08 nibble 0 raw readback: 0053
09.793: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0053
09.793: <09>Lane 08 nibble 0 adjusted value (post nibble): 0053
09.793: AgesaHwWlPhase1: training nibble 1
09.793: DIMM 1 RttNom: 4
09.793: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.793: DIMM 1 RttWr: 1
09.794: DIMM 1 RttWr: 1
09.794: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.794: DIMM 1 RttWr: 1
09.794: DIMM 1 RttNom: 4
09.794: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.794: DIMM 1 RttNom: 4
09.794: DIMM 1 RttWr: 1
09.794: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.794: DIMM 1 RttWr: 1
09.794: DIMM 0 RttNom: 4
09.794: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.794: DIMM 1 RttNom: 4
09.794: DIMM 0 RttWr: 1
09.794: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.794: DIMM 1 RttWr: 1
09.794: DIMM 0 RttNom: 4
09.794: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.794: DIMM 1 RttNom: 4
09.794: DIMM 0 RttWr: 1
09.794: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.794: DIMM 1 RttWr: 1
09.794: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
09.794: <09>Lane 00 new seed: 006b
09.794: <09>Lane 01 new seed: 0064
09.794: <09>Lane 02 new seed: 005b
09.794: <09>Lane 03 new seed: 0059
09.794: <09>Lane 04 new seed: 0053
09.794: <09>Lane 05 new seed: 005b
09.794: <09>Lane 06 new seed: 0063
09.794: <09>Lane 07 new seed: 0069
09.794: <09>Lane 08 new seed: 004f
09.794: <09>Lane 00 nibble 1 raw readback: 002e
09.794: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006e
09.794: <09>Lane 00 nibble 1 adjusted value (post nibble): 006c
09.794: <09>Lane 01 nibble 1 raw readback: 0028
09.794: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0068
09.794: <09>Lane 01 nibble 1 adjusted value (post nibble): 0066
09.794: <09>Lane 02 nibble 1 raw readback: 005c
09.794: <09>Lane 02 nibble 1 adjusted value (pre nibble): 005c
09.794: <09>Lane 02 nibble 1 adjusted value (post nibble): 005b
09.794: <09>Lane 03 nibble 1 raw readback: 0059
09.794: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0059
09.794: <09>Lane 03 nibble 1 adjusted value (post nibble): 0059
09.794: <09>Lane 04 nibble 1 raw readback: 0054
09.794: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0054
09.794: <09>Lane 04 nibble 1 adjusted value (post nibble): 0053
09.794: <09>Lane 05 nibble 1 raw readback: 005d
09.794: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005d
09.794: <09>Lane 05 nibble 1 adjusted value (post nibble): 005c
09.794: <09>Lane 06 nibble 1 raw readback: 0026
09.794: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0066
09.794: <09>Lane 06 nibble 1 adjusted value (post nibble): 0064
09.794: <09>Lane 07 nibble 1 raw readback: 002b
09.794: <09>Lane 07 nibble 1 adjusted value (pre nibble): 006b
09.794: <09>Lane 07 nibble 1 adjusted value (post nibble): 006a
09.794: <09>Lane 08 nibble 1 raw readback: 0051
09.794: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0051
09.794: <09>Lane 08 nibble 1 adjusted value (post nibble): 0050
09.794: <09>original critical gross delay: 0
09.794: <09>new critical gross delay: 0
09.794: DIMM 1 RttNom: 4
09.794: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
09.794: DIMM 1 RttNom: 4
09.795: DIMM 1 RttWr: 1
09.794: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
09.794: DIMM 1 RttWr: 1
09.795: DIMM 1 RttNom: 4
09.795: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
09.795: DIMM 1 RttNom: 4
09.795: DIMM 1 RttWr: 1
09.795: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
09.795: DIMM 1 RttWr: 1
09.795: DIMM 0 RttNom: 4
09.795: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
09.795: DIMM 1 RttNom: 4
09.795: DIMM 0 RttWr: 1
09.795: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
09.795: DIMM 1 RttWr: 1
09.795: DIMM 0 RttNom: 4
09.795: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
09.795: DIMM 1 RttNom: 4
09.795: DIMM 0 RttWr: 1
09.795: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
09.795: DIMM 1 RttWr: 1
09.796: fam15_receiver_enable_training_seed: using seed: 0054
09.796: fam15_receiver_enable_training_seed: using seed: 0054
09.796: fam15_receiver_enable_training_seed: using seed: 0054
09.796: fam15_receiver_enable_training_seed: using seed: 0054
09.796: fam15_receiver_enable_training_seed: using seed: 0054
09.796: fam15_receiver_enable_training_seed: using seed: 0054
09.796: fam15_receiver_enable_training_seed: using seed: 0054
09.796: fam15_receiver_enable_training_seed: using seed: 0054
09.796: fam15_receiver_enable_training_seed: using seed: 004d
09.796: fam15_receiver_enable_training_seed: using seed: 004d
09.797: fam15_receiver_enable_training_seed: using seed: 004d
09.797: fam15_receiver_enable_training_seed: using seed: 004d
09.797: fam15_receiver_enable_training_seed: using seed: 004d
09.797: fam15_receiver_enable_training_seed: using seed: 004d
09.797: fam15_receiver_enable_training_seed: using seed: 004d
09.797: fam15_receiver_enable_training_seed: using seed: 004d
09.797: TrainRcvrEn: Status 2205
09.797: TrainRcvrEn: ErrStatus 0
09.797: TrainRcvrEn: ErrCode 0
09.797: TrainRcvrEn: Done
09.797: 
09.797: fam15_receiver_enable_training_seed: using seed: 0045
09.797: fam15_receiver_enable_training_seed: using seed: 0045
09.797: fam15_receiver_enable_training_seed: using seed: 0045
09.797: fam15_receiver_enable_training_seed: using seed: 0045
09.798: fam15_receiver_enable_training_seed: using seed: 0045
09.798: fam15_receiver_enable_training_seed: using seed: 0045
09.798: fam15_receiver_enable_training_seed: using seed: 0045
09.798: fam15_receiver_enable_training_seed: using seed: 0045
09.798: fam15_receiver_enable_training_seed: using seed: 0040
09.798: fam15_receiver_enable_training_seed: using seed: 0040
09.798: fam15_receiver_enable_training_seed: using seed: 0040
09.798: fam15_receiver_enable_training_seed: using seed: 0040
09.798: fam15_receiver_enable_training_seed: using seed: 0040
09.798: fam15_receiver_enable_training_seed: using seed: 0040
09.798: fam15_receiver_enable_training_seed: using seed: 0040
09.798: fam15_receiver_enable_training_seed: using seed: 0040
09.799: TrainRcvrEn: Status 2005
09.799: TrainRcvrEn: ErrStatus 0
09.799: TrainRcvrEn: ErrCode 0
09.799: TrainRcvrEn: Done
09.799: 
09.799: fam15_receiver_enable_training_seed: using seed: 0054
09.799: fam15_receiver_enable_training_seed: using seed: 0054
09.799: fam15_receiver_enable_training_seed: using seed: 0054
09.799: fam15_receiver_enable_training_seed: using seed: 0054
09.799: fam15_receiver_enable_training_seed: using seed: 0054
09.799: fam15_receiver_enable_training_seed: using seed: 0054
09.799: fam15_receiver_enable_training_seed: using seed: 0054
09.799: fam15_receiver_enable_training_seed: using seed: 0054
09.800: fam15_receiver_enable_training_seed: using seed: 004d
09.800: fam15_receiver_enable_training_seed: using seed: 004d
09.800: fam15_receiver_enable_training_seed: using seed: 004d
09.800: fam15_receiver_enable_training_seed: using seed: 004d
09.800: fam15_receiver_enable_training_seed: using seed: 004d
09.800: fam15_receiver_enable_training_seed: using seed: 004d
09.800: fam15_receiver_enable_training_seed: using seed: 004d
09.800: fam15_receiver_enable_training_seed: using seed: 004d
09.800: TrainRcvrEn: Status 2005
09.800: TrainRcvrEn: ErrStatus 0
09.800: TrainRcvrEn: ErrCode 0
09.800: TrainRcvrEn: Done
09.800: 
09.800: fam15_receiver_enable_training_seed: using seed: 0045
09.801: fam15_receiver_enable_training_seed: using seed: 0045
09.801: fam15_receiver_enable_training_seed: using seed: 0045
09.801: fam15_receiver_enable_training_seed: using seed: 0045
09.801: fam15_receiver_enable_training_seed: using seed: 0045
09.801: fam15_receiver_enable_training_seed: using seed: 0045
09.801: fam15_receiver_enable_training_seed: using seed: 0045
09.801: fam15_receiver_enable_training_seed: using seed: 0045
09.801: fam15_receiver_enable_training_seed: using seed: 0040
09.801: fam15_receiver_enable_training_seed: using seed: 0040
09.801: fam15_receiver_enable_training_seed: using seed: 0040
09.801: fam15_receiver_enable_training_seed: using seed: 0040
09.802: fam15_receiver_enable_training_seed: using seed: 0040
09.802: fam15_receiver_enable_training_seed: using seed: 0040
09.802: fam15_receiver_enable_training_seed: using seed: 0040
09.802: fam15_receiver_enable_training_seed: using seed: 0040
09.802: TrainRcvrEn: Status 2005
09.802: TrainRcvrEn: ErrStatus 0
09.802: TrainRcvrEn: ErrCode 0
09.802: TrainRcvrEn: Done
09.802: 
19.758: TrainDQSReceiverEnCyc: Status 2205
19.758: TrainDQSReceiverEnCyc: TrainErrors 4000
19.758: TrainDQSReceiverEnCyc: ErrStatus 4000
19.758: TrainDQSReceiverEnCyc: ErrCode 0
19.758: TrainDQSReceiverEnCyc: Done
19.758: 
30.849: TrainDQSReceiverEnCyc: Status 2005
30.849: TrainDQSReceiverEnCyc: TrainErrors 4000
30.849: TrainDQSReceiverEnCyc: ErrStatus 4000
30.849: TrainDQSReceiverEnCyc: ErrCode 0
30.849: TrainDQSReceiverEnCyc: Done
30.849: 
44.196: TrainDQSReceiverEnCyc: Status 2005
44.196: TrainDQSReceiverEnCyc: TrainErrors 4000
44.196: TrainDQSReceiverEnCyc: ErrStatus 4000
44.196: TrainDQSReceiverEnCyc: ErrCode 0
44.196: TrainDQSReceiverEnCyc: Done
44.196: 
56.920: TrainDQSReceiverEnCyc: Status 2005
56.920: TrainDQSReceiverEnCyc: TrainErrors 4000
56.919: TrainDQSReceiverEnCyc: ErrStatus 4000
56.920: TrainDQSReceiverEnCyc: ErrCode 0
56.920: TrainDQSReceiverEnCyc: Done
56.920: 
56.920: TrainMaxRdLatency: Status 2205
56.921: TrainMaxRdLatency: ErrStatus 4000
56.921: TrainMaxRdLatency: ErrCode 0
56.921: TrainMaxRdLatency: Done
56.921: 
56.921: TrainMaxRdLatency: Status 2005
56.921: TrainMaxRdLatency: ErrStatus 4000
56.921: TrainMaxRdLatency: ErrCode 0
56.921: TrainMaxRdLatency: Done
56.921: 
56.922: TrainMaxRdLatency: Status 2005
56.922: TrainMaxRdLatency: ErrStatus 4000
56.922: TrainMaxRdLatency: ErrCode 0
56.922: TrainMaxRdLatency: Done
56.922: 
56.923: TrainMaxRdLatency: Status 2005
56.923: TrainMaxRdLatency: ErrStatus 4000
56.923: TrainMaxRdLatency: ErrCode 0
56.923: TrainMaxRdLatency: Done
56.923: 
56.924: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
56.924: CBFS: Locating 'cmos_layout.bin'
56.924: CBFS: Found @ offset 2b0c0 size e88
56.925: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
56.925: CBFS: Locating 'cmos_layout.bin'
56.925: CBFS: Found @ offset 2b0c0 size e88
56.926: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
56.926: CBFS: Locating 'cmos_layout.bin'
56.926: CBFS: Found @ offset 2b0c0 size e88
56.926: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
56.926: CBFS: Locating 'cmos_layout.bin'
56.926: CBFS: Found @ offset 2b0c0 size e88
56.926: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
56.926: CBFS: Locating 'cmos_layout.bin'
56.926: CBFS: Found @ offset 2b0c0 size e88
56.927: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
56.927: CBFS: Locating 'cmos_layout.bin'
56.927: CBFS: Found @ offset 2b0c0 size e88
56.927: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
56.927: CBFS: Locating 'cmos_layout.bin'
56.927: CBFS: Found @ offset 2b0c0 size e88
56.927: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
56.927: CBFS: Locating 'cmos_layout.bin'
56.927: CBFS: Found @ offset 2b0c0 size e88
56.928: mctAutoInitMCT_D: :OtherTiming
56.929: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
56.929: CBFS: Locating 'cmos_layout.bin'
56.929: CBFS: Found @ offset 2b0c0 size e88
56.929: InterleaveNodes_D: Status 2205
56.929: InterleaveNodes_D: ErrStatus 4000
56.929: InterleaveNodes_D: ErrCode 0
56.929: InterleaveNodes_D: Done
56.929: 
56.929: InterleaveChannels_D: Node 0
56.929: InterleaveChannels_D: Status 2205
56.929: InterleaveChannels_D: ErrStatus 4000
56.929: InterleaveChannels_D: ErrCode 0
56.930: InterleaveChannels_D: Node 1
56.930: InterleaveChannels_D: Status 2005
56.930: InterleaveChannels_D: ErrStatus 4000
56.930: InterleaveChannels_D: ErrCode 0
56.930: InterleaveChannels_D: Node 2
56.930: InterleaveChannels_D: Status 2005
56.930: InterleaveChannels_D: ErrStatus 4000
56.930: InterleaveChannels_D: ErrCode 0
56.930: InterleaveChannels_D: Node 3
56.930: InterleaveChannels_D: Status 2005
56.930: InterleaveChannels_D: ErrStatus 4000
56.930: InterleaveChannels_D: ErrCode 0
56.930: InterleaveChannels_D: Node 4
56.930: InterleaveChannels_D: Status 2000
56.930: InterleaveChannels_D: ErrStatus 0
56.930: InterleaveChannels_D: ErrCode 0
56.930: InterleaveChannels_D: Node 5
56.930: InterleaveChannels_D: Status 2000
56.930: InterleaveChannels_D: ErrStatus 0
56.930: InterleaveChannels_D: ErrCode 0
56.930: InterleaveChannels_D: Node 6
56.930: InterleaveChannels_D: Status 2000
56.930: InterleaveChannels_D: ErrStatus 0
56.930: InterleaveChannels_D: ErrCode 0
56.930: InterleaveChannels_D: Node 7
56.930: InterleaveChannels_D: Status 2000
56.930: InterleaveChannels_D: ErrStatus 0
56.930: InterleaveChannels_D: ErrCode 0
56.930: InterleaveChannels_D: Done
56.930: 
56.930: mctAutoInitMCT_D: ECCInit_D
56.930: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
56.930: CBFS: Locating 'cmos_layout.bin'
56.930: CBFS: Found @ offset 2b0c0 size e88
56.931: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
56.931: CBFS: Locating 'cmos_layout.bin'
56.931: CBFS: Found @ offset 2b0c0 size e88
56.931:   ECC enabled on node: 00
56.931: DCTMemClr_Sync_D: Start
56.931: DCTMemClr_Sync_D: Waiting for memory clear to complete................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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57.910: .
57.910: DCTMemClr_Sync_D: Done
57.910:   ECC enabled on node: 01
57.910: DCTMemClr_Sync_D: Start
57.910: DCTMemClr_Sync_D: Waiting for memory clear to complete................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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58.889: .
58.889: DCTMemClr_Sync_D: Done
58.889:   ECC enabled on node: 02
58.889: DCTMemClr_Sync_D: Start
58.889: DCTMemClr_Sync_D: Waiting for memory clear to complete................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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59.868: .
59.868: DCTMemClr_Sync_D: Done
59.868:   ECC enabled on node: 03
59.868: DCTMemClr_Sync_D: Start
59.868: DCTMemClr_Sync_D: Waiting for memory clear to complete................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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60.847: .
60.847: DCTMemClr_Sync_D: Done
60.847: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
60.847: CBFS: Locating 'cmos_layout.bin'
60.847: CBFS: Found @ offset 2b0c0 size e88
60.847: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
60.847: CBFS: Locating 'cmos_layout.bin'
60.847: CBFS: Found @ offset 2b0c0 size e88
60.848: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
60.847: CBFS: Locating 'cmos_layout.bin'
60.848: CBFS: Found @ offset 2b0c0 size e88
60.848: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
60.848: CBFS: Locating 'cmos_layout.bin'
60.848: CBFS: Found @ offset 2b0c0 size e88
60.848: ECCInit: Node 00
60.848: ECCInit: Status 2205
60.848: ECCInit: ErrStatus 4000
60.848: ECCInit: ErrCode 0
60.848: ECCInit: Done
60.848: ECCInit: Node 01
60.848: ECCInit: Status 2005
60.848: ECCInit: ErrStatus 4000
60.848: ECCInit: ErrCode 0
60.848: ECCInit: Done
60.848: ECCInit: Node 02
60.848: ECCInit: Status 2005
60.848: ECCInit: ErrStatus 4000
60.848: ECCInit: ErrCode 0
60.848: ECCInit: Done
60.848: ECCInit: Node 03
60.848: ECCInit: Status 2005
60.848: ECCInit: ErrStatus 4000
60.848: ECCInit: ErrCode 0
60.848: ECCInit: Done
60.848: mctAutoInitMCT_D: CPUMemTyping_D
60.849: <09> CPUMemTyping: Cache32bTOP:c00000
60.849: <09> CPUMemTyping: Bottom32bIO:c00000
60.849: <09> CPUMemTyping: Bottom40bIO:40400000
60.849: mctAutoInitMCT_D: UMAMemTyping_D
60.849: mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15
60.849: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
60.849: CBFS: Locating 'cmos_layout.bin'
60.849: CBFS: Found @ offset 2b0c0 size e88
60.849: set_up_cc6_storage_fam15: Initializing CC6 DRAM storage area for node 0 (interleaved: 0)
60.850: set_up_cc6_storage_fam15:<09>original (node 3) max_range_limit:       403fffffff DRAM limit:       103fffffff
60.850: set_up_cc6_storage_fam15:<09>new max_range_limit:       403effffff
60.850: set_up_cc6_storage_fam15:<09>Target node: 3
60.850: set_up_cc6_storage_fam15:<09>Done
60.850: set_up_cc6_storage_fam15: Initializing CC6 DRAM storage area for node 1 (interleaved: 0)
60.850: set_up_cc6_storage_fam15:<09>original (node 3) max_range_limit:       403fffffff DRAM limit:       203fffffff
60.850: set_up_cc6_storage_fam15:<09>new max_range_limit:       403effffff
60.850: set_up_cc6_storage_fam15:<09>Target node: 3
60.850: set_up_cc6_storage_fam15:<09>Done
60.850: set_up_cc6_storage_fam15: Initializing CC6 DRAM storage area for node 2 (interleaved: 0)
60.850: set_up_cc6_storage_fam15:<09>original (node 3) max_range_limit:       403fffffff DRAM limit:       303fffffff
60.850: set_up_cc6_storage_fam15:<09>new max_range_limit:       403effffff
60.850: set_up_cc6_storage_fam15:<09>Target node: 3
60.850: set_up_cc6_storage_fam15:<09>Done
60.850: set_up_cc6_storage_fam15: Initializing CC6 DRAM storage area for node 3 (interleaved: 0)
60.850: set_up_cc6_storage_fam15:<09>original (node 3) max_range_limit:       403fffffff DRAM limit:       403fffffff
60.850: set_up_cc6_storage_fam15:<09>new max_range_limit:       403effffff
60.850: set_up_cc6_storage_fam15:<09>Target node: 3
60.850: set_up_cc6_storage_fam15:<09>Done
60.850: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
60.850: CBFS: Locating 'cmos_layout.bin'
60.850: CBFS: Found @ offset 2b0c0 size e88
60.851: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
60.851: CBFS: Locating 'cmos_layout.bin'
60.851: CBFS: Found @ offset 2b0c0 size e88
60.851: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
60.851: CBFS: Locating 'cmos_layout.bin'
60.851: CBFS: Found @ offset 2b0c0 size e88
60.851: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
60.851: CBFS: Locating 'cmos_layout.bin'
60.851: CBFS: Found @ offset 2b0c0 size e88
60.851: mctAutoInitMCT_D Done: Global Status: 12
60.851: raminit_amdmct end:
60.852: CBMEM:
60.852: IMD: root @ b7fff000 254 entries.
60.852: IMD: root @ b7ffec00 62 entries.
60.853: amdmct_cbmem_store_info: Storing AMDMCT configuration in CBMEM
60.853: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
60.853: CBFS: Locating 'cmos_layout.bin'
60.854: CBFS: Found @ offset 2b0c0 size e88
60.854: disable_spd()
60.980: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
60.981: CBFS: Locating 'fallback/ramstage'
60.981: CBFS: Found @ offset 3ff00 size 1544c
61.025: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
61.025: CBFS: Locating 'cmos_layout.bin'
61.025: CBFS: Found @ offset 2b0c0 size e88
61.025: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
61.025: CBFS: Locating 'cmos_layout.bin'
61.025: CBFS: Found @ offset 2b0c0 size e88
61.025: 
61.025: 
61.025: coreboot-4.5-1206-g589fc34 Fri Mar 10 10:20:39 UTC 2017 ramstage starting...
61.025: Moving GDT to b7ffe9e0...ok
61.025: Normal boot.
61.025: BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0
61.025: BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1 exit 0
61.025: Enumerating buses...
61.025: Show all devs... Before device enumeration.
61.025: Root Device: enabled 1
61.025: CPU_CLUSTER: 0: enabled 1
61.025: APIC: 00: enabled 1
61.025: DOMAIN: 0000: enabled 1
61.025: PCI: 00:18.0: enabled 1
61.025: PCI: 00:00.0: enabled 1
61.025: PCI: 00:00.1: enabled 1
61.025: PCI: 00:00.2: enabled 1
61.025: PCI: 00:02.0: enabled 1
61.025: PCI: 00:03.0: enabled 0
61.025: PCI: 00:04.0: enabled 1
61.025: PCI: 00:05.0: enabled 0
61.025: PCI: 00:06.0: enabled 0
61.025: PCI: 00:07.0: enabled 0
61.025: PCI: 00:08.0: enabled 0
61.025: PCI: 00:09.0: enabled 1
61.026: PCI: 00:0a.0: enabled 1
61.026: PCI: 00:0b.0: enabled 1
61.026: PCI: 00:0c.0: enabled 1
61.026: PCI: 00:0d.0: enabled 1
61.026: PCI: 00:11.0: enabled 1
61.026: PCI: 00:12.0: enabled 1
61.026: PCI: 00:12.1: enabled 1
61.026: PCI: 00:12.2: enabled 1
61.026: PCI: 00:13.0: enabled 1
61.026: PCI: 00:13.1: enabled 1
61.026: PCI: 00:13.2: enabled 1
61.026: PCI: 00:14.0: enabled 1
61.026: I2C: 00:50: enabled 1
61.026: I2C: 00:51: enabled 1
61.026: I2C: 00:52: enabled 1
61.026: I2C: 00:53: enabled 1
61.026: I2C: 00:54: enabled 1
61.026: I2C: 00:55: enabled 1
61.026: I2C: 00:56: enabled 1
61.026: I2C: 00:57: enabled 1
61.026: I2C: 00:2f: enabled 1
61.026: PCI: 00:14.1: enabled 1
61.026: PCI: 00:14.2: enabled 1
61.026: PCI: 00:14.3: enabled 1
61.026: PNP: 002e.0: enabled 0
61.026: PNP: 002e.1: enabled 0
61.026: PNP: 002e.2: enabled 1
61.026: PNP: 002e.3: enabled 1
61.026: PNP: 002e.5: enabled 1
61.026: PNP: 002e.106: enabled 0
61.026: PNP: 002e.107: enabled 0
61.026: PNP: 002e.207: enabled 0
61.026: PNP: 002e.307: enabled 0
61.026: PNP: 002e.407: enabled 0
61.026: PNP: 002e.8: enabled 0
61.026: PNP: 002e.108: enabled 0
61.026: PNP: 002e.9: enabled 0
61.026: PNP: 002e.109: enabled 0
61.026: PNP: 002e.209: enabled 0
61.026: PNP: 002e.309: enabled 0
61.026: PNP: 002e.a: enabled 1
61.026: PNP: 002e.b: enabled 1
61.026: PNP: 002e.c: enabled 0
61.026: PNP: 002e.d: enabled 0
61.026: PNP: 002e.f: enabled 0
61.026: PNP: 004e.0: enabled 1
61.026: PCI: 00:14.4: enabled 1
61.026: PCI: 00:01.0: enabled 1
61.026: PCI: 00:02.0: enabled 1
61.026: PCI: 00:03.0: enabled 1
61.026: PCI: 00:14.5: enabled 1
61.026: PCI: 00:18.1: enabled 1
61.026: PCI: 00:18.2: enabled 1
61.026: PCI: 00:18.3: enabled 1
61.026: PCI: 00:18.4: enabled 1
61.026: PCI: 00:18.5: enabled 1
61.026: PCI: 00:19.0: enabled 1
61.026: PCI: 00:19.1: enabled 1
61.026: PCI: 00:19.2: enabled 1
61.026: PCI: 00:19.3: enabled 1
61.026: PCI: 00:19.4: enabled 1
61.026: PCI: 00:19.5: enabled 1
61.026: PCI: 00:1a.0: enabled 1
61.026: PCI: 00:1a.1: enabled 1
61.026: PCI: 00:1a.2: enabled 1
61.026: PCI: 00:1a.3: enabled 1
61.026: PCI: 00:1a.4: enabled 1
61.026: PCI: 00:1a.5: enabled 1
61.026: PCI: 00:1b.0: enabled 1
61.026: PCI: 00:1b.1: enabled 1
61.027: PCI: 00:1b.2: enabled 1
61.026: PCI: 00:1b.3: enabled 1
61.027: PCI: 00:1b.4: enabled 1
61.027: PCI: 00:1b.5: enabled 1
61.027: Compare with tree...
61.027: Root Device: enabled 1
61.027:  CPU_CLUSTER: 0: enabled 1
61.027:   APIC: 00: enabled 1
61.027:  DOMAIN: 0000: enabled 1
61.027:   PCI: 00:18.0: enabled 1
61.027:    PCI: 00:00.0: enabled 1
61.027:    PCI: 00:00.1: enabled 1
61.027:    PCI: 00:00.2: enabled 1
61.027:    PCI: 00:02.0: enabled 1
61.027:    PCI: 00:03.0: enabled 0
61.027:    PCI: 00:04.0: enabled 1
61.027:    PCI: 00:05.0: enabled 0
61.027:    PCI: 00:06.0: enabled 0
61.027:    PCI: 00:07.0: enabled 0
61.027:    PCI: 00:08.0: enabled 0
61.027:    PCI: 00:09.0: enabled 1
61.027:    PCI: 00:0a.0: enabled 1
61.027:    PCI: 00:0b.0: enabled 1
61.027:    PCI: 00:0c.0: enabled 1
61.027:    PCI: 00:0d.0: enabled 1
61.027:    PCI: 00:11.0: enabled 1
61.027:    PCI: 00:12.0: enabled 1
61.027:    PCI: 00:12.1: enabled 1
61.027:    PCI: 00:12.2: enabled 1
61.027:    PCI: 00:13.0: enabled 1
61.027:    PCI: 00:13.1: enabled 1
61.027:    PCI: 00:13.2: enabled 1
61.027:    PCI: 00:14.0: enabled 1
61.027:     I2C: 00:50: enabled 1
61.027:     I2C: 00:51: enabled 1
61.027:     I2C: 00:52: enabled 1
61.027:     I2C: 00:53: enabled 1
61.027:     I2C: 00:54: enabled 1
61.027:     I2C: 00:55: enabled 1
61.027:     I2C: 00:56: enabled 1
61.027:     I2C: 00:57: enabled 1
61.027:     I2C: 00:2f: enabled 1
61.027:    PCI: 00:14.1: enabled 1
61.027:    PCI: 00:14.2: enabled 1
61.027:    PCI: 00:14.3: enabled 1
61.027:     PNP: 002e.0: enabled 0
61.027:     PNP: 002e.1: enabled 0
61.027:     PNP: 002e.2: enabled 1
61.027:     PNP: 002e.3: enabled 1
61.027:     PNP: 002e.5: enabled 1
61.027:     PNP: 002e.106: enabled 0
61.027:     PNP: 002e.107: enabled 0
61.027:     PNP: 002e.207: enabled 0
61.027:     PNP: 002e.307: enabled 0
61.027:     PNP: 002e.407: enabled 0
61.027:     PNP: 002e.8: enabled 0
61.027:     PNP: 002e.108: enabled 0
61.027:     PNP: 002e.9: enabled 0
61.027:     PNP: 002e.109: enabled 0
61.027:     PNP: 002e.209: enabled 0
61.027:     PNP: 002e.309: enabled 0
61.027:     PNP: 002e.a: enabled 1
61.027:     PNP: 002e.b: enabled 1
61.027:     PNP: 002e.c: enabled 0
61.027:     PNP: 002e.d: enabled 0
61.027:     PNP: 002e.f: enabled 0
61.027:     PNP: 004e.0: enabled 1
61.027:    PCI: 00:14.4: enabled 1
61.027:     PCI: 00:01.0: enabled 1
61.027:     PCI: 00:02.0: enabled 1
61.027:     PCI: 00:03.0: enabled 1
61.027:    PCI: 00:14.5: enabled 1
61.027:   PCI: 00:18.1: enabled 1
61.028:   PCI: 00:18.2: enabled 1
61.027:   PCI: 00:18.3: enabled 1
61.028:   PCI: 00:18.4: enabled 1
61.028:   PCI: 00:18.5: enabled 1
61.028:   PCI: 00:19.0: enabled 1
61.028:   PCI: 00:19.1: enabled 1
61.028:   PCI: 00:19.2: enabled 1
61.028:   PCI: 00:19.3: enabled 1
61.028:   PCI: 00:19.4: enabled 1
61.028:   PCI: 00:19.5: enabled 1
61.028:   PCI: 00:1a.0: enabled 1
61.028:   PCI: 00:1a.1: enabled 1
61.028:   PCI: 00:1a.2: enabled 1
61.028:   PCI: 00:1a.3: enabled 1
61.028:   PCI: 00:1a.4: enabled 1
61.028:   PCI: 00:1a.5: enabled 1
61.028:   PCI: 00:1b.0: enabled 1
61.028:   PCI: 00:1b.1: enabled 1
61.028:   PCI: 00:1b.2: enabled 1
61.028:   PCI: 00:1b.3: enabled 1
61.028:   PCI: 00:1b.4: enabled 1
61.028:   PCI: 00:1b.5: enabled 1
61.028: Mainboard KGPE-D16 Enable. dev=0x0012cbe0
61.028: mainboard_enable, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000
61.028: mainboard_enable, TOP MEM2: msr2.lo = 0x40000000, msr2.hi = 0x00000040
61.028: Root Device scanning...
61.028: root_dev_scan_bus for Root Device
61.028: setup_bsp_ramtop, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000
61.028: setup_bsp_ramtop, TOP MEM2: msr.lo = 0x40000000, msr.hi = 0x00000040
61.028: CPU_CLUSTER: 0 enabled
61.028: DOMAIN: 0000 enabled
61.028: CPU_CLUSTER: 0 scanning...
61.028: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
61.028: CBFS: Locating 'cmos_layout.bin'
61.028: CBFS: Found @ offset 2b0c0 size e88
61.028: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
61.028: CBFS: Locating 'cmos_layout.bin'
61.028: CBFS: Found @ offset 2b0c0 size e88
61.029:   PCI: 00:18.5 siblings=7
61.029: CPU: APIC: 00 enabled
61.029: CPU: APIC: 01 enabled
61.029: CPU: APIC: 02 enabled
61.029: CPU: APIC: 03 enabled
61.029: CPU: APIC: 04 enabled
61.029: CPU: APIC: 05 enabled
61.029: CPU: APIC: 06 enabled
61.029: CPU: APIC: 07 enabled
61.029:   PCI: 00:19.5 siblings=7
61.029: CPU: APIC: 08 enabled
61.029: CPU: APIC: 09 enabled
61.029: CPU: APIC: 0a enabled
61.029: CPU: APIC: 0b enabled
61.029: CPU: APIC: 0c enabled
61.029: CPU: APIC: 0d enabled
61.029: CPU: APIC: 0e enabled
61.029: CPU: APIC: 0f enabled
61.029:   PCI: 00:1a.5 siblings=7
61.029: CPU: APIC: 20 enabled
61.029: CPU: APIC: 21 enabled
61.029: CPU: APIC: 22 enabled
61.029: CPU: APIC: 23 enabled
61.029: CPU: APIC: 24 enabled
61.029: CPU: APIC: 25 enabled
61.029: CPU: APIC: 26 enabled
61.029: CPU: APIC: 27 enabled
61.029:   PCI: 00:1b.5 siblings=7
61.029: CPU: APIC: 28 enabled
61.029: CPU: APIC: 29 enabled
61.029: CPU: APIC: 2a enabled
61.029: CPU: APIC: 2b enabled
61.029: CPU: APIC: 2c enabled
61.029: CPU: APIC: 2d enabled
61.029: CPU: APIC: 2e enabled
61.029: CPU: APIC: 2f enabled
61.029: scan_bus: scanning of bus CPU_CLUSTER: 0 took 72637 usecs
61.029: DOMAIN: 0000 scanning...
61.029: PCI: pci_scan_bus for bus 00
61.029: PCI: 00:18.0 [1022/1600] bus ops
61.029: PCI: 00:18.0 [1022/1600] enabled
61.029: PCI: 00:18.1 [1022/1601] enabled
61.029: PCI: 00:18.2 [1022/1602] enabled
61.029: PCI: 00:18.3 [1022/1603] ops
61.029: PCI: 00:18.3 [1022/1603] enabled
61.029: PCI: 00:18.4 [1022/1604] ops
61.030: PCI: 00:18.4 [1022/1604] enabled
61.030: PCI: 00:18.5 [1022/1605] ops
61.030: PCI: 00:18.5 [1022/1605] enabled
61.030: PCI: 00:19.0 [1022/1600] bus ops
61.030: PCI: 00:19.0 [1022/1600] enabled
61.030: PCI: 00:19.1 [1022/1601] enabled
61.030: PCI: 00:19.2 [1022/1602] enabled
61.030: PCI: 00:19.3 [1022/1603] ops
61.030: PCI: 00:19.3 [1022/1603] enabled
61.030: PCI: 00:19.4 [1022/1604] ops
61.030: PCI: 00:19.4 [1022/1604] enabled
61.030: PCI: 00:19.5 [1022/1605] ops
61.030: PCI: 00:19.5 [1022/1605] enabled
61.030: PCI: 00:1a.0 [1022/1600] bus ops
61.030: PCI: 00:1a.0 [1022/1600] enabled
61.030: PCI: 00:1a.1 [1022/1601] enabled
61.030: PCI: 00:1a.2 [1022/1602] enabled
61.030: PCI: 00:1a.3 [1022/1603] ops
61.030: PCI: 00:1a.3 [1022/1603] enabled
61.030: PCI: 00:1a.4 [1022/1604] ops
61.030: PCI: 00:1a.4 [1022/1604] enabled
61.030: PCI: 00:1a.5 [1022/1605] ops
61.030: PCI: 00:1a.5 [1022/1605] enabled
61.030: PCI: 00:1b.0 [1022/1600] bus ops
61.030: PCI: 00:1b.0 [1022/1600] enabled
61.030: PCI: 00:1b.1 [1022/1601] enabled
61.030: PCI: 00:1b.2 [1022/1602] enabled
61.030: PCI: 00:1b.3 [1022/1603] ops
61.030: PCI: 00:1b.3 [1022/1603] enabled
61.030: PCI: 00:1b.4 [1022/1604] ops
61.030: PCI: 00:1b.4 [1022/1604] enabled
61.030: PCI: 00:1b.5 [1022/1605] ops
61.030: PCI: 00:1b.5 [1022/1605] enabled
61.030: PCI: 00:18.0 scanning...
61.030: do_hypertransport_scan_chain for bus 00
61.030: sr5650_enable: dev=0012f500, VID_DID=0x5a101002
61.030: Bus-0, Dev-0, Fun-0.
61.030: enable_pcie_bar3
61.033: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ef60, port=0x8
61.033: PciePowerOffGppPorts() port 8
61.033: NB_PCI_REG04 = 2.
61.033: NB_PCI_REG84 = 3000010.
61.033: NB_PCI_REG4C = 52042.
61.033: Sysmem TOM = 0_c0000000
61.033: Sysmem TOM2 = 40_40000000
61.033: PCI: 00:00.0 [1002/5a10] ops
61.033: PCI: 00:00.0 [1002/5a10] enabled
61.033: Capability: type 0x08 @ 0xf0
61.033: flags: 0xa803
61.033: Capability: type 0x08 @ 0xf0
61.033: Capability: type 0x08 @ 0xc4
61.033: flags: 0x0280
61.033: PCI: 00:00.0 count: 0014 static_count: 0015
61.033: PCI: 00:00.0 [1002/5a10] enabled next_unitid: 0015
61.033: PCI: pci_scan_bus for bus 00
61.033: sr5650_enable: dev=0012f500, VID_DID=0x5a101002
61.033: Bus-0, Dev-0, Fun-0.
61.033: enable_pcie_bar3
61.036: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ef60, port=0x8
61.036: PciePowerOffGppPorts() port 8
61.036: NB_PCI_REG04 = 2.
61.037: NB_PCI_REG84 = 3000010.
61.037: NB_PCI_REG4C = 52042.
61.037: Sysmem TOM = 0_c0000000
61.037: Sysmem TOM2 = 40_40000000
61.037: PCI: 00:00.0 [1002/5a10] enabled
61.037: sr5650_enable: dev=0012f460, VID_DID=0xffffffff
61.037: Bus-0, Dev-0, Fun-1.
61.037: PCI: Static device PCI: 00:00.1 not found, disabling it.
61.037: sr5650_enable: dev=0012f3c0, VID_DID=0x5a231002
61.037: Bus-0, Dev-0, Fun-2.
61.037: PCI: 00:00.2 [1002/5a23] ops
61.037: PCI: 00:00.2 [1002/5a23] enabled
61.037: sr5650_enable: dev=0012f320, VID_DID=0xffffffff
61.037: Bus-0, Dev-2,3, Fun-0. enable=1
61.037: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012f320, port=0x2
61.077: PcieLinkTraining port=2:lc current state=2030400
61.078: sr5650_gpp_sb_init: port=0x2 hw_port=0x2 result=0
61.078: PciePowerOffGppPorts() port 2
61.078: Capability: type 0x01 @ 0x50
61.078: Capability: type 0x10 @ 0x58
61.078: Capability: type 0x05 @ 0xa0
61.078: Capability: type 0x0d @ 0xb0
61.078: Capability: type 0x08 @ 0xb8
61.078: Capability: type 0x01 @ 0x50
61.078: Capability: type 0x10 @ 0x58
61.078: Capability: type 0x05 @ 0xa0
61.078: Capability: type 0x0d @ 0xb0
61.078: Capability: type 0x08 @ 0xb8
61.078: Capability: type 0x01 @ 0x50
61.078: Capability: type 0x10 @ 0x58
61.078: Capability: type 0x05 @ 0xa0
61.078: Capability: type 0x0d @ 0xb0
61.078: Capability: type 0x08 @ 0xb8
61.078: Capability: type 0x01 @ 0x50
61.078: Capability: type 0x10 @ 0x58
61.078: PCI: 00:02.0 subordinate bus PCI Express
61.078: PCI: 00:02.0 [1002/5a16] enabled
61.078: sr5650_enable: dev=0012f280, VID_DID=0xffffffff
61.078: Bus-0, Dev-2,3, Fun-0. enable=0
61.078: sr5650_enable: dev=0012f1e0, VID_DID=0xffffffff
61.078: enable_pcie_bar3
61.078: Bus-0, Dev-4,5,6,7, Fun-0. enable=1
61.078: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012f1e0, port=0x4
61.119: PcieLinkTraining port=4:lc current state=2030400
61.120: sr5650_gpp_sb_init: port=0x4 hw_port=0x4 result=0
61.120: PciePowerOffGppPorts() port 4
61.120: Capability: type 0x01 @ 0x50
61.120: Capability: type 0x10 @ 0x58
61.120: Capability: type 0x05 @ 0xa0
61.120: Capability: type 0x0d @ 0xb0
61.120: Capability: type 0x08 @ 0xb8
61.120: Capability: type 0x01 @ 0x50
61.120: Capability: type 0x10 @ 0x58
61.120: Capability: type 0x05 @ 0xa0
61.120: Capability: type 0x0d @ 0xb0
61.120: Capability: type 0x08 @ 0xb8
61.120: Capability: type 0x01 @ 0x50
61.120: Capability: type 0x10 @ 0x58
61.120: Capability: type 0x05 @ 0xa0
61.120: Capability: type 0x0d @ 0xb0
61.120: Capability: type 0x08 @ 0xb8
61.120: Capability: type 0x01 @ 0x50
61.120: Capability: type 0x10 @ 0x58
61.120: PCI: 00:04.0 subordinate bus PCI Express
61.120: PCI: 00:04.0 [1002/5a18] enabled
61.120: sr5650_enable: dev=0012f140, VID_DID=0xffffffff
61.120: enable_pcie_bar3
61.120: Bus-0, Dev-4,5,6,7, Fun-0. enable=0
61.120: sr5650_enable: dev=0012f0a0, VID_DID=0xffffffff
61.120: enable_pcie_bar3
61.120: Bus-0, Dev-4,5,6,7, Fun-0. enable=0
61.120: sr5650_enable: dev=0012f000, VID_DID=0xffffffff
61.120: enable_pcie_bar3
61.120: Bus-0, Dev-4,5,6,7, Fun-0. enable=0
61.120: sr5650_enable: dev=0012ef60, VID_DID=0xffffffff
61.120: Bus-0, Dev-8, Fun-0. enable=0
61.120: disable_pcie_bar3
61.120: sr5650_enable: dev=0012eec0, VID_DID=0xffffffff
61.120: Bus-0, Dev-9, 10, Fun-0. enable=1
61.120: enable_pcie_bar3
61.120: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012eec0, port=0x9
61.160: PcieLinkTraining port=5:lc current state=a0b0f10
61.160: addr=c0000000,bus=0,devfn=48
61.160: PcieTrainPort reg=0x10000
61.160: sr5650_gpp_sb_init: port=0x9 hw_port=0x5 result=1
61.160: Capability: type 0x01 @ 0x50
61.160: Capability: type 0x10 @ 0x58
61.160: Capability: type 0x05 @ 0xa0
61.160: Capability: type 0x0d @ 0xb0
61.160: Capability: type 0x08 @ 0xb8
61.160: Capability: type 0x01 @ 0x50
61.160: Capability: type 0x10 @ 0x58
61.160: Capability: type 0x05 @ 0xa0
61.160: Capability: type 0x0d @ 0xb0
61.160: Capability: type 0x08 @ 0xb8
61.160: Capability: type 0x01 @ 0x50
61.160: Capability: type 0x10 @ 0x58
61.161: Capability: type 0x05 @ 0xa0
61.161: Capability: type 0x0d @ 0xb0
61.160: Capability: type 0x08 @ 0xb8
61.161: Capability: type 0x01 @ 0x50
61.161: Capability: type 0x10 @ 0x58
61.161: PCI: 00:09.0 subordinate bus PCI Express
61.161: PCI: 00:09.0 [1002/5a1c] enabled
61.161: sr5650_enable: dev=0012ee20, VID_DID=0xffffffff
61.161: Bus-0, Dev-9, 10, Fun-0. enable=1
61.161: enable_pcie_bar3
61.161: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ee20, port=0xa
61.201: PcieLinkTraining port=6:lc current state=a0b0f10
61.201: addr=c0000000,bus=0,devfn=50
61.201: PcieTrainPort reg=0x10000
61.201: sr5650_gpp_sb_init: port=0xa hw_port=0x6 result=1
61.201: Capability: type 0x01 @ 0x50
61.201: Capability: type 0x10 @ 0x58
61.201: Capability: type 0x05 @ 0xa0
61.201: Capability: type 0x0d @ 0xb0
61.201: Capability: type 0x08 @ 0xb8
61.201: Capability: type 0x01 @ 0x50
61.201: Capability: type 0x10 @ 0x58
61.201: Capability: type 0x05 @ 0xa0
61.201: Capability: type 0x0d @ 0xb0
61.201: Capability: type 0x08 @ 0xb8
61.201: Capability: type 0x01 @ 0x50
61.201: Capability: type 0x10 @ 0x58
61.201: Capability: type 0x05 @ 0xa0
61.201: Capability: type 0x0d @ 0xb0
61.201: Capability: type 0x08 @ 0xb8
61.201: Capability: type 0x01 @ 0x50
61.201: Capability: type 0x10 @ 0x58
61.201: PCI: 00:0a.0 subordinate bus PCI Express
61.201: PCI: 00:0a.0 [1002/5a1d] enabled
61.201: sr5650_enable: dev=0012ed80, VID_DID=0xffffffff
61.201: Bus-0, Dev-11,12, Fun-0. enable=1
61.201: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ed80, port=0xb
61.241: PcieLinkTraining port=b:lc current state=2030400
61.242: sr5650_gpp_sb_init: port=0xb hw_port=0xb result=0
61.242: PciePowerOffGppPorts() port 11
61.242: Capability: type 0x01 @ 0x50
61.242: Capability: type 0x10 @ 0x58
61.242: Capability: type 0x05 @ 0xa0
61.242: Capability: type 0x0d @ 0xb0
61.242: Capability: type 0x08 @ 0xb8
61.242: Capability: type 0x01 @ 0x50
61.243: Capability: type 0x10 @ 0x58
61.243: Capability: type 0x05 @ 0xa0
61.243: Capability: type 0x0d @ 0xb0
61.243: Capability: type 0x08 @ 0xb8
61.243: Capability: type 0x01 @ 0x50
61.243: Capability: type 0x10 @ 0x58
61.243: Capability: type 0x05 @ 0xa0
61.243: Capability: type 0x0d @ 0xb0
61.243: Capability: type 0x08 @ 0xb8
61.243: Capability: type 0x01 @ 0x50
61.243: Capability: type 0x10 @ 0x58
61.243: PCI: 00:0b.0 subordinate bus PCI Express
61.243: PCI: 00:0b.0 [1002/5a1f] enabled
61.243: sr5650_enable: dev=0012ece0, VID_DID=0xffffffff
61.243: Bus-0, Dev-11,12, Fun-0. enable=1
61.243: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ece0, port=0xc
61.283: PcieLinkTraining port=c:lc current state=2030400
61.284: sr5650_gpp_sb_init: port=0xc hw_port=0xc result=0
61.284: PciePowerOffGppPorts() port 12
61.284: Capability: type 0x01 @ 0x50
61.284: Capability: type 0x10 @ 0x58
61.284: Capability: type 0x05 @ 0xa0
61.284: Capability: type 0x0d @ 0xb0
61.284: Capability: type 0x08 @ 0xb8
61.284: Capability: type 0x01 @ 0x50
61.284: Capability: type 0x10 @ 0x58
61.284: Capability: type 0x05 @ 0xa0
61.284: Capability: type 0x0d @ 0xb0
61.284: Capability: type 0x08 @ 0xb8
61.284: Capability: type 0x01 @ 0x50
61.284: Capability: type 0x10 @ 0x58
61.284: Capability: type 0x05 @ 0xa0
61.284: Capability: type 0x0d @ 0xb0
61.284: Capability: type 0x08 @ 0xb8
61.284: Capability: type 0x01 @ 0x50
61.284: Capability: type 0x10 @ 0x58
61.284: PCI: 00:0c.0 subordinate bus PCI Express
61.284: PCI: 00:0c.0 [1002/5a20] enabled
61.284: sr5650_enable: dev=0012ec40, VID_DID=0xffffffff
61.284: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ec40, port=0xd
61.325: PcieLinkTraining port=d:lc current state=20212210
61.324: addr=c0000000,bus=0,devfn=68
61.324: PcieTrainPort reg=0x10000
61.324: sr5650_gpp_sb_init: port=0xd hw_port=0xd result=1
62.324: Capability: type 0x01 @ 0x50
62.324: Capability: type 0x10 @ 0x58
62.324: Capability: type 0x05 @ 0xa0
62.324: Capability: type 0x0d @ 0xb0
62.324: Capability: type 0x08 @ 0xb8
62.324: Capability: type 0x01 @ 0x50
62.325: Capability: type 0x10 @ 0x58
62.324: Capability: type 0x05 @ 0xa0
62.325: Capability: type 0x0d @ 0xb0
62.325: Capability: type 0x08 @ 0xb8
62.325: Capability: type 0x01 @ 0x50
62.325: Capability: type 0x10 @ 0x58
62.325: Capability: type 0x05 @ 0xa0
62.325: Capability: type 0x0d @ 0xb0
62.325: Capability: type 0x08 @ 0xb8
62.325: Capability: type 0x01 @ 0x50
62.325: Capability: type 0x10 @ 0x58
62.325: PCI: 00:0d.0 subordinate bus PCI Express
62.325: PCI: 00:0d.0 [1002/5a1e] enabled
62.325: sb7xx_51xx_enable()
62.325: PCI: 00:11.0 [1002/4394] ops
62.325: PCI: 00:11.0 [1002/4394] enabled
62.325: sb7xx_51xx_enable()
62.325: PCI: 00:12.0 [1002/4397] ops
62.325: PCI: 00:12.0 [1002/4397] enabled
62.325: sb7xx_51xx_enable()
62.325: PCI: 00:12.1 [1002/4398] ops
62.325: PCI: 00:12.1 [1002/4398] enabled
62.325: sb7xx_51xx_enable()
62.325: PCI: 00:12.2 [1002/4396] ops
62.325: PCI: 00:12.2 [1002/4396] enabled
62.325: sb7xx_51xx_enable()
62.325: PCI: 00:13.0 [1002/4397] ops
62.325: PCI: 00:13.0 [1002/4397] enabled
62.325: sb7xx_51xx_enable()
62.325: PCI: 00:13.1 [1002/4398] ops
62.325: PCI: 00:13.1 [1002/4398] enabled
62.325: sb7xx_51xx_enable()
62.325: PCI: 00:13.2 [1002/4396] ops
62.325: PCI: 00:13.2 [1002/4396] enabled
62.325: sb7xx_51xx_enable()
62.325: PCI: 00:14.0 [1002/4385] bus ops
62.325: PCI: 00:14.0 [1002/4385] enabled
62.325: sb7xx_51xx_enable()
62.325: PCI: 00:14.1 [1002/439c] ops
62.325: PCI: 00:14.1 [1002/439c] enabled
62.325: sb7xx_51xx_enable()
62.325: PCI: 00:14.2 [1002/4383] ops
62.325: PCI: 00:14.2 [1002/4383] enabled
62.325: sb7xx_51xx_enable()
62.325: PCI: 00:14.3 [1002/439d] bus ops
62.325: PCI: 00:14.3 [1002/439d] enabled
62.325: sb7xx_51xx_enable()
62.325: PCI: 00:14.4 [1002/4384] bus ops
62.325: PCI: 00:14.4 [1002/4384] enabled
62.325: sb7xx_51xx_enable()
62.325: PCI: 00:14.5 [1002/4399] ops
62.325: PCI: 00:14.5 [1002/4399] enabled
62.325: PCI: 00:02.0 scanning...
62.325: do_pci_scan_bridge for PCI: 00:02.0
62.325: PCI: pci_scan_bus for bus 01
62.325: scan_bus: scanning of bus PCI: 00:02.0 took 5932 usecs
62.325: PCI: 00:04.0 scanning...
62.325: do_pci_scan_bridge for PCI: 00:04.0
62.325: PCI: pci_scan_bus for bus 02
62.325: scan_bus: scanning of bus PCI: 00:04.0 took 5921 usecs
62.325: PCI: 00:09.0 scanning...
62.325: do_pci_scan_bridge for PCI: 00:09.0
62.325: PCI: pci_scan_bus for bus 03
62.326: PCI: 03:00.0 [8086/10d3] enabled
62.326: Capability: type 0x01 @ 0xc8
62.326: Capability: type 0x05 @ 0xd0
62.326: Capability: type 0x10 @ 0xe0
62.326: Capability: type 0x01 @ 0x50
62.326: Capability: type 0x10 @ 0x58
62.326: Enabling Common Clock Configuration
62.326: PCIE CLK PM is not supported by endpointASPM: Enabled None
62.326: scan_bus: scanning of bus PCI: 00:09.0 took 23857 usecs
62.326: PCI: 00:0a.0 scanning...
62.326: do_pci_scan_bridge for PCI: 00:0a.0
62.326: PCI: pci_scan_bus for bus 04
62.326: PCI: 04:00.0 [8086/10d3] enabled
62.326: Capability: type 0x01 @ 0xc8
62.326: Capability: type 0x05 @ 0xd0
62.326: Capability: type 0x10 @ 0xe0
62.326: Capability: type 0x01 @ 0x50
62.326: Capability: type 0x10 @ 0x58
62.326: Enabling Common Clock Configuration
62.326: PCIE CLK PM is not supported by endpointASPM: Enabled None
62.326: scan_bus: scanning of bus PCI: 00:0a.0 took 23825 usecs
62.326: PCI: 00:0b.0 scanning...
62.326: do_pci_scan_bridge for PCI: 00:0b.0
62.326: PCI: pci_scan_bus for bus 05
62.326: scan_bus: scanning of bus PCI: 00:0b.0 took 5920 usecs
62.326: PCI: 00:0c.0 scanning...
62.326: do_pci_scan_bridge for PCI: 00:0c.0
62.326: PCI: pci_scan_bus for bus 06
62.326: scan_bus: scanning of bus PCI: 00:0c.0 took 5920 usecs
62.326: PCI: 00:0d.0 scanning...
62.326: do_pci_scan_bridge for PCI: 00:0d.0
62.326: PCI: pci_scan_bus for bus 07
62.326: PCI: 07:00.0 [8086/10fb] enabled
62.326: PCI: 07:00.1 [8086/10fb] enabled
62.326: Capability: type 0x01 @ 0x40
62.326: Capability: type 0x05 @ 0x50
62.326: Capability: type 0x11 @ 0x70
62.326: Capability: type 0x10 @ 0xa0
62.326: Capability: type 0x01 @ 0x50
62.326: Capability: type 0x10 @ 0x58
62.326: Enabling Common Clock Configuration
62.327: PCIE CLK PM is not supported by endpointASPM: Enabled None
62.327: Capability: type 0x01 @ 0x40
62.327: Capability: type 0x05 @ 0x50
62.327: Capability: type 0x11 @ 0x70
62.327: Capability: type 0x10 @ 0xa0
62.327: Capability: type 0x01 @ 0x50
62.327: Capability: type 0x10 @ 0x58
62.327: Enabling Common Clock Configuration
62.327: PCIE CLK PM is not supported by endpointASPM: Enabled None
62.327: scan_bus: scanning of bus PCI: 00:0d.0 took 45521 usecs
62.327: PCI: 00:14.0 scanning...
62.327: scan_generic_bus for PCI: 00:14.0
62.327: bus: PCI: 00:14.0[0]->I2C: 01:50 enabled
62.327: bus: PCI: 00:14.0[0]->I2C: 01:51 enabled
62.327: bus: PCI: 00:14.0[0]->I2C: 01:52 enabled
62.327: bus: PCI: 00:14.0[0]->I2C: 01:53 enabled
62.327: bus: PCI: 00:14.0[0]->I2C: 01:54 enabled
62.327: bus: PCI: 00:14.0[0]->I2C: 01:55 enabled
62.327: bus: PCI: 00:14.0[0]->I2C: 01:56 enabled
62.327: bus: PCI: 00:14.0[0]->I2C: 01:57 enabled
62.327: bus: PCI: 00:14.0[0]->I2C: 01:2f enabled
62.327: scan_generic_bus for PCI: 00:14.0 done
62.327: scan_bus: scanning of bus PCI: 00:14.0 took 30457 usecs
62.327: PCI: 00:14.3 scanning...
62.327: scan_lpc_bus for PCI: 00:14.3
62.327: PNP: 002e.0 disabled
62.327: PNP: 002e.1 disabled
62.327: PNP: 002e.2 enabled
62.327: PNP: 002e.3 enabled
62.327: PNP: 002e.5 enabled
62.327: PNP: 002e.106 disabled
62.327: PNP: 002e.107 disabled
62.327: PNP: 002e.207 disabled
62.327: PNP: 002e.307 disabled
62.327: PNP: 002e.407 disabled
62.328: PNP: 002e.8 disabled
62.328: PNP: 002e.108 disabled
62.328: PNP: 002e.9 disabled
62.328: PNP: 002e.109 disabled
62.328: PNP: 002e.209 disabled
62.328: PNP: 002e.309 disabled
62.328: PNP: 002e.a enabled
62.328: PNP: 002e.b enabled
62.328: PNP: 002e.c disabled
62.328: PNP: 002e.d disabled
62.328: PNP: 002e.f disabled
62.328: PNP: 004e.0 enabled
62.328: scan_lpc_bus for PCI: 00:14.3 done
62.328: scan_bus: scanning of bus PCI: 00:14.3 took 37768 usecs
62.328: PCI: 00:14.4 scanning...
62.328: do_pci_scan_bridge for PCI: 00:14.4
62.328: PCI: pci_scan_bus for bus 08
62.328: sb7xx_51xx_enable()
62.328: PCI: 08:01.0 [1a03/2000] ops
62.328: PCI: 08:01.0 [1a03/2000] enabled
62.328: sb7xx_51xx_enable()
62.328: PCI: 08:02.0 [11c1/5811] enabled
62.328: sb7xx_51xx_enable()
62.328: PCI: Static device PCI: 08:03.0 not found, disabling it.
62.328: scan_bus: scanning of bus PCI: 00:14.4 took 19824 usecs
62.328: scan_bus: scanning of bus PCI: 00:18.0 took 1755041 usecs
62.328: PCI: 00:19.0 scanning...
62.328: scan_bus: scanning of bus PCI: 00:19.0 took 1652 usecs
62.328: PCI: 00:1a.0 scanning...
62.328: scan_bus: scanning of bus PCI: 00:1a.0 took 1652 usecs
62.328: PCI: 00:1b.0 scanning...
62.328: scan_bus: scanning of bus PCI: 00:1b.0 took 1652 usecs
62.328: DOMAIN: 0000 passpw: enabled
62.328: DOMAIN: 0000 passpw: enabled
62.328: DOMAIN: 0000 passpw: enabled
62.328: DOMAIN: 0000 passpw: enabled
62.328: scan_bus: scanning of bus DOMAIN: 0000 took 1868798 usecs
62.328: root_dev_scan_bus for Root Device done
62.328: scan_bus: scanning of bus Root Device took 1966996 usecs
62.328: done
62.328: BS: BS_DEV_ENUMERATE times (us): entry 0 run 2288289 exit 0
62.328: found VGA at PCI: 08:01.0
62.328: Setting up VGA for PCI: 08:01.0
62.328: Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:14.4
62.328: Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
62.328: Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
62.328: Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
62.328: Allocating resources...
62.328: Reading resources...
62.328: Root Device read_resources bus 0 link: 0
62.328: CPU_CLUSTER: 0 read_resources bus 0 link: 0
62.328: CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
62.328: Adding PCIe enhanced config space BAR 0xc0000000-0xd0000000.
62.329: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.329: CBFS: Locating 'cmos_layout.bin'
62.329: CBFS: Found @ offset 2b0c0 size e88
62.329: Reserving CC6 save segment base: 4038000000 size: 08000000
62.329: DOMAIN: 0000 read_resources bus 0 link: 0
62.329: PCI: 00:18.0 read_resources bus 0 link: 2
62.329: PCI: 00:18.0 read_resources bus 0 link: 2 done
62.329: PCI: 00:18.0 read_resources bus 0 link: 3
62.329: PCI: 00:18.0 read_resources bus 0 link: 3 done
62.329: PCI: 00:18.0 read_resources bus 0 link: 0
62.329: PCI: 00:18.0 read_resources bus 0 link: 0 done
62.329: PCI: 00:18.0 read_resources bus 0 link: 1
62.329: sr5690_read_resource: PCI: 00:00.0
62.329: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.329: CBFS: Locating 'cmos_layout.bin'
62.329: CBFS: Found @ offset 2b0c0 size e88
62.330: PCI: 00:02.0 read_resources bus 1 link: 0
62.330: PCI: 00:02.0 read_resources bus 1 link: 0 done
62.330: PCI: 00:04.0 read_resources bus 2 link: 0
62.330: PCI: 00:04.0 read_resources bus 2 link: 0 done
62.330: PCI: 00:09.0 read_resources bus 3 link: 0
62.330: PCI: 00:09.0 read_resources bus 3 link: 0 done
62.330: PCI: 00:0a.0 read_resources bus 4 link: 0
62.330: PCI: 00:0a.0 read_resources bus 4 link: 0 done
62.330: PCI: 00:0b.0 read_resources bus 5 link: 0
62.330: PCI: 00:0b.0 read_resources bus 5 link: 0 done
62.330: PCI: 00:0c.0 read_resources bus 6 link: 0
62.330: PCI: 00:0c.0 read_resources bus 6 link: 0 done
62.330: PCI: 00:0d.0 read_resources bus 7 link: 0
62.330: PCI: 00:0d.0 read_resources bus 7 link: 0 done
62.331: PCI: 00:14.0 read_resources bus 1 link: 0
62.331: I2C: 01:50 missing read_resources
62.331: I2C: 01:51 missing read_resources
62.331: I2C: 01:52 missing read_resources
62.331: I2C: 01:53 missing read_resources
62.331: I2C: 01:54 missing read_resources
62.331: I2C: 01:55 missing read_resources
62.331: I2C: 01:56 missing read_resources
62.331: I2C: 01:57 missing read_resources
62.331: PCI: 00:14.0 read_resources bus 1 link: 0 done
62.331: PCI: 00:14.3 read_resources bus 0 link: 0
62.331: PNP: 004e.0 missing read_resources
62.331: PCI: 00:14.3 read_resources bus 0 link: 0 done
62.331: PCI: 00:14.4 read_resources bus 8 link: 0
62.331: PCI: 00:14.4 read_resources bus 8 link: 0 done
62.331: PCI: 00:18.0 read_resources bus 0 link: 1 done
62.331: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.331: CBFS: Locating 'cmos_layout.bin'
62.331: CBFS: Found @ offset 2b0c0 size e88
62.332: PCI: 00:18.4 read_resources bus 0 link: 0
62.332: PCI: 00:18.4 read_resources bus 0 link: 0 done
62.332: PCI: 00:18.4 read_resources bus 0 link: 1
62.332: PCI: 00:18.4 read_resources bus 0 link: 1 done
62.332: PCI: 00:18.4 read_resources bus 0 link: 2
62.332: PCI: 00:18.4 read_resources bus 0 link: 2 done
62.332: PCI: 00:18.4 read_resources bus 0 link: 3
62.332: PCI: 00:18.4 read_resources bus 0 link: 3 done
62.332: PCI: 00:19.0 read_resources bus 0 link: 3
62.332: PCI: 00:19.0 read_resources bus 0 link: 3 done
62.332: PCI: 00:19.0 read_resources bus 0 link: 2
62.332: PCI: 00:19.0 read_resources bus 0 link: 2 done
62.332: PCI: 00:19.0 read_resources bus 0 link: 0
62.332: PCI: 00:19.0 read_resources bus 0 link: 0 done
62.332: PCI: 00:19.0 read_resources bus 0 link: 1
62.332: PCI: 00:19.0 read_resources bus 0 link: 1 done
62.332: PCI: 00:19.4 read_resources bus 0 link: 0
62.332: PCI: 00:19.4 read_resources bus 0 link: 0 done
62.332: PCI: 00:19.4 read_resources bus 0 link: 1
62.332: PCI: 00:19.4 read_resources bus 0 link: 1 done
62.332: PCI: 00:19.4 read_resources bus 0 link: 2
62.332: PCI: 00:19.4 read_resources bus 0 link: 2 done
62.332: PCI: 00:19.4 read_resources bus 0 link: 3
62.332: PCI: 00:19.4 read_resources bus 0 link: 3 done
62.332: PCI: 00:1a.0 read_resources bus 0 link: 3
62.332: PCI: 00:1a.0 read_resources bus 0 link: 3 done
62.332: PCI: 00:1a.0 read_resources bus 0 link: 2
62.332: PCI: 00:1a.0 read_resources bus 0 link: 2 done
62.332: PCI: 00:1a.0 read_resources bus 0 link: 0
62.332: PCI: 00:1a.0 read_resources bus 0 link: 0 done
62.332: PCI: 00:1a.0 read_resources bus 0 link: 1
62.332: PCI: 00:1a.0 read_resources bus 0 link: 1 done
62.332: PCI: 00:1a.4 read_resources bus 0 link: 0
62.332: PCI: 00:1a.4 read_resources bus 0 link: 0 done
62.332: PCI: 00:1a.4 read_resources bus 0 link: 1
62.332: PCI: 00:1a.4 read_resources bus 0 link: 1 done
62.332: PCI: 00:1a.4 read_resources bus 0 link: 2
62.332: PCI: 00:1a.4 read_resources bus 0 link: 2 done
62.332: PCI: 00:1a.4 read_resources bus 0 link: 3
62.332: PCI: 00:1a.4 read_resources bus 0 link: 3 done
62.332: PCI: 00:1b.0 read_resources bus 0 link: 3
62.332: PCI: 00:1b.0 read_resources bus 0 link: 3 done
62.332: PCI: 00:1b.0 read_resources bus 0 link: 2
62.332: PCI: 00:1b.0 read_resources bus 0 link: 2 done
62.332: PCI: 00:1b.0 read_resources bus 0 link: 0
62.332: PCI: 00:1b.0 read_resources bus 0 link: 0 done
62.332: PCI: 00:1b.0 read_resources bus 0 link: 1
62.332: PCI: 00:1b.0 read_resources bus 0 link: 1 done
62.332: PCI: 00:1b.4 read_resources bus 0 link: 0
62.332: PCI: 00:1b.4 read_resources bus 0 link: 0 done
62.332: PCI: 00:1b.4 read_resources bus 0 link: 1
62.332: PCI: 00:1b.4 read_resources bus 0 link: 1 done
62.332: PCI: 00:1b.4 read_resources bus 0 link: 2
62.332: PCI: 00:1b.4 read_resources bus 0 link: 2 done
62.332: PCI: 00:1b.4 read_resources bus 0 link: 3
62.332: PCI: 00:1b.4 read_resources bus 0 link: 3 done
62.332: DOMAIN: 0000 read_resources bus 0 link: 0 done
62.332: Root Device read_resources bus 0 link: 0 done
62.332: Done reading resources.
62.333: Show resources in subtree (Root Device)...After reading.
62.333:  Root Device child on link 0 CPU_CLUSTER: 0
62.333:   CPU_CLUSTER: 0 child on link 0 APIC: 00
62.333:    APIC: 00
62.333:    APIC: 01
62.333:    APIC: 02
62.333:    APIC: 03
62.333:    APIC: 04
62.333:    APIC: 05
62.333:    APIC: 06
62.333:    APIC: 07
62.333:    APIC: 08
62.333:    APIC: 09
62.333:    APIC: 0a
62.333:    APIC: 0b
62.333:    APIC: 0c
62.333:    APIC: 0d
62.333:    APIC: 0e
62.333:    APIC: 0f
62.333:    APIC: 20
62.333:    APIC: 21
62.333:    APIC: 22
62.333:    APIC: 23
62.333:    APIC: 24
62.333:    APIC: 25
62.333:    APIC: 26
62.333:    APIC: 27
62.333:    APIC: 28
62.333:    APIC: 29
62.333:    APIC: 2a
62.334:    APIC: 2b
62.334:    APIC: 2c
62.334:    APIC: 2d
62.334:    APIC: 2e
62.334:    APIC: 2f
62.334:   DOMAIN: 0000 child on link 0 PCI: 00:18.0
62.334:   DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
62.334:   DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
62.334:   DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
62.334:   DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7
62.334:   DOMAIN: 0000 resource base 4038000000 size 8000000 align 0 gran 0 limit 0 flags f0004200 index 8
62.334:    PCI: 00:18.0
62.334:    PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 110b0
62.334:    PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 110b8
62.334:    PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 110d8
62.334:     PCI: 00:00.0
62.334:     PCI: 00:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 1200 index fc
62.334:     PCI: 00:00.1
62.334:     PCI: 00:00.2
62.334:     PCI: 00:00.2 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 10000200 index 44
62.334:     PCI: 00:02.0
62.334:     PCI: 00:02.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
62.334:     PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
62.334:     PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
62.334:     PCI: 00:03.0
62.334:     PCI: 00:04.0
62.334:     PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
62.334:     PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
62.334:     PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
62.334:     PCI: 00:05.0
62.334:     PCI: 00:06.0
62.334:     PCI: 00:07.0
62.334:     PCI: 00:08.0
62.334:     PCI: 00:09.0 child on link 0 PCI: 03:00.0
62.334:     PCI: 00:09.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
62.334:     PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
62.334:     PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
62.334:      PCI: 03:00.0
62.334:      PCI: 03:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
62.334:      PCI: 03:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
62.334:      PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
62.334:     PCI: 00:0a.0 child on link 0 PCI: 04:00.0
62.334:     PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
62.334:     PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
62.334:     PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
62.334:      PCI: 04:00.0
62.334:      PCI: 04:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
62.334:      PCI: 04:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
62.334:      PCI: 04:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
62.334:     PCI: 00:0b.0
62.334:     PCI: 00:0b.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
62.334:     PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
62.334:     PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
62.334:     PCI: 00:0c.0
62.334:     PCI: 00:0c.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
62.334:     PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
62.334:     PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
62.334:     PCI: 00:0d.0 child on link 0 PCI: 07:00.0
62.334:     PCI: 00:0d.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
62.334:     PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
62.334:     PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
62.334:      PCI: 07:00.0
62.335:      PCI: 07:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffffffffffff flags 1201 index 10
62.335:      PCI: 07:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
62.335:      PCI: 07:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
62.335:      PCI: 07:00.1
62.335:      PCI: 07:00.1 resource base 0 size 80000 align 19 gran 19 limit ffffffffffffffff flags 1201 index 10
62.335:      PCI: 07:00.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
62.335:      PCI: 07:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
62.335:     PCI: 00:11.0
62.335:     PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
62.335:     PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
62.335:     PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
62.335:     PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
62.335:     PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
62.335:     PCI: 00:11.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 24
62.335:     PCI: 00:12.0
62.335:     PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
62.335:     PCI: 00:12.1
62.335:     PCI: 00:12.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
62.335:     PCI: 00:12.2
62.335:     PCI: 00:12.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
62.335:     PCI: 00:13.0
62.335:     PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
62.335:     PCI: 00:13.1
62.335:     PCI: 00:13.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
62.335:     PCI: 00:13.2
62.335:     PCI: 00:13.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
62.335:     PCI: 00:14.0 child on link 0 I2C: 01:50
62.335:     PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
62.335:     PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c
62.335:     PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
62.335:     PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
62.335:     PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58
62.335:      I2C: 01:50
62.335:      I2C: 01:51
62.335:      I2C: 01:52
62.335:      I2C: 01:53
62.335:      I2C: 01:54
62.335:      I2C: 01:55
62.335:      I2C: 01:56
62.335:      I2C: 01:57
62.335:      I2C: 01:2f
62.335:     PCI: 00:14.1
62.335:     PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
62.335:     PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
62.335:     PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
62.335:     PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
62.335:     PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
62.335:     PCI: 00:14.2
62.335:     PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
62.335:     PCI: 00:14.3 child on link 0 PNP: 002e.0
62.335:     PCI: 00:14.3 resource base 0 size 1 align 12 gran 0 limit ffffffff flags 200 index a0
62.335:     PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
62.335:     PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
62.335:     PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
62.335:      PNP: 002e.0
62.335:      PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
62.335:      PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
62.335:      PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
62.335:      PNP: 002e.1
62.335:      PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
62.335:      PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
62.335:      PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
62.335:      PNP: 002e.2
62.335:      PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
62.335:      PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
62.335:      PNP: 002e.3
62.336:      PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
62.336:      PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
62.336:      PNP: 002e.5
62.336:      PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
62.336:      PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
62.336:      PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
62.336:      PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72
62.336:      PNP: 002e.106
62.336:      PNP: 002e.106 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
62.336:      PNP: 002e.107
62.336:      PNP: 002e.207
62.336:      PNP: 002e.307
62.336:      PNP: 002e.407
62.336:      PNP: 002e.8
62.336:      PNP: 002e.108
62.336:      PNP: 002e.9
62.336:      PNP: 002e.109
62.336:      PNP: 002e.209
62.336:      PNP: 002e.309
62.336:      PNP: 002e.a
62.336:      PNP: 002e.b
62.336:      PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags c0000100 index 60
62.336:      PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
62.336:      PNP: 002e.c
62.336:      PNP: 002e.d
62.336:      PNP: 002e.f
62.336:      PNP: 004e.0
62.336:     PCI: 00:14.4 child on link 0 PCI: 08:01.0
62.336:     PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
62.336:     PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
62.336:     PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
62.336:      PCI: 08:01.0
62.336:      PCI: 08:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffff flags 200 index 10
62.336:      PCI: 08:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 14
62.336:      PCI: 08:01.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 18
62.336:      PCI: 08:02.0
62.336:      PCI: 08:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
62.336:      PCI: 08:03.0
62.336:     PCI: 00:14.5
62.336:     PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
62.336:    PCI: 00:18.1
62.336:    PCI: 00:18.2
62.336:    PCI: 00:18.3
62.336:    PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
62.336:    PCI: 00:18.4
62.336:    PCI: 00:18.5
62.337:    PCI: 00:19.0
62.337:    PCI: 00:19.1
62.337:    PCI: 00:19.2
62.337:    PCI: 00:19.3
62.337:    PCI: 00:19.4
62.337:    PCI: 00:19.5
62.337:    PCI: 00:1a.0
62.337:    PCI: 00:1a.1
62.337:    PCI: 00:1a.2
62.337:    PCI: 00:1a.3
62.337:    PCI: 00:1a.4
62.337:    PCI: 00:1a.5
62.337:    PCI: 00:1b.0
62.337:    PCI: 00:1b.1
62.337:    PCI: 00:1b.2
62.337:    PCI: 00:1b.3
62.337:    PCI: 00:1b.4
62.337:    PCI: 00:1b.5
62.337: DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
62.337: PCI: 00:18.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
62.337: PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
62.337: PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
62.337: PCI: 00:04.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
62.337: PCI: 00:04.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
62.337: PCI: 00:09.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
62.337: PCI: 03:00.0 18 *  [0x0 - 0x1f] io
62.337: PCI: 00:09.0 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
62.337: PCI: 00:0a.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
62.337: PCI: 04:00.0 18 *  [0x0 - 0x1f] io
62.337: PCI: 00:0a.0 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
62.337: PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
62.337: PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
62.337: PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
62.337: PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
62.337: PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
62.337: PCI: 07:00.0 18 *  [0x0 - 0x1f] io
62.337: PCI: 07:00.1 18 *  [0x20 - 0x3f] io
62.337: PCI: 00:0d.0 io: base: 40 size: 1000 align: 12 gran: 12 limit: ffff done
62.337: PCI: 00:14.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
62.337: PCI: 08:01.0 18 *  [0x0 - 0x7f] io
62.337: PCI: 00:14.4 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done
62.337: PCI: 00:09.0 1c *  [0x0 - 0xfff] io
62.337: PCI: 00:0a.0 1c *  [0x1000 - 0x1fff] io
62.337: PCI: 00:0d.0 1c *  [0x2000 - 0x2fff] io
62.337: PCI: 00:14.4 1c *  [0x3000 - 0x3fff] io
62.337: PCI: 00:11.0 20 *  [0x4000 - 0x400f] io
62.337: PCI: 00:14.1 20 *  [0x4010 - 0x401f] io
62.337: PCI: 00:11.0 10 *  [0x4020 - 0x4027] io
62.337: PCI: 00:11.0 18 *  [0x4028 - 0x402f] io
62.337: PCI: 00:14.1 10 *  [0x4030 - 0x4037] io
62.337: PCI: 00:14.1 18 *  [0x4038 - 0x403f] io
62.337: PCI: 00:11.0 14 *  [0x4040 - 0x4043] io
62.337: PCI: 00:11.0 1c *  [0x4044 - 0x4047] io
62.337: PCI: 00:14.1 14 *  [0x4048 - 0x404b] io
62.337: PCI: 00:14.1 1c *  [0x404c - 0x404f] io
62.337: PCI: 00:18.0 io: base: 4050 size: 5000 align: 12 gran: 12 limit: ffff done
62.338: PCI: 00:18.0 110d8 *  [0x0 - 0x4fff] io
62.338: DOMAIN: 0000 io: base: 5000 size: 5000 align: 12 gran: 0 limit: ffff done
62.338: DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
62.338: PCI: 00:18.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
62.338: PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
62.338: PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
62.338: PCI: 00:04.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
62.338: PCI: 00:04.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
62.338: PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
62.338: PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
62.338: PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
62.338: PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
62.338: PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
62.338: PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
62.338: PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
62.338: PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
62.338: PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
62.338: PCI: 07:00.0 10 *  [0x0 - 0x7ffff] prefmem
62.338: PCI: 07:00.1 10 *  [0x80000 - 0xfffff] prefmem
62.338: PCI: 07:00.0 20 *  [0x100000 - 0x103fff] prefmem
62.338: PCI: 07:00.1 20 *  [0x104000 - 0x107fff] prefmem
62.338: PCI: 00:0d.0 prefmem: base: 108000 size: 200000 align: 20 gran: 20 limit: ffffffffffffffff done
62.338: PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
62.338: PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
62.338: PCI: 00:0d.0 24 *  [0x0 - 0x1fffff] prefmem
62.338: PCI: 00:00.0 fc *  [0x200000 - 0x2000ff] prefmem
62.338: PCI: 00:18.0 prefmem: base: 200100 size: 300000 align: 20 gran: 20 limit: ffffffff done
62.338: PCI: 00:18.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
62.338: PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
62.338: PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
62.338: PCI: 00:04.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
62.338: PCI: 00:04.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
62.338: PCI: 00:09.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
62.338: PCI: 03:00.0 10 *  [0x0 - 0x1ffff] mem
62.338: PCI: 03:00.0 1c *  [0x20000 - 0x23fff] mem
62.338: PCI: 00:09.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
62.338: PCI: 00:0a.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
62.338: PCI: 04:00.0 10 *  [0x0 - 0x1ffff] mem
62.338: PCI: 04:00.0 1c *  [0x20000 - 0x23fff] mem
62.338: PCI: 00:0a.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
62.338: PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
62.338: PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
62.338: PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
62.338: PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
62.338: PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
62.338: PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
62.338: PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
62.338: PCI: 08:01.0 10 *  [0x0 - 0x7fffff] mem
62.338: PCI: 08:01.0 14 *  [0x800000 - 0x81ffff] mem
62.338: PCI: 08:02.0 10 *  [0x820000 - 0x820fff] mem
62.338: PCI: 00:14.4 mem: base: 821000 size: 900000 align: 23 gran: 20 limit: ffffffff done
62.338: PCI: 00:14.4 20 *  [0x0 - 0x8fffff] mem
62.338: PCI: 00:09.0 20 *  [0x900000 - 0x9fffff] mem
62.338: PCI: 00:0a.0 20 *  [0xa00000 - 0xafffff] mem
62.338: PCI: 00:00.2 44 *  [0xb00000 - 0xb03fff] mem
62.338: PCI: 00:14.2 10 *  [0xb04000 - 0xb07fff] mem
62.338: PCI: 00:12.0 10 *  [0xb08000 - 0xb08fff] mem
62.338: PCI: 00:12.1 10 *  [0xb09000 - 0xb09fff] mem
62.338: PCI: 00:13.0 10 *  [0xb0a000 - 0xb0afff] mem
62.338: PCI: 00:13.1 10 *  [0xb0b000 - 0xb0bfff] mem
62.338: PCI: 00:14.5 10 *  [0xb0c000 - 0xb0cfff] mem
62.338: PCI: 00:11.0 24 *  [0xb0d000 - 0xb0d3ff] mem
62.338: PCI: 00:12.2 10 *  [0xb0e000 - 0xb0e0ff] mem
62.338: PCI: 00:13.2 10 *  [0xb0f000 - 0xb0f0ff] mem
62.338: PCI: 00:14.3 a0 *  [0xb10000 - 0xb10000] mem
62.338: PCI: 00:18.0 mem: base: b10001 size: c00000 align: 23 gran: 20 limit: ffffffff done
62.338: PCI: 00:18.3 94 *  [0x0 - 0x3ffffff] mem
62.338: PCI: 00:18.0 110b8 *  [0x4000000 - 0x4bfffff] mem
62.338: PCI: 00:18.0 110b0 *  [0x4c00000 - 0x4efffff] prefmem
62.338: DOMAIN: 0000 mem: base: 4f00000 size: 4f00000 align: 26 gran: 0 limit: ffffffff done
62.338: avoid_fixed_resources: DOMAIN: 0000
62.338: avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
62.338: avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
62.338: constrain_resources: DOMAIN: 0000 c0010058 base c0000000 limit cfffffff mem (fixed)
62.338: constrain_resources: DOMAIN: 0000 07 base 00000000 limit bfffffff mem (fixed)
62.338: constrain_resources: DOMAIN: 0000 08 base 4038000000 limit 403fffffff mem (fixed)
62.338: constrain_resources: PCI: 00:14.0 74 base fec00000 limit fec00fff mem (fixed)
62.338: constrain_resources: PCI: 00:14.0 b4 base fed00000 limit fed003ff mem (fixed)
62.338: constrain_resources: PCI: 00:14.0 90 base 00000b00 limit 00000b0f io (fixed)
62.338: constrain_resources: PCI: 00:14.0 58 base 00000b20 limit 00000b2f io (fixed)
62.338: constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed)
62.338: constrain_resources: PCI: 00:14.3 10000100 base ff800000 limit ffffffff mem (fixed)
62.338: avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff
62.338: avoid_fixed_resources:@DOMAIN: 0000 10000100 base f8000000 limit ffffffff
62.338: Setting resources...
62.338: DOMAIN: 0000 io: base:1000 size:5000 align:12 gran:0 limit:ffff
62.338: PCI: 00:18.0 110d8 *  [0x1000 - 0x5fff] io
62.338: DOMAIN: 0000 io: next_base: 6000 size: 5000 align: 12 gran: 0 done
62.338: PCI: 00:18.0 io: base:1000 size:5000 align:12 gran:12 limit:5fff
62.338: PCI: 00:09.0 1c *  [0x1000 - 0x1fff] io
62.338: PCI: 00:0a.0 1c *  [0x2000 - 0x2fff] io
62.338: PCI: 00:0d.0 1c *  [0x3000 - 0x3fff] io
62.338: PCI: 00:14.4 1c *  [0x4000 - 0x4fff] io
62.338: PCI: 00:11.0 20 *  [0x5000 - 0x500f] io
62.338: PCI: 00:14.1 20 *  [0x5010 - 0x501f] io
62.338: PCI: 00:11.0 10 *  [0x5020 - 0x5027] io
62.338: PCI: 00:11.0 18 *  [0x5028 - 0x502f] io
62.338: PCI: 00:14.1 10 *  [0x5030 - 0x5037] io
62.338: PCI: 00:14.1 18 *  [0x5038 - 0x503f] io
62.339: PCI: 00:11.0 14 *  [0x5040 - 0x5043] io
62.338: PCI: 00:11.0 1c *  [0x5044 - 0x5047] io
62.338: PCI: 00:14.1 14 *  [0x5048 - 0x504b] io
62.338: PCI: 00:14.1 1c *  [0x504c - 0x504f] io
62.339: PCI: 00:18.0 io: next_base: 5050 size: 5000 align: 12 gran: 12 done
62.339: PCI: 00:02.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
62.339: PCI: 00:02.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
62.339: PCI: 00:04.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
62.339: PCI: 00:04.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
62.339: PCI: 00:09.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff
62.339: PCI: 03:00.0 18 *  [0x1000 - 0x101f] io
62.339: PCI: 00:09.0 io: next_base: 1020 size: 1000 align: 12 gran: 12 done
62.339: PCI: 00:0a.0 io: base:2000 size:1000 align:12 gran:12 limit:2fff
62.339: PCI: 04:00.0 18 *  [0x2000 - 0x201f] io
62.339: PCI: 00:0a.0 io: next_base: 2020 size: 1000 align: 12 gran: 12 done
62.339: PCI: 00:0b.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
62.339: PCI: 00:0b.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
62.339: PCI: 00:0c.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
62.339: PCI: 00:0c.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
62.339: PCI: 00:0d.0 io: base:3000 size:1000 align:12 gran:12 limit:3fff
62.339: PCI: 07:00.0 18 *  [0x3000 - 0x301f] io
62.339: PCI: 07:00.1 18 *  [0x3020 - 0x303f] io
62.339: PCI: 00:0d.0 io: next_base: 3040 size: 1000 align: 12 gran: 12 done
62.339: PCI: 00:14.4 io: base:4000 size:1000 align:12 gran:12 limit:4fff
62.339: PCI: 08:01.0 18 *  [0x4000 - 0x407f] io
62.339: PCI: 00:14.4 io: next_base: 4080 size: 1000 align: 12 gran: 12 done
62.339: DOMAIN: 0000 mem: base:f8000000 size:4f00000 align:26 gran:0 limit:ffffffff
62.339: PCI: 00:18.3 94 *  [0xf8000000 - 0xfbffffff] mem
62.339: PCI: 00:18.0 110b8 *  [0xfc000000 - 0xfcbfffff] mem
62.339: PCI: 00:18.0 110b0 *  [0xfcc00000 - 0xfcefffff] prefmem
62.339: DOMAIN: 0000 mem: next_base: fcf00000 size: 4f00000 align: 26 gran: 0 done
62.339: PCI: 00:18.0 prefmem: base:fcc00000 size:300000 align:20 gran:20 limit:fcefffff
62.339: PCI: 00:0d.0 24 *  [0xfcc00000 - 0xfcdfffff] prefmem
62.339: PCI: 00:00.0 fc *  [0xfce00000 - 0xfce000ff] prefmem
62.339: PCI: 00:18.0 prefmem: next_base: fce00100 size: 300000 align: 20 gran: 20 done
62.339: PCI: 00:02.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
62.339: PCI: 00:02.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
62.339: PCI: 00:04.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
62.339: PCI: 00:04.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
62.339: PCI: 00:09.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
62.339: PCI: 00:09.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
62.339: PCI: 00:0a.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
62.339: PCI: 00:0a.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
62.339: PCI: 00:0b.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
62.339: PCI: 00:0b.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
62.339: PCI: 00:0c.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
62.339: PCI: 00:0c.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
62.339: PCI: 00:0d.0 prefmem: base:fcc00000 size:200000 align:20 gran:20 limit:fcdfffff
62.339: PCI: 07:00.0 10 *  [0xfcc00000 - 0xfcc7ffff] prefmem
62.339: PCI: 07:00.1 10 *  [0xfcc80000 - 0xfccfffff] prefmem
62.339: PCI: 07:00.0 20 *  [0xfcd00000 - 0xfcd03fff] prefmem
62.339: PCI: 07:00.1 20 *  [0xfcd04000 - 0xfcd07fff] prefmem
62.339: PCI: 00:0d.0 prefmem: next_base: fcd08000 size: 200000 align: 20 gran: 20 done
62.339: PCI: 00:14.4 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
62.339: PCI: 00:14.4 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
62.339: PCI: 00:18.0 mem: base:fc000000 size:c00000 align:23 gran:20 limit:fcbfffff
62.339: PCI: 00:14.4 20 *  [0xfc000000 - 0xfc8fffff] mem
62.339: PCI: 00:09.0 20 *  [0xfc900000 - 0xfc9fffff] mem
62.339: PCI: 00:0a.0 20 *  [0xfca00000 - 0xfcafffff] mem
62.339: PCI: 00:00.2 44 *  [0xfcb00000 - 0xfcb03fff] mem
62.339: PCI: 00:14.2 10 *  [0xfcb04000 - 0xfcb07fff] mem
62.339: PCI: 00:12.0 10 *  [0xfcb08000 - 0xfcb08fff] mem
62.339: PCI: 00:12.1 10 *  [0xfcb09000 - 0xfcb09fff] mem
62.339: PCI: 00:13.0 10 *  [0xfcb0a000 - 0xfcb0afff] mem
62.339: PCI: 00:13.1 10 *  [0xfcb0b000 - 0xfcb0bfff] mem
62.339: PCI: 00:14.5 10 *  [0xfcb0c000 - 0xfcb0cfff] mem
62.339: PCI: 00:11.0 24 *  [0xfcb0d000 - 0xfcb0d3ff] mem
62.339: PCI: 00:12.2 10 *  [0xfcb0e000 - 0xfcb0e0ff] mem
62.339: PCI: 00:13.2 10 *  [0xfcb0f000 - 0xfcb0f0ff] mem
62.339: PCI: 00:14.3 a0 *  [0xfcb10000 - 0xfcb10000] mem
62.339: PCI: 00:18.0 mem: next_base: fcb10001 size: c00000 align: 23 gran: 20 done
62.339: PCI: 00:02.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
62.339: PCI: 00:02.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
62.339: PCI: 00:04.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
62.339: PCI: 00:04.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
62.339: PCI: 00:09.0 mem: base:fc900000 size:100000 align:20 gran:20 limit:fc9fffff
62.339: PCI: 03:00.0 10 *  [0xfc900000 - 0xfc91ffff] mem
62.339: PCI: 03:00.0 1c *  [0xfc920000 - 0xfc923fff] mem
62.339: PCI: 00:09.0 mem: next_base: fc924000 size: 100000 align: 20 gran: 20 done
62.339: PCI: 00:0a.0 mem: base:fca00000 size:100000 align:20 gran:20 limit:fcafffff
62.339: PCI: 04:00.0 10 *  [0xfca00000 - 0xfca1ffff] mem
62.339: PCI: 04:00.0 1c *  [0xfca20000 - 0xfca23fff] mem
62.339: PCI: 00:0a.0 mem: next_base: fca24000 size: 100000 align: 20 gran: 20 done
62.339: PCI: 00:0b.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
62.339: PCI: 00:0b.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
62.339: PCI: 00:0c.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
62.339: PCI: 00:0c.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
62.339: PCI: 00:0d.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
62.339: PCI: 00:0d.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
62.339: PCI: 00:14.4 mem: base:fc000000 size:900000 align:23 gran:20 limit:fc8fffff
62.339: PCI: 08:01.0 10 *  [0xfc000000 - 0xfc7fffff] mem
62.339: PCI: 08:01.0 14 *  [0xfc800000 - 0xfc81ffff] mem
62.339: PCI: 08:02.0 10 *  [0xfc820000 - 0xfc820fff] mem
62.339: PCI: 00:14.4 mem: next_base: fc821000 size: 900000 align: 23 gran: 20 done
62.339: Root Device assign_resources, bus 0 link: 0
62.339: 0: mmio_basek=00300000, basek=00400000, limitk=04100000
62.339: 1: mmio_basek=00300000, basek=04100000, limitk=08100000
62.339: 2: mmio_basek=00300000, basek=08100000, limitk=0c100000
62.339: 3: mmio_basek=00300000, basek=0c100000, limitk=10100000
62.339: DOMAIN: 0000 assign_resources, bus 0 link: 0
62.339: VGA: PCI: 00:18.0 (aka node 0) link 1 has VGA device
62.339: PCI: 00:18.0 111b8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem <node 0 link 1>
62.339: PCI: 00:18.0 110b0 <- [0x00fcc00000 - 0x00fcefffff] size 0x00300000 gran 0x14 prefmem <node 0 link 1>
62.339: PCI: 00:18.0 110b8 <- [0x00fc000000 - 0x00fcbfffff] size 0x00c00000 gran 0x14 mem <node 0 link 1>
62.339: PCI: 00:18.0 110d8 <- [0x0000001000 - 0x0000005fff] size 0x00005000 gran 0x0c io <node 0 link 1>
62.339: PCI: 00:18.0 assign_resources, bus 0 link: 1
62.339: PCI: 00:00.0 sr5690_set_resources
62.339: sr5690_set_resources: PCI: 00:00.0[0x1c] base = c0000000 limit = cfffffff
62.339: PCI: 00:00.0 c0010058 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x00 mem <mmconfig>
62.339: sr5690_set_resources: PCI: 00:18.1 <- index a8 base c00003 limit cfff90
62.339: PCI: 00:00.0 fc <- [0x00fce00000 - 0x00fce000ff] size 0x00000100 gran 0x08 prefmem
62.340: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.340: CBFS: Locating 'cmos_layout.bin'
62.340: CBFS: Found @ offset 2b0c0 size e88
62.340: PCI: 00:00.2 44 <- [0x00fcb00000 - 0x00fcb03fff] size 0x00004000 gran 0x0e mem
62.340: PCI: 00:02.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 01 io
62.340: PCI: 00:02.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 01 prefmem
62.340: PCI: 00:02.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 01 mem
62.340: PCI: 00:04.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 02 io
62.340: PCI: 00:04.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 02 prefmem
62.340: PCI: 00:04.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 02 mem
62.340: PCI: 00:09.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io
62.340: PCI: 00:09.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 03 prefmem
62.340: PCI: 00:09.0 20 <- [0x00fc900000 - 0x00fc9fffff] size 0x00100000 gran 0x14 bus 03 mem
62.340: PCI: 00:09.0 assign_resources, bus 3 link: 0
62.340: PCI: 03:00.0 10 <- [0x00fc900000 - 0x00fc91ffff] size 0x00020000 gran 0x11 mem
62.340: PCI: 03:00.0 18 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io
62.340: PCI: 03:00.0 1c <- [0x00fc920000 - 0x00fc923fff] size 0x00004000 gran 0x0e mem
62.340: PCI: 00:09.0 assign_resources, bus 3 link: 0
62.340: PCI: 00:0a.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 04 io
62.340: PCI: 00:0a.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 04 prefmem
62.340: PCI: 00:0a.0 20 <- [0x00fca00000 - 0x00fcafffff] size 0x00100000 gran 0x14 bus 04 mem
62.340: PCI: 00:0a.0 assign_resources, bus 4 link: 0
62.340: PCI: 04:00.0 10 <- [0x00fca00000 - 0x00fca1ffff] size 0x00020000 gran 0x11 mem
62.340: PCI: 04:00.0 18 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io
62.340: PCI: 04:00.0 1c <- [0x00fca20000 - 0x00fca23fff] size 0x00004000 gran 0x0e mem
62.340: PCI: 00:0a.0 assign_resources, bus 4 link: 0
62.340: PCI: 00:0b.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 05 io
62.340: PCI: 00:0b.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 05 prefmem
62.340: PCI: 00:0b.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 05 mem
62.340: PCI: 00:0c.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 06 io
62.340: PCI: 00:0c.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 06 prefmem
62.340: PCI: 00:0c.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 06 mem
62.340: PCI: 00:0d.0 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 07 io
62.340: PCI: 00:0d.0 24 <- [0x00fcc00000 - 0x00fcdfffff] size 0x00200000 gran 0x14 bus 07 prefmem
62.340: PCI: 00:0d.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 07 mem
62.340: PCI: 00:0d.0 assign_resources, bus 7 link: 0
62.340: PCI: 07:00.0 10 <- [0x00fcc00000 - 0x00fcc7ffff] size 0x00080000 gran 0x13 prefmem64
62.340: PCI: 07:00.0 18 <- [0x0000003000 - 0x000000301f] size 0x00000020 gran 0x05 io
62.340: PCI: 07:00.0 20 <- [0x00fcd00000 - 0x00fcd03fff] size 0x00004000 gran 0x0e prefmem64
62.340: PCI: 07:00.1 10 <- [0x00fcc80000 - 0x00fccfffff] size 0x00080000 gran 0x13 prefmem64
62.340: PCI: 07:00.1 18 <- [0x0000003020 - 0x000000303f] size 0x00000020 gran 0x05 io
62.340: PCI: 07:00.1 20 <- [0x00fcd04000 - 0x00fcd07fff] size 0x00004000 gran 0x0e prefmem64
62.340: PCI: 00:0d.0 assign_resources, bus 7 link: 0
62.340: PCI: 00:11.0 10 <- [0x0000005020 - 0x0000005027] size 0x00000008 gran 0x03 io
62.340: PCI: 00:11.0 14 <- [0x0000005040 - 0x0000005043] size 0x00000004 gran 0x02 io
62.340: PCI: 00:11.0 18 <- [0x0000005028 - 0x000000502f] size 0x00000008 gran 0x03 io
62.341: PCI: 00:11.0 1c <- [0x0000005044 - 0x0000005047] size 0x00000004 gran 0x02 io
62.340: PCI: 00:11.0 20 <- [0x0000005000 - 0x000000500f] size 0x00000010 gran 0x04 io
62.340: PCI: 00:11.0 24 <- [0x00fcb0d000 - 0x00fcb0d3ff] size 0x00000400 gran 0x0a mem
62.340: PCI: 00:12.0 10 <- [0x00fcb08000 - 0x00fcb08fff] size 0x00001000 gran 0x0c mem
62.340: PCI: 00:12.1 10 <- [0x00fcb09000 - 0x00fcb09fff] size 0x00001000 gran 0x0c mem
62.341: PCI: 00:12.2 10 <- [0x00fcb0e000 - 0x00fcb0e0ff] size 0x00000100 gran 0x08 mem
62.341: PCI: 00:13.0 10 <- [0x00fcb0a000 - 0x00fcb0afff] size 0x00001000 gran 0x0c mem
62.341: PCI: 00:13.1 10 <- [0x00fcb0b000 - 0x00fcb0bfff] size 0x00001000 gran 0x0c mem
62.341: PCI: 00:13.2 10 <- [0x00fcb0f000 - 0x00fcb0f0ff] size 0x00000100 gran 0x08 mem
62.341: PCI: 00:14.0 assign_resources, bus 1 link: 0
62.341: PCI: 00:14.0 assign_resources, bus 1 link: 0
62.341: PCI: 00:14.1 10 <- [0x0000005030 - 0x0000005037] size 0x00000008 gran 0x03 io
62.341: PCI: 00:14.1 14 <- [0x0000005048 - 0x000000504b] size 0x00000004 gran 0x02 io
62.341: PCI: 00:14.1 18 <- [0x0000005038 - 0x000000503f] size 0x00000008 gran 0x03 io
62.341: PCI: 00:14.1 1c <- [0x000000504c - 0x000000504f] size 0x00000004 gran 0x02 io
62.341: PCI: 00:14.1 20 <- [0x0000005010 - 0x000000501f] size 0x00000010 gran 0x04 io
62.341: PCI: 00:14.2 10 <- [0x00fcb04000 - 0x00fcb07fff] size 0x00004000 gran 0x0e mem64
62.341: PCI: 00:14.3 a0 <- [0x00fcb10000 - 0x00fcb10000] size 0x00000001 gran 0x00 mem
62.341: PCI: 00:14.3 assign_resources, bus 0 link: 0
62.341: PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
62.341: PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
62.341: PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
62.341: PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
62.341: PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
62.341: PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
62.341: PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
62.341: PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
62.341: PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io
62.341: ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned
62.341: PCI: 00:14.3 assign_resources, bus 0 link: 0
62.341: PCI: 00:14.4 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 08 io
62.341: PCI: 00:14.4 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 08 prefmem
62.341: PCI: 00:14.4 20 <- [0x00fc000000 - 0x00fc8fffff] size 0x00900000 gran 0x14 bus 08 mem
62.341: PCI: 00:14.4 assign_resources, bus 8 link: 0
62.341: PCI: 08:01.0 10 <- [0x00fc000000 - 0x00fc7fffff] size 0x00800000 gran 0x17 mem
62.341: PCI: 08:01.0 14 <- [0x00fc800000 - 0x00fc81ffff] size 0x00020000 gran 0x11 mem
62.341: PCI: 08:01.0 18 <- [0x0000004000 - 0x000000407f] size 0x00000080 gran 0x07 io
62.341: PCI: 08:02.0 10 <- [0x00fc820000 - 0x00fc820fff] size 0x00001000 gran 0x0c mem
62.341: PCI: 00:14.4 assign_resources, bus 8 link: 0
62.341: PCI: 00:14.5 10 <- [0x00fcb0c000 - 0x00fcb0cfff] size 0x00001000 gran 0x0c mem
62.341: PCI: 00:18.0 assign_resources, bus 0 link: 1
62.341: PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
62.341: PCI: 00:19.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
62.341: PCI: 00:1a.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
62.341: PCI: 00:1b.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
62.341: DOMAIN: 0000 assign_resources, bus 0 link: 0
62.341: Root Device assign_resources, bus 0 link: 0
62.341: Done setting resources.
62.341: Show resources in subtree (Root Device)...After assigning values.
62.341:  Root Device child on link 0 CPU_CLUSTER: 0
62.341:   CPU_CLUSTER: 0 child on link 0 APIC: 00
62.341:    APIC: 00
62.341:    APIC: 01
62.341:    APIC: 02
62.341:    APIC: 03
62.341:    APIC: 04
62.341:    APIC: 05
62.341:    APIC: 06
62.341:    APIC: 07
62.341:    APIC: 08
62.341:    APIC: 09
62.341:    APIC: 0a
62.341:    APIC: 0b
62.341:    APIC: 0c
62.342:    APIC: 0d
62.342:    APIC: 0e
62.342:    APIC: 0f
62.342:    APIC: 20
62.342:    APIC: 21
62.342:    APIC: 22
62.342:    APIC: 23
62.342:    APIC: 24
62.342:    APIC: 25
62.342:    APIC: 26
62.342:    APIC: 27
62.342:    APIC: 28
62.342:    APIC: 29
62.342:    APIC: 2a
62.342:    APIC: 2b
62.342:    APIC: 2c
62.342:    APIC: 2d
62.342:    APIC: 2e
62.342:    APIC: 2f
62.342:   DOMAIN: 0000 child on link 0 PCI: 00:18.0
62.342:   DOMAIN: 0000 resource base 1000 size 5000 align 12 gran 0 limit ffff flags 40040100 index 10000000
62.342:   DOMAIN: 0000 resource base f8000000 size 4f00000 align 26 gran 0 limit ffffffff flags 40040200 index 10000100
62.342:   DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
62.342:   DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7
62.342:   DOMAIN: 0000 resource base 4038000000 size 8000000 align 0 gran 0 limit 0 flags f0004200 index 8
62.342:   DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
62.342:   DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20
62.342:   DOMAIN: 0000 resource base 100000000 size f40000000 align 0 gran 0 limit 0 flags e0004200 index 30
62.342:   DOMAIN: 0000 resource base 1040000000 size 1000000000 align 0 gran 0 limit 0 flags e0004200 index 41
62.342:   DOMAIN: 0000 resource base 2040000000 size 1000000000 align 0 gran 0 limit 0 flags e0004200 index 52
62.342:   DOMAIN: 0000 resource base 3040000000 size 1000000000 align 0 gran 0 limit 0 flags e0004200 index 63
62.342:    PCI: 00:18.0
62.342:    PCI: 00:18.0 resource base fcc00000 size 300000 align 20 gran 20 limit fcefffff flags 60081200 index 110b0
62.342:    PCI: 00:18.0 resource base fc000000 size c00000 align 23 gran 20 limit fcbfffff flags 60080200 index 110b8
62.342:    PCI: 00:18.0 resource base 1000 size 5000 align 12 gran 12 limit 5fff flags 60080100 index 110d8
62.342:    PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags e0000200 index 111b8
62.342:     PCI: 00:00.0
62.342:     PCI: 00:00.0 resource base fce00000 size 100 align 12 gran 8 limit fce000ff flags 60001200 index fc
62.342:     PCI: 00:00.1
62.342:     PCI: 00:00.2
62.342:     PCI: 00:00.2 resource base fcb00000 size 4000 align 14 gran 14 limit fcb03fff flags 70000200 index 44
62.342:     PCI: 00:02.0
62.342:     PCI: 00:02.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
62.342:     PCI: 00:02.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
62.342:     PCI: 00:02.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
62.342:     PCI: 00:03.0
62.342:     PCI: 00:04.0
62.342:     PCI: 00:04.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
62.342:     PCI: 00:04.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
62.342:     PCI: 00:04.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
62.342:     PCI: 00:05.0
62.342:     PCI: 00:06.0
62.343:     PCI: 00:07.0
62.343:     PCI: 00:08.0
62.343:     PCI: 00:09.0 child on link 0 PCI: 03:00.0
62.343:     PCI: 00:09.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c
62.343:     PCI: 00:09.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
62.343:     PCI: 00:09.0 resource base fc900000 size 100000 align 20 gran 20 limit fc9fffff flags 60080202 index 20
62.343:      PCI: 03:00.0
62.343:      PCI: 03:00.0 resource base fc900000 size 20000 align 17 gran 17 limit fc91ffff flags 60000200 index 10
62.343:      PCI: 03:00.0 resource base 1000 size 20 align 5 gran 5 limit 101f flags 60000100 index 18
62.343:      PCI: 03:00.0 resource base fc920000 size 4000 align 14 gran 14 limit fc923fff flags 60000200 index 1c
62.343:     PCI: 00:0a.0 child on link 0 PCI: 04:00.0
62.343:     PCI: 00:0a.0 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c
62.343:     PCI: 00:0a.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
62.343:     PCI: 00:0a.0 resource base fca00000 size 100000 align 20 gran 20 limit fcafffff flags 60080202 index 20
62.343:      PCI: 04:00.0
62.343:      PCI: 04:00.0 resource base fca00000 size 20000 align 17 gran 17 limit fca1ffff flags 60000200 index 10
62.343:      PCI: 04:00.0 resource base 2000 size 20 align 5 gran 5 limit 201f flags 60000100 index 18
62.343:      PCI: 04:00.0 resource base fca20000 size 4000 align 14 gran 14 limit fca23fff flags 60000200 index 1c
62.343:     PCI: 00:0b.0
62.343:     PCI: 00:0b.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
62.343:     PCI: 00:0b.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
62.343:     PCI: 00:0b.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
62.343:     PCI: 00:0c.0
62.343:     PCI: 00:0c.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
62.343:     PCI: 00:0c.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
62.343:     PCI: 00:0c.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
62.343:     PCI: 00:0d.0 child on link 0 PCI: 07:00.0
62.343:     PCI: 00:0d.0 resource base 3000 size 1000 align 12 gran 12 limit 3fff flags 60080102 index 1c
62.343:     PCI: 00:0d.0 resource base fcc00000 size 200000 align 20 gran 20 limit fcdfffff flags 60081202 index 24
62.343:     PCI: 00:0d.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
62.343:      PCI: 07:00.0
62.343:      PCI: 07:00.0 resource base fcc00000 size 80000 align 19 gran 19 limit fcc7ffff flags 60001201 index 10
62.343:      PCI: 07:00.0 resource base 3000 size 20 align 5 gran 5 limit 301f flags 60000100 index 18
62.343:      PCI: 07:00.0 resource base fcd00000 size 4000 align 14 gran 14 limit fcd03fff flags 60001201 index 20
62.343:      PCI: 07:00.1
62.343:      PCI: 07:00.1 resource base fcc80000 size 80000 align 19 gran 19 limit fccfffff flags 60001201 index 10
62.343:      PCI: 07:00.1 resource base 3020 size 20 align 5 gran 5 limit 303f flags 60000100 index 18
62.343:      PCI: 07:00.1 resource base fcd04000 size 4000 align 14 gran 14 limit fcd07fff flags 60001201 index 20
62.343:     PCI: 00:11.0
62.343:     PCI: 00:11.0 resource base 5020 size 8 align 3 gran 3 limit 5027 flags 60000100 index 10
62.343:     PCI: 00:11.0 resource base 5040 size 4 align 2 gran 2 limit 5043 flags 60000100 index 14
62.343:     PCI: 00:11.0 resource base 5028 size 8 align 3 gran 3 limit 502f flags 60000100 index 18
62.343:     PCI: 00:11.0 resource base 5044 size 4 align 2 gran 2 limit 5047 flags 60000100 index 1c
62.343:     PCI: 00:11.0 resource base 5000 size 10 align 4 gran 4 limit 500f flags 60000100 index 20
62.343:     PCI: 00:11.0 resource base fcb0d000 size 400 align 12 gran 10 limit fcb0d3ff flags 60000200 index 24
62.343:     PCI: 00:12.0
62.343:     PCI: 00:12.0 resource base fcb08000 size 1000 align 12 gran 12 limit fcb08fff flags 60000200 index 10
62.343:     PCI: 00:12.1
62.343:     PCI: 00:12.1 resource base fcb09000 size 1000 align 12 gran 12 limit fcb09fff flags 60000200 index 10
62.343:     PCI: 00:12.2
62.343:     PCI: 00:12.2 resource base fcb0e000 size 100 align 12 gran 8 limit fcb0e0ff flags 60000200 index 10
62.343:     PCI: 00:13.0
62.343:     PCI: 00:13.0 resource base fcb0a000 size 1000 align 12 gran 12 limit fcb0afff flags 60000200 index 10
62.343:     PCI: 00:13.1
62.343:     PCI: 00:13.1 resource base fcb0b000 size 1000 align 12 gran 12 limit fcb0bfff flags 60000200 index 10
62.343:     PCI: 00:13.2
62.343:     PCI: 00:13.2 resource base fcb0f000 size 100 align 12 gran 8 limit fcb0f0ff flags 60000200 index 10
62.343:     PCI: 00:14.0 child on link 0 I2C: 01:50
62.343:     PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
62.343:     PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c
62.343:     PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
62.343:     PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
62.343:     PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58
62.343:      I2C: 01:50
62.343:      I2C: 01:51
62.343:      I2C: 01:52
62.343:      I2C: 01:53
62.343:      I2C: 01:54
62.343:      I2C: 01:55
62.343:      I2C: 01:56
62.344:      I2C: 01:57
62.344:      I2C: 01:2f
62.344:     PCI: 00:14.1
62.344:     PCI: 00:14.1 resource base 5030 size 8 align 3 gran 3 limit 5037 flags 60000100 index 10
62.344:     PCI: 00:14.1 resource base 5048 size 4 align 2 gran 2 limit 504b flags 60000100 index 14
62.344:     PCI: 00:14.1 resource base 5038 size 8 align 3 gran 3 limit 503f flags 60000100 index 18
62.344:     PCI: 00:14.1 resource base 504c size 4 align 2 gran 2 limit 504f flags 60000100 index 1c
62.344:     PCI: 00:14.1 resource base 5010 size 10 align 4 gran 4 limit 501f flags 60000100 index 20
62.344:     PCI: 00:14.2
62.344:     PCI: 00:14.2 resource base fcb04000 size 4000 align 14 gran 14 limit fcb07fff flags 60000201 index 10
62.344:     PCI: 00:14.3 child on link 0 PNP: 002e.0
62.344:     PCI: 00:14.3 resource base fcb10000 size 1 align 12 gran 0 limit fcb10000 flags 60000200 index a0
62.344:     PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
62.344:     PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
62.344:     PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
62.344:      PNP: 002e.0
62.344:      PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
62.344:      PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
62.344:      PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
62.344:      PNP: 002e.1
62.344:      PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
62.344:      PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
62.344:      PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
62.344:      PNP: 002e.2
62.344:      PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
62.344:      PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
62.344:      PNP: 002e.3
62.344:      PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
62.344:      PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
62.344:      PNP: 002e.5
62.344:      PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
62.344:      PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
62.344:      PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
62.344:      PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72
62.344:      PNP: 002e.106
62.344:      PNP: 002e.106 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
62.344:      PNP: 002e.107
62.344:      PNP: 002e.207
62.344:      PNP: 002e.307
62.344:      PNP: 002e.407
62.344:      PNP: 002e.8
62.344:      PNP: 002e.108
62.344:      PNP: 002e.9
62.344:      PNP: 002e.109
62.344:      PNP: 002e.209
62.344:      PNP: 002e.309
62.344:      PNP: 002e.a
62.344:      PNP: 002e.b
62.344:      PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags e0000100 index 60
62.344:      PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
62.344:      PNP: 002e.c
62.344:      PNP: 002e.d
62.344:      PNP: 002e.f
62.344:      PNP: 004e.0
62.345:     PCI: 00:14.4 child on link 0 PCI: 08:01.0
62.345:     PCI: 00:14.4 resource base 4000 size 1000 align 12 gran 12 limit 4fff flags 60080102 index 1c
62.345:     PCI: 00:14.4 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
62.345:     PCI: 00:14.4 resource base fc000000 size 900000 align 23 gran 20 limit fc8fffff flags 60080202 index 20
62.345:      PCI: 08:01.0
62.345:      PCI: 08:01.0 resource base fc000000 size 800000 align 23 gran 23 limit fc7fffff flags 60000200 index 10
62.345:      PCI: 08:01.0 resource base fc800000 size 20000 align 17 gran 17 limit fc81ffff flags 60000200 index 14
62.345:      PCI: 08:01.0 resource base 4000 size 80 align 7 gran 7 limit 407f flags 60000100 index 18
62.345:      PCI: 08:01.0 resource base a0000 size 1fc00 align 0 gran 0 limit 0 flags f0000200 index 3
62.345:      PCI: 08:02.0
62.345:      PCI: 08:02.0 resource base fc820000 size 1000 align 12 gran 12 limit fc820fff flags 60000200 index 10
62.345:      PCI: 08:03.0
62.345:     PCI: 00:14.5
62.345:     PCI: 00:14.5 resource base fcb0c000 size 1000 align 12 gran 12 limit fcb0cfff flags 60000200 index 10
62.345:    PCI: 00:18.1
62.345:    PCI: 00:18.2
62.345:    PCI: 00:18.3
62.345:    PCI: 00:18.3 resource base f8000000 size 4000000 align 26 gran 26 limit fbffffff flags 60000200 index 94
62.345:    PCI: 00:18.4
62.345:    PCI: 00:18.5
62.345:    PCI: 00:19.0
62.345:    PCI: 00:19.1
62.345:    PCI: 00:19.2
62.345:    PCI: 00:19.3
62.345:    PCI: 00:19.4
62.345:    PCI: 00:19.5
62.345:    PCI: 00:1a.0
62.345:    PCI: 00:1a.1
62.345:    PCI: 00:1a.2
62.345:    PCI: 00:1a.3
62.345:    PCI: 00:1a.4
62.345:    PCI: 00:1a.5
62.345:    PCI: 00:1b.0
62.345:    PCI: 00:1b.1
62.345:    PCI: 00:1b.2
62.345:    PCI: 00:1b.3
62.345:    PCI: 00:1b.4
62.345:    PCI: 00:1b.5
62.345: Done allocating resources.
62.345: BS: BS_DEV_RESOURCES times (us): entry 0 run 3292370 exit 0
62.345: Enabling resources...
62.345: PCI: 00:18.0 cmd <- 00
62.345: PCI: 00:18.1 subsystem <- 1043/8163
62.346: PCI: 00:18.1 cmd <- 00
62.346: PCI: 00:18.2 subsystem <- 1043/8163
62.346: PCI: 00:18.2 cmd <- 00
62.346: PCI: 00:18.3 cmd <- 00
62.346: PCI: 00:18.4 cmd <- 00
62.346: PCI: 00:18.5 cmd <- 00
62.346: PCI: 00:19.0 cmd <- 00
62.346: PCI: 00:19.1 subsystem <- 1043/8163
62.346: PCI: 00:19.1 cmd <- 00
62.346: PCI: 00:19.2 subsystem <- 1043/8163
62.346: PCI: 00:19.2 cmd <- 00
62.346: PCI: 00:19.3 cmd <- 00
62.346: PCI: 00:19.4 cmd <- 00
62.346: PCI: 00:19.5 cmd <- 00
62.346: PCI: 00:1a.0 cmd <- 00
62.346: PCI: 00:1a.1 subsystem <- 1043/8163
62.346: PCI: 00:1a.1 cmd <- 00
62.346: PCI: 00:1a.2 subsystem <- 1043/8163
62.346: PCI: 00:1a.2 cmd <- 00
62.346: PCI: 00:1a.3 cmd <- 00
62.346: PCI: 00:1a.4 cmd <- 00
62.346: PCI: 00:1a.5 cmd <- 00
62.346: PCI: 00:1b.0 cmd <- 00
62.346: PCI: 00:1b.1 subsystem <- 1043/8163
62.346: PCI: 00:1b.1 cmd <- 00
62.346: PCI: 00:1b.2 subsystem <- 1043/8163
62.346: PCI: 00:1b.2 cmd <- 00
62.346: PCI: 00:1b.3 cmd <- 00
62.346: PCI: 00:1b.4 cmd <- 00
62.346: PCI: 00:1b.5 cmd <- 00
62.346: PCI: 00:00.0 subsystem <- 1043/8163
62.346: PCI: 00:00.0 cmd <- 02
62.346: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.346: CBFS: Locating 'cmos_layout.bin'
62.346: CBFS: Found @ offset 2b0c0 size e88
62.347: Initializing IOMMU
62.347: PCI: 00:02.0 bridge ctrl <- 0003
62.347: PCI: 00:02.0 cmd <- 00
62.347: PCI: 00:04.0 bridge ctrl <- 0003
62.347: PCI: 00:04.0 cmd <- 00
62.347: PCI: 00:09.0 bridge ctrl <- 0003
62.347: PCI: 00:09.0 cmd <- 07
62.347: PCI: 00:0a.0 bridge ctrl <- 0003
62.347: PCI: 00:0a.0 cmd <- 07
62.347: PCI: 00:0b.0 bridge ctrl <- 0003
62.347: PCI: 00:0b.0 cmd <- 00
62.347: PCI: 00:0c.0 bridge ctrl <- 0003
62.347: PCI: 00:0c.0 cmd <- 00
62.347: PCI: 00:0d.0 bridge ctrl <- 0003
62.347: PCI: 00:0d.0 cmd <- 07
62.347: PCI: 00:11.0 subsystem <- 1043/8163
62.347: PCI: 00:11.0 cmd <- 03
62.347: PCI: 00:12.0 subsystem <- 1043/8163
62.347: PCI: 00:12.0 cmd <- 02
62.347: PCI: 00:12.1 subsystem <- 1043/8163
62.347: PCI: 00:12.1 cmd <- 02
62.347: PCI: 00:12.2 subsystem <- 1043/8163
62.347: PCI: 00:12.2 cmd <- 02
62.347: PCI: 00:13.0 subsystem <- 1043/8163
62.347: PCI: 00:13.0 cmd <- 02
62.347: PCI: 00:13.1 subsystem <- 1043/8163
62.347: PCI: 00:13.1 cmd <- 02
62.347: PCI: 00:13.2 subsystem <- 1043/8163
62.347: PCI: 00:13.2 cmd <- 02
62.347: PCI: 00:14.0 subsystem <- 1043/8163
62.347: PCI: 00:14.0 cmd <- 403
62.347: PCI: 00:14.1 subsystem <- 1043/8163
62.347: PCI: 00:14.1 cmd <- 01
62.347: PCI: 00:14.2 subsystem <- 1043/8163
62.347: PCI: 00:14.2 cmd <- 02
62.347: PCI: 00:14.3 subsystem <- 1043/8163
62.347: PCI: 00:14.3 cmd <- 0f
62.347: sb700 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff
62.347: sb700 lpc decode:PNP: 002e.3, base=0x000002f8, end=0x000002ff
62.347: sb700 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060
62.347: sb700 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064
62.347: sb700 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000291
62.347: PCI: 00:14.4 bridge ctrl <- 000b
62.347: PCI: 00:14.4 cmd <- 07
62.347: PCI: 00:14.5 subsystem <- 1043/8163
62.347: PCI: 00:14.5 cmd <- 02
62.347: PCI: 03:00.0 cmd <- 03
62.347: PCI: 04:00.0 cmd <- 03
62.347: PCI: 07:00.0 cmd <- 03
62.347: PCI: 07:00.1 cmd <- 03
62.347: PCI: 08:01.0 cmd <- 03
62.347: PCI: 08:02.0 subsystem <- 1043/8163
62.347: PCI: 08:02.0 cmd <- 02
62.347: done.
62.347: BS: BS_DEV_ENABLE times (us): entry 0 run 178661 exit 0
62.348: Initializing devices...
62.347: Root Device init ...
62.347: Root Device init finished in 1398 usecs
62.348: CPU_CLUSTER: 0 init ...
62.348: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.348: CBFS: Locating 'cmos_layout.bin'
62.348: CBFS: Found @ offset 2b0c0 size e88
62.348: Enabling probe filter
62.353: Enabling ATM mode
62.353: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.353: CBFS: Locating 'cmos_layout.bin'
62.353: CBFS: Found @ offset 2b0c0 size e88
62.354: start_eip=0x00001000, code_size=0x00000031
62.354: CPU1: stack_base 00150000, stack_end 00150ff8
62.354: Asserting INIT.
62.354: Waiting for send to finish...
62.354: +Deasserting INIT.
62.354: Waiting for send to finish...
62.354: +#startup loops: 1.
62.354: Sending STARTUP #1 to 1.
62.354: After apic_write.
62.354: Initializing CPU #1
62.354: Startup point 1.
62.354: Waiting for send to finish...
62.354: +CPU: vendor AMD device 600f12
62.354: After Startup.
62.354: CPU: family 15, model 01, stepping 02
62.354: CPU2: stack_base 0014f000, stack_end 0014fff8
62.354: nodeid = 00, coreid = 01
62.354: Asserting INIT.
62.354: Enabling cache
62.354: Waiting for send to finish...
62.354: +Deasserting INIT.
62.355: Waiting for send to finish...
62.355: +#startup loops: 1.
62.355: Sending STARTUP #1 to 2.
62.355: After apic_write.
62.355: Initializing CPU #2
62.355: Startup point 1.
62.355: Waiting for send to finish...
62.355: +CPU: vendor AMD device 600f12
62.355: After Startup.
62.355: CPU3: stack_base 0014e000, stack_end 0014eff8
62.355: CPU: family 15, model 01, stepping 02
62.355: Asserting INIT.
62.355: Waiting for send to finish...
62.355: +nodeid = 00, coreid = 02
62.355: Deasserting INIT.
62.355: Waiting for send to finish...
62.355: +Enabling cache
62.355: #startup loops: 1.
62.355: Sending STARTUP #1 to 3.
62.355: After apic_write.
62.355: CPU ID 0x80000001: 600f12
62.355: Startup point 1.
62.355: Waiting for send to finish...
62.355: +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
62.355: After Startup.
62.355: CPU4: stack_base 0014d000, stack_end 0014dff8
62.355: Initializing CPU #3
62.355: MTRR: Physical address space:
62.355: Asserting INIT.
62.355: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
62.355: Waiting for send to finish...
62.355: +CPU: vendor AMD device 600f12
62.355: Deasserting INIT.
62.355: CPU: family 15, model 01, stepping 02
62.355: Waiting for send to finish...
62.355: +nodeid = 00, coreid = 03
62.355: #startup loops: 1.
62.355: Sending STARTUP #1 to 4.
62.355: After apic_write.
62.355: Enabling cache
62.355: 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
62.355: 0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6
62.355: Startup point 1.
62.355: Waiting for send to finish...
62.355: +0x00000000c0000000 - 0x0000000100000000 size 0x40000000 type 0
62.356: 0x0000000100000000 - 0x0000004040000000 size 0x3f40000000 type 6
62.356: Initializing CPU #4
62.356: After Startup.
62.356: CPU: vendor AMD device 600f12
62.356: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
62.356: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
62.356: CPU5: stack_base 0014c000, stack_end 0014cff8
62.356: MTRR: Fixed MSR 0x259 0x0000000000000000
62.356: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
62.356: Asserting INIT.
62.356: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
62.356: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
62.356: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
62.356: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
62.356: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
62.356: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
62.356: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
62.356: Waiting for send to finish...
62.356: +CPU: family 15, model 01, stepping 02
62.356: Deasserting INIT.
62.356: MTRR: default type WB/UC MTRR counts: 1/2.
62.356: MTRR: WB selected as default type.
62.356: Waiting for send to finish...
62.356: MTRR: 0 base 0x00000000c0000000 mask 0x0000ffffc0000000 type 0
62.356: +nodeid = 00, coreid = 04
62.356: #startup loops: 1.
62.356: 
62.356: MTRR check
62.356: Sending STARTUP #1 to 5.
62.356: After apic_write.
62.356: Fixed MTRRs   : Enabled
62.356: Variable MTRRs: Startup point 1.
62.356: Waiting for send to finish...
62.356: Enabled
62.356: 
62.356: +Initializing CPU #5
62.356: After Startup.
62.356: Enabling cache
62.356: CPU6: stack_base 0014b000, stack_end 0014bff8
62.356: Setting up local APIC...Asserting INIT.
62.356:  apic_id: 0x02 done.
62.356: Waiting for send to finish...
62.356: +CPU model: AMD Opteron(tm) Processor 6278
62.356: Deasserting INIT.
62.356: siblings = 15, Waiting for send to finish...
62.356: +Disabling SMM ASeg memory
62.356: #startup loops: 1.
62.356: Sending STARTUP #1 to 6.
62.356: After apic_write.
62.356: CPU #2 initialized
62.356: Startup point 1.
62.356: Waiting for send to finish...
62.356: +
62.356: MTRR check
62.356: Fixed MTRRs   : Enabled
62.356: Variable MTRRs: Enabled
62.357: 
62.357: After Startup.
62.357: CPU7: stack_base 0014a000, stack_end 0014aff8
62.357: Setting up local APIC...Asserting INIT.
62.357:  apic_id: 0x03 done.
62.357: Waiting for send to finish...
62.357: CPU model: AMD Opteron(tm) Processor 6278
62.357: +siblings = 15, Deasserting INIT.
62.357: Disabling SMM ASeg memory
62.357: Waiting for send to finish...
62.357: +CPU #3 initialized
62.357: #startup loops: 1.
62.357: Sending STARTUP #1 to 7.
62.357: CPU: vendor AMD device 600f12
62.357: Initializing CPU #6
62.357: After apic_write.
62.357: CPU: family 15, model 01, stepping 02
62.357: Startup point 1.
62.357: Waiting for send to finish...
62.357: +CPU: vendor AMD device 600f12
62.357: After Startup.
62.357: CPU8: stack_base 00149000, stack_end 00149ff8
62.357: CPU: family 15, model 01, stepping 02
62.357: Asserting INIT.
62.357: Initializing CPU #7
62.357: Waiting for send to finish...
62.357: +nodeid = 00, coreid = 06
62.357: Deasserting INIT.
62.357: nodeid = 00, coreid = 05
62.357: CPU ID 0x80000001: 600f12
62.357: Waiting for send to finish...
62.357: +Enabling cache
62.357: #startup loops: 1.
62.357: Sending STARTUP #1 to 8.
62.357: After apic_write.
62.357: CPU: vendor AMD device 600f12
62.357: Startup point 1.
62.357: Waiting for send to finish...
62.357: +Enabling cache
62.357: After Startup.
62.357: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
62.357: CPU9: stack_base 00148000, stack_end 00148ff8
62.357: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
62.357: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
62.357: MTRR: Fixed MSR 0x259 0x0000000000000000
62.357: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
62.357: Asserting INIT.
62.357: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
62.357: Waiting for send to finish...
62.357: +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
62.357: Deasserting INIT.
62.357: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
62.357: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
62.357: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
62.357: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
62.358: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
62.357: Waiting for send to finish...
62.358: +Initializing CPU #8
62.358: #startup loops: 1.
62.358: Sending STARTUP #1 to 9.
62.358: 
62.358: MTRR check
62.358: Fixed MTRRs   : Enabled
62.358: After apic_write.
62.358: Variable MTRRs: Enabled
62.358: 
62.358: Startup point 1.
62.358: Waiting for send to finish...
62.358: +Setting up local APIC...After Startup.
62.358: CPU10: stack_base 00147000, stack_end 00147ff8
62.358:  apic_id: 0x04 done.
62.358: Asserting INIT.
62.358: CPU model: AMD Opteron(tm) Processor 6278
62.358: Waiting for send to finish...
62.358: +siblings = 15, Deasserting INIT.
62.358: Disabling SMM ASeg memory
62.358: Waiting for send to finish...
62.358: +
62.358: MTRR check
62.358: Fixed MTRRs   : Enabled
62.358: Variable MTRRs: #startup loops: 1.
62.358: CPU #4 initialized
62.358: Sending STARTUP #1 to 10.
62.358: Enabled
62.358: 
62.358: After apic_write.
62.358: CPU: family 15, model 01, stepping 02
62.358: Startup point 1.
62.358: Setting up local APIC...Waiting for send to finish...
62.358: + apic_id: 0x05 done.
62.358: After Startup.
62.358: CPU11: stack_base 00146000, stack_end 00146ff8
62.358: CPU model: AMD Opteron(tm) Processor 6278
62.358: Asserting INIT.
62.358: siblings = 15, Waiting for send to finish...
62.358: +Disabling SMM ASeg memory
62.358: Deasserting INIT.
62.358: CPU #5 initialized
62.358: Waiting for send to finish...
62.358: +nodeid = 00, coreid = 07
62.358: #startup loops: 1.
62.358: Sending STARTUP #1 to 11.
62.358: After apic_write.
62.358: Enabling cache
62.358: Initializing CPU #9
62.358: CPU ID 0x80000001: 600f12
62.359: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
62.358: Startup point 1.
62.359: Waiting for send to finish...
62.359: +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
62.359: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
62.359: MTRR: Fixed MSR 0x259 0x0000000000000000
62.359: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
62.359: After Startup.
62.359: CPU12: stack_base 00145000, stack_end 00145ff8
62.359: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
62.359: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
62.359: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
62.359: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
62.359: Asserting INIT.
62.359: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
62.359: Waiting for send to finish...
62.359: +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
62.359: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
62.359: Deasserting INIT.
62.359: Waiting for send to finish...
62.359: +CPU: vendor AMD device 600f12
62.359: #startup loops: 1.
62.359: 
62.359: MTRR check
62.359: Fixed MTRRs   : Enabled
62.359: Variable MTRRs: Enabled
62.359: 
62.359: Sending STARTUP #1 to 12.
62.359: After apic_write.
62.359: Setting up local APIC...Startup point 1.
62.359: Waiting for send to finish...
62.359:  apic_id: 0x06 done.
62.359: +CPU model: AMD Opteron(tm) Processor 6278
62.359: After Startup.
62.359: CPU13: stack_base 00144000, stack_end 00144ff8
62.359: siblings = 15, Asserting INIT.
62.359: Disabling SMM ASeg memory
62.359: Waiting for send to finish...
62.359: +
62.359: MTRR check
62.359: Deasserting INIT.
62.359: Fixed MTRRs   : Enabled
62.359: Waiting for send to finish...
62.359: CPU #6 initialized
62.359: +Variable MTRRs: Enabled
62.359: 
62.359: #startup loops: 1.
62.359: Sending STARTUP #1 to 13.
62.359: Setting up local APIC...After apic_write.
62.359:  apic_id: 0x07 done.
62.359: Startup point 1.
62.359: CPU model: AMD Opteron(tm) Processor 6278
62.359: Waiting for send to finish...
62.359: +siblings = 15, After Startup.
62.359: Disabling SMM ASeg memory
62.360: CPU14: stack_base 00143000, stack_end 00143ff8
62.360: CPU #7 initialized
62.360: Asserting INIT.
62.360: Waiting for send to finish...
62.360: +Initializing CPU #10
62.360: Deasserting INIT.
62.360: Waiting for send to finish...
62.360: +Initializing CPU #11
62.360: #startup loops: 1.
62.360: Sending STARTUP #1 to 14.
62.360: After apic_write.
62.360: CPU: family 15, model 01, stepping 02
62.360: Startup point 1.
62.360: Waiting for send to finish...
62.360: +Initializing CPU #14
62.360: After Startup.
62.360: CPU15: stack_base 00142000, stack_end 00142ff8
62.360: CPU: vendor AMD device 600f12
62.360: Asserting INIT.
62.360: Initializing CPU #12
62.360: Waiting for send to finish...
62.360: +CPU: vendor AMD device 600f12
62.360: Deasserting INIT.
62.360: Waiting for send to finish...
62.360: +nodeid = 01, coreid = 00
62.360: #startup loops: 1.
62.360: Sending STARTUP #1 to 15.
62.360: After apic_write.
62.360: CPU: vendor AMD device 600f12
62.360: Startup point 1.
62.360: Waiting for send to finish...
62.360: +Initializing CPU #15
62.360: After Startup.
62.360: CPU16: stack_base 00141000, stack_end 00141ff8
62.360: CPU: family 15, model 01, stepping 02
62.360: Asserting INIT.
62.360: CPU: family 15, model 01, stepping 02
62.360: Waiting for send to finish...
62.360: +CPU: family 15, model 01, stepping 02
62.360: Deasserting INIT.
62.360: Waiting for send to finish...
62.360: +CPU: vendor AMD device 600f12
62.360: #startup loops: 1.
62.360: Sending STARTUP #1 to 32.
62.360: After apic_write.
62.360: CPU: family 15, model 01, stepping 02
62.361: Startup point 1.
62.361: Waiting for send to finish...
62.361: +Initializing CPU #16
62.361: After Startup.
62.361: CPU17: stack_base 00140000, stack_end 00140ff8
62.361: CPU: vendor AMD device 600f12
62.361: Asserting INIT.
62.361: Enabling cache
62.361: Waiting for send to finish...
62.361: +nodeid = 01, coreid = 02
62.361: CPU ID 0x80000001: 600f12
62.361: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
62.361: Deasserting INIT.
62.361: CPU: vendor AMD device 600f12
62.361: Waiting for send to finish...
62.361: +nodeid = 01, coreid = 01
62.361: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
62.361: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
62.361: MTRR: Fixed MSR 0x259 0x0000000000000000
62.361: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
62.361: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
62.361: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
62.361: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
62.361: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
62.361: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
62.361: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
62.361: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
62.361: #startup loops: 1.
62.361: Sending STARTUP #1 to 33.
62.361: After apic_write.
62.361: CPU: family 15, model 01, stepping 02
62.361: Startup point 1.
62.361: Waiting for send to finish...
62.361: +Initializing CPU #13
62.361: 
62.361: MTRR check
62.361: Fixed MTRRs   : Enabled
62.361: Variable MTRRs: Enabled
62.361: 
62.361: After Startup.
62.361: CPU18: stack_base 0013f000, stack_end 0013fff8
62.361: nodeid = 01, coreid = 03
62.361: Asserting INIT.
62.361: Enabling cache
62.361: Setting up local APIC...Waiting for send to finish...
62.361: + apic_id: 0x08 done.
62.361: Deasserting INIT.
62.361: CPU model: AMD Opteron(tm) Processor 6278
62.361: Waiting for send to finish...
62.361: +siblings = 15, #startup loops: 1.
62.361: Disabling SMM ASeg memory
62.362: Sending STARTUP #1 to 34.
62.362: CPU #8 initialized
62.362: After apic_write.
62.362: 
62.362: MTRR check
62.362: Fixed MTRRs   : Enabled
62.362: Variable MTRRs: Enabled
62.362: 
62.362: Startup point 1.
62.362: Waiting for send to finish...
62.362: +Setting up local APIC...After Startup.
62.362: CPU19: stack_base 0013e000, stack_end 0013eff8
62.362:  apic_id: 0x09 done.
62.362: Asserting INIT.
62.362: CPU model: AMD Opteron(tm) Processor 6278
62.362: Waiting for send to finish...
62.362: +siblings = 15, Deasserting INIT.
62.362: Disabling SMM ASeg memory
62.362: Waiting for send to finish...
62.362: +CPU #9 initialized
62.362: #startup loops: 1.
62.362: Sending STARTUP #1 to 35.
62.362: After apic_write.
62.362: Initializing CPU #17
62.362: Startup point 1.
62.362: Waiting for send to finish...
62.362: +nodeid = 01, coreid = 07
62.362: After Startup.
62.362: CPU20: stack_base 0013d000, stack_end 0013dff8
62.362: Initializing CPU #19
62.362: Asserting INIT.
62.362: CPU: vendor AMD device 600f12
62.362: Waiting for send to finish...
62.362: +CPU: family 15, model 01, stepping 02
62.362: Deasserting INIT.
62.362: Enabling cache
62.362: Waiting for send to finish...
62.362: +CPU: family 15, model 01, stepping 02
62.362: #startup loops: 1.
62.362: Sending STARTUP #1 to 36.
62.362: After apic_write.
62.362: Initializing CPU #18
62.362: Startup point 1.
62.362: Waiting for send to finish...
62.362: +nodeid = 01, coreid = 06
62.362: After Startup.
62.362: CPU21: stack_base 0013c000, stack_end 0013cff8
62.363: Enabling cache
62.363: Asserting INIT.
62.363: Waiting for send to finish...
62.363: CPU ID 0x80000001: 600f12
62.363: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
62.363: +CPU: vendor AMD device 600f12
62.363: Deasserting INIT.
62.363: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
62.363: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
62.363: MTRR: Fixed MSR 0x259 0x0000000000000000
62.363: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
62.363: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
62.363: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
62.363: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
62.363: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
62.363: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
62.363: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
62.363: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
62.363: Waiting for send to finish...
62.363: +Enabling cache
62.363: #startup loops: 1.
62.363: Sending STARTUP #1 to 37.
62.363: After apic_write.
62.363: 
62.363: MTRR check
62.363: Fixed MTRRs   : Enabled
62.363: Variable MTRRs: Enabled
62.363: 
62.363: Startup point 1.
62.363: Waiting for send to finish...
62.363: +Setting up local APIC...Enabling cache
62.363: After Startup.
62.363: CPU22: stack_base 0013b000, stack_end 0013bff8
62.363:  apic_id: 0x0e done.
62.363: CPU ID 0x80000001: 600f12
62.363: CPU model: AMD Opteron(tm) Processor 6278
62.363: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
62.363: Asserting INIT.
62.363: siblings = 15, Waiting for send to finish...
62.363: +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
62.363: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
62.363: MTRR: Fixed MSR 0x259 0x0000000000000000
62.363: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
62.363: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
62.363: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
62.363: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
62.363: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
62.363: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
62.363: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
62.363: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
62.363: Disabling SMM ASeg memory
62.363: Deasserting INIT.
62.363: CPU #14 initialized
62.363: Waiting for send to finish...
62.363: 
62.363: MTRR check
62.363: Fixed MTRRs   : Enabled
62.363: Variable MTRRs: Enabled
62.363: 
62.363: 
62.363: MTRR check
62.363: Fixed MTRRs   : Enabled
62.364: Variable MTRRs: Enabled
62.364: 
62.364: Setting up local APIC...+ apic_id: 0x0f done.
62.364: #startup loops: 1.
62.364: Sending STARTUP #1 to 38.
62.364: Setting up local APIC...CPU model: AMD Opteron(tm) Processor 6278
62.364:  apic_id: 0x0a done.
62.364: siblings = 15, After apic_write.
62.364: CPU model: AMD Opteron(tm) Processor 6278
62.364: Disabling SMM ASeg memory
62.364: siblings = 15, CPU #15 initialized
62.364: CPU: vendor AMD device 600f12
62.364: Disabling SMM ASeg memory
62.364: Startup point 1.
62.364: Waiting for send to finish...
62.364: +CPU #10 initialized
62.364: After Startup.
62.364: CPU23: stack_base 0013a000, stack_end 0013aff8
62.364: 
62.364: MTRR check
62.364: Asserting INIT.
62.364: Fixed MTRRs   : Enabled
62.364: Variable MTRRs: Enabled
62.364: 
62.364: Waiting for send to finish...
62.364: +Setting up local APIC...Deasserting INIT.
62.364:  apic_id: 0x0b done.
62.364: Waiting for send to finish...
62.364: +CPU model: AMD Opteron(tm) Processor 6278
62.364: #startup loops: 1.
62.364: Sending STARTUP #1 to 39.
62.364: siblings = 15, After apic_write.
62.364: Disabling SMM ASeg memory
62.364: Startup point 1.
62.364: Waiting for send to finish...
62.364: +CPU #11 initialized
62.364: After Startup.
62.364: CPU24: stack_base 00139000, stack_end 00139ff8
62.364: nodeid = 01, coreid = 04
62.364: Asserting INIT.
62.364: Initializing CPU #23
62.364: Waiting for send to finish...
62.364: +Initializing CPU #22
62.364: Deasserting INIT.
62.364: Waiting for send to finish...
62.364: +CPU: family 15, model 01, stepping 02
62.365: #startup loops: 1.
62.365: Sending STARTUP #1 to 40.
62.365: After apic_write.
62.365: nodeid = 02, coreid = 00
62.365: Startup point 1.
62.365: Waiting for send to finish...
62.365: +Initializing CPU #20
62.365: After Startup.
62.365: CPU25: stack_base 00138000, stack_end 00138ff8
62.365: CPU: vendor AMD device 600f12
62.365: Asserting INIT.
62.365: Waiting for send to finish...
62.365: +Initializing CPU #24
62.365: Deasserting INIT.
62.365: Waiting for send to finish...
62.365: +CPU: vendor AMD device 600f12
62.365: #startup loops: 1.
62.365: Sending STARTUP #1 to 41.
62.365: After apic_write.
62.365: Enabling cache
62.365: Startup point 1.
62.365: Waiting for send to finish...
62.365: +CPU: family 15, model 01, stepping 02
62.365: After Startup.
62.365: CPU26: stack_base 00137000, stack_end 00137ff8
62.365: Enabling cache
62.365: Asserting INIT.
62.365: nodeid = 01, coreid = 05
62.365: CPU ID 0x80000001: 600f12
62.365: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
62.365: Waiting for send to finish...
62.365: +Enabling cache
62.365: Deasserting INIT.
62.365: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
62.365: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
62.365: MTRR: Fixed MSR 0x259 0x0000000000000000
62.365: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
62.365: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
62.365: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
62.365: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
62.365: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
62.365: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
62.365: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
62.365: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
62.365: Waiting for send to finish...
62.365: +CPU: family 15, model 01, stepping 02
62.365: CPU ID 0x80000001: 600f12
62.365: #startup loops: 1.
62.365: 
62.365: MTRR check
62.365: Fixed MTRRs   : Enabled
62.366: Variable MTRRs: Enabled
62.366: 
62.366: Initializing CPU #25
62.366: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
62.366: Setting up local APIC...Sending STARTUP #1 to 42.
62.366: After apic_write.
62.366:  apic_id: 0x0c done.
62.366: Startup point 1.
62.366: CPU model: AMD Opteron(tm) Processor 6278
62.366: Initializing CPU #26
62.366: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
62.366: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
62.366: MTRR: Fixed MSR 0x259 0x0000000000000000
62.366: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
62.366: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
62.366: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
62.366: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
62.366: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
62.366: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
62.366: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
62.366: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
62.366: siblings = 15, Waiting for send to finish...
62.366: +Disabling SMM ASeg memory
62.366: After Startup.
62.366: CPU27: stack_base 00136000, stack_end 00136ff8
62.366: 
62.366: MTRR check
62.366: Fixed MTRRs   : Enabled
62.366: Variable MTRRs: Enabled
62.366: 
62.366: Asserting INIT.
62.366: CPU: vendor AMD device 600f12
62.366: 
62.366: MTRR check
62.366: Fixed MTRRs   : Enabled
62.366: Variable MTRRs: Enabled
62.366: 
62.366: Waiting for send to finish...
62.366: +CPU #12 initialized
62.366: Setting up local APIC...Deasserting INIT.
62.366:  apic_id: 0x0d done.
62.366: Waiting for send to finish...
62.366: +CPU model: AMD Opteron(tm) Processor 6278
62.366: #startup loops: 1.
62.366: Sending STARTUP #1 to 43.
62.366: After apic_write.
62.366: siblings = 15, Startup point 1.
62.366: Waiting for send to finish...
62.366: +Disabling SMM ASeg memory
62.366: After Startup.
62.366: CPU28: stack_base 00135000, stack_end 00135ff8
62.366: CPU #13 initialized
62.366: Asserting INIT.
62.367: CPU: vendor AMD device 600f12
62.367: Setting up local APIC...Waiting for send to finish...
62.367: +CPU: family 15, model 01, stepping 02
62.367:  apic_id: 0x20 done.
62.367: Deasserting INIT.
62.367: nodeid = 02, coreid = 01
62.367: Waiting for send to finish...
62.367: +CPU: vendor AMD device 600f12
62.367: CPU model: AMD Opteron(tm) Processor 6278
62.367: #startup loops: 1.
62.367: Sending STARTUP #1 to 44.
62.367: After apic_write.
62.367: CPU: family 15, model 01, stepping 02
62.367: Startup point 1.
62.367: Waiting for send to finish...
62.367: +CPU: family 15, model 01, stepping 02
62.367: siblings = 15, After Startup.
62.367: CPU29: stack_base 00134000, stack_end 00134ff8
62.367: Disabling SMM ASeg memory
62.367: Asserting INIT.
62.367: CPU: vendor AMD device 600f12
62.367: Waiting for send to finish...
62.367: +Enabling cache
62.367: nodeid = 02, coreid = 04
62.367: Deasserting INIT.
62.367: CPU #16 initialized
62.367: Waiting for send to finish...
62.367: +
62.367: MTRR check
62.367: Fixed MTRRs   : Enabled
62.367: Variable MTRRs: Enabled
62.367: 
62.367: #startup loops: 1.
62.367: Sending STARTUP #1 to 45.
62.367: After apic_write.
62.367: Setting up local APIC...Startup point 1.
62.367: Waiting for send to finish...
62.367: + apic_id: 0x21 done.
62.367: After Startup.
62.367: CPU model: AMD Opteron(tm) Processor 6278
62.367: CPU30: stack_base 00133000, stack_end 00133ff8
62.367: siblings = 15, Asserting INIT.
62.368: Disabling SMM ASeg memory
62.367: Waiting for send to finish...
62.368: +CPU #17 initialized
62.368: Deasserting INIT.
62.368: Waiting for send to finish...
62.368: +CPU: vendor AMD device 600f12
62.368: #startup loops: 1.
62.368: Sending STARTUP #1 to 46.
62.368: After apic_write.
62.368: nodeid = 03, coreid = 02
62.368: Startup point 1.
62.368: Waiting for send to finish...
62.368: +CPU: family 15, model 01, stepping 02
62.368: After Startup.
62.368: CPU31: stack_base 00132000, stack_end 00132ff8
62.368: Initializing CPU #28
62.368: Asserting INIT.
62.368: Waiting for send to finish...
62.368: +CPU: vendor AMD device 600f12
62.368: Deasserting INIT.
62.368: Waiting for send to finish...
62.368: +CPU: family 15, model 01, stepping 02
62.368: #startup loops: 1.
62.368: Sending STARTUP #1 to 47.
62.368: After apic_write.
62.368: Initializing CPU #30
62.368: Startup point 1.
62.368: Waiting for send to finish...
62.368: +Enabling cache
62.368: After Startup.
62.368: Initializing CPU #0
62.368: Initializing CPU #21
62.368: CPU: vendor AMD device 600f12
62.368: CPU: family 15, model 01, stepping 02
62.368: Enabling cache
62.368: CPU ID 0x80000001: 600f12
62.368: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
62.368: nodeid = 00, coreid = 00
62.368: Enabling cache
62.368: nodeid = 02, coreid = 07
62.368: CPU ID 0x80000001: 600f12
62.368: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
62.368: CPU ID 0x80000001: 600f12
62.368: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
62.368: Initializing CPU #27
62.368: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
62.368: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
62.368: MTRR: Fixed MSR 0x259 0x0000000000000000
62.368: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
62.368: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
62.368: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
62.368: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
62.368: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
62.368: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
62.369: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
62.369: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
62.369: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
62.369: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
62.369: MTRR: Fixed MSR 0x259 0x0000000000000000
62.369: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
62.369: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
62.369: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
62.369: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
62.369: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
62.369: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
62.369: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
62.369: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
62.369: nodeid = 03, coreid = 00
62.369: CPU: vendor AMD device 600f12
62.369: CPU: vendor AMD device 600f12
62.369: 
62.369: MTRR check
62.369: Fixed MTRRs   : Enabled
62.369: Variable MTRRs: Enabled
62.369: 
62.369: 
62.369: MTRR check
62.369: Fixed MTRRs   : Enabled
62.369: Variable MTRRs: Enabled
62.369: 
62.369: Initializing CPU #31
62.369: Setting up local APIC...Setting up local APIC...CPU: family 15, model 01, stepping 02
62.369:  apic_id: 0x00 done.
62.369: Enabling cache
62.369: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
62.369: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
62.369: MTRR: Fixed MSR 0x259 0x0000000000000000
62.369: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
62.369: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
62.369: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
62.369: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
62.369: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
62.369: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
62.369: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
62.369: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
62.369: CPU model: AMD Opteron(tm) Processor 6278
62.369: CPU: vendor AMD device 600f12
62.369: siblings = 15, CPU: family 15, model 01, stepping 02
62.369: 
62.369: MTRR check
62.369: Fixed MTRRs   : Enabled
62.369: Variable MTRRs: Enabled
62.369: 
62.369: Disabling SMM ASeg memory
62.369: nodeid = 02, coreid = 03
62.369: 
62.369: MTRR check
62.369: Fixed MTRRs   : Enabled
62.369: Variable MTRRs: Enabled
62.370: 
62.370: nodeid = 02, coreid = 05
62.370: Setting up local APIC...Setting up local APIC...CPU: family 15, model 01, stepping 02
62.370:  apic_id: 0x2a done.
62.370:  apic_id: 0x01 done.
62.370: CPU #0 initialized
62.370: Waiting for 15 CPUS to stop
62.370: CPU model: AMD Opteron(tm) Processor 6278
62.370: nodeid = 03, coreid = 03
62.370: siblings = 15, CPU: family 15, model 01, stepping 02
62.370:  apic_id: 0x24 done.
62.370: Disabling SMM ASeg memory
62.370: CPU: family 15, model 01, stepping 02
62.370: CPU model: AMD Opteron(tm) Processor 6278
62.370: CPU #1 initialized
62.370: nodeid = 02, coreid = 06
62.370: siblings = 15, Enabling cache
62.370: Waiting for 14 CPUS to stop
62.370: CPU ID 0x80000001: 600f12
62.370: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
62.370: Enabling cache
62.370: CPU model: AMD Opteron(tm) Processor 6278
62.370: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
62.370: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
62.370: MTRR: Fixed MSR 0x259 0x0000000000000000
62.370: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
62.370: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
62.370: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
62.370: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
62.370: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
62.370: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
62.370: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
62.370: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
62.370: siblings = 15, Enabling cache
62.370: Disabling SMM ASeg memory
62.370: Disabling SMM ASeg memory
62.370: 
62.370: MTRR check
62.370: Fixed MTRRs   : Enabled
62.370: Variable MTRRs: Enabled
62.370: 
62.370: CPU #26 initialized
62.370: 
62.370: MTRR check
62.370: Fixed MTRRs   : Enabled
62.370: Variable MTRRs: Enabled
62.370: 
62.370: 
62.370: MTRR check
62.370: Fixed MTRRs   : Enabled
62.370: Variable MTRRs: Enabled
62.371: 
62.371: Setting up local APIC...Setting up local APIC...CPU #20 initialized
62.371:  apic_id: 0x25 done.
62.371: Setting up local APIC... apic_id: 0x26 done.
62.371:  apic_id: 0x2b done.
62.371: CPU model: AMD Opteron(tm) Processor 6278
62.371: CPU model: AMD Opteron(tm) Processor 6278
62.371: CPU model: AMD Opteron(tm) Processor 6278
62.371: siblings = 15, Waiting for 13 CPUS to stop
62.371: siblings = 15, Disabling SMM ASeg memory
62.371: Disabling SMM ASeg memory
62.371: siblings = 15, Waiting for 12 CPUS to stop
62.371: CPU #27 initialized
62.371: CPU #21 initialized
62.371: Disabling SMM ASeg memory
62.371: Waiting for 11 CPUS to stop
62.371: CPU #22 initialized
62.371: Waiting for 10 CPUS to stop
62.371: 
62.371: MTRR check
62.371: Fixed MTRRs   : Enabled
62.371: Variable MTRRs: Enabled
62.371: 
62.371: Waiting for 9 CPUS to stop
62.371: Setting up local APIC...CPU: vendor AMD device 600f12
62.371:  apic_id: 0x27 done.
62.371: Initializing CPU #29
62.371: CPU model: AMD Opteron(tm) Processor 6278
62.371: Enabling cache
62.371: siblings = 15, CPU: vendor AMD device 600f12
62.371: Disabling SMM ASeg memory
62.371: CPU #23 initialized
62.371: CPU: family 15, model 01, stepping 02
62.371: Waiting for 8 CPUS to stop
62.371: nodeid = 02, coreid = 02
62.371: CPU: vendor AMD device 600f12
62.371: Enabling cache
62.371: nodeid = 03, coreid = 05
62.371: CPU: family 15, model 01, stepping 02
62.371: CPU ID 0x80000001: 600f12
62.371: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
62.371: nodeid = 03, coreid = 06
62.372: CPU: family 15, model 01, stepping 02
62.372: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
62.372: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
62.372: MTRR: Fixed MSR 0x259 0x0000000000000000
62.372: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
62.372: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
62.372: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
62.372: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
62.372: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
62.372: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
62.372: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
62.372: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
62.372: nodeid = 03, coreid = 04
62.372: Enabling cache
62.372: Enabling cache
62.372: nodeid = 03, coreid = 01
62.372: 
62.372: MTRR check
62.372: Fixed MTRRs   : Enabled
62.372: Variable MTRRs: Enabled
62.372: 
62.372: CPU ID 0x80000001: 600f12
62.372: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
62.372: Setting up local APIC...Enabling cache
62.372:  apic_id: 0x22 done.
62.372: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
62.372: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
62.372: MTRR: Fixed MSR 0x259 0x0000000000000000
62.372: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
62.372: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
62.372: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
62.372: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
62.372: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
62.372: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
62.372: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
62.372: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
62.372: CPU model: AMD Opteron(tm) Processor 6278
62.372: Enabling cache
62.372: siblings = 15, nodeid = 03, coreid = 07
62.372: 
62.372: MTRR check
62.372: Fixed MTRRs   : Enabled
62.372: Variable MTRRs: Enabled
62.372: 
62.372: Disabling SMM ASeg memory
62.372: Setting up local APIC...CPU #18 initialized
62.372: 
62.372: MTRR check
62.372: Fixed MTRRs   : Enabled
62.372: Variable MTRRs: Enabled
62.372: 
62.372:  apic_id: 0x2c done.
62.372: Waiting for 7 CPUS to stop
62.372: CPU model: AMD Opteron(tm) Processor 6278
62.372: Setting up local APIC...siblings = 15,  apic_id: 0x23 done.
62.373: Disabling SMM ASeg memory
62.373: CPU model: AMD Opteron(tm) Processor 6278
62.373: CPU #28 initialized
62.373: siblings = 15, Waiting for 6 CPUS to stop
62.373: 
62.373: MTRR check
62.373: Fixed MTRRs   : Enabled
62.373: Variable MTRRs: Enabled
62.373: 
62.373: Disabling SMM ASeg memory
62.373: Setting up local APIC...CPU #19 initialized
62.373:  apic_id: 0x2d done.
62.373: Waiting for 5 CPUS to stop
62.373: CPU model: AMD Opteron(tm) Processor 6278
62.373: Enabling cache
62.373: siblings = 15, CPU ID 0x80000001: 600f12
62.373: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
62.373: Disabling SMM ASeg memory
62.373: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
62.373: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
62.373: MTRR: Fixed MSR 0x259 0x0000000000000000
62.373: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
62.373: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
62.373: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
62.373: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
62.373: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
62.373: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
62.373: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
62.373: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
62.373: CPU #29 initialized
62.373: CPU ID 0x80000001: 600f12
62.373: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
62.373: Waiting for 4 CPUS to stop
62.373: 
62.373: MTRR check
62.373: Fixed MTRRs   : Enabled
62.373: Variable MTRRs: Enabled
62.373: 
62.373: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
62.373: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
62.373: MTRR: Fixed MSR 0x259 0x0000000000000000
62.373: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
62.373: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
62.373: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
62.373: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
62.373: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
62.373: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
62.373: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
62.373: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
62.373: Setting up local APIC... apic_id: 0x28 done.
62.373: CPU model: AMD Opteron(tm) Processor 6278
62.373: Enabling cache
62.373: siblings = 15, 
62.373: MTRR check
62.373: Fixed MTRRs   : Enabled
62.373: Variable MTRRs: Enabled
62.373: 
62.373: Disabling SMM ASeg memory
62.373: Setting up local APIC...CPU #24 initialized
62.373:  apic_id: 0x2e done.
62.374: 
62.374: MTRR check
62.374: Fixed MTRRs   : Enabled
62.374: Variable MTRRs: Enabled
62.374: 
62.374: CPU model: AMD Opteron(tm) Processor 6278
62.374: Waiting for 3 CPUS to stop
62.374: siblings = 15, Setting up local APIC...Disabling SMM ASeg memory
62.374:  apic_id: 0x29 done.
62.374: CPU #30 initialized
62.374: CPU model: AMD Opteron(tm) Processor 6278
62.374: 
62.374: MTRR check
62.374: Fixed MTRRs   : Enabled
62.374: Variable MTRRs: Enabled
62.374: 
62.374: siblings = 15, Waiting for 2 CPUS to stop
62.374: Disabling SMM ASeg memory
62.374: Setting up local APIC...CPU #25 initialized
62.374:  apic_id: 0x2f done.
62.374: Waiting for 1 CPUS to stop
62.374: CPU model: AMD Opteron(tm) Processor 6278
62.374: siblings = 15, Disabling SMM ASeg memory
62.374: CPU #31 initialized
62.374: All AP CPUs stopped (44850 loops)
62.374: CPU0: stack: 00151000 - 00152000, lowest used address 001519e0, stack used: 1568 bytes
62.374: CPU1: stack: 00150000 - 00151000, lowest used address 00150de8, stack used: 536 bytes
62.374: CPU2: stack: 0014f000 - 00150000, lowest used address 0014fcac, stack used: 852 bytes
62.374: CPU3: stack: 0014e000 - 0014f000, lowest used address 0014ede8, stack used: 536 bytes
62.374: CPU4: stack: 0014d000 - 0014e000, lowest used address 0014dd08, stack used: 760 bytes
62.374: CPU5: stack: 0014c000 - 0014d000, lowest used address 0014cde8, stack used: 536 bytes
62.374: CPU6: stack: 0014b000 - 0014c000, lowest used address 0014bd08, stack used: 760 bytes
62.374: CPU7: stack: 0014a000 - 0014b000, lowest used address 0014ade8, stack used: 536 bytes
62.374: CPU8: stack: 00149000 - 0014a000, lowest used address 00149d08, stack used: 760 bytes
62.374: CPU9: stack: 00148000 - 00149000, lowest used address 00148de8, stack used: 536 bytes
62.374: CPU10: stack: 00147000 - 00148000, lowest used address 00147d08, stack used: 760 bytes
62.374: CPU11: stack: 00146000 - 00147000, lowest used address 00146de8, stack used: 536 bytes
62.374: CPU12: stack: 00145000 - 00146000, lowest used address 00145d08, stack used: 760 bytes
62.375: CPU13: stack: 00144000 - 00145000, lowest used address 00144de8, stack used: 536 bytes
62.375: CPU14: stack: 00143000 - 00144000, lowest used address 00143d08, stack used: 760 bytes
62.375: CPU15: stack: 00142000 - 00143000, lowest used address 00142de8, stack used: 536 bytes
62.375: CPU16: stack: 00141000 - 00142000, lowest used address 00141d08, stack used: 760 bytes
62.375: CPU17: stack: 00140000 - 00141000, lowest used address 00140de8, stack used: 536 bytes
62.375: CPU18: stack: 0013f000 - 00140000, lowest used address 0013fd08, stack used: 760 bytes
62.375: CPU19: stack: 0013e000 - 0013f000, lowest used address 0013ede8, stack used: 536 bytes
62.375: CPU20: stack: 0013d000 - 0013e000, lowest used address 0013dd08, stack used: 760 bytes
62.375: CPU21: stack: 0013c000 - 0013d000, lowest used address 0013cde8, stack used: 536 bytes
62.375: CPU22: stack: 0013b000 - 0013c000, lowest used address 0013bd08, stack used: 760 bytes
62.375: CPU23: stack: 0013a000 - 0013b000, lowest used address 0013ade8, stack used: 536 bytes
62.375: CPU24: stack: 00139000 - 0013a000, lowest used address 00139d08, stack used: 760 bytes
62.375: CPU25: stack: 00138000 - 00139000, lowest used address 00138de8, stack used: 536 bytes
62.375: CPU26: stack: 00137000 - 00138000, lowest used address 00137d08, stack used: 760 bytes
62.375: CPU27: stack: 00136000 - 00137000, lowest used address 00136de8, stack used: 536 bytes
62.375: CPU28: stack: 00135000 - 00136000, lowest used address 00135d08, stack used: 760 bytes
62.375: CPU29: stack: 00134000 - 00135000, lowest used address 00134de8, stack used: 536 bytes
62.375: CPU30: stack: 00133000 - 00134000, lowest used address 00133d08, stack used: 760 bytes
62.375: CPU31: stack: 00132000 - 00133000, lowest used address 00132de8, stack used: 536 bytes
62.375: CPU_CLUSTER: 0 init finished in 2107935 usecs
62.375: PCI: 00:18.0 init ...
62.375: PCI: 00:18.0 init finished in 1461 usecs
62.375: PCI: 00:18.1 init ...
62.375: PCI: 00:18.1 init finished in 1462 usecs
62.375: PCI: 00:18.2 init ...
62.375: PCI: 00:18.2 init finished in 1462 usecs
62.375: PCI: 00:18.3 init ...
62.375: NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.375: CBFS: Locating 'cmos_layout.bin'
62.376: CBFS: Found @ offset 2b0c0 size e88
62.376: done.
62.376: PCI: 00:18.3 init finished in 12599 usecs
62.376: PCI: 00:18.4 init ...
62.376: NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.376: CBFS: Locating 'cmos_layout.bin'
62.376: CBFS: Found @ offset 2b0c0 size e88
62.377: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.377: CBFS: Locating 'cmos_layout.bin'
62.377: CBFS: Found @ offset 2b0c0 size e88
62.377: done.
62.377: PCI: 00:18.4 init finished in 21317 usecs
62.377: PCI: 00:18.5 init ...
62.377: NB: Function 5 Northbridge Control.. done.
62.378: PCI: 00:18.5 init finished in 4259 usecs
62.378: PCI: 00:19.0 init ...
62.378: PCI: 00:19.0 init finished in 1462 usecs
62.378: PCI: 00:19.1 init ...
62.378: PCI: 00:19.1 init finished in 1462 usecs
62.378: PCI: 00:19.2 init ...
62.378: PCI: 00:19.2 init finished in 1462 usecs
62.378: PCI: 00:19.3 init ...
62.378: NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.378: CBFS: Locating 'cmos_layout.bin'
62.378: CBFS: Found @ offset 2b0c0 size e88
62.378: done.
62.378: PCI: 00:19.3 init finished in 12593 usecs
62.378: PCI: 00:19.4 init ...
62.378: NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.378: CBFS: Locating 'cmos_layout.bin'
62.379: CBFS: Found @ offset 2b0c0 size e88
62.379: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.379: CBFS: Locating 'cmos_layout.bin'
62.379: CBFS: Found @ offset 2b0c0 size e88
62.380: done.
62.380: PCI: 00:19.4 init finished in 21329 usecs
62.380: PCI: 00:19.5 init ...
62.380: NB: Function 5 Northbridge Control.. done.
62.380: PCI: 00:19.5 init finished in 4260 usecs
62.380: PCI: 00:1a.0 init ...
62.380: PCI: 00:1a.0 init finished in 1462 usecs
62.380: PCI: 00:1a.1 init ...
62.380: PCI: 00:1a.1 init finished in 1461 usecs
62.380: PCI: 00:1a.2 init ...
62.380: PCI: 00:1a.2 init finished in 1461 usecs
62.380: PCI: 00:1a.3 init ...
62.380: NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.380: CBFS: Locating 'cmos_layout.bin'
62.380: CBFS: Found @ offset 2b0c0 size e88
62.381: done.
62.381: PCI: 00:1a.3 init finished in 12587 usecs
62.381: PCI: 00:1a.4 init ...
62.381: NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.381: CBFS: Locating 'cmos_layout.bin'
62.381: CBFS: Found @ offset 2b0c0 size e88
62.381: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.381: CBFS: Locating 'cmos_layout.bin'
62.381: CBFS: Found @ offset 2b0c0 size e88
62.382: done.
62.382: PCI: 00:1a.4 init finished in 21324 usecs
62.382: PCI: 00:1a.5 init ...
62.382: NB: Function 5 Northbridge Control.. done.
62.382: PCI: 00:1a.5 init finished in 4260 usecs
62.382: PCI: 00:1b.0 init ...
62.382: PCI: 00:1b.0 init finished in 1461 usecs
62.382: PCI: 00:1b.1 init ...
62.382: PCI: 00:1b.1 init finished in 1461 usecs
62.382: PCI: 00:1b.2 init ...
62.382: PCI: 00:1b.2 init finished in 1462 usecs
62.382: PCI: 00:1b.3 init ...
62.382: NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.382: CBFS: Locating 'cmos_layout.bin'
62.382: CBFS: Found @ offset 2b0c0 size e88
62.383: done.
62.383: PCI: 00:1b.3 init finished in 12587 usecs
62.383: PCI: 00:1b.4 init ...
62.383: NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.383: CBFS: Locating 'cmos_layout.bin'
62.383: CBFS: Found @ offset 2b0c0 size e88
62.384: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.384: CBFS: Locating 'cmos_layout.bin'
62.384: CBFS: Found @ offset 2b0c0 size e88
62.384: done.
62.384: PCI: 00:1b.4 init finished in 21317 usecs
62.384: PCI: 00:1b.5 init ...
62.384: NB: Function 5 Northbridge Control.. done.
62.384: PCI: 00:1b.5 init finished in 4260 usecs
62.384: PCI: 00:00.0 init ...
62.384: pcie_init in sr5650_ht.c
62.384: IOAPIC: Initializing IOAPIC at 0xfce00000
62.384: IOAPIC: Bootstrap Processor Local APIC = 0x00
62.384: IOAPIC: ID = 0x01
62.384: IOAPIC: Dumping registers
62.384:   reg 0x0000: 0x01000000
62.384:   reg 0x0001: 0x001f8021
62.384:   reg 0x0002: 0x00000000
62.384: IOAPIC: 32 interrupts
62.384: IOAPIC: Enabling interrupts on FSB
62.384: IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
62.384: IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
62.384: IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
62.384: IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
62.384: IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
62.384: IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x00000018 value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x00000019 value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x0000001a value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x0000001b value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x0000001c value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x0000001d value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x0000001e value 0x00000000 0x00010000
62.385: IOAPIC: reg 0x0000001f value 0x00000000 0x00010000
62.385: PCI: 00:00.0 init finished in 125721 usecs
62.385: PCI: 00:11.0 init ...
62.385: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.385: CBFS: Locating 'cmos_layout.bin'
62.385: CBFS: Found @ offset 2b0c0 size e88
62.385: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.385: CBFS: Locating 'cmos_layout.bin'
62.386: CBFS: Found @ offset 2b0c0 size e88
62.386: rev_id=15
62.386: sata_bar0=5020
62.386: sata_bar1=5040
62.386: sata_bar2=5028
62.386: sata_bar3=5044
62.386: sata_bar4=5000
62.386: sata_bar5=fcb0d000
62.386: ide_bar0=5030
62.386: ide_bar1=5048
62.386: ide_bar2=5038
62.386: ide_bar3=504c
62.386: Maximum SATA port count supported by silicon: 6
62.398: SATA port 0 status = 23
62.398: 0x6=a0, 0x7=80
62.398: drive detection not yet completed, waiting...
62.408: 0x6=0, 0x7=50
62.408: drive no longer selected after 10 ms, retrying init
62.408: drive detection done after 0 ms
62.408: AHCI device 0 is ready after 2 tries
62.408: SATA port 1 status = 23
62.408: drive detection done after 0 ms
62.408: AHCI device 1 is ready after 1 tries
62.408: SATA port 2 status = 0
62.408: No AHCI SATA drive on Slot2
62.408: SATA port 3 status = 23
62.408: drive detection done after 0 ms
62.408: AHCI device 3 is ready after 1 tries
62.408: SATA port 4 status = 0
62.409: No AHCI SATA drive on Slot4
62.409: SATA port 5 status = 0
62.409: No AHCI SATA drive on Slot5
62.409: PCI: 00:11.0 init finished in 85667 usecs
62.409: PCI: 00:12.0 init ...
62.409: PCI: 00:12.0 init finished in 1484 usecs
62.409: PCI: 00:12.1 init ...
62.409: PCI: 00:12.1 init finished in 1483 usecs
62.409: PCI: 00:12.2 init ...
62.409: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.409: CBFS: Locating 'cmos_layout.bin'
62.409: CBFS: Found @ offset 2b0c0 size e88
62.410: usb2_bar0=0xfcb0e000
62.410: rpr 6.23, final dword=849e03c8
62.410: PCI: 00:12.2 init finished in 13778 usecs
62.410: PCI: 00:13.0 init ...
62.410: PCI: 00:13.0 init finished in 1484 usecs
62.410: PCI: 00:13.1 init ...
62.410: PCI: 00:13.1 init finished in 1484 usecs
62.410: PCI: 00:13.2 init ...
62.410: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.410: CBFS: Locating 'cmos_layout.bin'
62.410: CBFS: Found @ offset 2b0c0 size e88
62.411: usb2_bar0=0xfcb0f000
62.411: rpr 6.23, final dword=849e03c8
62.411: PCI: 00:13.2 init finished in 13778 usecs
62.411: PCI: 00:14.0 init ...
62.411: sm_init().
62.411: IOAPIC: Initializing IOAPIC at 0xfec00000
62.411: IOAPIC: Bootstrap Processor Local APIC = 0x00
62.411: IOAPIC: Dumping registers
62.411:   reg 0x0000: 0x00000000
62.411:   reg 0x0001: 0x00178021
62.411:   reg 0x0002: 0x00000000
62.411: IOAPIC: 24 interrupts
62.411: IOAPIC: Enabling interrupts on FSB
62.411: IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
62.411: IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
62.411: IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
62.411: IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
62.411: IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
62.411: IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
62.411: IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
62.411: IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
62.411: IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
62.411: IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
62.411: IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
62.411: IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
62.411: IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
62.411: IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
62.411: IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
62.411: IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
62.411: IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
62.411: IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
62.411: IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
62.411: IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
62.411: IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
62.411: IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
62.411: IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
62.411: IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
62.411: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.411: CBFS: Locating 'cmos_layout.bin'
62.411: CBFS: Found @ offset 2b0c0 size e88
62.412: WARNING: No CMOS option 'enable_legacy_usb'.
62.412: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.412: CBFS: Locating 'cmos_layout.bin'
62.412: CBFS: Found @ offset 2b0c0 size e88
62.412: set power "on" after power fail
62.412: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.412: CBFS: Locating 'cmos_layout.bin'
62.412: CBFS: Found @ offset 2b0c0 size e88
62.413: ++++++++++no set NMI+++++
62.413: RTC Init
62.413: sm_init() end
62.413: PCI: 00:14.0 init finished in 132054 usecs
62.413: PCI: 00:14.1 init ...
62.413: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.413: CBFS: Locating 'cmos_layout.bin'
62.413: CBFS: Found @ offset 2b0c0 size e88
62.414: PCI: 00:14.1 init finished in 10194 usecs
62.414: PCI: 00:14.2 init ...
62.414: base = 0xfcb04000
62.418: No codec!
62.418: PCI: 00:14.2 init finished in 6297 usecs
62.418: PCI: 00:14.3 init ...
62.418: lpc_init
62.418: PCI: 00:14.3 init finished in 2127 usecs
62.418: PCI: 00:14.4 init ...
62.418: PCI: 00:14.4 init finished in 1479 usecs
62.418: PCI: 00:14.5 init ...
62.418: PCI: 00:14.5 init finished in 1484 usecs
62.418: PCI: 03:00.0 init ...
62.418: PCI: 03:00.0 init finished in 1462 usecs
62.418: PCI: 04:00.0 init ...
62.418: PCI: 04:00.0 init finished in 1462 usecs
62.418: PCI: 07:00.0 init ...
62.418: PCI: 07:00.0 init finished in 1462 usecs
62.418: PCI: 07:00.1 init ...
62.418: PCI: 07:00.1 init finished in 1462 usecs
62.418: smbus: PCI: 00:14.0[0]->I2C: 01:2f init ...
62.418: Set SMBUS controller to channel 1
62.423: Found 64 pin W83795G Nuvoton H/W Monitor
62.706: W83795G/ADG work in Thermal Cruise Mode
62.706: Fan<09>CTFS(celsius)<09>TTTI(celsius)
62.709:  1<09>80<09>80
62.715:  2<09>80<09>80
62.720:  3<09>80<09>80
62.726:  4<09>80<09>80
62.731:  5<09>80<09>80
62.737:  6<09>80<09>80
62.742: DTS1 current value: 19
62.745: DTS2 current value: 18
62.748: DTS3 current value: 0
62.751: DTS4 current value: 0
62.754: DTS5 current value: 0
62.756: DTS6 current value: 0
62.759: DTS7 current value: 0
62.762: DTS8 current value: 0
62.767: Set SMBUS controller to channel 0
62.767: I2C: 01:2f init finished in 283804 usecs
62.767: PNP: 002e.2 init ...
62.767: PNP: 002e.2 init finished in 1399 usecs
62.767: PNP: 002e.3 init ...
62.767: PNP: 002e.3 init finished in 1399 usecs
62.767: PNP: 002e.5 init ...
62.767: PNP: 002e.5 init finished in 1415 usecs
62.767: PNP: 002e.a init ...
62.767: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.767: CBFS: Locating 'cmos_layout.bin'
62.767: CBFS: Found @ offset 2b0c0 size e88
62.768: set power on after power fail
62.768: PNP: 002e.a init finished in 12038 usecs
62.768: PNP: 002e.b init ...
62.768: PNP: 002e.b init finished in 1399 usecs
62.768: PCI: 08:01.0 init ...
62.768: ASpeed AST2050: initializing video device
62.768: ast_detect_chip: AST 1100 detected
62.768: ast_detect_chip: VGA not enabled on entry, requesting chip POST
62.768: ast_detect_chip: Analog VGA only
62.768: ast_driver_load: dram 800000000 0 16 00800000
62.789: ASpeed VGA text mode initialized
62.789: PCI: 08:01.0 init finished in 33343 usecs
62.789: PCI: 08:02.0 init ...
62.789: PCI: 08:02.0 init finished in 1462 usecs
62.789: Devices initialized
62.789: Show all devs... After init.
62.789: Root Device: enabled 1
62.789: CPU_CLUSTER: 0: enabled 1
62.789: APIC: 00: enabled 1
62.789: DOMAIN: 0000: enabled 1
62.789: PCI: 00:18.0: enabled 1
62.789: PCI: 00:00.0: enabled 1
62.789: PCI: 00:00.1: enabled 0
62.789: PCI: 00:00.2: enabled 1
62.789: PCI: 00:02.0: enabled 1
62.789: PCI: 00:03.0: enabled 0
62.789: PCI: 00:04.0: enabled 1
62.789: PCI: 00:05.0: enabled 0
62.789: PCI: 00:06.0: enabled 0
62.789: PCI: 00:07.0: enabled 0
62.789: PCI: 00:08.0: enabled 0
62.789: PCI: 00:09.0: enabled 1
62.789: PCI: 00:0a.0: enabled 1
62.789: PCI: 00:0b.0: enabled 1
62.789: PCI: 00:0c.0: enabled 1
62.789: PCI: 00:0d.0: enabled 1
62.789: PCI: 00:11.0: enabled 1
62.789: PCI: 00:12.0: enabled 1
62.790: PCI: 00:12.1: enabled 1
62.790: PCI: 00:12.2: enabled 1
62.790: PCI: 00:13.0: enabled 1
62.790: PCI: 00:13.1: enabled 1
62.790: PCI: 00:13.2: enabled 1
62.790: PCI: 00:14.0: enabled 1
62.790: I2C: 01:50: enabled 1
62.790: I2C: 01:51: enabled 1
62.790: I2C: 01:52: enabled 1
62.790: I2C: 01:53: enabled 1
62.790: I2C: 01:54: enabled 1
62.790: I2C: 01:55: enabled 1
62.790: I2C: 01:56: enabled 1
62.790: I2C: 01:57: enabled 1
62.790: I2C: 01:2f: enabled 1
62.790: PCI: 00:14.1: enabled 1
62.790: PCI: 00:14.2: enabled 1
62.790: PCI: 00:14.3: enabled 1
62.790: PNP: 002e.0: enabled 0
62.790: PNP: 002e.1: enabled 0
62.790: PNP: 002e.2: enabled 1
62.790: PNP: 002e.3: enabled 1
62.790: PNP: 002e.5: enabled 1
62.790: PNP: 002e.106: enabled 0
62.790: PNP: 002e.107: enabled 0
62.790: PNP: 002e.207: enabled 0
62.790: PNP: 002e.307: enabled 0
62.790: PNP: 002e.407: enabled 0
62.790: PNP: 002e.8: enabled 0
62.790: PNP: 002e.108: enabled 0
62.790: PNP: 002e.9: enabled 0
62.790: PNP: 002e.109: enabled 0
62.790: PNP: 002e.209: enabled 0
62.790: PNP: 002e.309: enabled 0
62.790: PNP: 002e.a: enabled 1
62.790: PNP: 002e.b: enabled 1
62.790: PNP: 002e.c: enabled 0
62.790: PNP: 002e.d: enabled 0
62.790: PNP: 002e.f: enabled 0
62.790: PNP: 004e.0: enabled 1
62.790: PCI: 00:14.4: enabled 1
62.790: PCI: 08:01.0: enabled 1
62.790: PCI: 08:02.0: enabled 1
62.790: PCI: 08:03.0: enabled 0
62.790: PCI: 00:14.5: enabled 1
62.790: PCI: 00:18.1: enabled 1
62.790: PCI: 00:18.2: enabled 1
62.790: PCI: 00:18.3: enabled 1
62.790: PCI: 00:18.4: enabled 1
62.790: PCI: 00:18.5: enabled 1
62.790: PCI: 00:19.0: enabled 1
62.790: PCI: 00:19.1: enabled 1
62.790: PCI: 00:19.2: enabled 1
62.790: PCI: 00:19.3: enabled 1
62.790: PCI: 00:19.4: enabled 1
62.790: PCI: 00:19.5: enabled 1
62.790: PCI: 00:1a.0: enabled 1
62.790: PCI: 00:1a.1: enabled 1
62.790: PCI: 00:1a.2: enabled 1
62.790: PCI: 00:1a.3: enabled 1
62.790: PCI: 00:1a.4: enabled 1
62.790: PCI: 00:1a.5: enabled 1
62.790: PCI: 00:1b.0: enabled 1
62.790: PCI: 00:1b.1: enabled 1
62.790: PCI: 00:1b.2: enabled 1
62.790: PCI: 00:1b.3: enabled 1
62.790: PCI: 00:1b.4: enabled 1
62.790: PCI: 00:1b.5: enabled 1
62.790: APIC: 01: enabled 1
62.790: APIC: 02: enabled 1
62.790: APIC: 03: enabled 1
62.790: APIC: 04: enabled 1
62.790: APIC: 05: enabled 1
62.791: APIC: 06: enabled 1
62.791: APIC: 07: enabled 1
62.791: APIC: 08: enabled 1
62.791: APIC: 09: enabled 1
62.791: APIC: 0a: enabled 1
62.791: APIC: 0b: enabled 1
62.791: APIC: 0c: enabled 1
62.791: APIC: 0d: enabled 1
62.791: APIC: 0e: enabled 1
62.791: APIC: 0f: enabled 1
62.791: APIC: 20: enabled 1
62.791: APIC: 21: enabled 1
62.791: APIC: 22: enabled 1
62.791: APIC: 23: enabled 1
62.791: APIC: 24: enabled 1
62.791: APIC: 25: enabled 1
62.791: APIC: 26: enabled 1
62.791: APIC: 27: enabled 1
62.791: APIC: 28: enabled 1
62.791: APIC: 29: enabled 1
62.791: APIC: 2a: enabled 1
62.791: APIC: 2b: enabled 1
62.791: APIC: 2c: enabled 1
62.791: APIC: 2d: enabled 1
62.791: APIC: 2e: enabled 1
62.791: APIC: 2f: enabled 1
62.791: PCI: 03:00.0: enabled 1
62.791: PCI: 04:00.0: enabled 1
62.791: PCI: 07:00.0: enabled 1
62.791: PCI: 07:00.1: enabled 1
62.791: BS: BS_DEV_INIT times (us): entry 0 run 3353525 exit 0
62.791: Finalize devices...
62.791: Devices finalized
62.791: BS: BS_POST_DEVICE times (us): entry 0 run 2546 exit 0
62.791: BS: BS_OS_RESUME_CHECK times (us): entry 0 run 0 exit 0
62.791: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.791: CBFS: Locating 'cmos_layout.bin'
62.791: CBFS: Found @ offset 2b0c0 size e88
62.792: Writing IRQ routing tables to 0xf0000...done.
62.792: Writing IRQ routing tables to 0xb7cbe000...done.
62.792: PIRQ table: 48 bytes.
62.792: Wrote the mp table end at: 000f0410 - 000f08ac
62.792: Wrote the mp table end at: b7cbd010 - b7cbd4ac
62.792: MP table: 1196 bytes.
62.792: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.792: CBFS: Locating 'fallback/dsdt.aml'
62.792: CBFS: Found @ offset 2bf80 size 2608
62.792: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.792: CBFS: Locating 'fallback/slic'
62.792: CBFS: 'fallback/slic' not found.
62.792: ACPI: Writing ACPI tables at b7c99000.
62.792: ACPI:    * FACS
62.792: ACPI:    * DSDT
62.796: ACPI:    * FADT
62.796: pm_base: 0x0800
62.796: ACPI: added table 1/32, length now 40
62.796: ACPI:     * SSDT
62.796: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.796: CBFS: Locating 'cmos_layout.bin'
62.796: CBFS: Found @ offset 2b0c0 size e88
62.796: processor_brand=AMD Opteron(tm) Processor 6278
62.796: Pstates algorithm ...
62.796: Pstate_freq[0] = 2400MHz<09>Pstate_power[0] = 6150mw
62.796: Pstate_latency[0] = 5us
62.796: Pstate_freq[1] = 2100MHz<09>Pstate_power[1] = 5233mw
62.796: Pstate_latency[1] = 5us
62.796: Pstate_freq[2] = 1900MHz<09>Pstate_power[2] = 4620mw
62.796: Pstate_latency[2] = 5us
62.796: Pstate_freq[3] = 1600MHz<09>Pstate_power[3] = 3990mw
62.796: Pstate_latency[3] = 5us
62.797: Pstate_freq[4] = 1400MHz<09>Pstate_power[4] = 3422mw
62.797: Pstate_latency[4] = 5us
62.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.797: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.797: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.797: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.797: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.797: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.798: PSS: 2400MHz power 6150 control 0x0 status 0x0
62.798: PSS: 2100MHz power 5233 control 0x1 status 0x1
62.798: PSS: 1900MHz power 4620 control 0x2 status 0x2
62.798: PSS: 1600MHz power 3990 control 0x3 status 0x3
62.798: PSS: 1400MHz power 3422 control 0x4 status 0x4
62.798: ACPI: added table 2/32, length now 44
62.798: ACPI:    * MCFG
62.798: ACPI: added table 3/32, length now 48
62.798: ACPI:    * TCPA
62.798: TCPA log created at b7c89000
62.798: ACPI: added table 4/32, length now 52
62.798: ACPI:    * MADT
62.798: ACPI: added table 5/32, length now 56
62.798: current = b7c9f410
62.798: ACPI:    * SRAT at b7c9f410
62.798: SRAT: lapic cpu_index=00, node_id=00, apic_id=00
62.798: SRAT: lapic cpu_index=01, node_id=00, apic_id=01
62.798: SRAT: lapic cpu_index=02, node_id=00, apic_id=02
62.798: SRAT: lapic cpu_index=03, node_id=00, apic_id=03
62.798: SRAT: lapic cpu_index=04, node_id=00, apic_id=04
62.798: SRAT: lapic cpu_index=05, node_id=00, apic_id=05
62.798: SRAT: lapic cpu_index=06, node_id=00, apic_id=06
62.798: SRAT: lapic cpu_index=07, node_id=00, apic_id=07
62.798: SRAT: lapic cpu_index=08, node_id=01, apic_id=08
62.798: SRAT: lapic cpu_index=09, node_id=01, apic_id=09
62.798: SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a
62.799: SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b
62.799: SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c
62.799: SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d
62.799: SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e
62.799: SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f
62.799: SRAT: lapic cpu_index=10, node_id=02, apic_id=20
62.799: SRAT: lapic cpu_index=11, node_id=02, apic_id=21
62.799: SRAT: lapic cpu_index=12, node_id=02, apic_id=22
62.799: SRAT: lapic cpu_index=13, node_id=02, apic_id=23
62.799: SRAT: lapic cpu_index=14, node_id=02, apic_id=24
62.799: SRAT: lapic cpu_index=15, node_id=02, apic_id=25
62.799: SRAT: lapic cpu_index=16, node_id=02, apic_id=26
62.799: SRAT: lapic cpu_index=17, node_id=02, apic_id=27
62.799: SRAT: lapic cpu_index=18, node_id=03, apic_id=28
62.799: SRAT: lapic cpu_index=19, node_id=03, apic_id=29
62.799: SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a
62.799: SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b
62.799: SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c
62.799: SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d
62.799: SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e
62.799: SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f
62.799: set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
62.799: set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=100e0000, sizek=00020000
62.799: set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
62.799: set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
62.799: set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=03d00000
62.799: set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=04100000, sizek=04000000
62.799: set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=08100000, sizek=04000000
62.799: set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=0c100000, sizek=04000000
62.799: ACPI: added table 6/32, length now 60
62.799: ACPI:   * SLIT at b7c9f730
62.799: ACPI: added table 7/32, length now 64
62.799: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.799: CBFS: Locating 'cmos_layout.bin'
62.799: CBFS: Found @ offset 2b0c0 size e88
62.800: ACPI:   * IVRS at b7c9f770
62.800: Capability: type 0x01 @ 0xc8
62.800: Capability: type 0x05 @ 0xd0
62.800: Capability: type 0x10 @ 0xe0
62.800: Capability: type 0x01 @ 0xc8
62.800: Capability: type 0x05 @ 0xd0
62.800: Capability: type 0x10 @ 0xe0
62.800: Capability: type 0x01 @ 0x40
62.800: Capability: type 0x05 @ 0x50
62.800: Capability: type 0x11 @ 0x70
62.800: Capability: type 0x10 @ 0xa0
62.800: Capability: type 0x01 @ 0x40
62.800: Capability: type 0x05 @ 0x50
62.800: Capability: type 0x11 @ 0x70
62.800: Capability: type 0x10 @ 0xa0
62.800: Capability: type 0x01 @ 0x40
62.800: Capability: type 0x01 @ 0x44
62.800: ACPI: added table 8/32, length now 68
62.800: ACPI:    * HPET
62.800: ACPI: added table 9/32, length now 72
62.800: ACPI:    * SRAT at b7c9f870
62.800: SRAT: lapic cpu_index=00, node_id=00, apic_id=00
62.800: SRAT: lapic cpu_index=01, node_id=00, apic_id=01
62.800: SRAT: lapic cpu_index=02, node_id=00, apic_id=02
62.800: SRAT: lapic cpu_index=03, node_id=00, apic_id=03
62.800: SRAT: lapic cpu_index=04, node_id=00, apic_id=04
62.800: SRAT: lapic cpu_index=05, node_id=00, apic_id=05
62.800: SRAT: lapic cpu_index=06, node_id=00, apic_id=06
62.800: SRAT: lapic cpu_index=07, node_id=00, apic_id=07
62.800: SRAT: lapic cpu_index=08, node_id=01, apic_id=08
62.800: SRAT: lapic cpu_index=09, node_id=01, apic_id=09
62.800: SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a
62.800: SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b
62.800: SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c
62.800: SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d
62.800: SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e
62.800: SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f
62.800: SRAT: lapic cpu_index=10, node_id=02, apic_id=20
62.800: SRAT: lapic cpu_index=11, node_id=02, apic_id=21
62.800: SRAT: lapic cpu_index=12, node_id=02, apic_id=22
62.800: SRAT: lapic cpu_index=13, node_id=02, apic_id=23
62.800: SRAT: lapic cpu_index=14, node_id=02, apic_id=24
62.800: SRAT: lapic cpu_index=15, node_id=02, apic_id=25
62.800: SRAT: lapic cpu_index=16, node_id=02, apic_id=26
62.800: SRAT: lapic cpu_index=17, node_id=02, apic_id=27
62.800: SRAT: lapic cpu_index=18, node_id=03, apic_id=28
62.800: SRAT: lapic cpu_index=19, node_id=03, apic_id=29
62.800: SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a
62.800: SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b
62.800: SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c
62.800: SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d
62.800: SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e
62.800: SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f
62.800: set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
62.800: set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=100e0000, sizek=00020000
62.800: set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
62.800: set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
62.800: set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=03d00000
62.800: set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=04100000, sizek=04000000
62.800: set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=08100000, sizek=04000000
62.800: set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=0c100000, sizek=04000000
62.800: ACPI: added table 10/32, length now 76
62.800: ACPI:   * SLIT at b7c9fb90
62.800: ACPI: added table 11/32, length now 80
62.800: ACPI:    * SRAT at b7c9fbd0
62.800: SRAT: lapic cpu_index=00, node_id=00, apic_id=00
62.800: SRAT: lapic cpu_index=01, node_id=00, apic_id=01
62.800: SRAT: lapic cpu_index=02, node_id=00, apic_id=02
62.800: SRAT: lapic cpu_index=03, node_id=00, apic_id=03
62.800: SRAT: lapic cpu_index=04, node_id=00, apic_id=04
62.800: SRAT: lapic cpu_index=05, node_id=00, apic_id=05
62.800: SRAT: lapic cpu_index=06, node_id=00, apic_id=06
62.800: SRAT: lapic cpu_index=07, node_id=00, apic_id=07
62.800: SRAT: lapic cpu_index=08, node_id=01, apic_id=08
62.800: SRAT: lapic cpu_index=09, node_id=01, apic_id=09
62.800: SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a
62.800: SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b
62.800: SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c
62.800: SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d
62.800: SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e
62.800: SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f
62.800: SRAT: lapic cpu_index=10, node_id=02, apic_id=20
62.800: SRAT: lapic cpu_index=11, node_id=02, apic_id=21
62.800: SRAT: lapic cpu_index=12, node_id=02, apic_id=22
62.800: SRAT: lapic cpu_index=13, node_id=02, apic_id=23
62.800: SRAT: lapic cpu_index=14, node_id=02, apic_id=24
62.800: SRAT: lapic cpu_index=15, node_id=02, apic_id=25
62.800: SRAT: lapic cpu_index=16, node_id=02, apic_id=26
62.800: SRAT: lapic cpu_index=17, node_id=02, apic_id=27
62.801: SRAT: lapic cpu_index=18, node_id=03, apic_id=28
62.801: SRAT: lapic cpu_index=19, node_id=03, apic_id=29
62.801: SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a
62.801: SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b
62.801: SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c
62.801: SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d
62.801: SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e
62.801: SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f
62.801: set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
62.801: set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=100e0000, sizek=00020000
62.801: set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
62.801: set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
62.801: set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=03d00000
62.801: set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=04100000, sizek=04000000
62.801: set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=08100000, sizek=04000000
62.801: set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=0c100000, sizek=04000000
62.801: ACPI: added table 12/32, length now 84
62.801: ACPI:   * SLIT at b7c9fef0
62.801: ACPI: added table 13/32, length now 88
62.801: ACPI:    * SRAT at b7c9ff30
62.801: SRAT: lapic cpu_index=00, node_id=00, apic_id=00
62.801: SRAT: lapic cpu_index=01, node_id=00, apic_id=01
62.801: SRAT: lapic cpu_index=02, node_id=00, apic_id=02
62.801: SRAT: lapic cpu_index=03, node_id=00, apic_id=03
62.801: SRAT: lapic cpu_index=04, node_id=00, apic_id=04
62.801: SRAT: lapic cpu_index=05, node_id=00, apic_id=05
62.801: SRAT: lapic cpu_index=06, node_id=00, apic_id=06
62.801: SRAT: lapic cpu_index=07, node_id=00, apic_id=07
62.801: SRAT: lapic cpu_index=08, node_id=01, apic_id=08
62.801: SRAT: lapic cpu_index=09, node_id=01, apic_id=09
62.801: SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a
62.801: SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b
62.801: SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c
62.801: SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d
62.801: SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e
62.801: SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f
62.801: SRAT: lapic cpu_index=10, node_id=02, apic_id=20
62.801: SRAT: lapic cpu_index=11, node_id=02, apic_id=21
62.801: SRAT: lapic cpu_index=12, node_id=02, apic_id=22
62.801: SRAT: lapic cpu_index=13, node_id=02, apic_id=23
62.801: SRAT: lapic cpu_index=14, node_id=02, apic_id=24
62.801: SRAT: lapic cpu_index=15, node_id=02, apic_id=25
62.801: SRAT: lapic cpu_index=16, node_id=02, apic_id=26
62.801: SRAT: lapic cpu_index=17, node_id=02, apic_id=27
62.801: SRAT: lapic cpu_index=18, node_id=03, apic_id=28
62.801: SRAT: lapic cpu_index=19, node_id=03, apic_id=29
62.801: SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a
62.801: SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b
62.801: SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c
62.801: SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d
62.801: SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e
62.801: SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f
62.801: set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
62.801: set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=100e0000, sizek=00020000
62.801: set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
62.801: set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
62.801: set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=03d00000
62.801: set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=04100000, sizek=04000000
62.801: set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=08100000, sizek=04000000
62.801: set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=0c100000, sizek=04000000
62.801: ACPI: added table 14/32, length now 92
62.801: ACPI:   * SLIT at b7ca0250
62.801: ACPI: added table 15/32, length now 96
62.801: ACPI: done.
62.801: ACPI tables: 29328 bytes.
62.801: smbios_write_tables: b7c88000
62.801: Root Device (ASUS KGPE-D16)
62.801: CPU_CLUSTER: 0 (AMD Family 10h/15h Root Complex)
62.801: APIC: 00 (unknown)
62.801: DOMAIN: 0000 (AMD Family 10h/15h Root Complex)
62.801: PCI: 00:18.0 (AMD Family 10h/15h Northbridge)
62.801: PCI: 00:00.0 (ATI SR5650)
62.801: PCI: 00:00.1 (ATI SR5650)
62.801: PCI: 00:00.2 (ATI SR5650)
62.801: PCI: 00:02.0 (ATI SR5650)
62.801: PCI: 00:03.0 (ATI SR5650)
62.801: PCI: 00:04.0 (ATI SR5650)
62.801: PCI: 00:05.0 (ATI SR5650)
62.801: PCI: 00:06.0 (ATI SR5650)
62.801: PCI: 00:07.0 (ATI SR5650)
62.801: PCI: 00:08.0 (ATI SR5650)
62.801: PCI: 00:09.0 (ATI SR5650)
62.801: PCI: 00:0a.0 (ATI SR5650)
62.801: PCI: 00:0b.0 (ATI SR5650)
62.801: PCI: 00:0c.0 (ATI SR5650)
62.801: PCI: 00:0d.0 (ATI SR5650)
62.801: PCI: 00:11.0 (ATI SP5100)
62.801: PCI: 00:12.0 (ATI SP5100)
62.801: PCI: 00:12.1 (ATI SP5100)
62.801: PCI: 00:12.2 (ATI SP5100)
62.801: PCI: 00:13.0 (ATI SP5100)
62.801: PCI: 00:13.1 (ATI SP5100)
62.801: PCI: 00:13.2 (ATI SP5100)
62.802: PCI: 00:14.0 (ATI SP5100)
62.802: I2C: 01:50 (unknown)
62.802: I2C: 01:51 (unknown)
62.802: I2C: 01:52 (unknown)
62.802: I2C: 01:53 (unknown)
62.802: I2C: 01:54 (unknown)
62.802: I2C: 01:55 (unknown)
62.802: I2C: 01:56 (unknown)
62.802: I2C: 01:57 (unknown)
62.802: I2C: 01:2f (Nuvoton W83795G/ADG Hardware Monitor)
62.802: PCI: 00:14.1 (ATI SP5100)
62.802: PCI: 00:14.2 (ATI SP5100)
62.802: PCI: 00:14.3 (ATI SP5100)
62.802: PNP: 002e.0 (WINBOND W83667HG-A Super I/O)
62.802: PNP: 002e.1 (WINBOND W83667HG-A Super I/O)
62.802: PNP: 002e.2 (WINBOND W83667HG-A Super I/O)
62.802: PNP: 002e.3 (WINBOND W83667HG-A Super I/O)
62.802: PNP: 002e.5 (WINBOND W83667HG-A Super I/O)
62.802: PNP: 002e.106 (WINBOND W83667HG-A Super I/O)
62.802: PNP: 002e.107 (WINBOND W83667HG-A Super I/O)
62.802: PNP: 002e.207 (WINBOND W83667HG-A Super I/O)
62.802: PNP: 002e.307 (WINBOND W83667HG-A Super I/O)
62.802: PNP: 002e.407 (WINBOND W83667HG-A Super I/O)
62.802: PNP: 002e.8 (WINBOND W83667HG-A Super I/O)
62.802: PNP: 002e.108 (WINBOND W83667HG-A Super I/O)
62.802: PNP: 002e.9 (WINBOND W83667HG-A Super I/O)
62.802: PNP: 002e.109 (WINBOND W83667HG-A Super I/O)
62.802: PNP: 002e.209 (WINBOND W83667HG-A Super I/O)
62.802: PNP: 002e.309 (WINBOND W83667HG-A Super I/O)
62.802: PNP: 002e.a (WINBOND W83667HG-A Super I/O)
62.802: PNP: 002e.b (WINBOND W83667HG-A Super I/O)
62.802: PNP: 002e.c (WINBOND W83667HG-A Super I/O)
62.802: PNP: 002e.d (WINBOND W83667HG-A Super I/O)
62.802: PNP: 002e.f (WINBOND W83667HG-A Super I/O)
62.802: PNP: 004e.0 (unknown)
62.802: PCI: 00:14.4 (ATI SP5100)
62.802: PCI: 08:01.0 (ATI SP5100)
62.802: PCI: 08:02.0 (ATI SP5100)
62.802: PCI: 08:03.0 (ATI SP5100)
62.802: PCI: 00:14.5 (ATI SP5100)
62.802: PCI: 00:18.1 (AMD Family 10h/15h Northbridge)
62.802: PCI: 00:18.2 (AMD Family 10h/15h Northbridge)
62.802: PCI: 00:18.3 (AMD Family 10h/15h Northbridge)
62.802: PCI: 00:18.4 (AMD Family 10h/15h Northbridge)
62.802: PCI: 00:18.5 (AMD Family 10h/15h Northbridge)
62.802: PCI: 00:19.0 (AMD Family 10h/15h Northbridge)
62.802: PCI: 00:19.1 (AMD Family 10h/15h Northbridge)
62.802: PCI: 00:19.2 (AMD Family 10h/15h Northbridge)
62.802: PCI: 00:19.3 (AMD Family 10h/15h Northbridge)
62.802: PCI: 00:19.4 (AMD Family 10h/15h Northbridge)
62.802: PCI: 00:19.5 (AMD Family 10h/15h Northbridge)
62.802: PCI: 00:1a.0 (AMD Family 10h/15h Northbridge)
62.802: PCI: 00:1a.1 (AMD Family 10h/15h Northbridge)
62.802: PCI: 00:1a.2 (AMD Family 10h/15h Northbridge)
62.802: PCI: 00:1a.3 (AMD Family 10h/15h Northbridge)
62.802: PCI: 00:1a.4 (AMD Family 10h/15h Northbridge)
62.802: PCI: 00:1a.5 (AMD Family 10h/15h Northbridge)
62.802: PCI: 00:1b.0 (AMD Family 10h/15h Northbridge)
62.802: PCI: 00:1b.1 (AMD Family 10h/15h Northbridge)
62.802: PCI: 00:1b.2 (AMD Family 10h/15h Northbridge)
62.802: PCI: 00:1b.3 (AMD Family 10h/15h Northbridge)
62.802: PCI: 00:1b.4 (AMD Family 10h/15h Northbridge)
62.802: PCI: 00:1b.5 (AMD Family 10h/15h Northbridge)
62.802: APIC: 01 (unknown)
62.802: APIC: 02 (unknown)
62.802: APIC: 03 (unknown)
62.802: APIC: 04 (unknown)
62.802: APIC: 05 (unknown)
62.802: APIC: 06 (unknown)
62.802: APIC: 07 (unknown)
62.802: APIC: 08 (unknown)
62.802: APIC: 09 (unknown)
62.802: APIC: 0a (unknown)
62.802: APIC: 0b (unknown)
62.802: APIC: 0c (unknown)
62.802: APIC: 0d (unknown)
62.802: APIC: 0e (unknown)
62.802: APIC: 0f (unknown)
62.802: APIC: 20 (unknown)
62.802: APIC: 21 (unknown)
62.803: APIC: 22 (unknown)
62.803: APIC: 23 (unknown)
62.803: APIC: 24 (unknown)
62.803: APIC: 25 (unknown)
62.803: APIC: 26 (unknown)
62.803: APIC: 27 (unknown)
62.803: APIC: 28 (unknown)
62.803: APIC: 29 (unknown)
62.803: APIC: 2a (unknown)
62.803: APIC: 2b (unknown)
62.803: APIC: 2c (unknown)
62.803: APIC: 2d (unknown)
62.803: APIC: 2e (unknown)
62.803: APIC: 2f (unknown)
62.803: PCI: 03:00.0 (unknown)
62.803: PCI: 04:00.0 (unknown)
62.803: PCI: 07:00.0 (unknown)
62.803: PCI: 07:00.1 (unknown)
62.803: SMBIOS tables: 1819 bytes.
62.803: Writing table forward entry at 0x00000500
62.803: Wrote coreboot table at: 00000500, 0x10 bytes, checksum 5812
62.803: Writing coreboot table at 0xb7cbf000
62.803: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.803: CBFS: Locating 'cmos_layout.bin'
62.803: CBFS: Found @ offset 2b0c0 size e88
62.804:  0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
62.804:  1. 0000000000001000-000000000009ffff: RAM
62.804:  2. 00000000000a0000-00000000000bffff: RESERVED
62.804:  3. 00000000000c0000-00000000b7c87fff: RAM
62.804:  4. 00000000b7c88000-00000000b7ffffff: CONFIGURATION TABLES
62.804:  5. 00000000b8000000-00000000bfffffff: RAM
62.804:  6. 00000000c0000000-00000000cfffffff: RESERVED
62.804:  7. 00000000fcb00000-00000000fcb03fff: RESERVED
62.804:  8. 00000000feb00000-00000000feb00fff: RESERVED
62.804:  9. 00000000fec00000-00000000fec00fff: RESERVED
62.804: 10. 00000000fed00000-00000000fed00fff: RESERVED
62.804: 11. 0000000100000000-0000004037ffffff: RAM
62.804: 12. 0000004038000000-000000403fffffff: RESERVED
62.804: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.804: CBFS: Locating 'cmos_layout.bin'
62.804: CBFS: Found @ offset 2b0c0 size e88
62.805: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.805: FMAP: Found "FLASH" version 1.1 at 0.
62.805: FMAP: base = ff000000 size = 1000000 #areas = 3
62.805: Wrote coreboot table at: b7cbf000, 0x1208 bytes, checksum deaf
62.805: coreboot table: 4640 bytes.
62.805: IMD ROOT    0. b7fff000 00001000
62.805: IMD SMALL   1. b7ffe000 00001000
62.805: CAR GLOBALS 2. b7ff3000 0000a6c0
62.805: CONSOLE     3. b7fd3000 00020000
62.805: TIME STAMP  4. b7fd2000 00000400
62.805: AMDMEM INFO 5. b7fc8000 000093fc
62.805: ACPI RESUME 6. b7cc7000 00301000
62.805: COREBOOT    7. b7cbf000 00008000
62.805: IRQ TABLE   8. b7cbe000 00001000
62.805: SMP TABLE   9. b7cbd000 00001000
62.805: ACPI       10. b7c99000 00024000
62.805: TCPA LOG   11. b7c89000 00010000
62.806: SMBIOS     12. b7c88000 00000800
62.806: IMD small region:
62.806:   IMD ROOT    0. b7ffec00 00000400
62.806:   ROMSTAGE    1. b7ffebe0 00000004
62.806:   GDT         2. b7ffe9e0 00000200
62.806: Writing AMD DCT configuration to Flash
62.808: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.808: CBFS: Locating 'cmos_layout.bin'
62.808: CBFS: Found @ offset 2b0c0 size e88
62.809: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.809: CBFS: Locating 'cmos_layout.bin'
62.809: CBFS: Found @ offset 2b0c0 size e88
62.809: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.809: CBFS: Locating 'cmos_layout.bin'
62.809: CBFS: Found @ offset 2b0c0 size e88
62.810: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.810: CBFS: Locating 'cmos_layout.bin'
62.810: CBFS: Found @ offset 2b0c0 size e88
62.811: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.811: CBFS: Locating 'cmos_layout.bin'
62.811: CBFS: Found @ offset 2b0c0 size e88
62.811: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.811: CBFS: Locating 'cmos_layout.bin'
62.811: CBFS: Found @ offset 2b0c0 size e88
62.812: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.812: CBFS: Locating 'cmos_layout.bin'
62.812: CBFS: Found @ offset 2b0c0 size e88
62.812: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.812: CBFS: Locating 'cmos_layout.bin'
62.812: CBFS: Found @ offset 2b0c0 size e88
62.813: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.813: CBFS: Locating 'cmos_layout.bin'
62.813: CBFS: Found @ offset 2b0c0 size e88
62.813: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.813: CBFS: Locating 'cmos_layout.bin'
62.813: CBFS: Found @ offset 2b0c0 size e88
62.814: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
62.814: CBFS: Locating 's3nv'
62.814: CBFS: Found @ offset 2fec0 size 10000
62.814: Manufacturer: ef
62.814: SF: Detected W25Q128 with sector size 0x1000, total 0x1000000
62.816: SF: Successfully erased 32768 bytes @ 0x38000
63.159: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
63.159: CBFS: Locating 'cmos_layout.bin'
63.159: CBFS: Found @ offset 2b0c0 size e88
63.160: BS: BS_WRITE_TABLES times (us): entry 0 run 1989715 exit 0
63.160: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
63.160: CBFS: Locating 'fallback/payload'
63.160: CBFS: Found @ offset 95600 size e920
63.160: Loading segment from ROM address 0xff095738
63.160:   code (compression=1)
63.160:   New segment dstaddr 0xe4460 memsize 0x1bba0 srcaddr 0xff095770 filesize 0xe8e8
63.160: Loading segment from ROM address 0xff095754
63.160:   Entry Point 0x000ff06e
63.160: Bounce Buffer at bfdd1000, 2287584 bytes
63.160: Loading Segment: addr: 0x00000000000e4460 memsz: 0x000000000001bba0 filesz: 0x000000000000e8e8
63.160: lb: [0x0000000000100000, 0x00000000002173f0)
63.160: Post relocation: addr: 0x00000000000e4460 memsz: 0x000000000001bba0 filesz: 0x000000000000e8e8
63.160: using LZMA
63.188: [ 0x000e4460, 00100000, 0x00100000) <- ff095770
63.188: dest 000e4460, end 00100000, bouncebuffer bfdd1000
63.188: Loaded segments
63.188: BS: BS_PAYLOAD_LOAD times (us): entry 0 run 68937 exit 0
63.188: Jumping to boot code at 000ff06e(b7cbf000)
63.188: CPU0: stack: 00151000 - 00152000, lowest used address 001519e0, stack used: 1568 bytes
63.188: entry    = 0x000ff06e
63.188: lb_start = 0x00100000
63.188: lb_size  = 0x001173f0
63.189: buffer   = 0xbfdd1000
63.189: SeaBIOS (version rel-1.10.0-25-g1415d46)
63.189: BUILD: gcc: (Ubuntu 6.2.0-5ubuntu12) 6.2.0 20161005 binutils: (GNU Binutils for Ubuntu) 2.27
63.189: Attempting to find coreboot table
63.189: Found coreboot table forwarder.
63.189: Now attempting to find coreboot memory map
63.189: SeaBIOS (version rel-1.10.0-25-g1415d46)
63.189: BUILD: gcc: (Ubuntu 6.2.0-5ubuntu12) 6.2.0 20161005 binutils: (GNU Binutils for Ubuntu) 2.27
63.189: Found coreboot cbmem console @ b7fd3000
63.189: Found mainboard ASUS KGPE-D16
63.189: malloc preinit
63.189: Relocating init from 0x000e5980 to 0xbffb4ca0 (size 45728)
63.189: malloc init
63.189: Found CBFS header at 0xff000138
63.189: Add romfile: cbfs master header (size=32)
63.189: Add romfile: fallback/romstage (size=174404)
63.189: Add romfile: config (size=603)
63.189: Add romfile: revision (size=570)
63.189: Add romfile: cmos.default (size=256)
63.189: Add romfile: cmos_layout.bin (size=3720)
63.189: Add romfile: fallback/dsdt.aml (size=9736)
63.189: Add romfile: bootorder (size=31)
63.190: Add romfile:  (size=6168)
63.190: Add romfile: s3nv (size=65536)
63.190: Add romfile: fallback/ramstage (size=87116)
63.190: Add romfile: pci1106,3230.rom (size=27648)
63.190: Add romfile: img/coreinfo (size=109556)
63.190: Add romfile: img/nvramcui (size=125256)
63.190: Add romfile: fallback/payload (size=59680)
63.190: Add romfile: img/memtest (size=180268)
63.190: Add romfile: microcode_amd.bin (size=12684)
63.190: Add romfile: microcode_amd_fam15h.bin (size=7876)
63.190: Add romfile: vgaroms/seavgabios.bin (size=27648)
63.190: Add romfile:  (size=15873240)
63.190: Add romfile: bootblock (size=3048)
63.190: multiboot: eax=0, ebx=0
63.190: init ivt
63.190: init bda
63.190: Copying romfile 'bootorder' (len 31)
63.190: Copying data 31@0xff02e738 to 31@0xbffb3ae0
63.190: boot order:
63.190: 1: /pci@i0cf8/*@11/drive@3/disk@0
63.190: 2: 
63.190: init bios32
63.190: init PMM
63.190: init PNPBIOS table
63.190: init keyboard
63.190: init mouse
63.190: init pic
63.190: math cp init
63.190: PCI probe
63.190: PCI device 00:00.0 (vd=1002:5a10 c=0600)
63.190: PCI device 00:00.2 (vd=1002:5a23 c=0806)
63.190: PCI device 00:02.0 (vd=1002:5a16 c=0604)
63.190: PCI device 00:04.0 (vd=1002:5a18 c=0604)
63.190: PCI device 00:09.0 (vd=1002:5a1c c=0604)
63.190: PCI device 00:0a.0 (vd=1002:5a1d c=0604)
63.190: PCI device 00:0b.0 (vd=1002:5a1f c=0604)
63.190: PCI device 00:0c.0 (vd=1002:5a20 c=0604)
63.190: PCI device 00:0d.0 (vd=1002:5a1e c=0604)
63.190: PCI device 00:11.0 (vd=1002:4394 c=0106)
63.190: PCI device 00:12.0 (vd=1002:4397 c=0c03)
63.190: PCI device 00:12.1 (vd=1002:4398 c=0c03)
63.190: PCI device 00:12.2 (vd=1002:4396 c=0c03)
63.190: PCI device 00:13.0 (vd=1002:4397 c=0c03)
63.190: PCI device 00:13.1 (vd=1002:4398 c=0c03)
63.190: PCI device 00:13.2 (vd=1002:4396 c=0c03)
63.191: PCI device 00:14.0 (vd=1002:4385 c=0c05)
63.191: PCI device 00:14.1 (vd=1002:439c c=0101)
63.191: PCI device 00:14.2 (vd=1002:4383 c=0403)
63.191: PCI device 00:14.3 (vd=1002:439d c=0601)
63.191: PCI device 00:14.4 (vd=1002:4384 c=0604)
63.191: PCI device 00:14.5 (vd=1002:4399 c=0c03)
63.191: PCI device 00:18.0 (vd=1022:1600 c=0600)
63.191: PCI device 00:18.1 (vd=1022:1601 c=0600)
63.191: PCI device 00:18.2 (vd=1022:1602 c=0600)
63.191: PCI device 00:18.3 (vd=1022:1603 c=0600)
63.191: PCI device 00:18.4 (vd=1022:1604 c=0600)
63.191: PCI device 00:18.5 (vd=1022:1605 c=0600)
63.191: PCI device 00:19.0 (vd=1022:1600 c=0600)
63.191: PCI device 00:19.1 (vd=1022:1601 c=0600)
63.191: PCI device 00:19.2 (vd=1022:1602 c=0600)
63.191: PCI device 00:19.3 (vd=1022:1603 c=0600)
63.191: PCI device 00:19.4 (vd=1022:1604 c=0600)
63.191: PCI device 00:19.5 (vd=1022:1605 c=0600)
63.191: PCI device 00:1a.0 (vd=1022:1600 c=0600)
63.191: PCI device 00:1a.1 (vd=1022:1601 c=0600)
63.191: PCI device 00:1a.2 (vd=1022:1602 c=0600)
63.191: PCI device 00:1a.3 (vd=1022:1603 c=0600)
63.191: PCI device 00:1a.4 (vd=1022:1604 c=0600)
63.191: PCI device 00:1a.5 (vd=1022:1605 c=0600)
63.191: PCI device 00:1b.0 (vd=1022:1600 c=0600)
63.191: PCI device 00:1b.1 (vd=1022:1601 c=0600)
63.191: PCI device 00:1b.2 (vd=1022:1602 c=0600)
63.191: PCI device 00:1b.3 (vd=1022:1603 c=0600)
63.191: PCI device 00:1b.4 (vd=1022:1604 c=0600)
63.191: PCI device 00:1b.5 (vd=1022:1605 c=0600)
63.191: PCI device 03:00.0 (vd=8086:10d3 c=0200)
63.191: PCI device 04:00.0 (vd=8086:10d3 c=0200)
63.191: PCI device 07:00.0 (vd=8086:10fb c=0200)
63.191: PCI device 07:00.1 (vd=8086:10fb c=0200)
63.191: PCI device 08:01.0 (vd=1a03:2000 c=0300)
63.191: PCI device 08:02.0 (vd=11c1:5811 c=0c00)
63.191: Found 52 PCI devices (max PCI bus is 08)
63.191: Relocating coreboot bios tables
63.191: Copying SMBIOS entry point from 0xb7c88000 to 0x000f0c00
63.191: Copying ACPI RSDP from 0xb7c99000 to 0x000f0bd0
63.191: Skipping MPTABLE copy due to large size (1196 bytes)
63.191: Copying PIR from 0xb7cbe000 to 0x000f0ba0
63.193: rsdp=0x000f0bd0
63.193: rsdt=0xb7c99030
63.193: table(50434146)=0xb7c9b890
63.193: pm_tmr_blk=820
63.193: Using pmtimer, ioport 0x820
63.193: init timer
63.193: Scan for VGA option rom
63.193: Attempting to init PCI bdf 08:01.0 (vd 1a03:2000)
63.193: Copying data 27648@0xff0d5288 to 27648@0x000c0000
63.202: Running option rom at c000:0003
63.202: Start SeaVGABIOS (version rel-1.10.0-25-g1415d46)
63.202: VGABUILD: gcc: (Ubuntu 6.2.0-5ubuntu12) 6.2.0 20161005 binutils: (GNU Binutils for Ubuntu) 2.27
63.202: enter vga_post:
63.202:    a=00000000  b=0000ffff  c=00000000  d=0000ffff ds=0000 es=f000 ss=0000
63.202:   si=00000000 di=00008020 bp=00000000 sp=00006dda cs=f000 ip=cfd0  f=0000
63.202: coreboot vga init
63.202: Found coreboot table forwarder.
63.202: Did not find coreboot framebuffer - assuming EGA text
63.202: Attempting to allocate VGA stack via pmm call to f000:d03f
63.202: pmm call arg1=0
63.202: pmm00: length=20 handle=ffffffff flags=9
63.202: VGA stack allocated at ef580
63.202: Hooking hardware timer irq (old=f000fea5 new=c0003ed0)
63.202: Turning on vga text mode console
63.202: set VGA mode 3
63.203: SeaBIOS (version rel-1.10.0-25-g1415d46)
63.203: init usb
63.203: EHCI init on dev 00:12.2 (regs=0xfcb0e020)
63.203: /bffb1000\ Start thread
63.203: EHCI init on dev 00:13.2 (regs=0xfcb0f020)
63.203: /bffb0000\ Start thread
63.203: OHCI init on dev 00:12.0 (regs=0xfcb08000)
63.203: /bffaf000\ Start thread
63.203: OHCI init on dev 00:12.1 (regs=0xfcb09000)
63.203: /bffae000\ Start thread
63.203: OHCI init on dev 00:13.0 (regs=0xfcb0a000)
63.203: /bffad000\ Start thread
63.203: /bffac000\ Start thread
63.203: \bffac000/ End thread
63.203: OHCI init on dev 00:13.1 (regs=0xfcb0b000)
63.203: /bffac000\ Start thread
63.203: /bffab000\ Start thread
63.203: /bffaa000\ Start thread
63.203: OHCI init on dev 00:14.5 (regs=0xfcb0c000)
63.203: /bffa9000\ Start thread
63.203: /bffa8000\ Start thread
63.203: /bffa7000\ Start thread
63.203: init ps2port
63.203: /bffa6000\ Start thread
63.207: /bffa5000\ Start thread
63.207: /bffa3000\ Start thread
63.207: init ahci
63.207: AHCI controller at 00:11.0, iobase 0xfcb0d000, irq 0
63.207: AHCI: cap 0xf322ff85, ports_impl 0x3f
63.207: /bffa2000\ Start thread
63.207: |bffa2000| AHCI/0: probing
63.207: |bffa2000| AHCI/0: link up
63.207: /bffa1000\ Start thread
63.207: /bffa0000\ Start thread
63.207: /bff9f000\ Start thread
63.207: |bff9f000| AHCI/1: probing
63.207: |bff9f000| AHCI/1: link up
63.207: |bffa2000| AHCI/0: ... finished, status 0x51, ERROR 0x4
63.207: /bff9d000\ Start thread
63.207: /bff9c000\ Start thread
63.207: /bff9b000\ Start thread
63.207: /bff9a000\ Start thread
63.207: /bff99000\ Start thread
63.207: /bff98000\ Start thread
63.207: |bff98000| AHCI/2: probing
63.207: |bff9f000| AHCI/1: ... finished, status 0x51, ERROR 0x4
63.207: |bffa2000| Searching bootorder for: /pci@i0cf8/*@11/drive@0/disk@0
63.207: |bffa2000| AHCI/0: supported modes: udma 6, multi-dma 2, pio 4
63.207: |bffa2000| AHCI/0: Set transfer mode to UDMA-6
63.207: /bff97000\ Start thread
63.207: /bff96000\ Start thread
63.207: /bff95000\ Start thread
63.207: /bff94000\ Start thread
63.207: |bff9b000| set_address 0xbffb2730
63.207: /bff93000\ Start thread
63.207: \bff93000/ End thread
63.207: \bff9a000/ End thread
63.207: \bffa1000/ End thread
63.207: \bffa5000/ End thread
63.208: \bffa8000/ End thread
63.208: \bffab000/ End thread
63.208: \bff99000/ End thread
63.208: \bffa0000/ End thread
63.208: \bffa3000/ End thread
63.208: \bffa7000/ End thread
63.208: \bffaa000/ End thread
63.208: /bffaa000\ Start thread
63.208: |bffaa000| AHCI/3: probing
63.208: |bffaa000| AHCI/3: link up
63.208: |bff98000| AHCI/2: link down
63.208: |bff9f000| Searching bootorder for: /pci@i0cf8/*@11/drive@1/disk@0
63.208: |bff9f000| AHCI/1: supported modes: udma 6, multi-dma 2, pio 4
63.208: |bff9f000| AHCI/1: Set transfer mode to UDMA-6
63.208: /bffa8000\ Start thread
63.208: /bffa7000\ Start thread
63.208: /bffa5000\ Start thread
63.208: \bffa5000/ End thread
63.208: \bff96000/ End thread
63.208: \bff9d000/ End thread
63.208: /bffa5000\ Start thread
63.208: \bffa5000/ End thread
63.208: \bff95000/ End thread
63.208: \bff9c000/ End thread
63.208: /bffa5000\ Start thread
63.208: \bffa5000/ End thread
63.208: \bff94000/ End thread
63.208: /bffa5000\ Start thread
63.208: |bffa5000| AHCI/4: probing
63.208: |bffaa000| AHCI/3: ... finished, status 0x51, ERROR 0x4
63.208: \bff98000/ End thread
63.208: |bffa2000| AHCI/0: registering: "AHCI/0: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes)"
63.208: |bffa2000| Registering bootable: AHCI/0: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes) (type:2 prio:103 data:f0b30)
63.208: \bffa2000/ End thread
63.208: /bffa3000\ Start thread
63.208: /bffa2000\ Start thread
63.208: \bffa2000/ End thread
63.208: \bffa7000/ End thread
63.208: \bff97000/ End thread
63.208: /bffa2000\ Start thread
63.208: |bffa2000| AHCI/5: probing
63.208: |bffa5000| AHCI/4: link down
63.208: |bffaa000| Searching bootorder for: /pci@i0cf8/*@11/drive@3/disk@0
63.208: |bffaa000| AHCI/3: supported modes: udma 6, multi-dma 2, pio 4
63.208: |bffaa000| AHCI/3: Set transfer mode to UDMA-6
63.208: |bff9f000| AHCI/1: registering: "AHCI/1: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes)"
63.208: |bff9f000| Registering bootable: AHCI/1: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes) (type:2 prio:103 data:f0ae0)
63.208: \bff9f000/ End thread
63.208: \bffa3000/ End thread
63.208: \bffa8000/ End thread
63.208: \bffad000/ End thread
63.208: \bffae000/ End thread
63.208: |bff9b000| config_usb: 0xbffab9b0
63.208: \bffb0000/ End thread
63.208: \bffb1000/ End thread
63.208: init lpt
63.208: Found 0 lpt ports
63.208: init serial
63.208: Found 2 serial ports
63.208: Searching bootorder for: /rom@img/memtest
63.208: Registering bootable: Payload [memtest] (type:32 prio:9999 data:ff0a4080)
63.208: Searching bootorder for: /rom@img/nvramcui
63.208: Registering bootable: Payload [nvramcui] (type:32 prio:9999 data:ff076d80)
63.208: Searching bootorder for: /rom@img/coreinfo
63.208: Registering bootable: Payload [coreinfo] (type:32 prio:9999 data:ff05c140)
63.209: |bffa2000| AHCI/5: link down
63.209: \bffa5000/ End thread
63.209: \bffac000/ End thread
63.209: |bff9b000| device rev=0110 cls=00 sub=00 proto=00 size=8
63.209: \bffa2000/ End thread
63.209: |bffaa000| AHCI/3: registering: "AHCI/3: Hitachi HUA721010KLA330 ATA-7 Hard-Disk (931 GiBytes)"
63.209: |bffaa000| Registering bootable: AHCI/3: Hitachi HUA721010KLA330 ATA-7 Hard-Disk (931 GiBytes) (type:2 prio:1 data:f0a90)
63.209: \bffaa000/ End thread
63.209: \bffa9000/ End thread
63.211: |bff9b000| usb_hid_setup 0xbffab9b0
63.211: |bff9b000| USB keyboard initialized
63.211: \bff9b000/ End thread
63.212: \bffaf000/ End thread
63.338: |bffa6000| PS2 keyboard initialized
63.338: \bffa6000/ End thread
63.338: All threads complete.
63.338: Scan for option roms
63.338: Attempting to init PCI bdf 00:00.0 (vd 1002:5a10)
63.338: Attempting to init PCI bdf 00:00.2 (vd 1002:5a23)
63.338: Attempting to init PCI bdf 00:02.0 (vd 1002:5a16)
63.338: Attempting to init PCI bdf 00:04.0 (vd 1002:5a18)
63.338: Attempting to init PCI bdf 00:09.0 (vd 1002:5a1c)
63.338: Attempting to init PCI bdf 00:0a.0 (vd 1002:5a1d)
63.338: Attempting to init PCI bdf 00:0b.0 (vd 1002:5a1f)
63.338: Attempting to init PCI bdf 00:0c.0 (vd 1002:5a20)
63.338: Attempting to init PCI bdf 00:0d.0 (vd 1002:5a1e)
63.338: Attempting to init PCI bdf 00:14.0 (vd 1002:4385)
63.338: Attempting to init PCI bdf 00:14.1 (vd 1002:439c)
63.338: Attempting to init PCI bdf 00:14.2 (vd 1002:4383)
63.338: Attempting to init PCI bdf 00:14.3 (vd 1002:439d)
63.338: Attempting to init PCI bdf 00:14.4 (vd 1002:4384)
63.338: Attempting to init PCI bdf 00:18.0 (vd 1022:1600)
63.338: Attempting to init PCI bdf 00:18.1 (vd 1022:1601)
63.338: Attempting to init PCI bdf 00:18.2 (vd 1022:1602)
63.338: Attempting to init PCI bdf 00:18.3 (vd 1022:1603)
63.338: Attempting to init PCI bdf 00:18.4 (vd 1022:1604)
63.338: Attempting to init PCI bdf 00:18.5 (vd 1022:1605)
63.338: Attempting to init PCI bdf 00:19.0 (vd 1022:1600)
63.338: Attempting to init PCI bdf 00:19.1 (vd 1022:1601)
63.338: Attempting to init PCI bdf 00:19.2 (vd 1022:1602)
63.338: Attempting to init PCI bdf 00:19.3 (vd 1022:1603)
63.338: Attempting to init PCI bdf 00:19.4 (vd 1022:1604)
63.338: Attempting to init PCI bdf 00:19.5 (vd 1022:1605)
63.338: Attempting to init PCI bdf 00:1a.0 (vd 1022:1600)
63.338: Attempting to init PCI bdf 00:1a.1 (vd 1022:1601)
63.338: Attempting to init PCI bdf 00:1a.2 (vd 1022:1602)
63.338: Attempting to init PCI bdf 00:1a.3 (vd 1022:1603)
63.338: Attempting to init PCI bdf 00:1a.4 (vd 1022:1604)
63.338: Attempting to init PCI bdf 00:1a.5 (vd 1022:1605)
63.338: Attempting to init PCI bdf 00:1b.0 (vd 1022:1600)
63.338: Attempting to init PCI bdf 00:1b.1 (vd 1022:1601)
63.338: Attempting to init PCI bdf 00:1b.2 (vd 1022:1602)
63.339: Attempting to init PCI bdf 00:1b.3 (vd 1022:1603)
63.339: Attempting to init PCI bdf 00:1b.4 (vd 1022:1604)
63.338: Attempting to init PCI bdf 00:1b.5 (vd 1022:1605)
63.339: Attempting to init PCI bdf 03:00.0 (vd 8086:10d3)
63.339: Attempting to init PCI bdf 04:00.0 (vd 8086:10d3)
63.339: Attempting to init PCI bdf 07:00.0 (vd 8086:10fb)
63.339: Attempting to init PCI bdf 07:00.1 (vd 8086:10fb)
63.339: Attempting to init PCI bdf 08:02.0 (vd 11c1:5811)
63.339: 
63.339: Press ESC for boot menu.
63.339: 
63.339: Checking for bootsplash
64.210: Select boot device:
64.210: 
64.210: 1. AHCI/3: Hitachi HUA721010KLA330 ATA-7 Hard-Disk (931 GiByte
64.210: 2. AHCI/0: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes)
64.210: 3. AHCI/1: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes)
64.210: 4. Payload [memtest]
64.210: 5. Payload [nvramcui]
64.210: 6. Payload [coreinfo]
74.346: 
74.346: Searching bootorder for: HALT
74.346: Mapping hd drive 0x000f0a90 to 0
74.346: drive 0x000f0a90: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1953525168
74.346: Mapping hd drive 0x000f0b30 to 1
74.346: drive 0x000f0b30: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1565565872
74.346: Mapping hd drive 0x000f0ae0 to 2
74.346: drive 0x000f0ae0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1565565872
74.346: finalize PMM
74.346: malloc finalize
74.346: Space available for UMB: c7000-ee800, f0000-f0a90
74.346: Returned 245760 bytes of ZoneHigh
74.346: e820 map has 13 items:
74.346:   0: 0000000000000000 - 000000000009fc00 = 1 RAM
74.346:   1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
74.346:   2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
74.346:   3: 0000000000100000 - 00000000b7c88000 = 1 RAM
74.346:   4: 00000000b7c88000 - 00000000b8000000 = 2 RESERVED
74.346:   5: 00000000b8000000 - 00000000bfffc000 = 1 RAM
74.346:   6: 00000000bfffc000 - 00000000d0000000 = 2 RESERVED
74.346:   7: 00000000fcb00000 - 00000000fcb04000 = 2 RESERVED
74.346:   8: 00000000feb00000 - 00000000feb01000 = 2 RESERVED
74.346:   9: 00000000fec00000 - 00000000fec01000 = 2 RESERVED
74.346:   10: 00000000fed00000 - 00000000fed01000 = 2 RESERVED
74.346:   11: 0000000100000000 - 0000004038000000 = 1 RAM
74.346:   12: 0000004038000000 - 0000004040000000 = 2 RESERVED
74.347: Jump to int19
74.347: enter handle_19:
74.347:   NULL
74.347: Booting from CBFS...
74.348: Run img/memtest
74.348: Segment 41544144 180212@0xff0a40e0 -> 180212@0x00010000
74.525: Calling addr 0x00010000
74.527: <1b>[LINE_SCROLL;24r<1b>[H<1b>[2J<1b>[37m<1b>[44m<1b>[0m<1b>[37m<1b>[44m<1b>[1;1HMemtest86+ 5.01 coreboot 001<1b>[0m<1b>[6;61H| Time:   0:00:00<1b>[2;31HPass   %<1b>[3;31HTest   %<1b>[4;31HTest #<1b>[5;31HTesting: <1b>[6;31HPattern: <1b>[2;1HCLK:           (32b Mode)<1b>[3;1HL1 Cache: Unknown <1b>[4;1HL2 Cache: Unknown <1b>[5;1HL3 Cache:  None    <1b>[6;1HMemory  :         <1b>[7;1H------------------------------------------------------------------------------<1b>[8;1HCore#:<1b>[9;1HState:<1b>[10;1HCores:    Active /    Total (Run: All) | Pass:       0        Errors:      0  <1b>[11;1H------------------------------------------------------------------------------<1b>[8;40H| Chipset : Unknown<1b>[9;40H| Memory Type : Unknown<1b>[1;29H| <1b>[2;29H| <1b>[3;29H| <1b>[4;29H| <1b>[5;29H| <1b>[6;29H| <1b>[25;1H(ESC)exit  (c)configuration  (SP)scroll_lock  (CR)scroll_unlock<1b>[6;12H256<1b>[6;15HG<1b>[1;31HAMD Opteron(tm) Processor 6278<1b>[2;11HMHz<1b>[2;6H2400<1b>[3;11H    K  <1b>[3;13H64<1b>[3;24HMB/s<1b>[3;18H22430<1b>[4;11H    K  <1b>[4;11H2048<1b>[4;24HMB/s<1b>[4;18H18045<1b>[5;12H   K  <1b>[5;13H12<1b>[5;15HM<1b>[5;24HMB/s<1b>[5;19H8000<1b>[19;19H==> Press F1 to enter Fail-Safe Mode <==<1b>[20;16H==> Press F2 to force Multi-Threading (SMP) <==<1b>[19;19H                                          <1b>[20;16H                                                <1b>[8;8H0<1b>[9;8HS<1b>[10;21H1<1b>[8;10H(SMP: Disabled)<1b>[9;10HRunning...<1b>[8;42HRAM:                                <1b>[8;47H800 <1b>[8;51HMHz (<1b>[8;56HDDR3-<1b>[8;61H1600<1b>[8;65H)<1b>[8;67H- BCLK: <1b>[8;76H88<1b>[9;42HTimings: CAS                        <1b>[9;55H11<1b>[9;57H-<1b>[9;58H11<1b>[9;60H-<1b>[9;61H11<1b>[9;63H-<1b>[9;64H28<1b>[9;67H@ 128-bit Mode<1b>[24;34HASUS<1b>[24;39HKGPE-D16<1b>[13;1HMemory SPD Informations<1b>[14;1H--------------------------<1b>[9;32H21<1b>[8;27H|  CPU Temp<1b>[9;27H|       C<1b>[2;17HPAE Mode)<1b>[2;17HX64 Mode)<1b>[6;24HMB/s<1b>[4;37H2 <1b>[4;40H[Address test, own address Parallel]   <1b>[9;8HW<1b>[10;9H1<1b>[9;8H-<1b>[6;57HR<1b>[5;43H0<1b>[5;44HK<1b>[5;46H- <1b>[5;50H32<1b>[5;52HM<1b>[5;58H32<1b>[5;60HM<1b>[5;62Hof <1b>[5;66H256<1b>[5;69HG<1b>[6;42Haddress <1b>[3;37H0<1b>[2;37H0<1b>[6;77H1<1b>[9;32H23<1b>[9;8HW<1b>[9;8H-<1b>[6;57H <1b>[5;40H1024<1b>[5;48H2048<1b>[5;56H2047<1b>[6;77H2<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;40H2048<1b>[5;44HM<1b>[5;48H3072<1b>[5;56H1024<1b>[3;37H1<1b>[6;77H3<1b>[9;8HW<1b>[9;8H-<1b>[5;40H4096<1b>[5;48H6144<1b>[5;56H2048<1b>[6;77H4<1b>[3;37H2<1b>[9;8HW<1b>[9;8H-<1b>[5;40H6144<1b>[5;48H8192<1b>[6;77H5<1b>[9;33H6<1b>[6;77H6<1b>[9;33H5<1b>[3;37H3<1b>[3;40H#<1b>[9;8HW<1b>[9;8H-<1b>[5;40H8192<1b>[5;48H  10<1b>[5;52HG<1b>[6;77H7<1b>[9;8HW<1b>[9;8H-<1b>[5;40H  10<1b>[5;44HG<1b>[5;51H2<1b>[3;37H4<1b>[6;77H8<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[3;37H5<1b>[6;77H9<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H0<1b>[6;76H1<1b>[3;37H6<1b>[3;41H#<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H1<1b>[6;77H2<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H20<1b>[3;37H7<1b>[6;77H3<1b>[9;8HW<1b>[9;8H-<1b>[5;42H20<1b>[5;51H2<1b>[6;77H4<1b>[3;37H8<1b>[3;42H#<1b>[6;77H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[6;77H6<1b>[3;37H9<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H7<1b>[3;36H10<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H8<1b>[9;33H6<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H30<1b>[3;37H1<1b>[3;43H#<1b>[6;77H9<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;42H30<1b>[5;51H2<1b>[6;77H0<1b>[6;76H2<1b>[3;37H2<1b>[6;77H1<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[6;77H2<1b>[3;37H3<1b>[3;44H#<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H3<1b>[6;77H4<1b>[9;33H6<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[3;37H4<1b>[6;77H5<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H40<1b>[3;37H5<1b>[6;77H6<1b>[9;8HW<1b>[9;8H-<1b>[5;42H40<1b>[5;51H2<1b>[3;37H6<1b>[3;45H#<1b>[6;77H7<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[6;77H8<1b>[9;33H6<1b>[3;37H7<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H9<1b>[6;77H0<1b>[6;76H3<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[3;37H8<1b>[3;46H#<1b>[6;77H1<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H50<1b>[6;77H2<1b>[3;37H9<1b>[9;8HW<1b>[9;8H-<1b>[5;42H50<1b>[5;51H2<1b>[6;77H3<1b>[3;36H20<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[6;77H4<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H5<1b>[3;37H1<1b>[3;47H#<1b>[6;77H6<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[3;37H2<1b>[6;77H7<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H60<1b>[6;77H8<1b>[3;37H3<1b>[6;77H9<1b>[9;33H6<1b>[9;8HW<1b>[9;8H-<1b>[5;42H60<1b>[5;51H2<1b>[6;77H0<1b>[6;76H4<1b>[9;33H5<1b>[3;37H4<1b>[3;48H#<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[6;77H1<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H2<1b>[3;37H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H3<1b>[3;37H6<1b>[3;49H#<1b>[6;77H4<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H70<1b>[6;77H5<1b>[6;77H6<1b>[3;37H7<1b>[9;8HW<1b>[9;8H-<1b>[5;42H70<1b>[5;51H2<1b>[6;77H7<1b>[6;77H8<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[3;37H8<1b>[6;77H9<1b>[6;77H0<1b>[6;76H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H1<1b>[3;37H9<1b>[3;50H#<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H2<1b>[6;77H3<1b>[3;36H30<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H80<1b>[6;77H4<1b>[6;77H5<1b>[9;33H4<1b>[3;37H1<1b>[3;51H#<1b>[9;8HW<1b>[9;8H-<1b>[5;42H80<1b>[5;51H2<1b>[6;77H6<1b>[9;33H5<1b>[6;77H7<1b>[9;33H4<1b>[6;77H8<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[3;37H2<1b>[6;77H9<1b>[9;33H4<1b>[6;77H0<1b>[6;76H0<1b>[6;74H1<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[3;37H3<1b>[6;77H1<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H2<1b>[9;33H4<1b>[3;37H4<1b>[3;52H#<1b>[6;77H3<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H90<1b>[6;77H4<1b>[9;33H4<1b>[6;77H5<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;42H90<1b>[5;51H2<1b>[3;37H5<1b>[6;77H6<1b>[6;77H7<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[3;37H6<1b>[3;53H#<1b>[6;77H8<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H9<1b>[3;37H7<1b>[6;77H0<1b>[6;76H1<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H1<1b>[6;77H2<1b>[3;37H8<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;49H100<1b>[6;77H3<1b>[6;77H4<1b>[9;8HW<1b>[9;8H-<1b>[5;41H100<1b>[5;51H2<1b>[3;37H9<1b>[3;54H#<1b>[6;77H5<1b>[6;77H6<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[3;36H40<1b>[6;77H7<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H8<1b>[6;77H9<1b>[3;37H1<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H0<1b>[6;76H2<1b>[6;77H1<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H10<1b>[3;37H2<1b>[3;55H#<1b>[6;77H2<1b>[6;77H3<1b>[9;8HW<1b>[9;8H-<1b>[5;42H10<1b>[5;51H2<1b>[6;77H4<1b>[3;37H3<1b>[6;77H5<1b>[9;33H4<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[3;37H4<1b>[3;56H#<1b>[6;77H6<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H7<1b>[6;77H8<1b>[3;37H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H9<1b>[6;77H0<1b>[6;76H3<1b>[9;33H4<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H20<1b>[6;77H1<1b>[9;33H5<1b>[3;37H6<1b>[6;77H2<1b>[9;33H4<1b>[6;77H3<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;42H20<1b>[5;51H2<1b>[3;37H7<1b>[3;57H#<1b>[6;77H4<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[6;77H5<1b>[9;33H4<1b>[3;37H8<1b>[6;77H6<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H7<1b>[9;33H4<1b>[6;77H8<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[3;37H9<1b>[3;58H#<1b>[6;77H9<1b>[9;33H4<1b>[6;77H0<1b>[6;76H4<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H30<1b>[3;36H50<1b>[6;77H1<1b>[9;33H4<1b>[9;8HW<1b>[9;8H-<1b>[5;42H30<1b>[5;51H2<1b>[6;77H2<1b>[3;37H1<1b>[6;77H3<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[6;77H4<1b>[9;33H4<1b>[6;77H5<1b>[3;37H2<1b>[3;59H#<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[6;77H6<1b>[6;77H7<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H8<1b>[9;33H5<1b>[3;37H3<1b>[6;77H9<1b>[9;33H4<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H40<1b>[6;77H0<1b>[6;76H5<1b>[9;33H5<1b>[3;37H4<1b>[3;60H#<1b>[6;77H1<1b>[9;8HW<1b>[9;8H-<1b>[5;42H40<1b>[5;51H2<1b>[6;77H2<1b>[9;33H4<1b>[3;37H5<1b>[6;77H3<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[6;77H4<1b>[6;77H5<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[3;37H6<1b>[6;77H6<1b>[9;33H4<1b>[6;77H7<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H8<1b>[3;37H7<1b>[3;61H#<1b>[6;77H9<1b>[9;33H4<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H50<1b>[3;37H8<1b>[6;77H0<1b>[6;76H0<1b>[6;74H2<1b>[6;77H1<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;42H50<1b>[5;51H2<1b>[6;77H2<1b>[9;33H4<1b>[3;37H9<1b>[3;62H#<1b>[6;77H3<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[6;77H4<1b>[9;33H4<1b>[6;77H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[3;36H60<1b>[6;77H6<1b>[6;77H7<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H8<1b>[3;37H1<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H60<1b>[6;77H9<1b>[6;77H0<1b>[6;76H1<1b>[9;33H4<1b>[3;37H2<1b>[3;63H#<1b>[9;8HW<1b>[9;8H-<1b>[5;42H60<1b>[5;51H2<1b>[6;77H1<1b>[9;33H5<1b>[6;77H2<1b>[9;33H4<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[3;37H3<1b>[6;77H3<1b>[9;33H5<1b>[6;77H4<1b>[9;33H4<1b>[6;77H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[3;37H4<1b>[6;77H6<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H7<1b>[3;37H5<1b>[3;64H#<1b>[6;77H8<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H70<1b>[6;77H9<1b>[9;33H5<1b>[6;77H0<1b>[6;76H2<1b>[9;33H4<1b>[3;37H6<1b>[9;8HW<1b>[9;8H-<1b>[5;42H70<1b>[5;51H2<1b>[6;77H1<1b>[9;33H5<1b>[6;77H2<1b>[9;33H4<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[6;77H3<1b>[9;33H5<1b>[3;37H7<1b>[3;65H#<1b>[6;77H4<1b>[9;33H4<1b>[9;8HW<1b>[9;8H-<1b>[5;43H4<1b>[5;51H6<1b>[3;37H8<1b>[6;77H5<1b>[6;77H6<1b>[9;33H5<1b>[9;8HW<1b>[9;8H-<1b>[5;43H6<1b>[5;51H8<1b>[6;77H7<1b>[9;33H4<1b>[3;37H9<1b>[6;77H8<1b>[9;8HW<1b>[9;8H-<1b>[5;43H8<1b>[5;50H80<1b>[6;77H9<1b>[6;77H0<1b>[6;76H3<1b>[3;36H70<1b>[3;66H#<1b>[9;8HW<1b>[9;8H-<1b>[5;42H80<1b>[5;51H2<1b>[6;77H1<1b>[6;77H2<1b>[9;8HW<1b>[9;8H-<1b>[5;43H2<1b>[5;51H4<1b>[5;54HHalting...<00>
237.422: <00>
237.610: 
237.610: 
237.610: coreboot-4.5-1206-g589fc34 Fri Mar 10 10:20:39 UTC 2017 romstage starting...
237.610: Initial stack pointer: 000dffb8
237.612: CPU APICID 00 start flag set
237.613: BSP Family_Model: 00600f12
237.613: *sysinfo range: [000c2d20,000cd28c]
237.613: bsp_apicid = 00
237.613: cpu_init_detectedx = 00000000
237.613: sb700 reset flags: 0020
237.613: WARNING: MC4 Machine Check Exception detected on node 0!
237.613: Signature: f256d7df2e1df6cb
237.614: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
237.614: CBFS: Locating 'microcode_amd.bin'
237.615: CBFS: Found @ offset d0000 size 318c
237.615: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
237.615: CBFS: Locating 'microcode_amd_fam15h.bin'
237.615: CBFS: Found @ offset d3200 size 1ec4
237.637: [microcode] patch id to apply = 0x0600063d
237.637: [microcode] updated to patch id = 0x0600063d success
237.637: cpuSetAMDMSR CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
237.639: CBFS: Locating 'cmos_layout.bin'
237.640: CBFS: Found @ offset 2b0c0 size e88
237.641: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
237.641: CBFS: Locating 'cmos_layout.bin'
237.641: CBFS: Found @ offset 2b0c0 size e88
237.641:  done
237.641: Enter amd_ht_init
237.645: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1
237.645: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2
237.645: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3
237.648: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
237.648: CBFS: Locating 'cmos_layout.bin'
237.649: CBFS: Found @ offset 2b0c0 size e88
237.649: Forcing HT links to isochronous mode due to enabled IOMMU
237.649: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
237.649: CBFS: Locating 'cmos_layout.bin'
237.649: CBFS: Found @ offset 2b0c0 size e88
237.651: Exit amd_ht_init
237.651: amd_ht_fixup
237.651: amd_ht_fixup: node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1)
237.651: amd_ht_fixup: node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1)
237.651: amd_ht_fixup: node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1)
237.651: amd_ht_fixup: node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1)
237.652: cpuSetAMDPCI 00 done
237.654: cpuSetAMDPCI 01 done
237.655: cpuSetAMDPCI 02 done
237.655: cpuSetAMDPCI 03 done
237.655: Prep FID/VID Node:00
237.656:   F3x80: e20be281
237.656:   F3x84: 01e200e2
237.656:   F3xD4: c3312f18
237.656:   F3xD8: 03000016
237.656:   F3xDC: 05475632
237.656: Prep FID/VID Node:01
237.656:   F3x80: e20be281
237.656:   F3x84: 01e200e2
237.656:   F3xD4: c3312f18
237.656:   F3xD8: 03000016
237.656:   F3xDC: 05475632
237.656: Prep FID/VID Node:02
237.656:   F3x80: e20be281
237.656:   F3x84: 01e200e2
237.656:   F3xD4: c3312f18
237.656:   F3xD8: 03000016
237.656:   F3xDC: 05475632
237.656: Prep FID/VID Node:03
237.656:   F3x80: e20be281
237.656:   F3x84: 01e200e2
237.656:   F3xD4: c3312f18
237.657:   F3xD8: 03000016
237.657:   F3xDC: 05475632
237.657: setup_remote_node: 01 done
237.657: Start node 01 done.
237.657: setup_remote_node: 02 done
237.657: Start node 02 done.
237.658: setup_remote_node: 03 done
237.659: Start node 03 done.
237.661: WARNING: MC4 Machine Check Exception detected on node 1!
237.666: Signature: f627f6fe561fd7bb
237.668: WARNING: MC4 Machine Check Exception detected on node 2!
237.671: Signature: fa100aa3ca054c0f
237.672: WARNING: MC4 Machine Check Exception detected on node 3!
237.674: Signature: f20736f100014e0f
237.674: core0 started:  01 02 03
237.674: sr5650_early_setup()
237.674: get_cpu_rev EAX=0x600f12.
237.675: CPU Rev is Fam 15.
237.675: NB Revision is A12.
237.675: fam10_optimization()
237.675: sr5650_por_init
237.678: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
237.678: CBFS: Locating 'cmos_layout.bin'
237.679: CBFS: Found @ offset 2b0c0 size e88
237.679: Enabling IOMMU
237.682: sb700_early_setup()
237.682: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
237.682: CBFS: Locating 'cmos_layout.bin'
237.685: CBFS: Found @ offset 2b0c0 size e88
237.687: sb700_devices_por_init()
237.688: sb700_devices_por_init(): SMBus Device, BDF:0-20-0
237.689: SMBus controller enabled, sb revision is A15
237.689: sb700_devices_por_init: Disabling ISA DMA support
237.689: sb700_devices_por_init(): IDE Device, BDF:0-20-1
237.692: sb700_devices_por_init(): LPC Device, BDF:0-20-3
237.693: sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
237.694: sb700_devices_por_init(): SATA Device, BDF:0-17-0
237.694: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
237.694: CBFS: Locating 'cmos_layout.bin'
237.694: CBFS: Found @ offset 2b0c0 size e88
237.695: sb700_pmio_por_init()
237.695: start_other_cores()
237.695: init node: 00  cores: 07 pass 1
237.695: Start other core - nodeid: 00  cores: 07
237.696: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
237.754: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
237.778: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
237.802: init node: 01  cores: 07 pass 1
237.804: Start other core - nodeid: 01  cores: 07
237.809: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
237.939: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
237.964: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
237.965: init node: 02  cores: 07 pass 1
237.966: Start other core - nodeid: 02  cores: 07
237.968: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
238.253: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
238.255: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
238.276: init node: 03  cores: 07 pass 1
238.278: Start other core - nodeid: 03  cores: 07
238.279: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
238.475: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
238.501: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
238.525: started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
238.528: * AP 01started
238.528: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
238.532: * AP 02started
238.535: get_boot_apic_id: using 3 as APIC ID for node 0, core 3
238.536: * AP 03started
238.536: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
238.536: * AP 04started
238.536: get_boot_apic_id: using 5 as APIC ID for node 0, core 5
238.536: * AP 05started
238.537: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
238.537: * AP 06started
238.538: get_boot_apic_id: using 7 as APIC ID for node 0, core 7
238.541: * AP 07started
238.541: get_boot_apic_id: using 9 as APIC ID for node 1, core 1
238.542: * AP 09started
238.542: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
238.542: * AP 0astarted
238.542: get_boot_apic_id: using 11 as APIC ID for node 1, core 3
238.543: * AP 0bstarted
238.543: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
238.546: * AP 0cstarted
238.547: get_boot_apic_id: using 13 as APIC ID for node 1, core 5
238.547: * AP 0dstarted
238.547: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
238.548: * AP 0estarted
238.548: get_boot_apic_id: using 15 as APIC ID for node 1, core 7
238.548: * AP 0fstarted
238.548: get_boot_apic_id: using 33 as APIC ID for node 2, core 1
238.551: * AP 21started
238.551: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
238.552: * AP 22started
238.553: get_boot_apic_id: using 35 as APIC ID for node 2, core 3
238.553: * AP 23started
238.553: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
238.553: * AP 24started
238.553: get_boot_apic_id: using 37 as APIC ID for node 2, core 5
238.555: * AP 25started
238.555: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
238.556: * AP 26started
238.556: get_boot_apic_id: using 39 as APIC ID for node 2, core 7
238.556: * AP 27started
238.556: get_boot_apic_id: using 41 as APIC ID for node 3, core 1
238.557: * AP 29started
238.557: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
238.557: * AP 2astarted
238.557: get_boot_apic_id: using 43 as APIC ID for node 3, core 3
238.557: * AP 2bstarted
238.557: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
238.558: * AP 2cstarted
238.558: get_boot_apic_id: using 45 as APIC ID for node 3, core 5
238.558: * AP 2dstarted
238.558: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
238.558: * AP 2estarted
238.558: get_boot_apic_id: using 47 as APIC ID for node 3, core 7
238.558: * AP 2fstarted
238.559: 
238.559: 
238.559: Begin FIDVID MSR 0xc0010071 0x52c2009e 0x3c06644c
238.559: FIDVID on BSP, APIC_id: 00
238.560: BSP fid = 0
238.560: get_boot_apic_id: using 0 as APIC ID for node 0, core 0
238.560: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
238.560: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
238.560: get_boot_apic_id: using 3 as APIC ID for node 0, core 3
238.560: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
238.561: get_boot_apic_id: using 5 as APIC ID for node 0, core 5
238.561: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
238.561: get_boot_apic_id: using 7 as APIC ID for node 0, core 7
238.561: get_boot_apic_id: using 8 as APIC ID for node 1, core 0
238.562: get_boot_apic_id: using 9 as APIC ID for node 1, core 1
238.562: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
238.562: get_boot_apic_id: using 11 as APIC ID for node 1, core 3
238.562: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
238.563: get_boot_apic_id: using 13 as APIC ID for node 1, core 5
238.563: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
238.563: get_boot_apic_id: using 15 as APIC ID for node 1, core 7
238.563: get_boot_apic_id: using 32 as APIC ID for node 2, core 0
238.563: get_boot_apic_id: using 33 as APIC ID for node 2, core 1
238.563: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
238.564: get_boot_apic_id: using 35 as APIC ID for node 2, core 3
238.564: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
238.564: get_boot_apic_id: using 37 as APIC ID for node 2, core 5
238.564: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
238.565: get_boot_apic_id: using 39 as APIC ID for node 2, core 7
238.565: get_boot_apic_id: using 40 as APIC ID for node 3, core 0
238.565: get_boot_apic_id: using 41 as APIC ID for node 3, core 1
238.565: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
238.565: get_boot_apic_id: using 43 as APIC ID for node 3, core 3
238.566: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
238.566: get_boot_apic_id: using 45 as APIC ID for node 3, core 5
238.566: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
238.566: get_boot_apic_id: using 47 as APIC ID for node 3, core 7
238.566: Wait for AP stage 1: ap_apicid = 1
238.567: <09>readback = 1000014
238.567: <09>common_fid(packed) = 0
238.567: Wait for AP stage 1: ap_apicid = 2
238.567: <09>readback = 2000014
238.567: <09>common_fid(packed) = 0
238.567: Wait for AP stage 1: ap_apicid = 3
238.567: <09>readback = 3000014
238.567: <09>common_fid(packed) = 0
238.568: Wait for AP stage 1: ap_apicid = 4
238.568: <09>readback = 4000014
238.568: <09>common_fid(packed) = 0
238.568: Wait for AP stage 1: ap_apicid = 5
238.568: <09>readback = 5000014
238.568: <09>common_fid(packed) = 0
238.568: Wait for AP stage 1: ap_apicid = 6
238.568: <09>readback = 6000014
238.568: <09>common_fid(packed) = 0
238.569: Wait for AP stage 1: ap_apicid = 7
238.569: <09>readback = 7000014
238.569: <09>common_fid(packed) = 0
238.569: Wait for AP stage 1: ap_apicid = 8
238.569: <09>readback = 8000014
238.569: <09>common_fid(packed) = 0
238.569: Wait for AP stage 1: ap_apicid = 9
238.569: <09>readback = 9000014
238.569: <09>common_fid(packed) = 0
238.570: Wait for AP stage 1: ap_apicid = a
238.570: <09>readback = a000014
238.570: <09>common_fid(packed) = 0
238.570: Wait for AP stage 1: ap_apicid = b
238.570: <09>readback = b000014
238.570: <09>common_fid(packed) = 0
238.570: Wait for AP stage 1: ap_apicid = c
238.570: <09>readback = c000014
238.571: <09>common_fid(packed) = 0
238.571: Wait for AP stage 1: ap_apicid = d
238.571: <09>readback = d000014
238.571: <09>common_fid(packed) = 0
238.571: Wait for AP stage 1: ap_apicid = e
238.571: <09>readback = e000014
238.571: <09>common_fid(packed) = 0
238.571: Wait for AP stage 1: ap_apicid = f
238.572: <09>readback = f000014
238.572: <09>common_fid(packed) = 0
238.572: Wait for AP stage 1: ap_apicid = 20
238.572: <09>readback = 20000014
238.572: <09>common_fid(packed) = 0
238.572: Wait for AP stage 1: ap_apicid = 21
238.572: <09>readback = 21000014
238.572: <09>common_fid(packed) = 0
238.573: Wait for AP stage 1: ap_apicid = 22
238.573: <09>readback = 22000014
238.573: <09>common_fid(packed) = 0
238.573: Wait for AP stage 1: ap_apicid = 23
238.573: <09>readback = 23000014
238.573: <09>common_fid(packed) = 0
238.573: Wait for AP stage 1: ap_apicid = 24
238.573: <09>readback = 24000014
238.573: <09>common_fid(packed) = 0
238.573: Wait for AP stage 1: ap_apicid = 25
238.574: <09>readback = 25000014
238.574: <09>common_fid(packed) = 0
238.574: Wait for AP stage 1: ap_apicid = 26
238.574: <09>readback = 26000014
238.574: <09>common_fid(packed) = 0
238.574: Wait for AP stage 1: ap_apicid = 27
238.574: <09>readback = 27000014
238.574: <09>common_fid(packed) = 0
238.574: Wait for AP stage 1: ap_apicid = 28
238.575: <09>readback = 28000014
238.575: <09>common_fid(packed) = 0
238.575: Wait for AP stage 1: ap_apicid = 29
238.575: <09>readback = 29000014
238.575: <09>common_fid(packed) = 0
238.575: Wait for AP stage 1: ap_apicid = 2a
238.575: <09>readback = 2a000014
238.575: <09>common_fid(packed) = 0
238.575: Wait for AP stage 1: ap_apicid = 2b
238.575: <09>readback = 2b000014
238.576: <09>common_fid(packed) = 0
238.576: Wait for AP stage 1: ap_apicid = 2c
238.576: <09>readback = 2c000014
238.576: <09>common_fid(packed) = 0
238.576: Wait for AP stage 1: ap_apicid = 2d
238.576: <09>readback = 2d000014
238.576: <09>common_fid(packed) = 0
238.577: Wait for AP stage 1: ap_apicid = 2e
238.577: <09>readback = 2e000014
238.577: <09>common_fid(packed) = 0
238.577: Wait for AP stage 1: ap_apicid = 2f
238.577: <09>readback = 2f000014
238.577: <09>common_fid(packed) = 0
238.577: common_fid = 0
238.577: End FIDVIDMSR 0xc0010071 0x52c2009e 0x3c06644c
238.578: sr5650_htinit: Node 0 Link 1, HT freq=e.
238.578: sr5650_htinit: HT3 mode
238.578: ...WARM RESET...
238.578: 
238.578: 
238.578: <00>
238.690: 
238.690: 
238.690: coreboot-4.5-1206-g589fc34 Fri Mar 10 10:20:39 UTC 2017 romstage starting...
238.690: Initial stack pointer: 000dffb8
238.691: CPU APICID 00 start flag set
238.692: BSP Family_Model: 00600f12
238.692: *sysinfo range: [000c2d20,000cd28c]
238.692: bsp_apicid = 00
238.692: cpu_init_detectedx = 00000000
238.692: sb700 reset flags: 0004
238.693: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
238.693: CBFS: Locating 'microcode_amd.bin'
238.694: CBFS: Found @ offset d0000 size 318c
238.694: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
238.694: CBFS: Locating 'microcode_amd_fam15h.bin'
238.694: CBFS: Found @ offset d3200 size 1ec4
238.716: [microcode] patch id to apply = 0x0600063d
238.717: [microcode] updated to patch id = 0x0600063d success
238.717: cpuSetAMDMSR CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
238.719: CBFS: Locating 'cmos_layout.bin'
238.719: CBFS: Found @ offset 2b0c0 size e88
238.720: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
238.720: CBFS: Locating 'cmos_layout.bin'
238.720: CBFS: Found @ offset 2b0c0 size e88
238.720:  done
238.721: Enter amd_ht_init
238.724: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1
238.724: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2
238.724: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3
238.727: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
238.727: CBFS: Locating 'cmos_layout.bin'
238.727: CBFS: Found @ offset 2b0c0 size e88
238.727: Forcing HT links to isochronous mode due to enabled IOMMU
238.727: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
238.727: CBFS: Locating 'cmos_layout.bin'
238.727: CBFS: Found @ offset 2b0c0 size e88
238.729: Exit amd_ht_init
238.729: amd_ht_fixup
238.729: amd_ht_fixup: node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1)
238.729: amd_ht_fixup: node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1)
238.729: amd_ht_fixup: node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1)
238.729: amd_ht_fixup: node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1)
238.729: cpuSetAMDPCI 00 done
238.732: cpuSetAMDPCI 01 done
238.732: cpuSetAMDPCI 02 done
238.732: cpuSetAMDPCI 03 done
238.732: Prep FID/VID Node:00
238.733:   F3x80: e20be281
238.733:   F3x84: 01e200e2
238.733:   F3xD4: c3312f18
238.733:   F3xD8: 03000016
238.733:   F3xDC: 05475632
238.733: Prep FID/VID Node:01
238.733:   F3x80: e20be281
238.733:   F3x84: 01e200e2
238.733:   F3xD4: c3312f18
238.733:   F3xD8: 03000016
238.733:   F3xDC: 05475632
238.733: Prep FID/VID Node:02
238.733:   F3x80: e20be281
238.733:   F3x84: 01e200e2
238.733:   F3xD4: c3312f18
238.733:   F3xD8: 03000016
238.733:   F3xDC: 05475632
238.733: Prep FID/VID Node:03
238.733:   F3x80: e20be281
238.733:   F3x84: 01e200e2
238.733:   F3xD4: c3312f18
238.733:   F3xD8: 03000016
238.733:   F3xDC: 05475632
238.733: setup_remote_node: 01 done
238.733: Start node 01 done.
238.733: setup_remote_node: 02 done
238.734: Start node 02 done.
238.734: setup_remote_node: 03 done
238.735: Start node 03 done.
238.739: core0 started:  01 02 03
238.741: sr5650_early_setup()
238.742: get_cpu_rev EAX=0x600f12.
238.743: CPU Rev is Fam 15.
238.745: NB Revision is A12.
238.746: fam10_optimization()
238.747: sr5650_por_init
238.748: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
238.750: CBFS: Locating 'cmos_layout.bin'
238.750: CBFS: Found @ offset 2b0c0 size e88
238.750: Enabling IOMMU
238.751: sb700_early_setup()
238.751: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
238.753: CBFS: Locating 'cmos_layout.bin'
238.754: CBFS: Found @ offset 2b0c0 size e88
238.754: sb700_devices_por_init()
238.756: sb700_devices_por_init(): SMBus Device, BDF:0-20-0
238.756: SMBus controller enabled, sb revision is A15
238.756: sb700_devices_por_init: Disabling ISA DMA support
238.758: sb700_devices_por_init(): IDE Device, BDF:0-20-1
238.761: sb700_devices_por_init(): LPC Device, BDF:0-20-3
238.762: sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
238.762: sb700_devices_por_init(): SATA Device, BDF:0-17-0
238.763: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
238.763: CBFS: Locating 'cmos_layout.bin'
238.764: CBFS: Found @ offset 2b0c0 size e88
238.764: sb700_pmio_por_init()
238.766: start_other_cores()
238.766: init node: 00  cores: 07 pass 1
238.766: Start other core - nodeid: 00  cores: 07
238.766: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
238.817: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
238.842: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
238.865: init node: 01  cores: 07 pass 1
238.868: Start other core - nodeid: 01  cores: 07
238.873: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
239.085: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
239.085: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
239.086: init node: 02  cores: 07 pass 1
239.087: Start other core - nodeid: 02  cores: 07
239.089: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
239.297: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
239.297: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
239.297: init node: 03  cores: 07 pass 1
239.299: Start other core - nodeid: 03  cores: 07
239.300: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
239.506: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
239.506: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
239.506: started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
239.511: * AP 01started
239.512: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
239.514: * AP 02started
239.518: get_boot_apic_id: using 3 as APIC ID for node 0, core 3
239.519: * AP 03started
239.519: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
239.519: * AP 04started
239.519: get_boot_apic_id: using 5 as APIC ID for node 0, core 5
239.522: * AP 05started
239.522: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
239.524: * AP 06started
239.524: get_boot_apic_id: using 7 as APIC ID for node 0, core 7
239.524: * AP 07started
239.524: get_boot_apic_id: using 9 as APIC ID for node 1, core 1
239.526: * AP 09started
239.526: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
239.528: * AP 0astarted
239.528: get_boot_apic_id: using 11 as APIC ID for node 1, core 3
239.528: * AP 0bstarted
239.528: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
239.530: * AP 0cstarted
239.531: get_boot_apic_id: using 13 as APIC ID for node 1, core 5
239.532: * AP 0dstarted
239.532: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
239.532: * AP 0estarted
239.532: get_boot_apic_id: using 15 as APIC ID for node 1, core 7
239.534: * AP 0fstarted
239.534: get_boot_apic_id: using 33 as APIC ID for node 2, core 1
239.534: * AP 21started
239.534: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
239.534: * AP 22started
239.535: get_boot_apic_id: using 35 as APIC ID for node 2, core 3
239.535: * AP 23started
239.535: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
239.535: * AP 24started
239.535: get_boot_apic_id: using 37 as APIC ID for node 2, core 5
239.535: * AP 25started
239.535: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
239.535: * AP 26started
239.535: get_boot_apic_id: using 39 as APIC ID for node 2, core 7
239.535: * AP 27started
239.535: get_boot_apic_id: using 41 as APIC ID for node 3, core 1
239.535: * AP 29started
239.535: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
239.535: * AP 2astarted
239.535: get_boot_apic_id: using 43 as APIC ID for node 3, core 3
239.535: * AP 2bstarted
239.535: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
239.535: * AP 2cstarted
239.535: get_boot_apic_id: using 45 as APIC ID for node 3, core 5
239.535: * AP 2dstarted
239.535: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
239.535: * AP 2estarted
239.535: get_boot_apic_id: using 47 as APIC ID for node 3, core 7
239.535: * AP 2fstarted
239.535: 
239.535: 
239.535: Begin FIDVID MSR 0xc0010071 0x52c2009e 0x3c025408
239.536: End FIDVIDMSR 0xc0010071 0x52c2009e 0x3c025408
239.536: sr5650_htinit: Node 0 Link 1, HT freq=e.
239.536: sr5650_htinit: HT3 mode
239.536: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
239.536: CBFS: Locating 'cmos_layout.bin'
239.536: CBFS: Found @ offset 2b0c0 size e88
239.537: ...WARM RESET...
239.537: 
239.537: 
239.537: <00>
239.641: 
239.641: 
239.641: coreboot-4.5-1206-g589fc34 Fri Mar 10 10:20:39 UTC 2017 romstage starting...
239.641: Initial stack pointer: 000dffb8
239.642: CPU APICID 00 start flag set
239.643: BSP Family_Model: 00600f12
239.643: *sysinfo range: [000c2d20,000cd28c]
239.643: bsp_apicid = 00
239.643: cpu_init_detectedx = 00000000
239.643: sb700 reset flags: 0004
239.644: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
239.644: CBFS: Locating 'microcode_amd.bin'
239.644: CBFS: Found @ offset d0000 size 318c
239.645: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
239.645: CBFS: Locating 'microcode_amd_fam15h.bin'
239.645: CBFS: Found @ offset d3200 size 1ec4
239.659: [microcode] patch id to apply = 0x0600063d
239.659: [microcode] updated to patch id = 0x0600063d success
239.659: cpuSetAMDMSR CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
239.661: CBFS: Locating 'cmos_layout.bin'
239.661: CBFS: Found @ offset 2b0c0 size e88
239.662: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
239.662: CBFS: Locating 'cmos_layout.bin'
239.662: CBFS: Found @ offset 2b0c0 size e88
239.663:  done
239.663: Enter amd_ht_init
239.666: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 2 new node: 1
239.666: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 0 new node: 2
239.666: AMD_CB_EventNotify: INFO: HT_EVENT_COH_NODE_DISCOVERED: node 0 link 3 new node: 3
239.669: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
239.669: CBFS: Locating 'cmos_layout.bin'
239.669: CBFS: Found @ offset 2b0c0 size e88
239.669: Forcing HT links to isochronous mode due to enabled IOMMU
239.669: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
239.669: CBFS: Locating 'cmos_layout.bin'
239.670: CBFS: Found @ offset 2b0c0 size e88
239.670: Exit amd_ht_init
239.671: amd_ht_fixup
239.671: amd_ht_fixup: node 0 (internal node ID 0): disabling defective HT link (L3 connected: 1)
239.671: amd_ht_fixup: node 1 (internal node ID 1): disabling defective HT link (L3 connected: 1)
239.671: amd_ht_fixup: node 2 (internal node ID 0): disabling defective HT link (L3 connected: 1)
239.671: amd_ht_fixup: node 3 (internal node ID 1): disabling defective HT link (L3 connected: 1)
239.671: cpuSetAMDPCI 00 done
239.674: cpuSetAMDPCI 01 done
239.674: cpuSetAMDPCI 02 done
239.674: cpuSetAMDPCI 03 done
239.674: Prep FID/VID Node:00
239.675:   F3x80: e20be281
239.675:   F3x84: 01e200e2
239.675:   F3xD4: c3312f18
239.675:   F3xD8: 03000016
239.675:   F3xDC: 05475632
239.675: Prep FID/VID Node:01
239.675:   F3x80: e20be281
239.675:   F3x84: 01e200e2
239.675:   F3xD4: c3312f18
239.675:   F3xD8: 03000016
239.675:   F3xDC: 05475632
239.675: Prep FID/VID Node:02
239.675:   F3x80: e20be281
239.675:   F3x84: 01e200e2
239.675:   F3xD4: c3312f18
239.675:   F3xD8: 03000016
239.675:   F3xDC: 05475632
239.675: Prep FID/VID Node:03
239.675:   F3x80: e20be281
239.675:   F3x84: 01e200e2
239.675:   F3xD4: c3312f18
239.675:   F3xD8: 03000016
239.675:   F3xDC: 05475632
239.675: setup_remote_node: 01 done
239.675: Start node 01 done.
239.675: setup_remote_node: 02 done
239.676: Start node 02 done.
239.676: setup_remote_node: 03 done
239.677: Start node 03 done.
239.680: core0 started:  01 02 03
239.683: sr5650_early_setup()
239.684: get_cpu_rev EAX=0x600f12.
239.685: CPU Rev is Fam 15.
239.686: NB Revision is A12.
239.687: fam10_optimization()
239.689: sr5650_por_init
239.690: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
239.692: CBFS: Locating 'cmos_layout.bin'
239.692: CBFS: Found @ offset 2b0c0 size e88
239.692: Enabling IOMMU
239.698: sb700_early_setup()
239.699: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
239.700: CBFS: Locating 'cmos_layout.bin'
239.700: CBFS: Found @ offset 2b0c0 size e88
239.700: sb700_devices_por_init()
239.700: sb700_devices_por_init(): SMBus Device, BDF:0-20-0
239.706: SMBus controller enabled, sb revision is A15
239.707: sb700_devices_por_init: Disabling ISA DMA support
239.707: sb700_devices_por_init(): IDE Device, BDF:0-20-1
239.709: sb700_devices_por_init(): LPC Device, BDF:0-20-3
239.710: sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
239.710: sb700_devices_por_init(): SATA Device, BDF:0-17-0
239.710: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
239.710: CBFS: Locating 'cmos_layout.bin'
239.710: CBFS: Found @ offset 2b0c0 size e88
239.711: sb700_pmio_por_init()
239.711: start_other_cores()
239.711: init node: 00  cores: 07 pass 1
239.711: Start other core - nodeid: 00  cores: 07
239.711: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
239.778: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
239.779: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
239.788: init node: 01  cores: 07 pass 1
239.791: Start other core - nodeid: 01  cores: 07
239.795: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
239.920: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
239.958: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
239.959: init node: 02  cores: 07 pass 1
239.960: Start other core - nodeid: 02  cores: 07
239.962: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
240.109: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
240.125: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
240.139: init node: 03  cores: 07 pass 1
240.140: Start other core - nodeid: 03  cores: 07
240.142: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
240.284: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
240.302: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
240.316: started ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
240.319: * AP 01started
240.320: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
240.325: * AP 02started
240.325: get_boot_apic_id: using 3 as APIC ID for node 0, core 3
240.326: * AP 03started
240.326: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
240.326: * AP 04started
240.326: get_boot_apic_id: using 5 as APIC ID for node 0, core 5
240.329: * AP 05started
240.330: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
240.330: * AP 06started
240.330: get_boot_apic_id: using 7 as APIC ID for node 0, core 7
240.330: * AP 07started
240.330: get_boot_apic_id: using 9 as APIC ID for node 1, core 1
240.334: * AP 09started
240.334: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
240.334: * AP 0astarted
240.335: get_boot_apic_id: using 11 as APIC ID for node 1, core 3
240.334: * AP 0bstarted
240.336: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
240.338: * AP 0cstarted
240.339: get_boot_apic_id: using 13 as APIC ID for node 1, core 5
240.339: * AP 0dstarted
240.339: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
240.339: * AP 0estarted
240.341: get_boot_apic_id: using 15 as APIC ID for node 1, core 7
240.341: * AP 0fstarted
240.341: get_boot_apic_id: using 33 as APIC ID for node 2, core 1
240.341: * AP 21started
240.341: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
240.341: * AP 22started
240.341: get_boot_apic_id: using 35 as APIC ID for node 2, core 3
240.342: * AP 23started
240.342: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
240.342: * AP 24started
240.342: get_boot_apic_id: using 37 as APIC ID for node 2, core 5
240.342: * AP 25started
240.342: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
240.342: * AP 26started
240.342: get_boot_apic_id: using 39 as APIC ID for node 2, core 7
240.342: * AP 27started
240.342: get_boot_apic_id: using 41 as APIC ID for node 3, core 1
240.342: * AP 29started
240.342: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
240.342: * AP 2astarted
240.342: get_boot_apic_id: using 43 as APIC ID for node 3, core 3
240.342: * AP 2bstarted
240.342: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
240.342: * AP 2cstarted
240.342: get_boot_apic_id: using 45 as APIC ID for node 3, core 5
240.342: * AP 2dstarted
240.342: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
240.342: * AP 2estarted
240.342: get_boot_apic_id: using 47 as APIC ID for node 3, core 7
240.342: * AP 2fstarted
240.342: 
240.342: 
240.342: Begin FIDVID MSR 0xc0010071 0x52c2009e 0x3c025408
240.342: End FIDVIDMSR 0xc0010071 0x52c2009e 0x3c025408
240.343: sr5650_htinit: Node 0 Link 1, HT freq=e.
240.343: sr5650_htinit: HT3 mode
240.343: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
240.343: CBFS: Locating 'cmos_layout.bin'
240.343: CBFS: Found @ offset 2b0c0 size e88
240.344: Node 00 DIMM voltage set to index 00
240.344: Node 01 DIMM voltage set to index 00
240.344: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
240.344: CBFS: Locating 'cmos_layout.bin'
240.344: CBFS: Found @ offset 2b0c0 size e88
240.344: stopped ap apicid: get_boot_apic_id: using 1 as APIC ID for node 0, core 1
240.344: * AP 01stopped
240.344: get_boot_apic_id: using 2 as APIC ID for node 0, core 2
240.344: * AP 02stopped
240.344: get_boot_apic_id: using 3 as APIC ID for node 0, core 3
240.344: * AP 03stopped
240.344: get_boot_apic_id: using 4 as APIC ID for node 0, core 4
240.344: * AP 04stopped
240.344: get_boot_apic_id: using 5 as APIC ID for node 0, core 5
240.344: * AP 05stopped
240.344: get_boot_apic_id: using 6 as APIC ID for node 0, core 6
240.344: * AP 06stopped
240.344: get_boot_apic_id: using 7 as APIC ID for node 0, core 7
240.344: * AP 07stopped
240.344: get_boot_apic_id: using 9 as APIC ID for node 1, core 1
240.344: * AP 09stopped
240.344: get_boot_apic_id: using 10 as APIC ID for node 1, core 2
240.344: * AP 0astopped
240.344: get_boot_apic_id: using 11 as APIC ID for node 1, core 3
240.344: * AP 0bstopped
240.344: get_boot_apic_id: using 12 as APIC ID for node 1, core 4
240.344: * AP 0cstopped
240.344: get_boot_apic_id: using 13 as APIC ID for node 1, core 5
240.344: * AP 0dstopped
240.344: get_boot_apic_id: using 14 as APIC ID for node 1, core 6
240.344: * AP 0estopped
240.344: get_boot_apic_id: using 15 as APIC ID for node 1, core 7
240.344: * AP 0fstopped
240.344: get_boot_apic_id: using 33 as APIC ID for node 2, core 1
240.344: * AP 21stopped
240.345: get_boot_apic_id: using 34 as APIC ID for node 2, core 2
240.345: * AP 22stopped
240.345: get_boot_apic_id: using 35 as APIC ID for node 2, core 3
240.345: * AP 23stopped
240.345: get_boot_apic_id: using 36 as APIC ID for node 2, core 4
240.345: * AP 24stopped
240.345: get_boot_apic_id: using 37 as APIC ID for node 2, core 5
240.345: * AP 25stopped
240.345: get_boot_apic_id: using 38 as APIC ID for node 2, core 6
240.345: * AP 26stopped
240.345: get_boot_apic_id: using 39 as APIC ID for node 2, core 7
240.345: * AP 27stopped
240.345: get_boot_apic_id: using 41 as APIC ID for node 3, core 1
240.345: * AP 29stopped
240.345: get_boot_apic_id: using 42 as APIC ID for node 3, core 2
240.345: * AP 2astopped
240.345: get_boot_apic_id: using 43 as APIC ID for node 3, core 3
240.345: * AP 2bstopped
240.345: get_boot_apic_id: using 44 as APIC ID for node 3, core 4
240.345: * AP 2cstopped
240.345: get_boot_apic_id: using 45 as APIC ID for node 3, core 5
240.345: * AP 2dstopped
240.345: get_boot_apic_id: using 46 as APIC ID for node 3, core 6
240.345: * AP 2estopped
240.345: get_boot_apic_id: using 47 as APIC ID for node 3, core 7
240.345: * AP 2fstopped
240.345: 
240.345: fill_mem_ctrl() detected 4 nodes
240.345: raminit_amdmct()
240.345: raminit_amdmct begin:
240.346: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
240.346: CBFS: Locating 'cmos_layout.bin'
240.346: CBFS: Found @ offset 2b0c0 size e88
240.346: mctAutoInitMCT_D: mct_init Node 0
240.347: mctAutoInitMCT_D: mct_InitialMCT_D
240.347: mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
240.347: mctAutoInitMCT_D: mctSMBhub_Init
240.348: activate_spd_rom() for node 00
240.348: enable_spd_node0()
240.348: mctAutoInitMCT_D: mct_preInitDCT
240.348: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
240.348: CBFS: Locating 'cmos_layout.bin'
240.349: CBFS: Found @ offset 2b0c0 size e88
241.957: <09> DIMMPresence: DIMMValid=f
241.957: <09> DIMMPresence: DIMMPresent=f
241.957: <09> DIMMPresence: RegDIMMPresent=f
241.957: <09> DIMMPresence: LRDIMMPresent=0
241.957: <09> DIMMPresence: DimmECCPresent=f
241.957: <09> DIMMPresence: DimmPARPresent=0
241.957: <09> DIMMPresence: Dimmx4Present=f
241.957: <09> DIMMPresence: Dimmx8Present=0
241.957: <09> DIMMPresence: Dimmx16Present=0
241.957: <09> DIMMPresence: DimmPlPresent=0
241.957: <09> DIMMPresence: DimmDRPresent=f
241.957: <09> DIMMPresence: DimmQRPresent=0
241.957: <09> DIMMPresence: DATAload[0]=4
241.957: <09> DIMMPresence: MAload[0]=40
241.957: <09> DIMMPresence: MAdimms[0]=2
241.957: <09> DIMMPresence: DATAload[1]=4
241.957: <09> DIMMPresence: MAload[1]=40
241.957: <09> DIMMPresence: MAdimms[1]=2
241.957: <09> DIMMPresence: Status 2005
241.957: <09> DIMMPresence: ErrStatus 0
241.958: <09> DIMMPresence: ErrCode 0
241.958: <09> DIMMPresence: Done
241.958: 
241.958: <09><09>DCTPreInit_D: mct_DIMMPresence Done
241.958: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
241.958: CBFS: Locating 's3nv'
241.958: CBFS: Found @ offset 2fec0 size 10000
241.958: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
241.958: CBFS: Locating 's3nv'
241.958: CBFS: Found @ offset 2fec0 size 10000
241.959: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
241.959: CBFS: Locating 'cmos_layout.bin'
241.959: CBFS: Found @ offset 2b0c0 size e88
241.959: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
241.959: CBFS: Locating 'cmos_layout.bin'
241.959: CBFS: Found @ offset 2b0c0 size e88
241.959: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
241.959: CBFS: Locating 'cmos_layout.bin'
241.959: CBFS: Found @ offset 2b0c0 size e88
241.960: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
241.959: CBFS: Locating 'cmos_layout.bin'
241.960: CBFS: Found @ offset 2b0c0 size e88
241.960: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
241.960: CBFS: Locating 'cmos_layout.bin'
241.960: CBFS: Found @ offset 2b0c0 size e88
241.960: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
241.960: CBFS: Locating 'cmos_layout.bin'
241.960: CBFS: Found @ offset 2b0c0 size e88
241.960: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
241.960: CBFS: Locating 'cmos_layout.bin'
241.960: CBFS: Found @ offset 2b0c0 size e88
241.960: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
241.960: CBFS: Locating 'cmos_layout.bin'
241.960: CBFS: Found @ offset 2b0c0 size e88
241.960: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
241.960: CBFS: Locating 'cmos_layout.bin'
241.961: CBFS: Found @ offset 2b0c0 size e88
241.961: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
241.961: CBFS: Locating 'cmos_layout.bin'
241.961: CBFS: Found @ offset 2b0c0 size e88
241.961: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
241.961: CBFS: Locating 'cmos_layout.bin'
241.961: CBFS: Found @ offset 2b0c0 size e88
241.961: mctAutoInitMCT_D: mct_init Node 1
241.961: mctAutoInitMCT_D: mct_InitialMCT_D
241.961: mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
241.961: mctAutoInitMCT_D: mctSMBhub_Init
241.961: activate_spd_rom() for node 01
241.961: enable_spd_node1()
241.961: mctAutoInitMCT_D: mct_preInitDCT
241.961: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
241.961: CBFS: Locating 'cmos_layout.bin'
241.961: CBFS: Found @ offset 2b0c0 size e88
243.570: <09> DIMMPresence: DIMMValid=f
243.569: <09> DIMMPresence: DIMMPresent=f
243.569: <09> DIMMPresence: RegDIMMPresent=f
243.569: <09> DIMMPresence: LRDIMMPresent=0
243.569: <09> DIMMPresence: DimmECCPresent=f
243.569: <09> DIMMPresence: DimmPARPresent=0
243.569: <09> DIMMPresence: Dimmx4Present=f
243.569: <09> DIMMPresence: Dimmx8Present=0
243.570: <09> DIMMPresence: Dimmx16Present=0
243.570: <09> DIMMPresence: DimmPlPresent=0
243.570: <09> DIMMPresence: DimmDRPresent=f
243.570: <09> DIMMPresence: DimmQRPresent=0
243.570: <09> DIMMPresence: DATAload[0]=4
243.570: <09> DIMMPresence: MAload[0]=40
243.570: <09> DIMMPresence: MAdimms[0]=2
243.570: <09> DIMMPresence: DATAload[1]=4
243.570: <09> DIMMPresence: MAload[1]=40
243.570: <09> DIMMPresence: MAdimms[1]=2
243.570: <09> DIMMPresence: Status 2005
243.570: <09> DIMMPresence: ErrStatus 0
243.570: <09> DIMMPresence: ErrCode 0
243.570: <09> DIMMPresence: Done
243.570: 
243.570: <09><09>DCTPreInit_D: mct_DIMMPresence Done
243.570: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
243.570: CBFS: Locating 's3nv'
243.570: CBFS: Found @ offset 2fec0 size 10000
243.570: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
243.570: CBFS: Locating 's3nv'
243.570: CBFS: Found @ offset 2fec0 size 10000
243.570: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
243.570: CBFS: Locating 'cmos_layout.bin'
243.570: CBFS: Found @ offset 2b0c0 size e88
243.570: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
243.570: CBFS: Locating 'cmos_layout.bin'
243.570: CBFS: Found @ offset 2b0c0 size e88
243.570: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
243.570: CBFS: Locating 'cmos_layout.bin'
243.570: CBFS: Found @ offset 2b0c0 size e88
243.571: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
243.571: CBFS: Locating 'cmos_layout.bin'
243.571: CBFS: Found @ offset 2b0c0 size e88
243.571: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
243.571: CBFS: Locating 'cmos_layout.bin'
243.571: CBFS: Found @ offset 2b0c0 size e88
243.571: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
243.571: CBFS: Locating 'cmos_layout.bin'
243.571: CBFS: Found @ offset 2b0c0 size e88
243.571: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
243.571: CBFS: Locating 'cmos_layout.bin'
243.571: CBFS: Found @ offset 2b0c0 size e88
243.571: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
243.571: CBFS: Locating 'cmos_layout.bin'
243.571: CBFS: Found @ offset 2b0c0 size e88
243.572: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
243.572: CBFS: Locating 'cmos_layout.bin'
243.572: CBFS: Found @ offset 2b0c0 size e88
243.572: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
243.572: CBFS: Locating 'cmos_layout.bin'
243.572: CBFS: Found @ offset 2b0c0 size e88
243.572: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
243.572: CBFS: Locating 'cmos_layout.bin'
243.572: CBFS: Found @ offset 2b0c0 size e88
243.572: mctAutoInitMCT_D: mct_init Node 2
243.572: mctAutoInitMCT_D: mct_InitialMCT_D
243.572: mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
243.572: mctAutoInitMCT_D: mctSMBhub_Init
243.572: activate_spd_rom() for node 02
243.572: enable_spd_node2()
243.572: mctAutoInitMCT_D: mct_preInitDCT
243.572: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
243.572: CBFS: Locating 'cmos_layout.bin'
243.572: CBFS: Found @ offset 2b0c0 size e88
245.180: <09> DIMMPresence: DIMMValid=f
245.180: <09> DIMMPresence: DIMMPresent=f
245.180: <09> DIMMPresence: RegDIMMPresent=f
245.180: <09> DIMMPresence: LRDIMMPresent=0
245.180: <09> DIMMPresence: DimmECCPresent=f
245.180: <09> DIMMPresence: DimmPARPresent=0
245.180: <09> DIMMPresence: Dimmx4Present=f
245.180: <09> DIMMPresence: Dimmx8Present=0
245.180: <09> DIMMPresence: Dimmx16Present=0
245.181: <09> DIMMPresence: DimmPlPresent=0
245.181: <09> DIMMPresence: DimmDRPresent=f
245.181: <09> DIMMPresence: DimmQRPresent=0
245.181: <09> DIMMPresence: DATAload[0]=4
245.181: <09> DIMMPresence: MAload[0]=40
245.181: <09> DIMMPresence: MAdimms[0]=2
245.181: <09> DIMMPresence: DATAload[1]=4
245.181: <09> DIMMPresence: MAload[1]=40
245.181: <09> DIMMPresence: MAdimms[1]=2
245.181: <09> DIMMPresence: Status 2005
245.181: <09> DIMMPresence: ErrStatus 0
245.181: <09> DIMMPresence: ErrCode 0
245.181: <09> DIMMPresence: Done
245.181: 
245.181: <09><09>DCTPreInit_D: mct_DIMMPresence Done
245.181: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
245.181: CBFS: Locating 's3nv'
245.181: CBFS: Found @ offset 2fec0 size 10000
245.181: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
245.181: CBFS: Locating 's3nv'
245.181: CBFS: Found @ offset 2fec0 size 10000
245.181: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
245.181: CBFS: Locating 'cmos_layout.bin'
245.181: CBFS: Found @ offset 2b0c0 size e88
245.181: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
245.181: CBFS: Locating 'cmos_layout.bin'
245.181: CBFS: Found @ offset 2b0c0 size e88
245.181: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
245.181: CBFS: Locating 'cmos_layout.bin'
245.181: CBFS: Found @ offset 2b0c0 size e88
245.182: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
245.182: CBFS: Locating 'cmos_layout.bin'
245.182: CBFS: Found @ offset 2b0c0 size e88
245.182: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
245.182: CBFS: Locating 'cmos_layout.bin'
245.182: CBFS: Found @ offset 2b0c0 size e88
245.182: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
245.182: CBFS: Locating 'cmos_layout.bin'
245.182: CBFS: Found @ offset 2b0c0 size e88
245.182: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
245.182: CBFS: Locating 'cmos_layout.bin'
245.182: CBFS: Found @ offset 2b0c0 size e88
245.182: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
245.182: CBFS: Locating 'cmos_layout.bin'
245.182: CBFS: Found @ offset 2b0c0 size e88
245.183: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
245.183: CBFS: Locating 'cmos_layout.bin'
245.183: CBFS: Found @ offset 2b0c0 size e88
245.183: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
245.183: CBFS: Locating 'cmos_layout.bin'
245.183: CBFS: Found @ offset 2b0c0 size e88
245.183: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
245.183: CBFS: Locating 'cmos_layout.bin'
245.183: CBFS: Found @ offset 2b0c0 size e88
245.183: mctAutoInitMCT_D: mct_init Node 3
245.183: mctAutoInitMCT_D: mct_InitialMCT_D
245.183: mct_InitialMCT_D: mct_ForceNBPState0_En_Fam15
245.183: mctAutoInitMCT_D: mctSMBhub_Init
245.183: activate_spd_rom() for node 03
245.183: enable_spd_node3()
245.183: mctAutoInitMCT_D: mct_preInitDCT
245.183: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
245.183: CBFS: Locating 'cmos_layout.bin'
245.183: CBFS: Found @ offset 2b0c0 size e88
246.791: <09> DIMMPresence: DIMMValid=f
246.791: <09> DIMMPresence: DIMMPresent=f
246.791: <09> DIMMPresence: RegDIMMPresent=f
246.791: <09> DIMMPresence: LRDIMMPresent=0
246.791: <09> DIMMPresence: DimmECCPresent=f
246.791: <09> DIMMPresence: DimmPARPresent=0
246.791: <09> DIMMPresence: Dimmx4Present=f
246.791: <09> DIMMPresence: Dimmx8Present=0
246.791: <09> DIMMPresence: Dimmx16Present=0
246.792: <09> DIMMPresence: DimmPlPresent=0
246.792: <09> DIMMPresence: DimmDRPresent=f
246.792: <09> DIMMPresence: DimmQRPresent=0
246.792: <09> DIMMPresence: DATAload[0]=4
246.792: <09> DIMMPresence: MAload[0]=40
246.792: <09> DIMMPresence: MAdimms[0]=2
246.792: <09> DIMMPresence: DATAload[1]=4
246.792: <09> DIMMPresence: MAload[1]=40
246.792: <09> DIMMPresence: MAdimms[1]=2
246.792: <09> DIMMPresence: Status 2005
246.792: <09> DIMMPresence: ErrStatus 0
246.792: <09> DIMMPresence: ErrCode 0
246.792: <09> DIMMPresence: Done
246.792: 
246.792: <09><09>DCTPreInit_D: mct_DIMMPresence Done
246.792: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.792: CBFS: Locating 's3nv'
246.792: CBFS: Found @ offset 2fec0 size 10000
246.792: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.792: CBFS: Locating 's3nv'
246.792: CBFS: Found @ offset 2fec0 size 10000
246.792: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.792: CBFS: Locating 'cmos_layout.bin'
246.792: CBFS: Found @ offset 2b0c0 size e88
246.792: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.792: CBFS: Locating 'cmos_layout.bin'
246.792: CBFS: Found @ offset 2b0c0 size e88
246.792: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.792: CBFS: Locating 'cmos_layout.bin'
246.792: CBFS: Found @ offset 2b0c0 size e88
246.793: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.793: CBFS: Locating 'cmos_layout.bin'
246.793: CBFS: Found @ offset 2b0c0 size e88
246.793: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.793: CBFS: Locating 'cmos_layout.bin'
246.793: CBFS: Found @ offset 2b0c0 size e88
246.793: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.793: CBFS: Locating 'cmos_layout.bin'
246.793: CBFS: Found @ offset 2b0c0 size e88
246.793: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.793: CBFS: Locating 'cmos_layout.bin'
246.793: CBFS: Found @ offset 2b0c0 size e88
246.793: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.793: CBFS: Locating 'cmos_layout.bin'
246.793: CBFS: Found @ offset 2b0c0 size e88
246.794: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.794: CBFS: Locating 'cmos_layout.bin'
246.794: CBFS: Found @ offset 2b0c0 size e88
246.794: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.794: CBFS: Locating 'cmos_layout.bin'
246.794: CBFS: Found @ offset 2b0c0 size e88
246.794: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.794: CBFS: Locating 'cmos_layout.bin'
246.794: CBFS: Found @ offset 2b0c0 size e88
246.794: mctAutoInitMCT_D: mct_init Node 4
246.794: mctAutoInitMCT_D: mct_init Node 5
246.794: mctAutoInitMCT_D: mct_init Node 6
246.794: mctAutoInitMCT_D: mct_init Node 7
246.794: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.795: CBFS: Locating 'cmos_layout.bin'
246.795: CBFS: Found @ offset 2b0c0 size e88
246.795: mctAutoInitMCT_D: DIMMSetVoltage
246.795: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.795: CBFS: Locating 'cmos_layout.bin'
246.795: CBFS: Found @ offset 2b0c0 size e88
246.796: Node 00 DIMM voltage set to index 00
246.796: Node 01 DIMM voltage set to index 00
246.896: mctAutoInitMCT_D: mctSMBhub_Init
246.896: activate_spd_rom() for node 00
246.896: enable_spd_node0()
246.896: mctAutoInitMCT_D: mct_initDCT
246.896: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.896: CBFS: Locating 'cmos_layout.bin'
246.896: CBFS: Found @ offset 2b0c0 size e88
246.897: SPDCalcWidth: Status 2005
246.897: SPDCalcWidth: ErrStatus 0
246.897: SPDCalcWidth: ErrCode 0
246.897: SPDCalcWidth: Done
246.897: <09><09>DCTInit_D: mct_SPDCalcWidth Done
246.897: AutoCycTiming_D: Start
246.897: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.897: CBFS: Locating 'cmos_layout.bin'
246.897: CBFS: Found @ offset 2b0c0 size e88
246.897: GetPresetmaxF_D: Start
246.897: GetPresetmaxF_D: Done
246.898: SPDGetTCL_D: Start
246.898: SPDGetTCL_D: DIMMCASL 5
246.898: SPDGetTCL_D: DIMMAutoSpeed 4
246.898: SPDGetTCL_D: Status 2005
246.898: SPDGetTCL_D: ErrStatus 0
246.898: SPDGetTCL_D: ErrCode 0
246.898: SPDGetTCL_D: Done
246.898: 
246.898: SPD2ndTiming: Start
246.899: SPD2ndTiming: Done
246.899: AutoCycTiming: Status 2005
246.899: AutoCycTiming: ErrStatus 0
246.899: AutoCycTiming: ErrCode 0
246.899: AutoCycTiming: Done
246.899: 
246.899: <09><09>DCTInit_D: AutoCycTiming_D Done
246.900: SPDSetBanks: CSPresent f
246.900: SPDSetBanks: Status 2005
246.900: SPDSetBanks: ErrStatus 0
246.900: SPDSetBanks: ErrCode 0
246.900: SPDSetBanks: Done
246.900: 
246.900: AfterStitch pDCTstat->NodeSysBase = 0
246.900: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7ffffff
246.900: StitchMemory: Status 2005
246.900: StitchMemory: ErrStatus 0
246.900: StitchMemory: ErrCode 0
246.900: StitchMemory: Done
246.900: 
246.900: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.900: CBFS: Locating 'cmos_layout.bin'
246.900: CBFS: Found @ offset 2b0c0 size e88
246.901: InterleaveBanks_D: Status 2005
246.901: InterleaveBanks_D: ErrStatus 0
246.901: InterleaveBanks_D: ErrCode 0
246.901: InterleaveBanks_D: Done
246.901: 
246.901: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.901: CBFS: Locating 'cmos_layout.bin'
246.901: CBFS: Found @ offset 2b0c0 size e88
246.902: AutoConfig_D: DramControl:     00002a06
246.902: AutoConfig_D: DramTimingLo:    00000000
246.902: AutoConfig_D: DramConfigMisc:  00000000
246.902: AutoConfig_D: DramConfigMisc2: 00000000
246.902: AutoConfig_D: DramConfigLo:    03083000
246.902: AutoConfig_D: DramConfigHi:    0f090084
246.902: InitDDRPhy: Start
246.903: InitDDRPhy: Done
246.903: mct_SetDramConfigHi_D: Start
246.904: set_2t_configuration: Start
246.904: set_2t_configuration: Done
246.904: mct_BeforePlatformSpec: Start
246.904: mct_BeforePlatformSpec: Done
246.904: mct_PlatformSpec: Start
246.904: Programmed DCT 0 timing/termination pattern 00000000 10222222
246.904: mct_PlatformSpec: Done
246.904: mct_SetDramConfigHi_D: DramConfigHi:    0f090084
246.904: *
246.904: mct_SetDramConfigHi_D: Done
246.904: mct_EarlyArbEn_D: Start
246.904: mct_EarlyArbEn_D: Done
246.904: AutoConfig: Status 2005
246.904: AutoConfig: ErrStatus 0
246.904: AutoConfig: ErrCode 0
246.904: AutoConfig: Done
246.904: 
246.904: <09><09>DCTInit_D: AutoConfig_D Done
246.904: <09><09>DCTInit_D: PlatformSpec_D Done
246.904: <09><09>DCTFinalInit_D: StartupDCT_D Start
246.904: mct_BeforeDramInit_Prod_D: Start
246.904: mct_ProgramODT_D: Start
246.905: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
246.905: mct_ProgramODT_D: Done
246.905: mct_BeforeDramInit_Prod_D: Done
246.905: mct_DramInit_Sw_D: Start
246.905: mct_DCTAccessDone: Start
246.905: mct_DCTAccessDone: Done
246.906: mct_DramControlReg_Init_D: Start
246.907: mct_DramControlReg_Init_D: F2xA8: 00000300
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC0: 02
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC1: 00
246.907: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC3: 05
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC4: 05
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC5: 05
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC6: 00
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC7: 00
246.907: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC9: 0d
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC10: 00
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC11: 00
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC12: 00
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC13: 00
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC14: 00
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC15: 00
246.907: mct_DramControlReg_Init_D: F2xA8: 00000c00
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
246.907: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
246.907: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 00
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
246.907: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
246.907: mct_DramControlReg_Init_D: Done
246.908: DIMM 0 RttWr: 2
246.908: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.908: mct_SendMrsCmd: Start
246.908: mct_SendMrsCmd: Done
246.908: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
246.908: mct_SendMrsCmd: Start
246.908: mct_SendMrsCmd: Done
246.908: DIMM 0 RttNom: 3
246.908: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.908: mct_SendMrsCmd: Start
246.908: mct_SendMrsCmd: Done
246.909: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001318
246.909: mct_SendMrsCmd: Start
246.909: mct_SendMrsCmd: Done
246.909: DIMM 0 RttWr: 2
246.909: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.909: mct_SendMrsCmd: Start
246.909: mct_SendMrsCmd: Done
246.909: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
246.909: mct_SendMrsCmd: Start
246.909: mct_SendMrsCmd: Done
246.909: DIMM 0 RttNom: 3
246.909: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.909: mct_SendMrsCmd: Start
246.909: mct_SendMrsCmd: Done
246.909: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201318
246.909: mct_SendMrsCmd: Start
246.909: mct_SendMrsCmd: Done
246.909: DIMM 1 RttWr: 2
246.909: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.909: mct_SendMrsCmd: Start
246.909: mct_SendMrsCmd: Done
246.909: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
246.909: mct_SendMrsCmd: Start
246.909: mct_SendMrsCmd: Done
246.909: DIMM 1 RttNom: 3
246.909: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.909: mct_SendMrsCmd: Start
246.909: mct_SendMrsCmd: Done
246.909: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401318
246.909: mct_SendMrsCmd: Start
246.909: mct_SendMrsCmd: Done
246.909: DIMM 1 RttWr: 2
246.909: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.909: mct_SendMrsCmd: Start
246.909: mct_SendMrsCmd: Done
246.909: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
246.909: mct_SendMrsCmd: Start
246.909: mct_SendMrsCmd: Done
246.909: DIMM 1 RttNom: 3
246.909: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.909: mct_SendMrsCmd: Start
246.909: mct_SendMrsCmd: Done
246.909: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601318
246.909: mct_SendMrsCmd: Start
246.909: mct_SendMrsCmd: Done
246.909: mct_SendZQCmd: Start
246.909: mct_SendZQCmd: Done
246.909: mct_SendZQCmd: Start
246.909: mct_SendZQCmd: Done
246.909: mct_DCTAccessDone: Start
246.909: mct_DCTAccessDone: Done
246.909: mct_DramInit_Sw_D: Done
246.909: <09><09>DCTFinalInit_D: StartupDCT_D Done
246.909: SPDCalcWidth: Status 2005
246.909: SPDCalcWidth: ErrStatus 0
246.909: SPDCalcWidth: ErrCode 0
246.909: SPDCalcWidth: Done
246.909: <09><09>DCTInit_D: mct_SPDCalcWidth Done
246.910: AutoCycTiming_D: Start
246.910: SPD2ndTiming: Start
246.910: SPD2ndTiming: Done
246.910: AutoCycTiming: Status 2005
246.910: AutoCycTiming: ErrStatus 0
246.910: AutoCycTiming: ErrCode 0
246.910: AutoCycTiming: Done
246.910: 
246.910: <09><09>DCTInit_D: AutoCycTiming_D Done
246.910: <09><09>DCTInit_D: enabling intra-channel clock skew
246.910: SPDSetBanks: CSPresent f
246.910: SPDSetBanks: Status 2005
246.910: SPDSetBanks: ErrStatus 0
246.910: SPDSetBanks: ErrCode 0
246.910: SPDSetBanks: Done
246.910: 
246.910: AfterStitch pDCTstat->NodeSysBase = 0
246.910: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffffe
246.910: StitchMemory: Status 2005
246.910: StitchMemory: ErrStatus 0
246.910: StitchMemory: ErrCode 0
246.910: StitchMemory: Done
246.910: 
246.910: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.910: CBFS: Locating 'cmos_layout.bin'
246.910: CBFS: Found @ offset 2b0c0 size e88
246.911: InterleaveBanks_D: Status 2005
246.911: InterleaveBanks_D: ErrStatus 0
246.911: InterleaveBanks_D: ErrCode 0
246.911: InterleaveBanks_D: Done
246.911: 
246.911: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.911: CBFS: Locating 'cmos_layout.bin'
246.911: CBFS: Found @ offset 2b0c0 size e88
246.911: AutoConfig_D: DramControl:     00002a06
246.911: AutoConfig_D: DramTimingLo:    00000000
246.911: AutoConfig_D: DramConfigMisc:  00000000
246.911: AutoConfig_D: DramConfigMisc2: 00000000
246.911: AutoConfig_D: DramConfigLo:    03083000
246.911: AutoConfig_D: DramConfigHi:    0f090084
246.911: InitDDRPhy: Start
246.911: InitDDRPhy: Done
246.911: mct_SetDramConfigHi_D: Start
246.911: set_2t_configuration: Start
246.911: set_2t_configuration: Done
246.911: mct_BeforePlatformSpec: Start
246.911: mct_BeforePlatformSpec: Done
246.911: mct_PlatformSpec: Start
246.911: Programmed DCT 1 timing/termination pattern 00000000 10222222
246.911: mct_PlatformSpec: Done
246.911: mct_SetDramConfigHi_D: DramConfigHi:    0f090084
246.911: *
246.911: mct_SetDramConfigHi_D: Done
246.911: mct_EarlyArbEn_D: Start
246.911: mct_EarlyArbEn_D: Done
246.911: AutoConfig: Status 2005
246.911: AutoConfig: ErrStatus 0
246.911: AutoConfig: ErrCode 0
246.911: AutoConfig: Done
246.911: 
246.911: <09><09>DCTInit_D: AutoConfig_D Done
246.912: <09><09>DCTInit_D: PlatformSpec_D Done
246.912: <09><09>DCTFinalInit_D: StartupDCT_D Start
246.912: mct_BeforeDramInit_Prod_D: Start
246.912: mct_ProgramODT_D: Start
246.912: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
246.912: mct_ProgramODT_D: Done
246.912: mct_BeforeDramInit_Prod_D: Done
246.912: mct_DramInit_Sw_D: Start
246.912: mct_DCTAccessDone: Start
246.912: mct_DCTAccessDone: Done
246.913: mct_DramControlReg_Init_D: Start
246.913: mct_DramControlReg_Init_D: F2xA8: 00000300
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC0: 02
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC1: 00
246.913: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC3: 05
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC4: 05
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC5: 05
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC6: 00
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC7: 00
246.913: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC9: 0d
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC10: 00
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC11: 00
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC12: 00
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC13: 00
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC14: 00
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC15: 00
246.913: mct_DramControlReg_Init_D: F2xA8: 00000c00
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00
246.913: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00
246.913: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 00
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00
246.913: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00
246.913: mct_DramControlReg_Init_D: Done
246.913: DIMM 0 RttWr: 2
246.913: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.913: mct_SendMrsCmd: Start
246.913: mct_SendMrsCmd: Done
246.913: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
246.913: mct_SendMrsCmd: Start
246.913: mct_SendMrsCmd: Done
246.913: DIMM 0 RttNom: 3
246.914: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.914: mct_SendMrsCmd: Start
246.914: mct_SendMrsCmd: Done
246.914: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001318
246.914: mct_SendMrsCmd: Start
246.914: mct_SendMrsCmd: Done
246.914: DIMM 0 RttWr: 2
246.914: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.914: mct_SendMrsCmd: Start
246.914: mct_SendMrsCmd: Done
246.914: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
246.914: mct_SendMrsCmd: Start
246.914: mct_SendMrsCmd: Done
246.914: DIMM 0 RttNom: 3
246.914: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.914: mct_SendMrsCmd: Start
246.914: mct_SendMrsCmd: Done
246.914: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201318
246.914: mct_SendMrsCmd: Start
246.914: mct_SendMrsCmd: Done
246.914: DIMM 1 RttWr: 2
246.914: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.914: mct_SendMrsCmd: Start
246.914: mct_SendMrsCmd: Done
246.914: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
246.914: mct_SendMrsCmd: Start
246.914: mct_SendMrsCmd: Done
246.914: DIMM 1 RttNom: 3
246.914: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.914: mct_SendMrsCmd: Start
246.914: mct_SendMrsCmd: Done
246.914: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401318
246.914: mct_SendMrsCmd: Start
246.914: mct_SendMrsCmd: Done
246.914: DIMM 1 RttWr: 2
246.914: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.914: mct_SendMrsCmd: Start
246.914: mct_SendMrsCmd: Done
246.914: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
246.914: mct_SendMrsCmd: Start
246.914: mct_SendMrsCmd: Done
246.914: DIMM 1 RttNom: 3
246.914: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.914: mct_SendMrsCmd: Start
246.914: mct_SendMrsCmd: Done
246.914: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601318
246.914: mct_SendMrsCmd: Start
246.914: mct_SendMrsCmd: Done
246.914: mct_SendZQCmd: Start
246.914: mct_SendZQCmd: Done
246.914: mct_SendZQCmd: Start
246.914: mct_SendZQCmd: Done
246.914: mct_DCTAccessDone: Start
246.914: mct_DCTAccessDone: Done
246.914: mct_DramInit_Sw_D: Done
246.914: <09><09>DCTFinalInit_D: StartupDCT_D Done
246.914: mctAutoInitMCT_D: mctSMBhub_Init
246.914: activate_spd_rom() for node 01
246.914: enable_spd_node1()
246.914: mctAutoInitMCT_D: mct_initDCT
246.915: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.915: CBFS: Locating 'cmos_layout.bin'
246.915: CBFS: Found @ offset 2b0c0 size e88
246.915: SPDCalcWidth: Status 2005
246.915: SPDCalcWidth: ErrStatus 0
246.915: SPDCalcWidth: ErrCode 0
246.915: SPDCalcWidth: Done
246.915: <09><09>DCTInit_D: mct_SPDCalcWidth Done
246.915: AutoCycTiming_D: Start
246.915: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.915: CBFS: Locating 'cmos_layout.bin'
246.915: CBFS: Found @ offset 2b0c0 size e88
246.915: GetPresetmaxF_D: Start
246.915: GetPresetmaxF_D: Done
246.915: SPDGetTCL_D: Start
246.915: SPDGetTCL_D: DIMMCASL 5
246.915: SPDGetTCL_D: DIMMAutoSpeed 4
246.915: SPDGetTCL_D: Status 2005
246.915: SPDGetTCL_D: ErrStatus 0
246.915: SPDGetTCL_D: ErrCode 0
246.915: SPDGetTCL_D: Done
246.915: 
246.915: SPD2ndTiming: Start
246.915: SPD2ndTiming: Done
246.915: AutoCycTiming: Status 2005
246.915: AutoCycTiming: ErrStatus 0
246.915: AutoCycTiming: ErrCode 0
246.915: AutoCycTiming: Done
246.915: 
246.915: <09><09>DCTInit_D: AutoCycTiming_D Done
246.916: SPDSetBanks: CSPresent f
246.916: SPDSetBanks: Status 2005
246.916: SPDSetBanks: ErrStatus 0
246.916: SPDSetBanks: ErrCode 0
246.916: SPDSetBanks: Done
246.916: 
246.916: AfterStitch pDCTstat->NodeSysBase = 0
246.916: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7ffffff
246.916: StitchMemory: Status 2005
246.916: StitchMemory: ErrStatus 0
246.916: StitchMemory: ErrCode 0
246.916: StitchMemory: Done
246.916: 
246.916: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.916: CBFS: Locating 'cmos_layout.bin'
246.916: CBFS: Found @ offset 2b0c0 size e88
246.916: InterleaveBanks_D: Status 2005
246.916: InterleaveBanks_D: ErrStatus 0
246.916: InterleaveBanks_D: ErrCode 0
246.916: InterleaveBanks_D: Done
246.916: 
246.917: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.917: CBFS: Locating 'cmos_layout.bin'
246.917: CBFS: Found @ offset 2b0c0 size e88
246.917: AutoConfig_D: DramControl:     00002a06
246.917: AutoConfig_D: DramTimingLo:    00000000
246.917: AutoConfig_D: DramConfigMisc:  00000000
246.917: AutoConfig_D: DramConfigMisc2: 00000000
246.917: AutoConfig_D: DramConfigLo:    03083000
246.917: AutoConfig_D: DramConfigHi:    0f090084
246.917: InitDDRPhy: Start
246.917: InitDDRPhy: Done
246.917: mct_SetDramConfigHi_D: Start
246.917: set_2t_configuration: Start
246.917: set_2t_configuration: Done
246.917: mct_BeforePlatformSpec: Start
246.917: mct_BeforePlatformSpec: Done
246.917: mct_PlatformSpec: Start
246.917: Programmed DCT 0 timing/termination pattern 00000000 10222222
246.917: mct_PlatformSpec: Done
246.917: mct_SetDramConfigHi_D: DramConfigHi:    0f090084
246.917: *
246.917: mct_SetDramConfigHi_D: Done
246.917: mct_EarlyArbEn_D: Start
246.917: mct_EarlyArbEn_D: Done
246.917: AutoConfig: Status 2005
246.917: AutoConfig: ErrStatus 0
246.917: AutoConfig: ErrCode 0
246.917: AutoConfig: Done
246.917: 
246.917: <09><09>DCTInit_D: AutoConfig_D Done
246.917: <09><09>DCTInit_D: PlatformSpec_D Done
246.917: <09><09>DCTFinalInit_D: StartupDCT_D Start
246.917: mct_BeforeDramInit_Prod_D: Start
246.917: mct_ProgramODT_D: Start
246.917: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
246.917: mct_ProgramODT_D: Done
246.917: mct_BeforeDramInit_Prod_D: Done
246.918: mct_DramInit_Sw_D: Start
246.918: mct_DCTAccessDone: Start
246.918: mct_DCTAccessDone: Done
246.918: mct_DramControlReg_Init_D: Start
246.918: mct_DramControlReg_Init_D: F2xA8: 00000300
246.918: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC0: 02
246.918: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC1: 00
246.918: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
246.918: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC3: 05
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC4: 05
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC5: 05
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC6: 00
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC7: 00
246.919: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC9: 0d
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC10: 00
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC11: 00
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC12: 00
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC13: 00
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC14: 00
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC15: 00
246.919: mct_DramControlReg_Init_D: F2xA8: 00000c00
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
246.919: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
246.919: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 00
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
246.919: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
246.919: mct_DramControlReg_Init_D: Done
246.919: DIMM 0 RttWr: 2
246.919: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.919: mct_SendMrsCmd: Start
246.919: mct_SendMrsCmd: Done
246.919: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
246.919: mct_SendMrsCmd: Start
246.919: mct_SendMrsCmd: Done
246.919: DIMM 0 RttNom: 3
246.919: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.919: mct_SendMrsCmd: Start
246.919: mct_SendMrsCmd: Done
246.920: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001318
246.920: mct_SendMrsCmd: Start
246.920: mct_SendMrsCmd: Done
246.920: DIMM 0 RttWr: 2
246.920: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.920: mct_SendMrsCmd: Start
246.920: mct_SendMrsCmd: Done
246.920: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
246.920: mct_SendMrsCmd: Start
246.920: mct_SendMrsCmd: Done
246.920: DIMM 0 RttNom: 3
246.920: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.920: mct_SendMrsCmd: Start
246.920: mct_SendMrsCmd: Done
246.920: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201318
246.920: mct_SendMrsCmd: Start
246.920: mct_SendMrsCmd: Done
246.920: DIMM 1 RttWr: 2
246.920: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.920: mct_SendMrsCmd: Start
246.920: mct_SendMrsCmd: Done
246.920: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
246.920: mct_SendMrsCmd: Start
246.920: mct_SendMrsCmd: Done
246.920: DIMM 1 RttNom: 3
246.920: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.920: mct_SendMrsCmd: Start
246.920: mct_SendMrsCmd: Done
246.920: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401318
246.920: mct_SendMrsCmd: Start
246.920: mct_SendMrsCmd: Done
246.920: DIMM 1 RttWr: 2
246.920: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.920: mct_SendMrsCmd: Start
246.920: mct_SendMrsCmd: Done
246.920: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
246.920: mct_SendMrsCmd: Start
246.920: mct_SendMrsCmd: Done
246.920: DIMM 1 RttNom: 3
246.920: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.920: mct_SendMrsCmd: Start
246.920: mct_SendMrsCmd: Done
246.920: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601318
246.920: mct_SendMrsCmd: Start
246.920: mct_SendMrsCmd: Done
246.920: mct_SendZQCmd: Start
246.920: mct_SendZQCmd: Done
246.920: mct_SendZQCmd: Start
246.920: mct_SendZQCmd: Done
246.920: mct_DCTAccessDone: Start
246.920: mct_DCTAccessDone: Done
246.920: mct_DramInit_Sw_D: Done
246.920: <09><09>DCTFinalInit_D: StartupDCT_D Done
246.920: SPDCalcWidth: Status 2005
246.920: SPDCalcWidth: ErrStatus 0
246.920: SPDCalcWidth: ErrCode 0
246.920: SPDCalcWidth: Done
246.920: <09><09>DCTInit_D: mct_SPDCalcWidth Done
246.920: AutoCycTiming_D: Start
246.920: SPD2ndTiming: Start
246.920: SPD2ndTiming: Done
246.920: AutoCycTiming: Status 2005
246.920: AutoCycTiming: ErrStatus 0
246.920: AutoCycTiming: ErrCode 0
246.920: AutoCycTiming: Done
246.920: 
246.921: <09><09>DCTInit_D: AutoCycTiming_D Done
246.921: <09><09>DCTInit_D: enabling intra-channel clock skew
246.921: SPDSetBanks: CSPresent f
246.921: SPDSetBanks: Status 2005
246.921: SPDSetBanks: ErrStatus 0
246.921: SPDSetBanks: ErrCode 0
246.921: SPDSetBanks: Done
246.921: 
246.921: AfterStitch pDCTstat->NodeSysBase = 0
246.921: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffffe
246.921: StitchMemory: Status 2005
246.921: StitchMemory: ErrStatus 0
246.921: StitchMemory: ErrCode 0
246.921: StitchMemory: Done
246.921: 
246.921: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.921: CBFS: Locating 'cmos_layout.bin'
246.921: CBFS: Found @ offset 2b0c0 size e88
246.922: InterleaveBanks_D: Status 2005
246.921: InterleaveBanks_D: ErrStatus 0
246.922: InterleaveBanks_D: ErrCode 0
246.922: InterleaveBanks_D: Done
246.922: 
246.922: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.922: CBFS: Locating 'cmos_layout.bin'
246.922: CBFS: Found @ offset 2b0c0 size e88
246.922: AutoConfig_D: DramControl:     00002a06
246.922: AutoConfig_D: DramTimingLo:    00000000
246.922: AutoConfig_D: DramConfigMisc:  00000000
246.922: AutoConfig_D: DramConfigMisc2: 00000000
246.922: AutoConfig_D: DramConfigLo:    03083000
246.922: AutoConfig_D: DramConfigHi:    0f090084
246.922: InitDDRPhy: Start
246.922: InitDDRPhy: Done
246.922: mct_SetDramConfigHi_D: Start
246.922: set_2t_configuration: Start
246.922: set_2t_configuration: Done
246.922: mct_BeforePlatformSpec: Start
246.922: mct_BeforePlatformSpec: Done
246.922: mct_PlatformSpec: Start
246.922: Programmed DCT 1 timing/termination pattern 00000000 10222222
246.922: mct_PlatformSpec: Done
246.922: mct_SetDramConfigHi_D: DramConfigHi:    0f090084
246.922: *
246.922: mct_SetDramConfigHi_D: Done
246.922: mct_EarlyArbEn_D: Start
246.922: mct_EarlyArbEn_D: Done
246.922: AutoConfig: Status 2005
246.922: AutoConfig: ErrStatus 0
246.922: AutoConfig: ErrCode 0
246.922: AutoConfig: Done
246.922: 
246.922: <09><09>DCTInit_D: AutoConfig_D Done
246.922: <09><09>DCTInit_D: PlatformSpec_D Done
246.922: <09><09>DCTFinalInit_D: StartupDCT_D Start
246.922: mct_BeforeDramInit_Prod_D: Start
246.923: mct_ProgramODT_D: Start
246.922: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
246.922: mct_ProgramODT_D: Done
246.923: mct_BeforeDramInit_Prod_D: Done
246.923: mct_DramInit_Sw_D: Start
246.923: mct_DCTAccessDone: Start
246.923: mct_DCTAccessDone: Done
246.924: mct_DramControlReg_Init_D: Start
246.924: mct_DramControlReg_Init_D: F2xA8: 00000300
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC0: 02
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC1: 00
246.924: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC3: 05
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC4: 05
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC5: 05
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC6: 00
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC7: 00
246.924: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC9: 0d
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC10: 00
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC11: 00
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC12: 00
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC13: 00
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC14: 00
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC15: 00
246.924: mct_DramControlReg_Init_D: F2xA8: 00000c00
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00
246.924: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00
246.924: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 00
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00
246.924: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00
246.924: mct_DramControlReg_Init_D: Done
246.924: DIMM 0 RttWr: 2
246.924: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.924: mct_SendMrsCmd: Start
246.924: mct_SendMrsCmd: Done
246.924: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
246.924: mct_SendMrsCmd: Start
246.924: mct_SendMrsCmd: Done
246.924: DIMM 0 RttNom: 3
246.924: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.925: mct_SendMrsCmd: Start
246.924: mct_SendMrsCmd: Done
246.925: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001318
246.925: mct_SendMrsCmd: Start
246.925: mct_SendMrsCmd: Done
246.925: DIMM 0 RttWr: 2
246.925: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.925: mct_SendMrsCmd: Start
246.925: mct_SendMrsCmd: Done
246.925: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
246.925: mct_SendMrsCmd: Start
246.925: mct_SendMrsCmd: Done
246.925: DIMM 0 RttNom: 3
246.925: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.925: mct_SendMrsCmd: Start
246.925: mct_SendMrsCmd: Done
246.925: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201318
246.925: mct_SendMrsCmd: Start
246.925: mct_SendMrsCmd: Done
246.925: DIMM 1 RttWr: 2
246.925: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.925: mct_SendMrsCmd: Start
246.925: mct_SendMrsCmd: Done
246.925: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
246.925: mct_SendMrsCmd: Start
246.925: mct_SendMrsCmd: Done
246.925: DIMM 1 RttNom: 3
246.925: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.925: mct_SendMrsCmd: Start
246.925: mct_SendMrsCmd: Done
246.925: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401318
246.925: mct_SendMrsCmd: Start
246.925: mct_SendMrsCmd: Done
246.925: DIMM 1 RttWr: 2
246.925: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.925: mct_SendMrsCmd: Start
246.925: mct_SendMrsCmd: Done
246.925: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
246.925: mct_SendMrsCmd: Start
246.925: mct_SendMrsCmd: Done
246.925: DIMM 1 RttNom: 3
246.925: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.925: mct_SendMrsCmd: Start
246.925: mct_SendMrsCmd: Done
246.925: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601318
246.925: mct_SendMrsCmd: Start
246.925: mct_SendMrsCmd: Done
246.925: mct_SendZQCmd: Start
246.925: mct_SendZQCmd: Done
246.925: mct_SendZQCmd: Start
246.925: mct_SendZQCmd: Done
246.925: mct_DCTAccessDone: Start
246.925: mct_DCTAccessDone: Done
246.925: mct_DramInit_Sw_D: Done
246.925: <09><09>DCTFinalInit_D: StartupDCT_D Done
246.925: mctAutoInitMCT_D: mctSMBhub_Init
246.925: activate_spd_rom() for node 02
246.925: enable_spd_node2()
246.925: mctAutoInitMCT_D: mct_initDCT
246.925: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.925: CBFS: Locating 'cmos_layout.bin'
246.925: CBFS: Found @ offset 2b0c0 size e88
246.926: SPDCalcWidth: Status 2005
246.926: SPDCalcWidth: ErrStatus 0
246.926: SPDCalcWidth: ErrCode 0
246.926: SPDCalcWidth: Done
246.926: <09><09>DCTInit_D: mct_SPDCalcWidth Done
246.926: AutoCycTiming_D: Start
246.926: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.926: CBFS: Locating 'cmos_layout.bin'
246.926: CBFS: Found @ offset 2b0c0 size e88
246.926: GetPresetmaxF_D: Start
246.926: GetPresetmaxF_D: Done
246.926: SPDGetTCL_D: Start
246.926: SPDGetTCL_D: DIMMCASL 5
246.926: SPDGetTCL_D: DIMMAutoSpeed 4
246.926: SPDGetTCL_D: Status 2005
246.926: SPDGetTCL_D: ErrStatus 0
246.926: SPDGetTCL_D: ErrCode 0
246.926: SPDGetTCL_D: Done
246.926: 
246.926: SPD2ndTiming: Start
246.926: SPD2ndTiming: Done
246.926: AutoCycTiming: Status 2005
246.926: AutoCycTiming: ErrStatus 0
246.926: AutoCycTiming: ErrCode 0
246.926: AutoCycTiming: Done
246.926: 
246.926: <09><09>DCTInit_D: AutoCycTiming_D Done
246.927: SPDSetBanks: CSPresent f
246.927: SPDSetBanks: Status 2005
246.927: SPDSetBanks: ErrStatus 0
246.927: SPDSetBanks: ErrCode 0
246.927: SPDSetBanks: Done
246.927: 
246.927: AfterStitch pDCTstat->NodeSysBase = 0
246.927: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7ffffff
246.927: StitchMemory: Status 2005
246.927: StitchMemory: ErrStatus 0
246.927: StitchMemory: ErrCode 0
246.927: StitchMemory: Done
246.927: 
246.927: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.927: CBFS: Locating 'cmos_layout.bin'
246.927: CBFS: Found @ offset 2b0c0 size e88
246.927: InterleaveBanks_D: Status 2005
246.927: InterleaveBanks_D: ErrStatus 0
246.927: InterleaveBanks_D: ErrCode 0
246.927: InterleaveBanks_D: Done
246.927: 
246.927: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.927: CBFS: Locating 'cmos_layout.bin'
246.927: CBFS: Found @ offset 2b0c0 size e88
246.928: AutoConfig_D: DramControl:     00002a06
246.928: AutoConfig_D: DramTimingLo:    00000000
246.928: AutoConfig_D: DramConfigMisc:  00000000
246.928: AutoConfig_D: DramConfigMisc2: 00000000
246.928: AutoConfig_D: DramConfigLo:    03083000
246.928: AutoConfig_D: DramConfigHi:    0f090084
246.928: InitDDRPhy: Start
246.928: InitDDRPhy: Done
246.928: mct_SetDramConfigHi_D: Start
246.928: set_2t_configuration: Start
246.928: set_2t_configuration: Done
246.928: mct_BeforePlatformSpec: Start
246.928: mct_BeforePlatformSpec: Done
246.928: mct_PlatformSpec: Start
246.928: Programmed DCT 0 timing/termination pattern 00000000 10222222
246.928: mct_PlatformSpec: Done
246.928: mct_SetDramConfigHi_D: DramConfigHi:    0f090084
246.928: *
246.928: mct_SetDramConfigHi_D: Done
246.928: mct_EarlyArbEn_D: Start
246.928: mct_EarlyArbEn_D: Done
246.928: AutoConfig: Status 2005
246.928: AutoConfig: ErrStatus 0
246.928: AutoConfig: ErrCode 0
246.928: AutoConfig: Done
246.928: 
246.928: <09><09>DCTInit_D: AutoConfig_D Done
246.928: <09><09>DCTInit_D: PlatformSpec_D Done
246.928: <09><09>DCTFinalInit_D: StartupDCT_D Start
246.928: mct_BeforeDramInit_Prod_D: Start
246.928: mct_ProgramODT_D: Start
246.928: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
246.928: mct_ProgramODT_D: Done
246.928: mct_BeforeDramInit_Prod_D: Done
246.928: mct_DramInit_Sw_D: Start
246.928: mct_DCTAccessDone: Start
246.928: mct_DCTAccessDone: Done
246.929: mct_DramControlReg_Init_D: Start
246.929: mct_DramControlReg_Init_D: F2xA8: 00000300
246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC0: 02
246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC1: 00
246.929: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC3: 05
246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC4: 05
246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC5: 05
246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC6: 00
246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC7: 00
246.929: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC9: 0d
246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC10: 00
246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC11: 00
246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC12: 00
246.929: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC13: 00
246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC14: 00
246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC15: 00
246.930: mct_DramControlReg_Init_D: F2xA8: 00000c00
246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
246.930: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
246.930: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 00
246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
246.930: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
246.930: mct_DramControlReg_Init_D: Done
246.930: DIMM 0 RttWr: 2
246.930: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.930: mct_SendMrsCmd: Start
246.930: mct_SendMrsCmd: Done
246.930: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
246.930: mct_SendMrsCmd: Start
246.930: mct_SendMrsCmd: Done
246.930: DIMM 0 RttNom: 3
246.930: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.930: mct_SendMrsCmd: Start
246.930: mct_SendMrsCmd: Done
246.930: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001318
246.930: mct_SendMrsCmd: Start
246.930: mct_SendMrsCmd: Done
246.931: DIMM 0 RttWr: 2
246.930: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.931: mct_SendMrsCmd: Start
246.931: mct_SendMrsCmd: Done
246.931: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
246.931: mct_SendMrsCmd: Start
246.931: mct_SendMrsCmd: Done
246.931: DIMM 0 RttNom: 3
246.931: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.931: mct_SendMrsCmd: Start
246.931: mct_SendMrsCmd: Done
246.931: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201318
246.931: mct_SendMrsCmd: Start
246.931: mct_SendMrsCmd: Done
246.931: DIMM 1 RttWr: 2
246.931: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.931: mct_SendMrsCmd: Start
246.931: mct_SendMrsCmd: Done
246.931: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
246.931: mct_SendMrsCmd: Start
246.931: mct_SendMrsCmd: Done
246.931: DIMM 1 RttNom: 3
246.931: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.931: mct_SendMrsCmd: Start
246.931: mct_SendMrsCmd: Done
246.931: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401318
246.931: mct_SendMrsCmd: Start
246.931: mct_SendMrsCmd: Done
246.931: DIMM 1 RttWr: 2
246.931: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.931: mct_SendMrsCmd: Start
246.931: mct_SendMrsCmd: Done
246.931: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
246.931: mct_SendMrsCmd: Start
246.931: mct_SendMrsCmd: Done
246.931: DIMM 1 RttNom: 3
246.931: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.931: mct_SendMrsCmd: Start
246.931: mct_SendMrsCmd: Done
246.931: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601318
246.931: mct_SendMrsCmd: Start
246.931: mct_SendMrsCmd: Done
246.931: mct_SendZQCmd: Start
246.931: mct_SendZQCmd: Done
246.931: mct_SendZQCmd: Start
246.931: mct_SendZQCmd: Done
246.931: mct_DCTAccessDone: Start
246.931: mct_DCTAccessDone: Done
246.931: mct_DramInit_Sw_D: Done
246.931: <09><09>DCTFinalInit_D: StartupDCT_D Done
246.931: SPDCalcWidth: Status 2005
246.931: SPDCalcWidth: ErrStatus 0
246.931: SPDCalcWidth: ErrCode 0
246.931: SPDCalcWidth: Done
246.931: <09><09>DCTInit_D: mct_SPDCalcWidth Done
246.931: AutoCycTiming_D: Start
246.931: SPD2ndTiming: Start
246.931: SPD2ndTiming: Done
246.931: AutoCycTiming: Status 2005
246.931: AutoCycTiming: ErrStatus 0
246.931: AutoCycTiming: ErrCode 0
246.931: AutoCycTiming: Done
246.931: 
246.931: <09><09>DCTInit_D: AutoCycTiming_D Done
246.931: <09><09>DCTInit_D: enabling intra-channel clock skew
246.932: SPDSetBanks: CSPresent f
246.932: SPDSetBanks: Status 2005
246.932: SPDSetBanks: ErrStatus 0
246.932: SPDSetBanks: ErrCode 0
246.932: SPDSetBanks: Done
246.932: 
246.932: AfterStitch pDCTstat->NodeSysBase = 0
246.932: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffffe
246.932: StitchMemory: Status 2005
246.932: StitchMemory: ErrStatus 0
246.932: StitchMemory: ErrCode 0
246.932: StitchMemory: Done
246.932: 
246.932: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.932: CBFS: Locating 'cmos_layout.bin'
246.932: CBFS: Found @ offset 2b0c0 size e88
246.932: InterleaveBanks_D: Status 2005
246.932: InterleaveBanks_D: ErrStatus 0
246.932: InterleaveBanks_D: ErrCode 0
246.932: InterleaveBanks_D: Done
246.932: 
246.932: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.932: CBFS: Locating 'cmos_layout.bin'
246.932: CBFS: Found @ offset 2b0c0 size e88
246.933: AutoConfig_D: DramControl:     00002a06
246.933: AutoConfig_D: DramTimingLo:    00000000
246.933: AutoConfig_D: DramConfigMisc:  00000000
246.933: AutoConfig_D: DramConfigMisc2: 00000000
246.933: AutoConfig_D: DramConfigLo:    03083000
246.933: AutoConfig_D: DramConfigHi:    0f090084
246.933: InitDDRPhy: Start
246.933: InitDDRPhy: Done
246.933: mct_SetDramConfigHi_D: Start
246.933: set_2t_configuration: Start
246.933: set_2t_configuration: Done
246.933: mct_BeforePlatformSpec: Start
246.933: mct_BeforePlatformSpec: Done
246.933: mct_PlatformSpec: Start
246.933: Programmed DCT 1 timing/termination pattern 00000000 10222222
246.933: mct_PlatformSpec: Done
246.933: mct_SetDramConfigHi_D: DramConfigHi:    0f090084
246.933: *
246.933: mct_SetDramConfigHi_D: Done
246.933: mct_EarlyArbEn_D: Start
246.933: mct_EarlyArbEn_D: Done
246.933: AutoConfig: Status 2005
246.933: AutoConfig: ErrStatus 0
246.933: AutoConfig: ErrCode 0
246.933: AutoConfig: Done
246.933: 
246.933: <09><09>DCTInit_D: AutoConfig_D Done
246.933: <09><09>DCTInit_D: PlatformSpec_D Done
246.933: <09><09>DCTFinalInit_D: StartupDCT_D Start
246.933: mct_BeforeDramInit_Prod_D: Start
246.933: mct_ProgramODT_D: Start
246.933: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
246.933: mct_ProgramODT_D: Done
246.933: mct_BeforeDramInit_Prod_D: Done
246.933: mct_DramInit_Sw_D: Start
246.933: mct_DCTAccessDone: Start
246.933: mct_DCTAccessDone: Done
246.934: mct_DramControlReg_Init_D: Start
246.934: mct_DramControlReg_Init_D: F2xA8: 00000300
246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC0: 02
246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC1: 00
246.934: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC3: 05
246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC4: 05
246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC5: 05
246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC6: 00
246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC7: 00
246.934: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC9: 0d
246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC10: 00
246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC11: 00
246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC12: 00
246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC13: 00
246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC14: 00
246.934: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC15: 00
246.934: mct_DramControlReg_Init_D: F2xA8: 00000c00
246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02
246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00
246.935: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05
246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05
246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05
246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00
246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00
246.935: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d
246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00
246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 00
246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00
246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00
246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00
246.935: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00
246.935: mct_DramControlReg_Init_D: Done
246.935: DIMM 0 RttWr: 2
246.935: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.935: mct_SendMrsCmd: Start
246.935: mct_SendMrsCmd: Done
246.935: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
246.935: mct_SendMrsCmd: Start
246.935: mct_SendMrsCmd: Done
246.935: DIMM 0 RttNom: 3
246.935: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.935: mct_SendMrsCmd: Start
246.935: mct_SendMrsCmd: Done
246.935: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001318
246.935: mct_SendMrsCmd: Start
246.935: mct_SendMrsCmd: Done
246.935: DIMM 0 RttWr: 2
246.935: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.935: mct_SendMrsCmd: Start
246.936: mct_SendMrsCmd: Done
246.936: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
246.936: mct_SendMrsCmd: Start
246.936: mct_SendMrsCmd: Done
246.936: DIMM 0 RttNom: 3
246.936: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.936: mct_SendMrsCmd: Start
246.936: mct_SendMrsCmd: Done
246.936: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201318
246.936: mct_SendMrsCmd: Start
246.936: mct_SendMrsCmd: Done
246.936: DIMM 1 RttWr: 2
246.936: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.936: mct_SendMrsCmd: Start
246.936: mct_SendMrsCmd: Done
246.936: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
246.936: mct_SendMrsCmd: Start
246.936: mct_SendMrsCmd: Done
246.936: DIMM 1 RttNom: 3
246.936: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.936: mct_SendMrsCmd: Start
246.936: mct_SendMrsCmd: Done
246.936: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401318
246.936: mct_SendMrsCmd: Start
246.936: mct_SendMrsCmd: Done
246.936: DIMM 1 RttWr: 2
246.936: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.936: mct_SendMrsCmd: Start
246.936: mct_SendMrsCmd: Done
246.936: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
246.936: mct_SendMrsCmd: Start
246.936: mct_SendMrsCmd: Done
246.936: DIMM 1 RttNom: 3
246.936: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.936: mct_SendMrsCmd: Start
246.936: mct_SendMrsCmd: Done
246.936: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601318
246.936: mct_SendMrsCmd: Start
246.936: mct_SendMrsCmd: Done
246.936: mct_SendZQCmd: Start
246.936: mct_SendZQCmd: Done
246.936: mct_SendZQCmd: Start
246.936: mct_SendZQCmd: Done
246.936: mct_DCTAccessDone: Start
246.936: mct_DCTAccessDone: Done
246.936: mct_DramInit_Sw_D: Done
246.936: <09><09>DCTFinalInit_D: StartupDCT_D Done
246.936: mctAutoInitMCT_D: mctSMBhub_Init
246.936: activate_spd_rom() for node 03
246.936: enable_spd_node3()
246.936: mctAutoInitMCT_D: mct_initDCT
246.936: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.936: CBFS: Locating 'cmos_layout.bin'
246.936: CBFS: Found @ offset 2b0c0 size e88
246.937: SPDCalcWidth: Status 2005
246.937: SPDCalcWidth: ErrStatus 0
246.937: SPDCalcWidth: ErrCode 0
246.937: SPDCalcWidth: Done
246.937: <09><09>DCTInit_D: mct_SPDCalcWidth Done
246.937: AutoCycTiming_D: Start
246.937: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.937: CBFS: Locating 'cmos_layout.bin'
246.937: CBFS: Found @ offset 2b0c0 size e88
246.937: GetPresetmaxF_D: Start
246.937: GetPresetmaxF_D: Done
246.937: SPDGetTCL_D: Start
246.937: SPDGetTCL_D: DIMMCASL 5
246.937: SPDGetTCL_D: DIMMAutoSpeed 4
246.937: SPDGetTCL_D: Status 2005
246.937: SPDGetTCL_D: ErrStatus 0
246.937: SPDGetTCL_D: ErrCode 0
246.937: SPDGetTCL_D: Done
246.937: 
246.937: SPD2ndTiming: Start
246.937: SPD2ndTiming: Done
246.937: AutoCycTiming: Status 2005
246.937: AutoCycTiming: ErrStatus 0
246.937: AutoCycTiming: ErrCode 0
246.937: AutoCycTiming: Done
246.937: 
246.937: <09><09>DCTInit_D: AutoCycTiming_D Done
246.937: SPDSetBanks: CSPresent f
246.937: SPDSetBanks: Status 2005
246.937: SPDSetBanks: ErrStatus 0
246.937: SPDSetBanks: ErrCode 0
246.937: SPDSetBanks: Done
246.937: 
246.938: AfterStitch pDCTstat->NodeSysBase = 0
246.938: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7ffffff
246.938: StitchMemory: Status 2005
246.938: StitchMemory: ErrStatus 0
246.938: StitchMemory: ErrCode 0
246.938: StitchMemory: Done
246.938: 
246.938: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.938: CBFS: Locating 'cmos_layout.bin'
246.938: CBFS: Found @ offset 2b0c0 size e88
246.938: InterleaveBanks_D: Status 2005
246.938: InterleaveBanks_D: ErrStatus 0
246.938: InterleaveBanks_D: ErrCode 0
246.938: InterleaveBanks_D: Done
246.938: 
246.938: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.938: CBFS: Locating 'cmos_layout.bin'
246.938: CBFS: Found @ offset 2b0c0 size e88
246.939: AutoConfig_D: DramControl:     00002a06
246.939: AutoConfig_D: DramTimingLo:    00000000
246.939: AutoConfig_D: DramConfigMisc:  00000000
246.939: AutoConfig_D: DramConfigMisc2: 00000000
246.939: AutoConfig_D: DramConfigLo:    03083000
246.939: AutoConfig_D: DramConfigHi:    0f090084
246.939: InitDDRPhy: Start
246.939: InitDDRPhy: Done
246.939: mct_SetDramConfigHi_D: Start
246.939: set_2t_configuration: Start
246.939: set_2t_configuration: Done
246.939: mct_BeforePlatformSpec: Start
246.939: mct_BeforePlatformSpec: Done
246.939: mct_PlatformSpec: Start
246.939: Programmed DCT 0 timing/termination pattern 00000000 10222222
246.939: mct_PlatformSpec: Done
246.939: mct_SetDramConfigHi_D: DramConfigHi:    0f090084
246.939: *
246.939: mct_SetDramConfigHi_D: Done
246.939: mct_EarlyArbEn_D: Start
246.939: mct_EarlyArbEn_D: Done
246.939: AutoConfig: Status 2005
246.939: AutoConfig: ErrStatus 0
246.939: AutoConfig: ErrCode 0
246.939: AutoConfig: Done
246.939: 
246.939: <09><09>DCTInit_D: AutoConfig_D Done
246.939: <09><09>DCTInit_D: PlatformSpec_D Done
246.939: <09><09>DCTFinalInit_D: StartupDCT_D Start
246.939: mct_BeforeDramInit_Prod_D: Start
246.939: mct_ProgramODT_D: Start
246.939: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
246.939: mct_ProgramODT_D: Done
246.939: mct_BeforeDramInit_Prod_D: Done
246.939: mct_DramInit_Sw_D: Start
246.939: mct_DCTAccessDone: Start
246.939: mct_DCTAccessDone: Done
246.940: mct_DramControlReg_Init_D: Start
246.940: mct_DramControlReg_Init_D: F2xA8: 00000300
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC0: 02
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC1: 00
246.940: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC3: 05
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC4: 05
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC5: 05
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC6: 00
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC7: 00
246.940: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC9: 0d
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC10: 00
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC11: 00
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC12: 00
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC13: 00
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC14: 00
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC15: 00
246.940: mct_DramControlReg_Init_D: F2xA8: 00000c00
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC0: 02
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC1: 00
246.940: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC3: 05
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC4: 05
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC5: 05
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC6: 00
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC7: 00
246.940: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC9: 0d
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC10: 00
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC11: 00
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC12: 00
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC13: 00
246.940: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC14: 00
246.941: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC15: 00
246.941: mct_DramControlReg_Init_D: Done
246.941: DIMM 0 RttWr: 2
246.941: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.941: mct_SendMrsCmd: Start
246.941: mct_SendMrsCmd: Done
246.941: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
246.941: mct_SendMrsCmd: Start
246.941: mct_SendMrsCmd: Done
246.941: DIMM 0 RttNom: 3
246.941: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.941: mct_SendMrsCmd: Start
246.941: mct_SendMrsCmd: Done
246.941: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001318
246.941: mct_SendMrsCmd: Start
246.941: mct_SendMrsCmd: Done
246.941: DIMM 0 RttWr: 2
246.941: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.941: mct_SendMrsCmd: Start
246.941: mct_SendMrsCmd: Done
246.941: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
246.941: mct_SendMrsCmd: Start
246.941: mct_SendMrsCmd: Done
246.941: DIMM 0 RttNom: 3
246.941: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.941: mct_SendMrsCmd: Start
246.941: mct_SendMrsCmd: Done
246.941: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201318
246.941: mct_SendMrsCmd: Start
246.941: mct_SendMrsCmd: Done
246.941: DIMM 1 RttWr: 2
246.941: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.941: mct_SendMrsCmd: Start
246.942: mct_SendMrsCmd: Done
246.942: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
246.942: mct_SendMrsCmd: Start
246.942: mct_SendMrsCmd: Done
246.942: DIMM 1 RttNom: 3
246.942: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.942: mct_SendMrsCmd: Start
246.942: mct_SendMrsCmd: Done
246.942: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401318
246.942: mct_SendMrsCmd: Start
246.942: mct_SendMrsCmd: Done
246.942: DIMM 1 RttWr: 2
246.942: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.942: mct_SendMrsCmd: Start
246.942: mct_SendMrsCmd: Done
246.942: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
246.942: mct_SendMrsCmd: Start
246.942: mct_SendMrsCmd: Done
246.942: DIMM 1 RttNom: 3
246.942: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.942: mct_SendMrsCmd: Start
246.942: mct_SendMrsCmd: Done
246.942: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601318
246.942: mct_SendMrsCmd: Start
246.942: mct_SendMrsCmd: Done
246.942: mct_SendZQCmd: Start
246.942: mct_SendZQCmd: Done
246.942: mct_SendZQCmd: Start
246.942: mct_SendZQCmd: Done
246.942: mct_DCTAccessDone: Start
246.942: mct_DCTAccessDone: Done
246.942: mct_DramInit_Sw_D: Done
246.942: <09><09>DCTFinalInit_D: StartupDCT_D Done
246.942: SPDCalcWidth: Status 2005
246.942: SPDCalcWidth: ErrStatus 0
246.942: SPDCalcWidth: ErrCode 0
246.942: SPDCalcWidth: Done
246.942: <09><09>DCTInit_D: mct_SPDCalcWidth Done
246.942: AutoCycTiming_D: Start
246.942: SPD2ndTiming: Start
246.942: SPD2ndTiming: Done
246.942: AutoCycTiming: Status 2005
246.942: AutoCycTiming: ErrStatus 0
246.942: AutoCycTiming: ErrCode 0
246.942: AutoCycTiming: Done
246.942: 
246.942: <09><09>DCTInit_D: AutoCycTiming_D Done
246.942: <09><09>DCTInit_D: enabling intra-channel clock skew
246.942: SPDSetBanks: CSPresent f
246.942: SPDSetBanks: Status 2005
246.942: SPDSetBanks: ErrStatus 0
246.942: SPDSetBanks: ErrCode 0
246.942: SPDSetBanks: Done
246.942: 
246.943: AfterStitch pDCTstat->NodeSysBase = 0
246.943: mct_AfterStitchMemory: pDCTstat->NodeSysLimit = ffffffe
246.943: StitchMemory: Status 2005
246.943: StitchMemory: ErrStatus 0
246.943: StitchMemory: ErrCode 0
246.943: StitchMemory: Done
246.943: 
246.943: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.943: CBFS: Locating 'cmos_layout.bin'
246.943: CBFS: Found @ offset 2b0c0 size e88
246.943: InterleaveBanks_D: Status 2005
246.943: InterleaveBanks_D: ErrStatus 0
246.943: InterleaveBanks_D: ErrCode 0
246.943: InterleaveBanks_D: Done
246.943: 
246.944: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
246.943: CBFS: Locating 'cmos_layout.bin'
246.943: CBFS: Found @ offset 2b0c0 size e88
246.944: AutoConfig_D: DramControl:     00002a06
246.944: AutoConfig_D: DramTimingLo:    00000000
246.944: AutoConfig_D: DramConfigMisc:  00000000
246.944: AutoConfig_D: DramConfigMisc2: 00000000
246.944: AutoConfig_D: DramConfigLo:    03083000
246.944: AutoConfig_D: DramConfigHi:    0f090084
246.944: InitDDRPhy: Start
246.944: InitDDRPhy: Done
246.944: mct_SetDramConfigHi_D: Start
246.944: set_2t_configuration: Start
246.944: set_2t_configuration: Done
246.944: mct_BeforePlatformSpec: Start
246.944: mct_BeforePlatformSpec: Done
246.944: mct_PlatformSpec: Start
246.944: Programmed DCT 1 timing/termination pattern 00000000 10222222
246.944: mct_PlatformSpec: Done
246.944: mct_SetDramConfigHi_D: DramConfigHi:    0f090084
246.944: *
246.944: mct_SetDramConfigHi_D: Done
246.944: mct_EarlyArbEn_D: Start
246.944: mct_EarlyArbEn_D: Done
246.944: AutoConfig: Status 2005
246.944: AutoConfig: ErrStatus 0
246.944: AutoConfig: ErrCode 0
246.944: AutoConfig: Done
246.944: 
246.944: <09><09>DCTInit_D: AutoConfig_D Done
246.944: <09><09>DCTInit_D: PlatformSpec_D Done
246.944: <09><09>DCTFinalInit_D: StartupDCT_D Start
246.944: mct_BeforeDramInit_Prod_D: Start
246.944: mct_ProgramODT_D: Start
246.944: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
246.944: mct_ProgramODT_D: Done
246.944: mct_BeforeDramInit_Prod_D: Done
246.944: mct_DramInit_Sw_D: Start
246.944: mct_DCTAccessDone: Start
246.944: mct_DCTAccessDone: Done
246.945: mct_DramControlReg_Init_D: Start
246.945: mct_DramControlReg_Init_D: F2xA8: 00000300
246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC0: 02
246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC1: 00
246.945: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC3: 05
246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC4: 05
246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC5: 05
246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC6: 00
246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC7: 00
246.945: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC9: 0d
246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC10: 00
246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC11: 00
246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC12: 00
246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC13: 00
246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC14: 00
246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC15: 00
246.945: mct_DramControlReg_Init_D: F2xA8: 00000c00
246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC0: 02
246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC1: 00
246.946: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
246.945: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC3: 05
246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC4: 05
246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC5: 05
246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC6: 00
246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC7: 00
246.946: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC9: 0d
246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC10: 00
246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC11: 00
246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC12: 00
246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC13: 00
246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC14: 00
246.946: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC15: 00
246.946: mct_DramControlReg_Init_D: Done
246.946: DIMM 0 RttWr: 2
246.946: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.946: mct_SendMrsCmd: Start
246.946: mct_SendMrsCmd: Done
246.946: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
246.946: mct_SendMrsCmd: Start
246.946: mct_SendMrsCmd: Done
246.946: DIMM 0 RttNom: 3
246.946: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.946: mct_SendMrsCmd: Start
246.946: mct_SendMrsCmd: Done
246.946: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001318
246.946: mct_SendMrsCmd: Start
246.946: mct_SendMrsCmd: Done
246.946: DIMM 0 RttWr: 2
246.946: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.946: mct_SendMrsCmd: Start
246.946: mct_SendMrsCmd: Done
246.946: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
246.946: mct_SendMrsCmd: Start
246.946: mct_SendMrsCmd: Done
246.946: DIMM 0 RttNom: 3
246.946: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.946: mct_SendMrsCmd: Start
246.947: mct_SendMrsCmd: Done
246.947: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201318
246.947: mct_SendMrsCmd: Start
246.947: mct_SendMrsCmd: Done
246.947: DIMM 1 RttWr: 2
246.947: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.947: mct_SendMrsCmd: Start
246.947: mct_SendMrsCmd: Done
246.947: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
246.947: mct_SendMrsCmd: Start
246.947: mct_SendMrsCmd: Done
246.947: DIMM 1 RttNom: 3
246.947: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.947: mct_SendMrsCmd: Start
246.947: mct_SendMrsCmd: Done
246.947: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401318
246.947: mct_SendMrsCmd: Start
246.947: mct_SendMrsCmd: Done
246.947: DIMM 1 RttWr: 2
246.947: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.947: mct_SendMrsCmd: Start
246.947: mct_SendMrsCmd: Done
246.947: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
246.947: mct_SendMrsCmd: Start
246.947: mct_SendMrsCmd: Done
246.947: DIMM 1 RttNom: 3
246.947: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.947: mct_SendMrsCmd: Start
246.947: mct_SendMrsCmd: Done
246.947: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601318
246.947: mct_SendMrsCmd: Start
246.947: mct_SendMrsCmd: Done
246.947: mct_SendZQCmd: Start
246.947: mct_SendZQCmd: Done
246.947: mct_SendZQCmd: Start
246.947: mct_SendZQCmd: Done
246.947: mct_DCTAccessDone: Start
246.947: mct_DCTAccessDone: Done
246.947: mct_DramInit_Sw_D: Done
246.947: <09><09>DCTFinalInit_D: StartupDCT_D Done
246.947: mctAutoInitMCT_D: SyncDCTsReady_D
246.947: mctAutoInitMCT_D: HTMemMapInit_D
246.947:  Node: 00  base: 00  limit: fffffff  BottomIO: c00000
246.947:  Node: 00  base: 03  limit: 103fffff
246.948:  Node: 01  base: 10400000  limit: 203fffff  BottomIO: c00000
246.948:  Node: 01  base: 10400003  limit: 203fffff
246.948:  Node: 02  base: 20400000  limit: 303fffff  BottomIO: c00000
246.948:  Node: 02  base: 20400003  limit: 303fffff
246.948:  Node: 03  base: 30400000  limit: 403fffff  BottomIO: c00000
246.948:  Node: 03  base: 30400003  limit: 403fffff
246.948:  Node: 04  base: 00  limit: 00
246.948:  Node: 05  base: 00  limit: 00
246.948:  Node: 06  base: 00  limit: 00
246.948:  Node: 07  base: 00  limit: 00
246.948:  Copy dram map from Node 0 to Node 01
246.948:  Copy dram map from Node 0 to Node 02
246.948:  Copy dram map from Node 0 to Node 03
246.948: mctAutoInitMCT_D: mctHookAfterCPU
246.948: mctAutoInitMCT_D: DQSTiming_D
246.948: phyAssistedMemFnceTraining: Start
246.948: phyAssistedMemFnceTraining: training node 0 DCT 0
246.949: phyAssistedMemFnceTraining: done training node 0 DCT 0
246.949: phyAssistedMemFnceTraining: training node 0 DCT 1
246.949: phyAssistedMemFnceTraining: done training node 0 DCT 1
246.949: phyAssistedMemFnceTraining: training node 1 DCT 0
246.949: phyAssistedMemFnceTraining: done training node 1 DCT 0
246.949: phyAssistedMemFnceTraining: training node 1 DCT 1
246.949: phyAssistedMemFnceTraining: done training node 1 DCT 1
246.949: phyAssistedMemFnceTraining: training node 2 DCT 0
246.949: phyAssistedMemFnceTraining: done training node 2 DCT 0
246.949: phyAssistedMemFnceTraining: training node 2 DCT 1
246.949: phyAssistedMemFnceTraining: done training node 2 DCT 1
246.949: phyAssistedMemFnceTraining: training node 3 DCT 0
246.949: phyAssistedMemFnceTraining: done training node 3 DCT 0
246.950: phyAssistedMemFnceTraining: training node 3 DCT 1
246.950: phyAssistedMemFnceTraining: done training node 3 DCT 1
246.950: phyAssistedMemFnceTraining: Done
246.950: InitPhyCompensation: DCT 0: Start
246.951: Waiting for predriver calibration to be applied...done!
246.951: InitPhyCompensation: DCT 0: Done
246.951: InitPhyCompensation: DCT 1: Start
246.951: Waiting for predriver calibration to be applied...done!
246.951: InitPhyCompensation: DCT 1: Done
246.951: InitPhyCompensation: DCT 0: Start
246.951: Waiting for predriver calibration to be applied...done!
246.951: InitPhyCompensation: DCT 0: Done
246.951: InitPhyCompensation: DCT 1: Start
246.951: Waiting for predriver calibration to be applied...done!
246.951: InitPhyCompensation: DCT 1: Done
246.951: InitPhyCompensation: DCT 0: Start
246.951: Waiting for predriver calibration to be applied...done!
246.951: InitPhyCompensation: DCT 0: Done
246.951: InitPhyCompensation: DCT 1: Start
246.951: Waiting for predriver calibration to be applied...done!
246.951: InitPhyCompensation: DCT 1: Done
246.951: InitPhyCompensation: DCT 0: Start
246.951: Waiting for predriver calibration to be applied...done!
246.951: InitPhyCompensation: DCT 0: Done
246.951: InitPhyCompensation: DCT 1: Start
246.951: Waiting for predriver calibration to be applied...done!
246.952: InitPhyCompensation: DCT 1: Done
246.952: activate_spd_rom() for node 00
246.952: enable_spd_node0()
246.954: AgesaHwWlPhase1: training nibble 0
246.954: DIMM 0 RttNom: 3
246.954: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.954: DIMM 0 RttWr: 2
246.954: DIMM 0 RttWr: 2
246.954: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.954: DIMM 0 RttWr: 2
246.954: DIMM 0 RttNom: 3
246.954: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.954: DIMM 0 RttNom: 3
246.954: DIMM 0 RttWr: 2
246.954: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.954: DIMM 0 RttWr: 2
246.955: DIMM 1 RttNom: 3
246.955: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.955: DIMM 0 RttNom: 3
246.955: DIMM 1 RttWr: 2
246.955: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.955: DIMM 0 RttWr: 2
246.955: DIMM 1 RttNom: 3
246.955: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.955: DIMM 0 RttNom: 3
246.955: DIMM 1 RttWr: 2
246.955: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.955: DIMM 0 RttWr: 2
246.956: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
246.956: <09>Lane 00 initial seed: 0041
246.956: <09>Lane 01 initial seed: 0041
246.956: <09>Lane 02 initial seed: 0041
246.956: <09>Lane 03 initial seed: 0041
246.956: <09>Lane 04 initial seed: 0041
246.956: <09>Lane 05 initial seed: 0041
246.956: <09>Lane 06 initial seed: 0041
246.956: <09>Lane 07 initial seed: 0041
246.956: <09>Lane 08 initial seed: 0041
246.957: <09>Lane 00 nibble 0 raw readback: 004d
246.957: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004d
246.957: <09>Lane 00 nibble 0 adjusted value (post nibble): 004d
246.957: <09>Lane 01 nibble 0 raw readback: 0047
246.957: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0047
246.957: <09>Lane 01 nibble 0 adjusted value (post nibble): 0047
246.957: <09>Lane 02 nibble 0 raw readback: 0045
246.957: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0045
246.957: <09>Lane 02 nibble 0 adjusted value (post nibble): 0045
246.957: <09>Lane 03 nibble 0 raw readback: 0042
246.957: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0042
246.957: <09>Lane 03 nibble 0 adjusted value (post nibble): 0042
246.957: <09>Lane 04 nibble 0 raw readback: 003a
246.957: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
246.957: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
246.957: <09>Lane 05 nibble 0 raw readback: 003d
246.957: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
246.957: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
246.957: <09>Lane 06 nibble 0 raw readback: 0040
246.957: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
246.957: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
246.957: <09>Lane 07 nibble 0 raw readback: 0041
246.957: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0041
246.957: <09>Lane 07 nibble 0 adjusted value (post nibble): 0041
246.957: <09>Lane 08 nibble 0 raw readback: 003b
246.957: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003b
246.957: <09>Lane 08 nibble 0 adjusted value (post nibble): 003b
246.957: AgesaHwWlPhase1: training nibble 1
246.957: DIMM 0 RttNom: 3
246.957: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.957: DIMM 0 RttWr: 2
246.957: DIMM 0 RttWr: 2
246.957: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.957: DIMM 0 RttWr: 2
246.957: DIMM 0 RttNom: 3
246.957: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.957: DIMM 0 RttNom: 3
246.957: DIMM 0 RttWr: 2
246.957: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.957: DIMM 0 RttWr: 2
246.957: DIMM 1 RttNom: 3
246.957: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.957: DIMM 0 RttNom: 3
246.957: DIMM 1 RttWr: 2
246.957: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.957: DIMM 0 RttWr: 2
246.957: DIMM 1 RttNom: 3
246.957: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.957: DIMM 0 RttNom: 3
246.957: DIMM 1 RttWr: 2
246.957: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.957: DIMM 0 RttWr: 2
246.957: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
246.957: <09>Lane 00 initial seed: 0041
246.958: <09>Lane 01 initial seed: 0041
246.958: <09>Lane 02 initial seed: 0041
246.958: <09>Lane 03 initial seed: 0041
246.958: <09>Lane 04 initial seed: 0041
246.958: <09>Lane 05 initial seed: 0041
246.958: <09>Lane 06 initial seed: 0041
246.958: <09>Lane 07 initial seed: 0041
246.958: <09>Lane 08 initial seed: 0041
246.958: <09>Lane 00 nibble 1 raw readback: 004c
246.958: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004c
246.958: <09>Lane 00 nibble 1 adjusted value (post nibble): 0046
246.958: <09>Lane 01 nibble 1 raw readback: 0047
246.958: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0047
246.958: <09>Lane 01 nibble 1 adjusted value (post nibble): 0044
246.958: <09>Lane 02 nibble 1 raw readback: 0046
246.958: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0046
246.958: <09>Lane 02 nibble 1 adjusted value (post nibble): 0043
246.958: <09>Lane 03 nibble 1 raw readback: 0043
246.958: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0043
246.958: <09>Lane 03 nibble 1 adjusted value (post nibble): 0042
246.958: <09>Lane 04 nibble 1 raw readback: 003a
246.958: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003a
246.958: <09>Lane 04 nibble 1 adjusted value (post nibble): 003d
246.958: <09>Lane 05 nibble 1 raw readback: 003d
246.958: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003d
246.958: <09>Lane 05 nibble 1 adjusted value (post nibble): 003f
246.958: <09>Lane 06 nibble 1 raw readback: 0040
246.958: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0040
246.958: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
246.958: <09>Lane 07 nibble 1 raw readback: 0041
246.958: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
246.958: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
246.958: <09>Lane 08 nibble 1 raw readback: 003b
246.958: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003b
246.958: <09>Lane 08 nibble 1 adjusted value (post nibble): 003e
246.958: <09>original critical gross delay: 0
246.958: <09>new critical gross delay: 0
246.958: DIMM 0 RttNom: 3
246.958: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.958: DIMM 0 RttNom: 3
246.958: DIMM 0 RttWr: 2
246.958: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.958: DIMM 0 RttWr: 2
246.958: DIMM 0 RttNom: 3
246.958: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.958: DIMM 0 RttNom: 3
246.958: DIMM 0 RttWr: 2
246.958: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.959: DIMM 0 RttWr: 2
246.959: DIMM 1 RttNom: 3
246.959: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.959: DIMM 0 RttNom: 3
246.959: DIMM 1 RttWr: 2
246.959: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.959: DIMM 0 RttWr: 2
246.959: DIMM 1 RttNom: 3
246.959: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.959: DIMM 0 RttNom: 3
246.959: DIMM 1 RttWr: 2
246.959: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.959: DIMM 0 RttWr: 2
246.959: AgesaHwWlPhase1: training nibble 0
246.959: DIMM 1 RttNom: 3
246.959: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.959: DIMM 1 RttWr: 2
246.959: DIMM 1 RttWr: 2
246.959: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.959: DIMM 1 RttWr: 2
246.959: DIMM 1 RttNom: 3
246.959: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.959: DIMM 1 RttNom: 3
246.959: DIMM 1 RttWr: 2
246.959: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.959: DIMM 1 RttWr: 2
246.959: DIMM 0 RttNom: 3
246.959: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.959: DIMM 1 RttNom: 3
246.959: DIMM 0 RttWr: 2
246.959: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.959: DIMM 1 RttWr: 2
246.959: DIMM 0 RttNom: 3
246.959: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.959: DIMM 1 RttNom: 3
246.959: DIMM 0 RttWr: 2
246.959: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.959: DIMM 1 RttWr: 2
246.959: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
246.959: <09>Lane 00 initial seed: 0041
246.959: <09>Lane 01 initial seed: 0041
246.959: <09>Lane 02 initial seed: 0041
246.959: <09>Lane 03 initial seed: 0041
246.959: <09>Lane 04 initial seed: 0041
246.959: <09>Lane 05 initial seed: 0041
246.959: <09>Lane 06 initial seed: 0041
246.959: <09>Lane 07 initial seed: 0041
246.959: <09>Lane 08 initial seed: 0041
246.959: <09>Lane 00 nibble 0 raw readback: 003f
246.959: <09>Lane 00 nibble 0 adjusted value (pre nibble): 003f
246.959: <09>Lane 00 nibble 0 adjusted value (post nibble): 003f
246.959: <09>Lane 01 nibble 0 raw readback: 003a
246.959: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003a
246.959: <09>Lane 01 nibble 0 adjusted value (post nibble): 003a
246.959: <09>Lane 02 nibble 0 raw readback: 0038
246.959: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0038
246.959: <09>Lane 02 nibble 0 adjusted value (post nibble): 0038
246.959: <09>Lane 03 nibble 0 raw readback: 0035
246.959: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0035
246.959: <09>Lane 03 nibble 0 adjusted value (post nibble): 0035
246.959: <09>Lane 04 nibble 0 raw readback: 002f
246.959: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002f
246.959: <09>Lane 04 nibble 0 adjusted value (post nibble): 002f
246.959: <09>Lane 05 nibble 0 raw readback: 0031
246.959: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0031
246.959: <09>Lane 05 nibble 0 adjusted value (post nibble): 0031
246.959: <09>Lane 06 nibble 0 raw readback: 0033
246.959: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0033
246.959: <09>Lane 06 nibble 0 adjusted value (post nibble): 0033
246.959: <09>Lane 07 nibble 0 raw readback: 0036
246.959: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0036
246.959: <09>Lane 07 nibble 0 adjusted value (post nibble): 0036
246.959: <09>Lane 08 nibble 0 raw readback: 002f
246.960: <09>Lane 08 nibble 0 adjusted value (pre nibble): 002f
246.960: <09>Lane 08 nibble 0 adjusted value (post nibble): 002f
246.960: AgesaHwWlPhase1: training nibble 1
246.960: DIMM 1 RttNom: 3
246.960: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.960: DIMM 1 RttWr: 2
246.960: DIMM 1 RttWr: 2
246.960: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.960: DIMM 1 RttWr: 2
246.960: DIMM 1 RttNom: 3
246.960: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.960: DIMM 1 RttNom: 3
246.960: DIMM 1 RttWr: 2
246.960: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.960: DIMM 1 RttWr: 2
246.960: DIMM 0 RttNom: 3
246.960: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.960: DIMM 1 RttNom: 3
246.960: DIMM 0 RttWr: 2
246.960: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.960: DIMM 1 RttWr: 2
246.960: DIMM 0 RttNom: 3
246.960: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.960: DIMM 1 RttNom: 3
246.960: DIMM 0 RttWr: 2
246.960: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.960: DIMM 1 RttWr: 2
246.960: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
246.960: <09>Lane 00 initial seed: 0041
246.960: <09>Lane 01 initial seed: 0041
246.960: <09>Lane 02 initial seed: 0041
246.960: <09>Lane 03 initial seed: 0041
246.960: <09>Lane 04 initial seed: 0041
246.960: <09>Lane 05 initial seed: 0041
246.960: <09>Lane 06 initial seed: 0041
246.960: <09>Lane 07 initial seed: 0041
246.960: <09>Lane 08 initial seed: 0041
246.960: <09>Lane 00 nibble 1 raw readback: 0040
246.960: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0040
246.960: <09>Lane 00 nibble 1 adjusted value (post nibble): 0040
246.960: <09>Lane 01 nibble 1 raw readback: 003b
246.960: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003b
246.960: <09>Lane 01 nibble 1 adjusted value (post nibble): 003e
246.960: <09>Lane 02 nibble 1 raw readback: 0039
246.960: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0039
246.960: <09>Lane 02 nibble 1 adjusted value (post nibble): 003d
246.960: <09>Lane 03 nibble 1 raw readback: 0037
246.960: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0037
246.960: <09>Lane 03 nibble 1 adjusted value (post nibble): 003c
246.960: <09>Lane 04 nibble 1 raw readback: 002e
246.960: <09>Lane 04 nibble 1 adjusted value (pre nibble): 002e
246.960: <09>Lane 04 nibble 1 adjusted value (post nibble): 0037
246.960: <09>Lane 05 nibble 1 raw readback: 0032
246.960: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0032
246.960: <09>Lane 05 nibble 1 adjusted value (post nibble): 0039
246.960: <09>Lane 06 nibble 1 raw readback: 0034
246.960: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0034
246.960: <09>Lane 06 nibble 1 adjusted value (post nibble): 003a
246.960: <09>Lane 07 nibble 1 raw readback: 0036
246.960: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0036
246.960: <09>Lane 07 nibble 1 adjusted value (post nibble): 003b
246.960: <09>Lane 08 nibble 1 raw readback: 002f
246.960: <09>Lane 08 nibble 1 adjusted value (pre nibble): 002f
246.960: <09>Lane 08 nibble 1 adjusted value (post nibble): 0038
246.960: <09>original critical gross delay: 0
246.960: <09>new critical gross delay: 0
246.961: DIMM 1 RttNom: 3
246.961: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.961: DIMM 1 RttNom: 3
246.961: DIMM 1 RttWr: 2
246.961: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.961: DIMM 1 RttWr: 2
246.961: DIMM 1 RttNom: 3
246.961: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.961: DIMM 1 RttNom: 3
246.961: DIMM 1 RttWr: 2
246.961: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.961: DIMM 1 RttWr: 2
246.961: DIMM 0 RttNom: 3
246.961: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.961: DIMM 1 RttNom: 3
246.961: DIMM 0 RttWr: 2
246.961: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.961: DIMM 1 RttWr: 2
246.961: DIMM 0 RttNom: 3
246.961: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.961: DIMM 1 RttNom: 3
246.961: DIMM 0 RttWr: 2
246.961: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.961: DIMM 1 RttWr: 2
246.961: AgesaHwWlPhase1: training nibble 0
246.961: DIMM 0 RttNom: 3
246.961: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.961: DIMM 0 RttWr: 2
246.961: DIMM 0 RttWr: 2
246.961: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.961: DIMM 0 RttWr: 2
246.961: DIMM 0 RttNom: 3
246.961: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.961: DIMM 0 RttNom: 3
246.961: DIMM 0 RttWr: 2
246.961: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.961: DIMM 0 RttWr: 2
246.961: DIMM 1 RttNom: 3
246.961: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.961: DIMM 0 RttNom: 3
246.961: DIMM 1 RttWr: 2
246.961: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.961: DIMM 0 RttWr: 2
246.961: DIMM 1 RttNom: 3
246.961: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.961: DIMM 0 RttNom: 3
246.961: DIMM 1 RttWr: 2
246.961: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.961: DIMM 0 RttWr: 2
246.961: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
246.961: <09>Lane 00 initial seed: 0041
246.961: <09>Lane 01 initial seed: 0041
246.961: <09>Lane 02 initial seed: 0041
246.961: <09>Lane 03 initial seed: 0041
246.961: <09>Lane 04 initial seed: 0041
246.961: <09>Lane 05 initial seed: 0041
246.961: <09>Lane 06 initial seed: 0041
246.961: <09>Lane 07 initial seed: 0041
246.961: <09>Lane 08 initial seed: 0041
246.961: <09>Lane 00 nibble 0 raw readback: 0049
246.961: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0049
246.961: <09>Lane 00 nibble 0 adjusted value (post nibble): 0049
246.961: <09>Lane 01 nibble 0 raw readback: 0046
246.961: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0046
246.962: <09>Lane 01 nibble 0 adjusted value (post nibble): 0046
246.961: <09>Lane 02 nibble 0 raw readback: 0043
246.962: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0043
246.962: <09>Lane 02 nibble 0 adjusted value (post nibble): 0043
246.962: <09>Lane 03 nibble 0 raw readback: 0040
246.962: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0040
246.962: <09>Lane 03 nibble 0 adjusted value (post nibble): 0040
246.962: <09>Lane 04 nibble 0 raw readback: 0039
246.962: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
246.962: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
246.962: <09>Lane 05 nibble 0 raw readback: 003b
246.962: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003b
246.962: <09>Lane 05 nibble 0 adjusted value (post nibble): 003b
246.962: <09>Lane 06 nibble 0 raw readback: 003d
246.962: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003d
246.962: <09>Lane 06 nibble 0 adjusted value (post nibble): 003d
246.962: <09>Lane 07 nibble 0 raw readback: 003f
246.962: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003f
246.962: <09>Lane 07 nibble 0 adjusted value (post nibble): 003f
246.962: <09>Lane 08 nibble 0 raw readback: 003a
246.962: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003a
246.962: <09>Lane 08 nibble 0 adjusted value (post nibble): 003a
246.962: AgesaHwWlPhase1: training nibble 1
246.962: DIMM 0 RttNom: 3
246.962: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.962: DIMM 0 RttWr: 2
246.962: DIMM 0 RttWr: 2
246.962: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.962: DIMM 0 RttWr: 2
246.962: DIMM 0 RttNom: 3
246.962: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.962: DIMM 0 RttNom: 3
246.962: DIMM 0 RttWr: 2
246.962: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.962: DIMM 0 RttWr: 2
246.962: DIMM 1 RttNom: 3
246.962: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.962: DIMM 0 RttNom: 3
246.962: DIMM 1 RttWr: 2
246.962: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.962: DIMM 0 RttWr: 2
246.962: DIMM 1 RttNom: 3
246.962: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.962: DIMM 0 RttNom: 3
246.962: DIMM 1 RttWr: 2
246.962: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.962: DIMM 0 RttWr: 2
246.962: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
246.962: <09>Lane 00 initial seed: 0041
246.962: <09>Lane 01 initial seed: 0041
246.962: <09>Lane 02 initial seed: 0041
246.962: <09>Lane 03 initial seed: 0041
246.962: <09>Lane 04 initial seed: 0041
246.962: <09>Lane 05 initial seed: 0041
246.962: <09>Lane 06 initial seed: 0041
246.962: <09>Lane 07 initial seed: 0041
246.962: <09>Lane 08 initial seed: 0041
246.962: <09>Lane 00 nibble 1 raw readback: 0049
246.962: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0049
246.962: <09>Lane 00 nibble 1 adjusted value (post nibble): 0045
246.962: <09>Lane 01 nibble 1 raw readback: 0045
246.962: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0045
246.962: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
246.962: <09>Lane 02 nibble 1 raw readback: 0043
246.962: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0043
246.962: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
246.962: <09>Lane 03 nibble 1 raw readback: 0041
246.962: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0041
246.962: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
246.962: <09>Lane 04 nibble 1 raw readback: 0038
246.962: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
246.962: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
246.962: <09>Lane 05 nibble 1 raw readback: 003a
246.962: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003a
246.962: <09>Lane 05 nibble 1 adjusted value (post nibble): 003d
246.962: <09>Lane 06 nibble 1 raw readback: 003e
246.962: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003e
246.962: <09>Lane 06 nibble 1 adjusted value (post nibble): 003f
246.962: <09>Lane 07 nibble 1 raw readback: 003f
246.962: <09>Lane 07 nibble 1 adjusted value (pre nibble): 003f
246.962: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
246.962: <09>Lane 08 nibble 1 raw readback: 003a
246.963: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003a
246.963: <09>Lane 08 nibble 1 adjusted value (post nibble): 003d
246.963: <09>original critical gross delay: 0
246.963: <09>new critical gross delay: 0
246.963: DIMM 0 RttNom: 3
246.963: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.963: DIMM 0 RttNom: 3
246.963: DIMM 0 RttWr: 2
246.963: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.963: DIMM 0 RttWr: 2
246.963: DIMM 0 RttNom: 3
246.963: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.963: DIMM 0 RttNom: 3
246.963: DIMM 0 RttWr: 2
246.963: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.963: DIMM 0 RttWr: 2
246.963: DIMM 1 RttNom: 3
246.963: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.963: DIMM 0 RttNom: 3
246.963: DIMM 1 RttWr: 2
246.963: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.963: DIMM 0 RttWr: 2
246.963: DIMM 1 RttNom: 3
246.963: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.963: DIMM 0 RttNom: 3
246.963: DIMM 1 RttWr: 2
246.963: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.963: DIMM 0 RttWr: 2
246.963: AgesaHwWlPhase1: training nibble 0
246.963: DIMM 1 RttNom: 3
246.963: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.963: DIMM 1 RttWr: 2
246.963: DIMM 1 RttWr: 2
246.963: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.963: DIMM 1 RttWr: 2
246.963: DIMM 1 RttNom: 3
246.963: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.963: DIMM 1 RttNom: 3
246.963: DIMM 1 RttWr: 2
246.963: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.963: DIMM 1 RttWr: 2
246.963: DIMM 0 RttNom: 3
246.963: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.963: DIMM 1 RttNom: 3
246.963: DIMM 0 RttWr: 2
246.963: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.963: DIMM 1 RttWr: 2
246.963: DIMM 0 RttNom: 3
246.963: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.963: DIMM 1 RttNom: 3
246.963: DIMM 0 RttWr: 2
246.963: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.963: DIMM 1 RttWr: 2
246.963: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
246.963: <09>Lane 00 initial seed: 0041
246.963: <09>Lane 01 initial seed: 0041
246.963: <09>Lane 02 initial seed: 0041
246.963: <09>Lane 03 initial seed: 0041
246.964: <09>Lane 04 initial seed: 0041
246.963: <09>Lane 05 initial seed: 0041
246.963: <09>Lane 06 initial seed: 0041
246.963: <09>Lane 07 initial seed: 0041
246.963: <09>Lane 08 initial seed: 0041
246.964: <09>Lane 00 nibble 0 raw readback: 003f
246.964: <09>Lane 00 nibble 0 adjusted value (pre nibble): 003f
246.964: <09>Lane 00 nibble 0 adjusted value (post nibble): 003f
246.964: <09>Lane 01 nibble 0 raw readback: 003d
246.964: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003d
246.964: <09>Lane 01 nibble 0 adjusted value (post nibble): 003d
246.964: <09>Lane 02 nibble 0 raw readback: 0039
246.964: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0039
246.964: <09>Lane 02 nibble 0 adjusted value (post nibble): 0039
246.964: <09>Lane 03 nibble 0 raw readback: 0037
246.964: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0037
246.964: <09>Lane 03 nibble 0 adjusted value (post nibble): 0037
246.964: <09>Lane 04 nibble 0 raw readback: 002e
246.964: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002e
246.964: <09>Lane 04 nibble 0 adjusted value (post nibble): 002e
246.964: <09>Lane 05 nibble 0 raw readback: 0030
246.964: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0030
246.964: <09>Lane 05 nibble 0 adjusted value (post nibble): 0030
246.964: <09>Lane 06 nibble 0 raw readback: 0034
246.964: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0034
246.964: <09>Lane 06 nibble 0 adjusted value (post nibble): 0034
246.964: <09>Lane 07 nibble 0 raw readback: 0036
246.964: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0036
246.964: <09>Lane 07 nibble 0 adjusted value (post nibble): 0036
246.964: <09>Lane 08 nibble 0 raw readback: 0030
246.964: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0030
246.964: <09>Lane 08 nibble 0 adjusted value (post nibble): 0030
246.964: AgesaHwWlPhase1: training nibble 1
246.964: DIMM 1 RttNom: 3
246.964: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.964: DIMM 1 RttWr: 2
246.964: DIMM 1 RttWr: 2
246.964: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.964: DIMM 1 RttWr: 2
246.964: DIMM 1 RttNom: 3
246.964: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.964: DIMM 1 RttNom: 3
246.964: DIMM 1 RttWr: 2
246.964: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.964: DIMM 1 RttWr: 2
246.964: DIMM 0 RttNom: 3
246.964: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.964: DIMM 1 RttNom: 3
246.964: DIMM 0 RttWr: 2
246.964: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.964: DIMM 1 RttWr: 2
246.964: DIMM 0 RttNom: 3
246.964: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.964: DIMM 1 RttNom: 3
246.964: DIMM 0 RttWr: 2
246.964: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.964: DIMM 1 RttWr: 2
246.964: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
246.964: <09>Lane 00 initial seed: 0041
246.964: <09>Lane 01 initial seed: 0041
246.964: <09>Lane 02 initial seed: 0041
246.964: <09>Lane 03 initial seed: 0041
246.964: <09>Lane 04 initial seed: 0041
246.964: <09>Lane 05 initial seed: 0041
246.964: <09>Lane 06 initial seed: 0041
246.964: <09>Lane 07 initial seed: 0041
246.964: <09>Lane 08 initial seed: 0041
246.964: <09>Lane 00 nibble 1 raw readback: 003f
246.964: <09>Lane 00 nibble 1 adjusted value (pre nibble): 003f
246.964: <09>Lane 00 nibble 1 adjusted value (post nibble): 0040
246.964: <09>Lane 01 nibble 1 raw readback: 003c
246.964: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003c
246.964: <09>Lane 01 nibble 1 adjusted value (post nibble): 003e
246.964: <09>Lane 02 nibble 1 raw readback: 0039
246.964: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0039
246.964: <09>Lane 02 nibble 1 adjusted value (post nibble): 003d
246.964: <09>Lane 03 nibble 1 raw readback: 0039
246.964: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0039
246.964: <09>Lane 03 nibble 1 adjusted value (post nibble): 003d
246.964: <09>Lane 04 nibble 1 raw readback: 002f
246.964: <09>Lane 04 nibble 1 adjusted value (pre nibble): 002f
246.964: <09>Lane 04 nibble 1 adjusted value (post nibble): 0038
246.964: <09>Lane 05 nibble 1 raw readback: 0031
246.964: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0031
246.965: <09>Lane 05 nibble 1 adjusted value (post nibble): 0039
246.964: <09>Lane 06 nibble 1 raw readback: 0033
246.965: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0033
246.965: <09>Lane 06 nibble 1 adjusted value (post nibble): 003a
246.965: <09>Lane 07 nibble 1 raw readback: 0036
246.965: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0036
246.965: <09>Lane 07 nibble 1 adjusted value (post nibble): 003b
246.965: <09>Lane 08 nibble 1 raw readback: 0030
246.965: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0030
246.965: <09>Lane 08 nibble 1 adjusted value (post nibble): 0038
246.965: <09>original critical gross delay: 0
246.965: <09>new critical gross delay: 0
246.965: DIMM 1 RttNom: 3
246.965: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.965: DIMM 1 RttNom: 3
246.965: DIMM 1 RttWr: 2
246.965: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.965: DIMM 1 RttWr: 2
246.965: DIMM 1 RttNom: 3
246.965: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.965: DIMM 1 RttNom: 3
246.965: DIMM 1 RttWr: 2
246.965: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.965: DIMM 1 RttWr: 2
246.965: DIMM 0 RttNom: 3
246.965: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.965: DIMM 1 RttNom: 3
246.965: DIMM 0 RttWr: 2
246.965: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.965: DIMM 1 RttWr: 2
246.965: DIMM 0 RttNom: 3
246.965: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.965: DIMM 1 RttNom: 3
246.965: DIMM 0 RttWr: 2
246.965: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.965: DIMM 1 RttWr: 2
246.965: activate_spd_rom() for node 01
246.965: enable_spd_node1()
246.965: AgesaHwWlPhase1: training nibble 0
246.966: DIMM 0 RttNom: 3
246.966: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.966: DIMM 0 RttWr: 2
246.966: DIMM 0 RttWr: 2
246.966: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.966: DIMM 0 RttWr: 2
246.966: DIMM 0 RttNom: 3
246.966: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.966: DIMM 0 RttNom: 3
246.966: DIMM 0 RttWr: 2
246.966: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.966: DIMM 0 RttWr: 2
246.966: DIMM 1 RttNom: 3
246.966: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.966: DIMM 0 RttNom: 3
246.966: DIMM 1 RttWr: 2
246.966: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.966: DIMM 0 RttWr: 2
246.966: DIMM 1 RttNom: 3
246.966: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.966: DIMM 0 RttNom: 3
246.966: DIMM 1 RttWr: 2
246.966: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.966: DIMM 0 RttWr: 2
246.966: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
246.966: <09>Lane 00 initial seed: 0041
246.966: <09>Lane 01 initial seed: 0041
246.966: <09>Lane 02 initial seed: 0041
246.966: <09>Lane 03 initial seed: 0041
246.966: <09>Lane 04 initial seed: 0041
246.966: <09>Lane 05 initial seed: 0041
246.966: <09>Lane 06 initial seed: 0041
246.966: <09>Lane 07 initial seed: 0041
246.966: <09>Lane 08 initial seed: 0041
246.966: <09>Lane 00 nibble 0 raw readback: 003b
246.966: <09>Lane 00 nibble 0 adjusted value (pre nibble): 003b
246.966: <09>Lane 00 nibble 0 adjusted value (post nibble): 003b
246.966: <09>Lane 01 nibble 0 raw readback: 0037
246.966: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0037
246.966: <09>Lane 01 nibble 0 adjusted value (post nibble): 0037
246.966: <09>Lane 02 nibble 0 raw readback: 0033
246.966: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0033
246.966: <09>Lane 02 nibble 0 adjusted value (post nibble): 0033
246.966: <09>Lane 03 nibble 0 raw readback: 0031
246.966: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0031
246.966: <09>Lane 03 nibble 0 adjusted value (post nibble): 0031
246.966: <09>Lane 04 nibble 0 raw readback: 002f
246.966: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002f
246.966: <09>Lane 04 nibble 0 adjusted value (post nibble): 002f
246.966: <09>Lane 05 nibble 0 raw readback: 0032
246.966: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0032
246.966: <09>Lane 05 nibble 0 adjusted value (post nibble): 0032
246.966: <09>Lane 06 nibble 0 raw readback: 0035
246.966: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0035
246.966: <09>Lane 06 nibble 0 adjusted value (post nibble): 0035
246.966: <09>Lane 07 nibble 0 raw readback: 0038
246.966: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0038
246.966: <09>Lane 07 nibble 0 adjusted value (post nibble): 0038
246.966: <09>Lane 08 nibble 0 raw readback: 002f
246.966: <09>Lane 08 nibble 0 adjusted value (pre nibble): 002f
246.966: <09>Lane 08 nibble 0 adjusted value (post nibble): 002f
246.966: AgesaHwWlPhase1: training nibble 1
246.966: DIMM 0 RttNom: 3
246.966: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.966: DIMM 0 RttWr: 2
246.967: DIMM 0 RttWr: 2
246.967: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.967: DIMM 0 RttWr: 2
246.967: DIMM 0 RttNom: 3
246.967: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.967: DIMM 0 RttNom: 3
246.967: DIMM 0 RttWr: 2
246.967: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.967: DIMM 0 RttWr: 2
246.967: DIMM 1 RttNom: 3
246.967: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.967: DIMM 0 RttNom: 3
246.967: DIMM 1 RttWr: 2
246.967: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.967: DIMM 0 RttWr: 2
246.967: DIMM 1 RttNom: 3
246.967: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.967: DIMM 0 RttNom: 3
246.967: DIMM 1 RttWr: 2
246.967: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.967: DIMM 0 RttWr: 2
246.967: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
246.967: <09>Lane 00 initial seed: 0041
246.967: <09>Lane 01 initial seed: 0041
246.967: <09>Lane 02 initial seed: 0041
246.967: <09>Lane 03 initial seed: 0041
246.967: <09>Lane 04 initial seed: 0041
246.967: <09>Lane 05 initial seed: 0041
246.967: <09>Lane 06 initial seed: 0041
246.967: <09>Lane 07 initial seed: 0041
246.967: <09>Lane 08 initial seed: 0041
246.967: <09>Lane 00 nibble 1 raw readback: 0039
246.967: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0039
246.967: <09>Lane 00 nibble 1 adjusted value (post nibble): 003d
246.967: <09>Lane 01 nibble 1 raw readback: 0037
246.967: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0037
246.967: <09>Lane 01 nibble 1 adjusted value (post nibble): 003c
246.967: <09>Lane 02 nibble 1 raw readback: 0033
246.967: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0033
246.967: <09>Lane 02 nibble 1 adjusted value (post nibble): 003a
246.967: <09>Lane 03 nibble 1 raw readback: 0032
246.967: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0032
246.967: <09>Lane 03 nibble 1 adjusted value (post nibble): 0039
246.967: <09>Lane 04 nibble 1 raw readback: 0030
246.967: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0030
246.967: <09>Lane 04 nibble 1 adjusted value (post nibble): 0038
246.967: <09>Lane 05 nibble 1 raw readback: 0031
246.967: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0031
246.967: <09>Lane 05 nibble 1 adjusted value (post nibble): 0039
246.967: <09>Lane 06 nibble 1 raw readback: 0035
246.967: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0035
246.967: <09>Lane 06 nibble 1 adjusted value (post nibble): 003b
246.967: <09>Lane 07 nibble 1 raw readback: 0038
246.967: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0038
246.967: <09>Lane 07 nibble 1 adjusted value (post nibble): 003c
246.967: <09>Lane 08 nibble 1 raw readback: 002f
246.967: <09>Lane 08 nibble 1 adjusted value (pre nibble): 002f
246.967: <09>Lane 08 nibble 1 adjusted value (post nibble): 0038
246.967: <09>original critical gross delay: 0
246.967: <09>new critical gross delay: 0
246.968: DIMM 0 RttNom: 3
246.968: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.968: DIMM 0 RttNom: 3
246.968: DIMM 0 RttWr: 2
246.968: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.968: DIMM 0 RttWr: 2
246.968: DIMM 0 RttNom: 3
246.968: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.968: DIMM 0 RttNom: 3
246.968: DIMM 0 RttWr: 2
246.968: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.968: DIMM 0 RttWr: 2
246.968: DIMM 1 RttNom: 3
246.968: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.968: DIMM 0 RttNom: 3
246.968: DIMM 1 RttWr: 2
246.968: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.968: DIMM 0 RttWr: 2
246.968: DIMM 1 RttNom: 3
246.968: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.968: DIMM 0 RttNom: 3
246.968: DIMM 1 RttWr: 2
246.968: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.968: DIMM 0 RttWr: 2
246.968: AgesaHwWlPhase1: training nibble 0
246.968: DIMM 1 RttNom: 3
246.968: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.968: DIMM 1 RttWr: 2
246.968: DIMM 1 RttWr: 2
246.968: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.968: DIMM 1 RttWr: 2
246.968: DIMM 1 RttNom: 3
246.968: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.968: DIMM 1 RttNom: 3
246.968: DIMM 1 RttWr: 2
246.968: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.968: DIMM 1 RttWr: 2
246.968: DIMM 0 RttNom: 3
246.968: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.968: DIMM 1 RttNom: 3
246.968: DIMM 0 RttWr: 2
246.968: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.968: DIMM 1 RttWr: 2
246.968: DIMM 0 RttNom: 3
246.968: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.968: DIMM 1 RttNom: 3
246.968: DIMM 0 RttWr: 2
246.968: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.968: DIMM 1 RttWr: 2
246.968: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
246.968: <09>Lane 00 initial seed: 0041
246.968: <09>Lane 01 initial seed: 0041
246.968: <09>Lane 02 initial seed: 0041
246.968: <09>Lane 03 initial seed: 0041
246.968: <09>Lane 04 initial seed: 0041
246.968: <09>Lane 05 initial seed: 0041
246.968: <09>Lane 06 initial seed: 0041
246.968: <09>Lane 07 initial seed: 0041
246.968: <09>Lane 08 initial seed: 0041
246.968: <09>Lane 00 nibble 0 raw readback: 0043
246.968: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0043
246.968: <09>Lane 00 nibble 0 adjusted value (post nibble): 0043
246.968: <09>Lane 01 nibble 0 raw readback: 003e
246.968: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003e
246.969: <09>Lane 01 nibble 0 adjusted value (post nibble): 003e
246.969: <09>Lane 02 nibble 0 raw readback: 003b
246.969: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003b
246.969: <09>Lane 02 nibble 0 adjusted value (post nibble): 003b
246.969: <09>Lane 03 nibble 0 raw readback: 003a
246.969: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003a
246.969: <09>Lane 03 nibble 0 adjusted value (post nibble): 003a
246.969: <09>Lane 04 nibble 0 raw readback: 0038
246.969: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0038
246.969: <09>Lane 04 nibble 0 adjusted value (post nibble): 0038
246.969: <09>Lane 05 nibble 0 raw readback: 003b
246.969: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003b
246.969: <09>Lane 05 nibble 0 adjusted value (post nibble): 003b
246.969: <09>Lane 06 nibble 0 raw readback: 003c
246.969: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003c
246.969: <09>Lane 06 nibble 0 adjusted value (post nibble): 003c
246.969: <09>Lane 07 nibble 0 raw readback: 0040
246.969: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0040
246.969: <09>Lane 07 nibble 0 adjusted value (post nibble): 0040
246.969: <09>Lane 08 nibble 0 raw readback: 0036
246.969: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
246.969: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
246.969: AgesaHwWlPhase1: training nibble 1
246.969: DIMM 1 RttNom: 3
246.969: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.969: DIMM 1 RttWr: 2
246.969: DIMM 1 RttWr: 2
246.969: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.969: DIMM 1 RttWr: 2
246.969: DIMM 1 RttNom: 3
246.969: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.969: DIMM 1 RttNom: 3
246.969: DIMM 1 RttWr: 2
246.969: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.969: DIMM 1 RttWr: 2
246.969: DIMM 0 RttNom: 3
246.969: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.969: DIMM 1 RttNom: 3
246.969: DIMM 0 RttWr: 2
246.969: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.969: DIMM 1 RttWr: 2
246.969: DIMM 0 RttNom: 3
246.969: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.969: DIMM 1 RttNom: 3
246.969: DIMM 0 RttWr: 2
246.969: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.969: DIMM 1 RttWr: 2
246.969: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
246.969: <09>Lane 00 initial seed: 0041
246.969: <09>Lane 01 initial seed: 0041
246.969: <09>Lane 02 initial seed: 0041
246.969: <09>Lane 03 initial seed: 0041
246.969: <09>Lane 04 initial seed: 0041
246.969: <09>Lane 05 initial seed: 0041
246.969: <09>Lane 06 initial seed: 0041
246.969: <09>Lane 07 initial seed: 0041
246.969: <09>Lane 08 initial seed: 0041
246.969: <09>Lane 00 nibble 1 raw readback: 0044
246.969: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0044
246.969: <09>Lane 00 nibble 1 adjusted value (post nibble): 0042
246.969: <09>Lane 01 nibble 1 raw readback: 003e
246.969: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003e
246.969: <09>Lane 01 nibble 1 adjusted value (post nibble): 003f
246.969: <09>Lane 02 nibble 1 raw readback: 003c
246.969: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003c
246.969: <09>Lane 02 nibble 1 adjusted value (post nibble): 003e
246.969: <09>Lane 03 nibble 1 raw readback: 003b
246.969: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
246.969: <09>Lane 03 nibble 1 adjusted value (post nibble): 003e
246.969: <09>Lane 04 nibble 1 raw readback: 0038
246.969: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
246.969: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
246.969: <09>Lane 05 nibble 1 raw readback: 003b
246.969: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003b
246.969: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
246.969: <09>Lane 06 nibble 1 raw readback: 003d
246.969: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003d
246.969: <09>Lane 06 nibble 1 adjusted value (post nibble): 003f
246.970: <09>Lane 07 nibble 1 raw readback: 0040
246.970: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0040
246.970: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
246.970: <09>Lane 08 nibble 1 raw readback: 0037
246.970: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
246.970: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
246.970: <09>original critical gross delay: 0
246.970: <09>new critical gross delay: 0
246.970: DIMM 1 RttNom: 3
246.970: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.970: DIMM 1 RttNom: 3
246.970: DIMM 1 RttWr: 2
246.970: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.970: DIMM 1 RttWr: 2
246.970: DIMM 1 RttNom: 3
246.970: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.970: DIMM 1 RttNom: 3
246.970: DIMM 1 RttWr: 2
246.970: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.970: DIMM 1 RttWr: 2
246.970: DIMM 0 RttNom: 3
246.970: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.970: DIMM 1 RttNom: 3
246.970: DIMM 0 RttWr: 2
246.970: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.970: DIMM 1 RttWr: 2
246.970: DIMM 0 RttNom: 3
246.970: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.970: DIMM 1 RttNom: 3
246.970: DIMM 0 RttWr: 2
246.970: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.970: DIMM 1 RttWr: 2
246.970: AgesaHwWlPhase1: training nibble 0
246.970: DIMM 0 RttNom: 3
246.970: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.970: DIMM 0 RttWr: 2
246.970: DIMM 0 RttWr: 2
246.970: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.970: DIMM 0 RttWr: 2
246.970: DIMM 0 RttNom: 3
246.970: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.970: DIMM 0 RttNom: 3
246.970: DIMM 0 RttWr: 2
246.970: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.970: DIMM 0 RttWr: 2
246.970: DIMM 1 RttNom: 3
246.970: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.970: DIMM 0 RttNom: 3
246.970: DIMM 1 RttWr: 2
246.970: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.970: DIMM 0 RttWr: 2
246.970: DIMM 1 RttNom: 3
246.970: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.970: DIMM 0 RttNom: 3
246.970: DIMM 1 RttWr: 2
246.970: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.970: DIMM 0 RttWr: 2
246.970: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
246.970: <09>Lane 00 initial seed: 0041
246.971: <09>Lane 01 initial seed: 0041
246.971: <09>Lane 02 initial seed: 0041
246.971: <09>Lane 03 initial seed: 0041
246.971: <09>Lane 04 initial seed: 0041
246.971: <09>Lane 05 initial seed: 0041
246.971: <09>Lane 06 initial seed: 0041
246.971: <09>Lane 07 initial seed: 0041
246.971: <09>Lane 08 initial seed: 0041
246.971: <09>Lane 00 nibble 0 raw readback: 003c
246.971: <09>Lane 00 nibble 0 adjusted value (pre nibble): 003c
246.971: <09>Lane 00 nibble 0 adjusted value (post nibble): 003c
246.971: <09>Lane 01 nibble 0 raw readback: 0037
246.971: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0037
246.971: <09>Lane 01 nibble 0 adjusted value (post nibble): 0037
246.971: <09>Lane 02 nibble 0 raw readback: 0034
246.971: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0034
246.971: <09>Lane 02 nibble 0 adjusted value (post nibble): 0034
246.971: <09>Lane 03 nibble 0 raw readback: 0031
246.971: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0031
246.971: <09>Lane 03 nibble 0 adjusted value (post nibble): 0031
246.971: <09>Lane 04 nibble 0 raw readback: 0030
246.971: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0030
246.971: <09>Lane 04 nibble 0 adjusted value (post nibble): 0030
246.971: <09>Lane 05 nibble 0 raw readback: 0034
246.971: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0034
246.971: <09>Lane 05 nibble 0 adjusted value (post nibble): 0034
246.971: <09>Lane 06 nibble 0 raw readback: 0035
246.971: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0035
246.971: <09>Lane 06 nibble 0 adjusted value (post nibble): 0035
246.971: <09>Lane 07 nibble 0 raw readback: 0039
246.971: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0039
246.971: <09>Lane 07 nibble 0 adjusted value (post nibble): 0039
246.971: <09>Lane 08 nibble 0 raw readback: 002f
246.971: <09>Lane 08 nibble 0 adjusted value (pre nibble): 002f
246.971: <09>Lane 08 nibble 0 adjusted value (post nibble): 002f
246.971: AgesaHwWlPhase1: training nibble 1
246.971: DIMM 0 RttNom: 3
246.971: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.971: DIMM 0 RttWr: 2
246.971: DIMM 0 RttWr: 2
246.971: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.971: DIMM 0 RttWr: 2
246.971: DIMM 0 RttNom: 3
246.971: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.971: DIMM 0 RttNom: 3
246.971: DIMM 0 RttWr: 2
246.971: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.971: DIMM 0 RttWr: 2
246.971: DIMM 1 RttNom: 3
246.971: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.971: DIMM 0 RttNom: 3
246.971: DIMM 1 RttWr: 2
246.971: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.971: DIMM 0 RttWr: 2
246.971: DIMM 1 RttNom: 3
246.971: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.971: DIMM 0 RttNom: 3
246.971: DIMM 1 RttWr: 2
246.971: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.971: DIMM 0 RttWr: 2
246.971: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
246.971: <09>Lane 00 initial seed: 0041
246.971: <09>Lane 01 initial seed: 0041
246.971: <09>Lane 02 initial seed: 0041
246.971: <09>Lane 03 initial seed: 0041
246.971: <09>Lane 04 initial seed: 0041
246.971: <09>Lane 05 initial seed: 0041
246.971: <09>Lane 06 initial seed: 0041
246.971: <09>Lane 07 initial seed: 0041
246.971: <09>Lane 08 initial seed: 0041
246.971: <09>Lane 00 nibble 1 raw readback: 003b
246.972: <09>Lane 00 nibble 1 adjusted value (pre nibble): 003b
246.972: <09>Lane 00 nibble 1 adjusted value (post nibble): 003e
246.972: <09>Lane 01 nibble 1 raw readback: 0037
246.972: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0037
246.972: <09>Lane 01 nibble 1 adjusted value (post nibble): 003c
246.972: <09>Lane 02 nibble 1 raw readback: 0033
246.972: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0033
246.972: <09>Lane 02 nibble 1 adjusted value (post nibble): 003a
246.972: <09>Lane 03 nibble 1 raw readback: 0031
246.972: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0031
246.972: <09>Lane 03 nibble 1 adjusted value (post nibble): 0039
246.972: <09>Lane 04 nibble 1 raw readback: 002f
246.972: <09>Lane 04 nibble 1 adjusted value (pre nibble): 002f
246.972: <09>Lane 04 nibble 1 adjusted value (post nibble): 0038
246.972: <09>Lane 05 nibble 1 raw readback: 0032
246.972: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0032
246.972: <09>Lane 05 nibble 1 adjusted value (post nibble): 0039
246.972: <09>Lane 06 nibble 1 raw readback: 0035
246.972: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0035
246.972: <09>Lane 06 nibble 1 adjusted value (post nibble): 003b
246.972: <09>Lane 07 nibble 1 raw readback: 0039
246.972: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0039
246.972: <09>Lane 07 nibble 1 adjusted value (post nibble): 003d
246.972: <09>Lane 08 nibble 1 raw readback: 002e
246.972: <09>Lane 08 nibble 1 adjusted value (pre nibble): 002e
246.972: <09>Lane 08 nibble 1 adjusted value (post nibble): 0037
246.972: <09>original critical gross delay: 0
246.972: <09>new critical gross delay: 0
246.972: DIMM 0 RttNom: 3
246.972: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.972: DIMM 0 RttNom: 3
246.972: DIMM 0 RttWr: 2
246.972: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.972: DIMM 0 RttWr: 2
246.972: DIMM 0 RttNom: 3
246.972: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.972: DIMM 0 RttNom: 3
246.972: DIMM 0 RttWr: 2
246.972: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.972: DIMM 0 RttWr: 2
246.972: DIMM 1 RttNom: 3
246.972: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.972: DIMM 0 RttNom: 3
246.972: DIMM 1 RttWr: 2
246.972: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.972: DIMM 0 RttWr: 2
246.972: DIMM 1 RttNom: 3
246.972: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.972: DIMM 0 RttNom: 3
246.972: DIMM 1 RttWr: 2
246.972: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.972: DIMM 0 RttWr: 2
246.972: AgesaHwWlPhase1: training nibble 0
246.972: DIMM 1 RttNom: 3
246.972: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.972: DIMM 1 RttWr: 2
246.972: DIMM 1 RttWr: 2
246.972: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.972: DIMM 1 RttWr: 2
246.972: DIMM 1 RttNom: 3
246.972: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.972: DIMM 1 RttNom: 3
246.972: DIMM 1 RttWr: 2
246.972: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.972: DIMM 1 RttWr: 2
246.973: DIMM 0 RttNom: 3
246.973: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.973: DIMM 1 RttNom: 3
246.973: DIMM 0 RttWr: 2
246.973: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.973: DIMM 1 RttWr: 2
246.973: DIMM 0 RttNom: 3
246.973: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.973: DIMM 1 RttNom: 3
246.973: DIMM 0 RttWr: 2
246.973: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.973: DIMM 1 RttWr: 2
246.973: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
246.973: <09>Lane 00 initial seed: 0041
246.973: <09>Lane 01 initial seed: 0041
246.973: <09>Lane 02 initial seed: 0041
246.973: <09>Lane 03 initial seed: 0041
246.973: <09>Lane 04 initial seed: 0041
246.973: <09>Lane 05 initial seed: 0041
246.973: <09>Lane 06 initial seed: 0041
246.973: <09>Lane 07 initial seed: 0041
246.973: <09>Lane 08 initial seed: 0041
246.973: <09>Lane 00 nibble 0 raw readback: 0041
246.973: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0041
246.973: <09>Lane 00 nibble 0 adjusted value (post nibble): 0041
246.973: <09>Lane 01 nibble 0 raw readback: 003f
246.973: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003f
246.973: <09>Lane 01 nibble 0 adjusted value (post nibble): 003f
246.973: <09>Lane 02 nibble 0 raw readback: 003c
246.973: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003c
246.973: <09>Lane 02 nibble 0 adjusted value (post nibble): 003c
246.973: <09>Lane 03 nibble 0 raw readback: 0039
246.973: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0039
246.973: <09>Lane 03 nibble 0 adjusted value (post nibble): 0039
246.973: <09>Lane 04 nibble 0 raw readback: 0038
246.973: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0038
246.973: <09>Lane 04 nibble 0 adjusted value (post nibble): 0038
246.973: <09>Lane 05 nibble 0 raw readback: 003b
246.973: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003b
246.973: <09>Lane 05 nibble 0 adjusted value (post nibble): 003b
246.973: <09>Lane 06 nibble 0 raw readback: 003e
246.973: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003e
246.973: <09>Lane 06 nibble 0 adjusted value (post nibble): 003e
246.973: <09>Lane 07 nibble 0 raw readback: 0040
246.973: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0040
246.973: <09>Lane 07 nibble 0 adjusted value (post nibble): 0040
246.973: <09>Lane 08 nibble 0 raw readback: 0036
246.973: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
246.973: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
246.973: AgesaHwWlPhase1: training nibble 1
246.973: DIMM 1 RttNom: 3
246.973: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.973: DIMM 1 RttWr: 2
246.973: DIMM 1 RttWr: 2
246.973: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.973: DIMM 1 RttWr: 2
246.973: DIMM 1 RttNom: 3
246.973: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.973: DIMM 1 RttNom: 3
246.973: DIMM 1 RttWr: 2
246.973: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.973: DIMM 1 RttWr: 2
246.973: DIMM 0 RttNom: 3
246.973: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.973: DIMM 1 RttNom: 3
246.973: DIMM 0 RttWr: 2
246.973: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.973: DIMM 1 RttWr: 2
246.973: DIMM 0 RttNom: 3
246.974: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.973: DIMM 1 RttNom: 3
246.974: DIMM 0 RttWr: 2
246.974: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.974: DIMM 1 RttWr: 2
246.974: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
246.974: <09>Lane 00 initial seed: 0041
246.974: <09>Lane 01 initial seed: 0041
246.974: <09>Lane 02 initial seed: 0041
246.974: <09>Lane 03 initial seed: 0041
246.974: <09>Lane 04 initial seed: 0041
246.974: <09>Lane 05 initial seed: 0041
246.974: <09>Lane 06 initial seed: 0041
246.974: <09>Lane 07 initial seed: 0041
246.974: <09>Lane 08 initial seed: 0041
246.974: <09>Lane 00 nibble 1 raw readback: 0043
246.974: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0043
246.974: <09>Lane 00 nibble 1 adjusted value (post nibble): 0042
246.974: <09>Lane 01 nibble 1 raw readback: 0040
246.974: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0040
246.974: <09>Lane 01 nibble 1 adjusted value (post nibble): 0040
246.974: <09>Lane 02 nibble 1 raw readback: 003c
246.974: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003c
246.974: <09>Lane 02 nibble 1 adjusted value (post nibble): 003e
246.974: <09>Lane 03 nibble 1 raw readback: 003a
246.974: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003a
246.974: <09>Lane 03 nibble 1 adjusted value (post nibble): 003d
246.974: <09>Lane 04 nibble 1 raw readback: 0037
246.974: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0037
246.974: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
246.974: <09>Lane 05 nibble 1 raw readback: 003b
246.974: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003b
246.974: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
246.974: <09>Lane 06 nibble 1 raw readback: 003e
246.974: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003e
246.974: <09>Lane 06 nibble 1 adjusted value (post nibble): 003f
246.974: <09>Lane 07 nibble 1 raw readback: 0042
246.974: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
246.974: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
246.974: <09>Lane 08 nibble 1 raw readback: 0037
246.974: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
246.974: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
246.974: <09>original critical gross delay: 0
246.974: <09>new critical gross delay: 0
246.974: DIMM 1 RttNom: 3
246.974: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.974: DIMM 1 RttNom: 3
246.974: DIMM 1 RttWr: 2
246.974: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.974: DIMM 1 RttWr: 2
246.974: DIMM 1 RttNom: 3
246.974: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.974: DIMM 1 RttNom: 3
246.974: DIMM 1 RttWr: 2
246.974: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.974: DIMM 1 RttWr: 2
246.974: DIMM 0 RttNom: 3
246.974: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.974: DIMM 1 RttNom: 3
246.974: DIMM 0 RttWr: 2
246.974: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.974: DIMM 1 RttWr: 2
246.974: DIMM 0 RttNom: 3
246.974: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.974: DIMM 1 RttNom: 3
246.974: DIMM 0 RttWr: 2
246.974: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.975: DIMM 1 RttWr: 2
246.975: activate_spd_rom() for node 02
246.975: enable_spd_node2()
246.975: AgesaHwWlPhase1: training nibble 0
246.975: DIMM 0 RttNom: 3
246.975: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.975: DIMM 0 RttWr: 2
246.975: DIMM 0 RttWr: 2
246.975: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.975: DIMM 0 RttWr: 2
246.975: DIMM 0 RttNom: 3
246.975: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.975: DIMM 0 RttNom: 3
246.975: DIMM 0 RttWr: 2
246.975: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.975: DIMM 0 RttWr: 2
246.975: DIMM 1 RttNom: 3
246.975: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.975: DIMM 0 RttNom: 3
246.975: DIMM 1 RttWr: 2
246.975: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.975: DIMM 0 RttWr: 2
246.975: DIMM 1 RttNom: 3
246.975: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.975: DIMM 0 RttNom: 3
246.975: DIMM 1 RttWr: 2
246.975: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.975: DIMM 0 RttWr: 2
246.975: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
246.975: <09>Lane 00 initial seed: 0041
246.975: <09>Lane 01 initial seed: 0041
246.975: <09>Lane 02 initial seed: 0041
246.975: <09>Lane 03 initial seed: 0041
246.975: <09>Lane 04 initial seed: 0041
246.975: <09>Lane 05 initial seed: 0041
246.975: <09>Lane 06 initial seed: 0041
246.975: <09>Lane 07 initial seed: 0041
246.975: <09>Lane 08 initial seed: 0041
246.975: <09>Lane 00 nibble 0 raw readback: 004b
246.975: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004b
246.975: <09>Lane 00 nibble 0 adjusted value (post nibble): 004b
246.975: <09>Lane 01 nibble 0 raw readback: 0045
246.975: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0045
246.976: <09>Lane 01 nibble 0 adjusted value (post nibble): 0045
246.976: <09>Lane 02 nibble 0 raw readback: 0043
246.976: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0043
246.976: <09>Lane 02 nibble 0 adjusted value (post nibble): 0043
246.976: <09>Lane 03 nibble 0 raw readback: 0042
246.976: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0042
246.976: <09>Lane 03 nibble 0 adjusted value (post nibble): 0042
246.976: <09>Lane 04 nibble 0 raw readback: 0039
246.976: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
246.976: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
246.976: <09>Lane 05 nibble 0 raw readback: 003c
246.976: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003c
246.976: <09>Lane 05 nibble 0 adjusted value (post nibble): 003c
246.976: <09>Lane 06 nibble 0 raw readback: 003f
246.976: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003f
246.976: <09>Lane 06 nibble 0 adjusted value (post nibble): 003f
246.976: <09>Lane 07 nibble 0 raw readback: 0041
246.976: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0041
246.976: <09>Lane 07 nibble 0 adjusted value (post nibble): 0041
246.976: <09>Lane 08 nibble 0 raw readback: 003b
246.976: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003b
246.976: <09>Lane 08 nibble 0 adjusted value (post nibble): 003b
246.976: AgesaHwWlPhase1: training nibble 1
246.976: DIMM 0 RttNom: 3
246.976: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.976: DIMM 0 RttWr: 2
246.976: DIMM 0 RttWr: 2
246.976: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.976: DIMM 0 RttWr: 2
246.976: DIMM 0 RttNom: 3
246.976: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.976: DIMM 0 RttNom: 3
246.976: DIMM 0 RttWr: 2
246.976: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.976: DIMM 0 RttWr: 2
246.976: DIMM 1 RttNom: 3
246.976: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.976: DIMM 0 RttNom: 3
246.976: DIMM 1 RttWr: 2
246.976: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.976: DIMM 0 RttWr: 2
246.976: DIMM 1 RttNom: 3
246.976: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.976: DIMM 0 RttNom: 3
246.976: DIMM 1 RttWr: 2
246.976: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.976: DIMM 0 RttWr: 2
246.976: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
246.976: <09>Lane 00 initial seed: 0041
246.976: <09>Lane 01 initial seed: 0041
246.976: <09>Lane 02 initial seed: 0041
246.976: <09>Lane 03 initial seed: 0041
246.976: <09>Lane 04 initial seed: 0041
246.976: <09>Lane 05 initial seed: 0041
246.976: <09>Lane 06 initial seed: 0041
246.976: <09>Lane 07 initial seed: 0041
246.976: <09>Lane 08 initial seed: 0041
246.976: <09>Lane 00 nibble 1 raw readback: 004a
246.976: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004a
246.976: <09>Lane 00 nibble 1 adjusted value (post nibble): 0045
246.976: <09>Lane 01 nibble 1 raw readback: 0046
246.976: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0046
246.976: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
246.976: <09>Lane 02 nibble 1 raw readback: 0044
246.976: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0044
246.976: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
246.976: <09>Lane 03 nibble 1 raw readback: 0042
246.977: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0042
246.976: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
246.976: <09>Lane 04 nibble 1 raw readback: 0039
246.977: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
246.977: <09>Lane 04 nibble 1 adjusted value (post nibble): 003d
246.977: <09>Lane 05 nibble 1 raw readback: 003b
246.977: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003b
246.977: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
246.977: <09>Lane 06 nibble 1 raw readback: 003f
246.977: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
246.977: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
246.977: <09>Lane 07 nibble 1 raw readback: 0040
246.977: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0040
246.977: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
246.977: <09>Lane 08 nibble 1 raw readback: 0039
246.977: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0039
246.977: <09>Lane 08 nibble 1 adjusted value (post nibble): 003d
246.977: <09>original critical gross delay: 0
246.977: <09>new critical gross delay: 0
246.977: DIMM 0 RttNom: 3
246.977: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.977: DIMM 0 RttNom: 3
246.977: DIMM 0 RttWr: 2
246.977: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.977: DIMM 0 RttWr: 2
246.977: DIMM 0 RttNom: 3
246.977: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.977: DIMM 0 RttNom: 3
246.977: DIMM 0 RttWr: 2
246.977: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.977: DIMM 0 RttWr: 2
246.977: DIMM 1 RttNom: 3
246.977: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.977: DIMM 0 RttNom: 3
246.977: DIMM 1 RttWr: 2
246.977: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.977: DIMM 0 RttWr: 2
246.977: DIMM 1 RttNom: 3
246.977: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.977: DIMM 0 RttNom: 3
246.977: DIMM 1 RttWr: 2
246.977: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.977: DIMM 0 RttWr: 2
246.977: AgesaHwWlPhase1: training nibble 0
246.977: DIMM 1 RttNom: 3
246.977: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.977: DIMM 1 RttWr: 2
246.977: DIMM 1 RttWr: 2
246.977: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.977: DIMM 1 RttWr: 2
246.977: DIMM 1 RttNom: 3
246.977: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.977: DIMM 1 RttNom: 3
246.977: DIMM 1 RttWr: 2
246.977: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.977: DIMM 1 RttWr: 2
246.977: DIMM 0 RttNom: 3
246.977: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.977: DIMM 1 RttNom: 3
246.977: DIMM 0 RttWr: 2
246.977: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.977: DIMM 1 RttWr: 2
246.977: DIMM 0 RttNom: 3
246.978: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.978: DIMM 1 RttNom: 3
246.978: DIMM 0 RttWr: 2
246.978: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.978: DIMM 1 RttWr: 2
246.978: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
246.978: <09>Lane 00 initial seed: 0041
246.978: <09>Lane 01 initial seed: 0041
246.978: <09>Lane 02 initial seed: 0041
246.978: <09>Lane 03 initial seed: 0041
246.978: <09>Lane 04 initial seed: 0041
246.978: <09>Lane 05 initial seed: 0041
246.978: <09>Lane 06 initial seed: 0041
246.978: <09>Lane 07 initial seed: 0041
246.978: <09>Lane 08 initial seed: 0041
246.978: <09>Lane 00 nibble 0 raw readback: 0040
246.978: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0040
246.978: <09>Lane 00 nibble 0 adjusted value (post nibble): 0040
246.978: <09>Lane 01 nibble 0 raw readback: 003a
246.978: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003a
246.978: <09>Lane 01 nibble 0 adjusted value (post nibble): 003a
246.978: <09>Lane 02 nibble 0 raw readback: 0039
246.978: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0039
246.978: <09>Lane 02 nibble 0 adjusted value (post nibble): 0039
246.978: <09>Lane 03 nibble 0 raw readback: 0036
246.978: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0036
246.978: <09>Lane 03 nibble 0 adjusted value (post nibble): 0036
246.978: <09>Lane 04 nibble 0 raw readback: 002d
246.978: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002d
246.978: <09>Lane 04 nibble 0 adjusted value (post nibble): 002d
246.978: <09>Lane 05 nibble 0 raw readback: 0031
246.978: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0031
246.978: <09>Lane 05 nibble 0 adjusted value (post nibble): 0031
246.978: <09>Lane 06 nibble 0 raw readback: 0033
246.978: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0033
246.978: <09>Lane 06 nibble 0 adjusted value (post nibble): 0033
246.978: <09>Lane 07 nibble 0 raw readback: 0036
246.978: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0036
246.978: <09>Lane 07 nibble 0 adjusted value (post nibble): 0036
246.978: <09>Lane 08 nibble 0 raw readback: 0030
246.978: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0030
246.978: <09>Lane 08 nibble 0 adjusted value (post nibble): 0030
246.978: AgesaHwWlPhase1: training nibble 1
246.978: DIMM 1 RttNom: 3
246.978: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.978: DIMM 1 RttWr: 2
246.978: DIMM 1 RttWr: 2
246.978: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.978: DIMM 1 RttWr: 2
246.978: DIMM 1 RttNom: 3
246.978: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.978: DIMM 1 RttNom: 3
246.978: DIMM 1 RttWr: 2
246.978: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.978: DIMM 1 RttWr: 2
246.978: DIMM 0 RttNom: 3
246.978: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.978: DIMM 1 RttNom: 3
246.978: DIMM 0 RttWr: 2
246.978: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.978: DIMM 1 RttWr: 2
246.978: DIMM 0 RttNom: 3
246.978: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.978: DIMM 1 RttNom: 3
246.978: DIMM 0 RttWr: 2
246.978: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.978: DIMM 1 RttWr: 2
246.978: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
246.978: <09>Lane 00 initial seed: 0041
246.979: <09>Lane 01 initial seed: 0041
246.978: <09>Lane 02 initial seed: 0041
246.978: <09>Lane 03 initial seed: 0041
246.979: <09>Lane 04 initial seed: 0041
246.979: <09>Lane 05 initial seed: 0041
246.979: <09>Lane 06 initial seed: 0041
246.979: <09>Lane 07 initial seed: 0041
246.979: <09>Lane 08 initial seed: 0041
246.979: <09>Lane 00 nibble 1 raw readback: 003e
246.979: <09>Lane 00 nibble 1 adjusted value (pre nibble): 003e
246.979: <09>Lane 00 nibble 1 adjusted value (post nibble): 003f
246.979: <09>Lane 01 nibble 1 raw readback: 003a
246.979: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003a
246.979: <09>Lane 01 nibble 1 adjusted value (post nibble): 003d
246.979: <09>Lane 02 nibble 1 raw readback: 003a
246.979: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003a
246.979: <09>Lane 02 nibble 1 adjusted value (post nibble): 003d
246.979: <09>Lane 03 nibble 1 raw readback: 0037
246.979: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0037
246.979: <09>Lane 03 nibble 1 adjusted value (post nibble): 003c
246.979: <09>Lane 04 nibble 1 raw readback: 002e
246.979: <09>Lane 04 nibble 1 adjusted value (pre nibble): 002e
246.979: <09>Lane 04 nibble 1 adjusted value (post nibble): 0037
246.979: <09>Lane 05 nibble 1 raw readback: 0031
246.979: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0031
246.979: <09>Lane 05 nibble 1 adjusted value (post nibble): 0039
246.979: <09>Lane 06 nibble 1 raw readback: 0033
246.979: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0033
246.979: <09>Lane 06 nibble 1 adjusted value (post nibble): 003a
246.979: <09>Lane 07 nibble 1 raw readback: 0036
246.979: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0036
246.979: <09>Lane 07 nibble 1 adjusted value (post nibble): 003b
246.979: <09>Lane 08 nibble 1 raw readback: 002f
246.979: <09>Lane 08 nibble 1 adjusted value (pre nibble): 002f
246.979: <09>Lane 08 nibble 1 adjusted value (post nibble): 0038
246.979: <09>original critical gross delay: 0
246.979: <09>new critical gross delay: 0
246.979: DIMM 1 RttNom: 3
246.979: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.979: DIMM 1 RttNom: 3
246.979: DIMM 1 RttWr: 2
246.979: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.979: DIMM 1 RttWr: 2
246.979: DIMM 1 RttNom: 3
246.979: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.979: DIMM 1 RttNom: 3
246.979: DIMM 1 RttWr: 2
246.979: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.979: DIMM 1 RttWr: 2
246.979: DIMM 0 RttNom: 3
246.979: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.979: DIMM 1 RttNom: 3
246.979: DIMM 0 RttWr: 2
246.979: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.979: DIMM 1 RttWr: 2
246.979: DIMM 0 RttNom: 3
246.979: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.979: DIMM 1 RttNom: 3
246.979: DIMM 0 RttWr: 2
246.979: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.979: DIMM 1 RttWr: 2
246.979: AgesaHwWlPhase1: training nibble 0
246.979: DIMM 0 RttNom: 3
246.979: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.979: DIMM 0 RttWr: 2
246.980: DIMM 0 RttWr: 2
246.980: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.980: DIMM 0 RttWr: 2
246.980: DIMM 0 RttNom: 3
246.980: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.980: DIMM 0 RttNom: 3
246.980: DIMM 0 RttWr: 2
246.980: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.980: DIMM 0 RttWr: 2
246.980: DIMM 1 RttNom: 3
246.980: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.980: DIMM 0 RttNom: 3
246.980: DIMM 1 RttWr: 2
246.980: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.980: DIMM 0 RttWr: 2
246.980: DIMM 1 RttNom: 3
246.980: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.980: DIMM 0 RttNom: 3
246.980: DIMM 1 RttWr: 2
246.980: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.980: DIMM 0 RttWr: 2
246.980: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
246.980: <09>Lane 00 initial seed: 0041
246.980: <09>Lane 01 initial seed: 0041
246.980: <09>Lane 02 initial seed: 0041
246.980: <09>Lane 03 initial seed: 0041
246.980: <09>Lane 04 initial seed: 0041
246.980: <09>Lane 05 initial seed: 0041
246.980: <09>Lane 06 initial seed: 0041
246.980: <09>Lane 07 initial seed: 0041
246.980: <09>Lane 08 initial seed: 0041
246.980: <09>Lane 00 nibble 0 raw readback: 004a
246.980: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004a
246.980: <09>Lane 00 nibble 0 adjusted value (post nibble): 004a
246.980: <09>Lane 01 nibble 0 raw readback: 0046
246.980: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0046
246.980: <09>Lane 01 nibble 0 adjusted value (post nibble): 0046
246.980: <09>Lane 02 nibble 0 raw readback: 0044
246.980: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0044
246.980: <09>Lane 02 nibble 0 adjusted value (post nibble): 0044
246.980: <09>Lane 03 nibble 0 raw readback: 0041
246.980: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0041
246.980: <09>Lane 03 nibble 0 adjusted value (post nibble): 0041
246.980: <09>Lane 04 nibble 0 raw readback: 0039
246.980: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
246.980: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
246.980: <09>Lane 05 nibble 0 raw readback: 003c
246.980: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003c
246.980: <09>Lane 05 nibble 0 adjusted value (post nibble): 003c
246.980: <09>Lane 06 nibble 0 raw readback: 003f
246.980: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003f
246.980: <09>Lane 06 nibble 0 adjusted value (post nibble): 003f
246.980: <09>Lane 07 nibble 0 raw readback: 0040
246.980: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0040
246.980: <09>Lane 07 nibble 0 adjusted value (post nibble): 0040
246.980: <09>Lane 08 nibble 0 raw readback: 003b
246.980: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003b
246.980: <09>Lane 08 nibble 0 adjusted value (post nibble): 003b
246.980: AgesaHwWlPhase1: training nibble 1
246.980: DIMM 0 RttNom: 3
246.980: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.980: DIMM 0 RttWr: 2
246.980: DIMM 0 RttWr: 2
246.980: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.980: DIMM 0 RttWr: 2
246.980: DIMM 0 RttNom: 3
246.980: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.980: DIMM 0 RttNom: 3
246.980: DIMM 0 RttWr: 2
246.980: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.980: DIMM 0 RttWr: 2
246.981: DIMM 1 RttNom: 3
246.981: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.981: DIMM 0 RttNom: 3
246.981: DIMM 1 RttWr: 2
246.981: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.981: DIMM 0 RttWr: 2
246.981: DIMM 1 RttNom: 3
246.981: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.981: DIMM 0 RttNom: 3
246.981: DIMM 1 RttWr: 2
246.981: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.981: DIMM 0 RttWr: 2
246.981: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
246.981: <09>Lane 00 initial seed: 0041
246.981: <09>Lane 01 initial seed: 0041
246.981: <09>Lane 02 initial seed: 0041
246.981: <09>Lane 03 initial seed: 0041
246.981: <09>Lane 04 initial seed: 0041
246.981: <09>Lane 05 initial seed: 0041
246.981: <09>Lane 06 initial seed: 0041
246.981: <09>Lane 07 initial seed: 0041
246.981: <09>Lane 08 initial seed: 0041
246.981: <09>Lane 00 nibble 1 raw readback: 004a
246.981: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004a
246.981: <09>Lane 00 nibble 1 adjusted value (post nibble): 0045
246.981: <09>Lane 01 nibble 1 raw readback: 0047
246.981: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0047
246.981: <09>Lane 01 nibble 1 adjusted value (post nibble): 0044
246.981: <09>Lane 02 nibble 1 raw readback: 0044
246.981: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0044
246.981: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
246.981: <09>Lane 03 nibble 1 raw readback: 0042
246.981: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0042
246.981: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
246.981: <09>Lane 04 nibble 1 raw readback: 0039
246.981: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
246.981: <09>Lane 04 nibble 1 adjusted value (post nibble): 003d
246.981: <09>Lane 05 nibble 1 raw readback: 003c
246.981: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
246.981: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
246.981: <09>Lane 06 nibble 1 raw readback: 003f
246.981: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
246.981: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
246.981: <09>Lane 07 nibble 1 raw readback: 0040
246.981: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0040
246.981: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
246.981: <09>Lane 08 nibble 1 raw readback: 003b
246.981: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003b
246.981: <09>Lane 08 nibble 1 adjusted value (post nibble): 003e
246.981: <09>original critical gross delay: 0
246.981: <09>new critical gross delay: 0
246.981: DIMM 0 RttNom: 3
246.981: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.981: DIMM 0 RttNom: 3
246.981: DIMM 0 RttWr: 2
246.981: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.981: DIMM 0 RttWr: 2
246.981: DIMM 0 RttNom: 3
246.981: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.981: DIMM 0 RttNom: 3
246.981: DIMM 0 RttWr: 2
246.981: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.982: DIMM 0 RttWr: 2
246.981: DIMM 1 RttNom: 3
246.981: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.982: DIMM 0 RttNom: 3
246.982: DIMM 1 RttWr: 2
246.982: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.982: DIMM 0 RttWr: 2
246.982: DIMM 1 RttNom: 3
246.982: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.982: DIMM 0 RttNom: 3
246.982: DIMM 1 RttWr: 2
246.982: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.982: DIMM 0 RttWr: 2
246.982: AgesaHwWlPhase1: training nibble 0
246.982: DIMM 1 RttNom: 3
246.982: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.982: DIMM 1 RttWr: 2
246.982: DIMM 1 RttWr: 2
246.982: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.982: DIMM 1 RttWr: 2
246.982: DIMM 1 RttNom: 3
246.982: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.982: DIMM 1 RttNom: 3
246.982: DIMM 1 RttWr: 2
246.982: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.982: DIMM 1 RttWr: 2
246.982: DIMM 0 RttNom: 3
246.982: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.982: DIMM 1 RttNom: 3
246.982: DIMM 0 RttWr: 2
246.982: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.982: DIMM 1 RttWr: 2
246.982: DIMM 0 RttNom: 3
246.982: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.982: DIMM 1 RttNom: 3
246.982: DIMM 0 RttWr: 2
246.982: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.982: DIMM 1 RttWr: 2
246.982: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
246.982: <09>Lane 00 initial seed: 0041
246.982: <09>Lane 01 initial seed: 0041
246.982: <09>Lane 02 initial seed: 0041
246.982: <09>Lane 03 initial seed: 0041
246.982: <09>Lane 04 initial seed: 0041
246.982: <09>Lane 05 initial seed: 0041
246.982: <09>Lane 06 initial seed: 0041
246.982: <09>Lane 07 initial seed: 0041
246.982: <09>Lane 08 initial seed: 0041
246.982: <09>Lane 00 nibble 0 raw readback: 003f
246.982: <09>Lane 00 nibble 0 adjusted value (pre nibble): 003f
246.982: <09>Lane 00 nibble 0 adjusted value (post nibble): 003f
246.982: <09>Lane 01 nibble 0 raw readback: 003c
246.982: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003c
246.982: <09>Lane 01 nibble 0 adjusted value (post nibble): 003c
246.982: <09>Lane 02 nibble 0 raw readback: 0038
246.982: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0038
246.982: <09>Lane 02 nibble 0 adjusted value (post nibble): 0038
246.982: <09>Lane 03 nibble 0 raw readback: 0036
246.982: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0036
246.982: <09>Lane 03 nibble 0 adjusted value (post nibble): 0036
246.982: <09>Lane 04 nibble 0 raw readback: 002d
246.982: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002d
246.982: <09>Lane 04 nibble 0 adjusted value (post nibble): 002d
246.982: <09>Lane 05 nibble 0 raw readback: 0030
246.982: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0030
246.982: <09>Lane 05 nibble 0 adjusted value (post nibble): 0030
246.982: <09>Lane 06 nibble 0 raw readback: 0033
246.982: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0033
246.982: <09>Lane 06 nibble 0 adjusted value (post nibble): 0033
246.982: <09>Lane 07 nibble 0 raw readback: 0036
246.982: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0036
246.982: <09>Lane 07 nibble 0 adjusted value (post nibble): 0036
246.982: <09>Lane 08 nibble 0 raw readback: 0030
246.982: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0030
246.982: <09>Lane 08 nibble 0 adjusted value (post nibble): 0030
246.983: AgesaHwWlPhase1: training nibble 1
246.983: DIMM 1 RttNom: 3
246.983: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.983: DIMM 1 RttWr: 2
246.983: DIMM 1 RttWr: 2
246.983: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.983: DIMM 1 RttWr: 2
246.983: DIMM 1 RttNom: 3
246.983: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.983: DIMM 1 RttNom: 3
246.983: DIMM 1 RttWr: 2
246.983: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.983: DIMM 1 RttWr: 2
246.983: DIMM 0 RttNom: 3
246.983: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.983: DIMM 1 RttNom: 3
246.983: DIMM 0 RttWr: 2
246.983: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.983: DIMM 1 RttWr: 2
246.983: DIMM 0 RttNom: 3
246.983: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.983: DIMM 1 RttNom: 3
246.983: DIMM 0 RttWr: 2
246.983: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.983: DIMM 1 RttWr: 2
246.983: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
246.983: <09>Lane 00 initial seed: 0041
246.983: <09>Lane 01 initial seed: 0041
246.983: <09>Lane 02 initial seed: 0041
246.983: <09>Lane 03 initial seed: 0041
246.983: <09>Lane 04 initial seed: 0041
246.983: <09>Lane 05 initial seed: 0041
246.983: <09>Lane 06 initial seed: 0041
246.983: <09>Lane 07 initial seed: 0041
246.983: <09>Lane 08 initial seed: 0041
246.983: <09>Lane 00 nibble 1 raw readback: 003e
246.983: <09>Lane 00 nibble 1 adjusted value (pre nibble): 003e
246.983: <09>Lane 00 nibble 1 adjusted value (post nibble): 003f
246.983: <09>Lane 01 nibble 1 raw readback: 003c
246.983: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003c
246.983: <09>Lane 01 nibble 1 adjusted value (post nibble): 003e
246.983: <09>Lane 02 nibble 1 raw readback: 0038
246.983: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0038
246.983: <09>Lane 02 nibble 1 adjusted value (post nibble): 003c
246.983: <09>Lane 03 nibble 1 raw readback: 0037
246.983: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0037
246.983: <09>Lane 03 nibble 1 adjusted value (post nibble): 003c
246.983: <09>Lane 04 nibble 1 raw readback: 002d
246.983: <09>Lane 04 nibble 1 adjusted value (pre nibble): 002d
246.983: <09>Lane 04 nibble 1 adjusted value (post nibble): 0037
246.983: <09>Lane 05 nibble 1 raw readback: 0030
246.983: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0030
246.983: <09>Lane 05 nibble 1 adjusted value (post nibble): 0038
246.983: <09>Lane 06 nibble 1 raw readback: 0033
246.983: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0033
246.983: <09>Lane 06 nibble 1 adjusted value (post nibble): 003a
246.983: <09>Lane 07 nibble 1 raw readback: 0035
246.983: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0035
246.983: <09>Lane 07 nibble 1 adjusted value (post nibble): 003b
246.983: <09>Lane 08 nibble 1 raw readback: 002f
246.983: <09>Lane 08 nibble 1 adjusted value (pre nibble): 002f
246.983: <09>Lane 08 nibble 1 adjusted value (post nibble): 0038
246.983: <09>original critical gross delay: 0
246.983: <09>new critical gross delay: 0
246.984: DIMM 1 RttNom: 3
246.984: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.984: DIMM 1 RttNom: 3
246.984: DIMM 1 RttWr: 2
246.984: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.984: DIMM 1 RttWr: 2
246.984: DIMM 1 RttNom: 3
246.984: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.984: DIMM 1 RttNom: 3
246.984: DIMM 1 RttWr: 2
246.984: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.984: DIMM 1 RttWr: 2
246.984: DIMM 0 RttNom: 3
246.984: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.984: DIMM 1 RttNom: 3
246.984: DIMM 0 RttWr: 2
246.984: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.984: DIMM 1 RttWr: 2
246.984: DIMM 0 RttNom: 3
246.984: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.984: DIMM 1 RttNom: 3
246.984: DIMM 0 RttWr: 2
246.984: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.984: DIMM 1 RttWr: 2
246.984: activate_spd_rom() for node 03
246.984: enable_spd_node3()
246.984: AgesaHwWlPhase1: training nibble 0
246.984: DIMM 0 RttNom: 3
246.984: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.984: DIMM 0 RttWr: 2
246.984: DIMM 0 RttWr: 2
246.984: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.984: DIMM 0 RttWr: 2
246.984: DIMM 0 RttNom: 3
246.984: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.984: DIMM 0 RttNom: 3
246.984: DIMM 0 RttWr: 2
246.984: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.984: DIMM 0 RttWr: 2
246.984: DIMM 1 RttNom: 3
246.984: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.984: DIMM 0 RttNom: 3
246.984: DIMM 1 RttWr: 2
246.984: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.984: DIMM 0 RttWr: 2
246.984: DIMM 1 RttNom: 3
246.984: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.984: DIMM 0 RttNom: 3
246.984: DIMM 1 RttWr: 2
246.984: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.984: DIMM 0 RttWr: 2
246.985: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
246.985: <09>Lane 00 initial seed: 0041
246.985: <09>Lane 01 initial seed: 0041
246.985: <09>Lane 02 initial seed: 0041
246.985: <09>Lane 03 initial seed: 0041
246.985: <09>Lane 04 initial seed: 0041
246.985: <09>Lane 05 initial seed: 0041
246.985: <09>Lane 06 initial seed: 0041
246.985: <09>Lane 07 initial seed: 0041
246.985: <09>Lane 08 initial seed: 0041
246.985: <09>Lane 00 nibble 0 raw readback: 0043
246.985: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0043
246.985: <09>Lane 00 nibble 0 adjusted value (post nibble): 0043
246.985: <09>Lane 01 nibble 0 raw readback: 003e
246.985: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003e
246.985: <09>Lane 01 nibble 0 adjusted value (post nibble): 003e
246.985: <09>Lane 02 nibble 0 raw readback: 003b
246.985: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003b
246.985: <09>Lane 02 nibble 0 adjusted value (post nibble): 003b
246.985: <09>Lane 03 nibble 0 raw readback: 003b
246.985: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
246.985: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
246.985: <09>Lane 04 nibble 0 raw readback: 003a
246.985: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
246.985: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
246.985: <09>Lane 05 nibble 0 raw readback: 003c
246.985: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003c
246.985: <09>Lane 05 nibble 0 adjusted value (post nibble): 003c
246.985: <09>Lane 06 nibble 0 raw readback: 003e
246.985: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003e
246.985: <09>Lane 06 nibble 0 adjusted value (post nibble): 003e
246.985: <09>Lane 07 nibble 0 raw readback: 0041
246.985: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0041
246.985: <09>Lane 07 nibble 0 adjusted value (post nibble): 0041
246.985: <09>Lane 08 nibble 0 raw readback: 0036
246.985: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
246.985: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
246.985: AgesaHwWlPhase1: training nibble 1
246.985: DIMM 0 RttNom: 3
246.985: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.985: DIMM 0 RttWr: 2
246.985: DIMM 0 RttWr: 2
246.985: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.985: DIMM 0 RttWr: 2
246.985: DIMM 0 RttNom: 3
246.985: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.985: DIMM 0 RttNom: 3
246.985: DIMM 0 RttWr: 2
246.985: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.985: DIMM 0 RttWr: 2
246.985: DIMM 1 RttNom: 3
246.985: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.985: DIMM 0 RttNom: 3
246.985: DIMM 1 RttWr: 2
246.985: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.985: DIMM 0 RttWr: 2
246.985: DIMM 1 RttNom: 3
246.985: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.985: DIMM 0 RttNom: 3
246.985: DIMM 1 RttWr: 2
246.985: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.985: DIMM 0 RttWr: 2
246.985: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
246.985: <09>Lane 00 initial seed: 0041
246.985: <09>Lane 01 initial seed: 0041
246.985: <09>Lane 02 initial seed: 0041
246.985: <09>Lane 03 initial seed: 0041
246.986: <09>Lane 04 initial seed: 0041
246.986: <09>Lane 05 initial seed: 0041
246.986: <09>Lane 06 initial seed: 0041
246.986: <09>Lane 07 initial seed: 0041
246.986: <09>Lane 08 initial seed: 0041
246.986: <09>Lane 00 nibble 1 raw readback: 0044
246.986: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0044
246.986: <09>Lane 00 nibble 1 adjusted value (post nibble): 0042
246.986: <09>Lane 01 nibble 1 raw readback: 003f
246.986: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003f
246.986: <09>Lane 01 nibble 1 adjusted value (post nibble): 0040
246.986: <09>Lane 02 nibble 1 raw readback: 003c
246.986: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003c
246.986: <09>Lane 02 nibble 1 adjusted value (post nibble): 003e
246.986: <09>Lane 03 nibble 1 raw readback: 003a
246.986: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003a
246.986: <09>Lane 03 nibble 1 adjusted value (post nibble): 003d
246.986: <09>Lane 04 nibble 1 raw readback: 0038
246.986: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
246.986: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
246.986: <09>Lane 05 nibble 1 raw readback: 003b
246.986: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003b
246.986: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
246.986: <09>Lane 06 nibble 1 raw readback: 003e
246.986: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003e
246.986: <09>Lane 06 nibble 1 adjusted value (post nibble): 003f
246.986: <09>Lane 07 nibble 1 raw readback: 0041
246.986: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
246.986: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
246.986: <09>Lane 08 nibble 1 raw readback: 0037
246.986: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
246.986: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
246.986: <09>original critical gross delay: 0
246.986: <09>new critical gross delay: 0
246.986: DIMM 0 RttNom: 3
246.986: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.986: DIMM 0 RttNom: 3
246.986: DIMM 0 RttWr: 2
246.986: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.986: DIMM 0 RttWr: 2
246.986: DIMM 0 RttNom: 3
246.986: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.986: DIMM 0 RttNom: 3
246.986: DIMM 0 RttWr: 2
246.986: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.986: DIMM 0 RttWr: 2
246.986: DIMM 1 RttNom: 3
246.986: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.986: DIMM 0 RttNom: 3
246.986: DIMM 1 RttWr: 2
246.986: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.986: DIMM 0 RttWr: 2
246.986: DIMM 1 RttNom: 3
246.986: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.986: DIMM 0 RttNom: 3
246.986: DIMM 1 RttWr: 2
246.986: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.986: DIMM 0 RttWr: 2
246.986: AgesaHwWlPhase1: training nibble 0
246.986: DIMM 1 RttNom: 3
246.986: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.986: DIMM 1 RttWr: 2
246.987: DIMM 1 RttWr: 2
246.986: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.987: DIMM 1 RttWr: 2
246.987: DIMM 1 RttNom: 3
246.987: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.987: DIMM 1 RttNom: 3
246.987: DIMM 1 RttWr: 2
246.987: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.987: DIMM 1 RttWr: 2
246.987: DIMM 0 RttNom: 3
246.987: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.987: DIMM 1 RttNom: 3
246.987: DIMM 0 RttWr: 2
246.987: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.987: DIMM 1 RttWr: 2
246.987: DIMM 0 RttNom: 3
246.987: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.987: DIMM 1 RttNom: 3
246.987: DIMM 0 RttWr: 2
246.987: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.987: DIMM 1 RttWr: 2
246.987: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
246.987: <09>Lane 00 initial seed: 0041
246.987: <09>Lane 01 initial seed: 0041
246.987: <09>Lane 02 initial seed: 0041
246.987: <09>Lane 03 initial seed: 0041
246.987: <09>Lane 04 initial seed: 0041
246.987: <09>Lane 05 initial seed: 0041
246.987: <09>Lane 06 initial seed: 0041
246.987: <09>Lane 07 initial seed: 0041
246.987: <09>Lane 08 initial seed: 0041
246.987: <09>Lane 00 nibble 0 raw readback: 0042
246.987: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0042
246.987: <09>Lane 00 nibble 0 adjusted value (post nibble): 0042
246.987: <09>Lane 01 nibble 0 raw readback: 003e
246.987: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003e
246.987: <09>Lane 01 nibble 0 adjusted value (post nibble): 003e
246.987: <09>Lane 02 nibble 0 raw readback: 003c
246.987: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003c
246.987: <09>Lane 02 nibble 0 adjusted value (post nibble): 003c
246.987: <09>Lane 03 nibble 0 raw readback: 003b
246.987: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
246.987: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
246.987: <09>Lane 04 nibble 0 raw readback: 0038
246.987: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0038
246.987: <09>Lane 04 nibble 0 adjusted value (post nibble): 0038
246.987: <09>Lane 05 nibble 0 raw readback: 003b
246.987: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003b
246.987: <09>Lane 05 nibble 0 adjusted value (post nibble): 003b
246.987: <09>Lane 06 nibble 0 raw readback: 003d
246.987: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003d
246.987: <09>Lane 06 nibble 0 adjusted value (post nibble): 003d
246.987: <09>Lane 07 nibble 0 raw readback: 0040
246.987: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0040
246.987: <09>Lane 07 nibble 0 adjusted value (post nibble): 0040
246.987: <09>Lane 08 nibble 0 raw readback: 0037
246.987: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0037
246.987: <09>Lane 08 nibble 0 adjusted value (post nibble): 0037
246.987: AgesaHwWlPhase1: training nibble 1
246.987: DIMM 1 RttNom: 3
246.987: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.987: DIMM 1 RttWr: 2
246.987: DIMM 1 RttWr: 2
246.987: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.987: DIMM 1 RttWr: 2
246.987: DIMM 1 RttNom: 3
246.987: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.987: DIMM 1 RttNom: 3
246.987: DIMM 1 RttWr: 2
246.987: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.987: DIMM 1 RttWr: 2
246.987: DIMM 0 RttNom: 3
246.987: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.987: DIMM 1 RttNom: 3
246.988: DIMM 0 RttWr: 2
246.988: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.988: DIMM 1 RttWr: 2
246.988: DIMM 0 RttNom: 3
246.988: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.988: DIMM 1 RttNom: 3
246.988: DIMM 0 RttWr: 2
246.988: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.988: DIMM 1 RttWr: 2
246.988: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
246.988: <09>Lane 00 initial seed: 0041
246.988: <09>Lane 01 initial seed: 0041
246.988: <09>Lane 02 initial seed: 0041
246.988: <09>Lane 03 initial seed: 0041
246.988: <09>Lane 04 initial seed: 0041
246.988: <09>Lane 05 initial seed: 0041
246.988: <09>Lane 06 initial seed: 0041
246.988: <09>Lane 07 initial seed: 0041
246.988: <09>Lane 08 initial seed: 0041
246.988: <09>Lane 00 nibble 1 raw readback: 0043
246.988: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0043
246.988: <09>Lane 00 nibble 1 adjusted value (post nibble): 0042
246.988: <09>Lane 01 nibble 1 raw readback: 003f
246.988: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003f
246.988: <09>Lane 01 nibble 1 adjusted value (post nibble): 0040
246.988: <09>Lane 02 nibble 1 raw readback: 003c
246.988: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003c
246.988: <09>Lane 02 nibble 1 adjusted value (post nibble): 003e
246.988: <09>Lane 03 nibble 1 raw readback: 003c
246.988: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003c
246.988: <09>Lane 03 nibble 1 adjusted value (post nibble): 003e
246.988: <09>Lane 04 nibble 1 raw readback: 0038
246.988: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
246.988: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
246.988: <09>Lane 05 nibble 1 raw readback: 003b
246.988: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003b
246.988: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
246.988: <09>Lane 06 nibble 1 raw readback: 003c
246.988: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003c
246.988: <09>Lane 06 nibble 1 adjusted value (post nibble): 003e
246.988: <09>Lane 07 nibble 1 raw readback: 0040
246.988: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0040
246.988: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
246.988: <09>Lane 08 nibble 1 raw readback: 0036
246.988: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0036
246.988: <09>Lane 08 nibble 1 adjusted value (post nibble): 003b
246.988: <09>original critical gross delay: 0
246.988: <09>new critical gross delay: 0
246.988: DIMM 1 RttNom: 3
246.988: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
246.988: DIMM 1 RttNom: 3
246.988: DIMM 1 RttWr: 2
246.988: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
246.988: DIMM 1 RttWr: 2
246.988: DIMM 1 RttNom: 3
246.988: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
246.988: DIMM 1 RttNom: 3
246.988: DIMM 1 RttWr: 2
246.988: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
246.988: DIMM 1 RttWr: 2
246.988: DIMM 0 RttNom: 3
246.988: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
246.988: DIMM 1 RttNom: 3
246.988: DIMM 0 RttWr: 2
246.988: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
246.988: DIMM 1 RttWr: 2
246.989: DIMM 0 RttNom: 3
246.989: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
246.989: DIMM 1 RttNom: 3
246.989: DIMM 0 RttWr: 2
246.989: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
246.989: DIMM 1 RttWr: 2
246.989: AgesaHwWlPhase1: training nibble 0
246.989: DIMM 0 RttNom: 3
246.989: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.989: DIMM 0 RttWr: 2
246.989: DIMM 0 RttWr: 2
246.989: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.989: DIMM 0 RttWr: 2
246.989: DIMM 0 RttNom: 3
246.989: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.989: DIMM 0 RttNom: 3
246.989: DIMM 0 RttWr: 2
246.989: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.989: DIMM 0 RttWr: 2
246.989: DIMM 1 RttNom: 3
246.989: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.989: DIMM 0 RttNom: 3
246.989: DIMM 1 RttWr: 2
246.989: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.989: DIMM 0 RttWr: 2
246.989: DIMM 1 RttNom: 3
246.989: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.989: DIMM 0 RttNom: 3
246.989: DIMM 1 RttWr: 2
246.989: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.989: DIMM 0 RttWr: 2
246.989: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
246.989: <09>Lane 00 initial seed: 0041
246.989: <09>Lane 01 initial seed: 0041
246.989: <09>Lane 02 initial seed: 0041
246.989: <09>Lane 03 initial seed: 0041
246.989: <09>Lane 04 initial seed: 0041
246.989: <09>Lane 05 initial seed: 0041
246.989: <09>Lane 06 initial seed: 0041
246.989: <09>Lane 07 initial seed: 0041
246.989: <09>Lane 08 initial seed: 0041
246.989: <09>Lane 00 nibble 0 raw readback: 0044
246.989: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0044
246.989: <09>Lane 00 nibble 0 adjusted value (post nibble): 0044
246.989: <09>Lane 01 nibble 0 raw readback: 003f
246.989: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003f
246.989: <09>Lane 01 nibble 0 adjusted value (post nibble): 003f
246.989: <09>Lane 02 nibble 0 raw readback: 003d
246.989: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003d
246.989: <09>Lane 02 nibble 0 adjusted value (post nibble): 003d
246.989: <09>Lane 03 nibble 0 raw readback: 003a
246.989: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003a
246.989: <09>Lane 03 nibble 0 adjusted value (post nibble): 003a
246.989: <09>Lane 04 nibble 0 raw readback: 003a
246.989: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
246.989: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
246.989: <09>Lane 05 nibble 0 raw readback: 003d
246.989: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
246.989: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
246.989: <09>Lane 06 nibble 0 raw readback: 0040
246.989: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
246.989: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
246.989: <09>Lane 07 nibble 0 raw readback: 0043
246.989: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0043
246.989: <09>Lane 07 nibble 0 adjusted value (post nibble): 0043
246.989: <09>Lane 08 nibble 0 raw readback: 0037
246.989: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0037
246.990: <09>Lane 08 nibble 0 adjusted value (post nibble): 0037
246.989: AgesaHwWlPhase1: training nibble 1
246.990: DIMM 0 RttNom: 3
246.990: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.990: DIMM 0 RttWr: 2
246.990: DIMM 0 RttWr: 2
246.990: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.990: DIMM 0 RttWr: 2
246.990: DIMM 0 RttNom: 3
246.990: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.990: DIMM 0 RttNom: 3
246.990: DIMM 0 RttWr: 2
246.990: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.990: DIMM 0 RttWr: 2
246.990: DIMM 1 RttNom: 3
246.990: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.990: DIMM 0 RttNom: 3
246.990: DIMM 1 RttWr: 2
246.990: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.990: DIMM 0 RttWr: 2
246.990: DIMM 1 RttNom: 3
246.990: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.990: DIMM 0 RttNom: 3
246.990: DIMM 1 RttWr: 2
246.990: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.990: DIMM 0 RttWr: 2
246.990: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
246.990: <09>Lane 00 initial seed: 0041
246.990: <09>Lane 01 initial seed: 0041
246.990: <09>Lane 02 initial seed: 0041
246.990: <09>Lane 03 initial seed: 0041
246.990: <09>Lane 04 initial seed: 0041
246.990: <09>Lane 05 initial seed: 0041
246.990: <09>Lane 06 initial seed: 0041
246.990: <09>Lane 07 initial seed: 0041
246.990: <09>Lane 08 initial seed: 0041
246.990: <09>Lane 00 nibble 1 raw readback: 0044
246.990: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0044
246.990: <09>Lane 00 nibble 1 adjusted value (post nibble): 0042
246.990: <09>Lane 01 nibble 1 raw readback: 0041
246.990: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0041
246.990: <09>Lane 01 nibble 1 adjusted value (post nibble): 0041
246.990: <09>Lane 02 nibble 1 raw readback: 003d
246.990: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003d
246.990: <09>Lane 02 nibble 1 adjusted value (post nibble): 003f
246.990: <09>Lane 03 nibble 1 raw readback: 003a
246.990: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003a
246.990: <09>Lane 03 nibble 1 adjusted value (post nibble): 003d
246.990: <09>Lane 04 nibble 1 raw readback: 0039
246.990: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
246.990: <09>Lane 04 nibble 1 adjusted value (post nibble): 003d
246.990: <09>Lane 05 nibble 1 raw readback: 003c
246.990: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
246.990: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
246.990: <09>Lane 06 nibble 1 raw readback: 003f
246.990: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
246.990: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
246.990: <09>Lane 07 nibble 1 raw readback: 0042
246.990: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
246.990: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
246.990: <09>Lane 08 nibble 1 raw readback: 0038
246.990: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0038
246.990: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
246.990: <09>original critical gross delay: 0
246.990: <09>new critical gross delay: 0
246.990: DIMM 0 RttNom: 3
246.990: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.991: DIMM 0 RttNom: 3
246.991: DIMM 0 RttWr: 2
246.991: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.991: DIMM 0 RttWr: 2
246.991: DIMM 0 RttNom: 3
246.991: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.991: DIMM 0 RttNom: 3
246.991: DIMM 0 RttWr: 2
246.991: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.991: DIMM 0 RttWr: 2
246.991: DIMM 1 RttNom: 3
246.991: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.991: DIMM 0 RttNom: 3
246.991: DIMM 1 RttWr: 2
246.991: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.991: DIMM 0 RttWr: 2
246.991: DIMM 1 RttNom: 3
246.991: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.991: DIMM 0 RttNom: 3
246.991: DIMM 1 RttWr: 2
246.991: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.991: DIMM 0 RttWr: 2
246.991: AgesaHwWlPhase1: training nibble 0
246.991: DIMM 1 RttNom: 3
246.991: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.991: DIMM 1 RttWr: 2
246.991: DIMM 1 RttWr: 2
246.991: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.991: DIMM 1 RttWr: 2
246.991: DIMM 1 RttNom: 3
246.991: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.991: DIMM 1 RttNom: 3
246.991: DIMM 1 RttWr: 2
246.991: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.991: DIMM 1 RttWr: 2
246.991: DIMM 0 RttNom: 3
246.991: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.991: DIMM 1 RttNom: 3
246.991: DIMM 0 RttWr: 2
246.991: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.991: DIMM 1 RttWr: 2
246.991: DIMM 0 RttNom: 3
246.991: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.991: DIMM 1 RttNom: 3
246.991: DIMM 0 RttWr: 2
246.991: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.991: DIMM 1 RttWr: 2
246.991: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
246.991: <09>Lane 00 initial seed: 0041
246.991: <09>Lane 01 initial seed: 0041
246.991: <09>Lane 02 initial seed: 0041
246.991: <09>Lane 03 initial seed: 0041
246.991: <09>Lane 04 initial seed: 0041
246.991: <09>Lane 05 initial seed: 0041
246.991: <09>Lane 06 initial seed: 0041
246.991: <09>Lane 07 initial seed: 0041
246.991: <09>Lane 08 initial seed: 0041
246.991: <09>Lane 00 nibble 0 raw readback: 0044
246.991: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0044
246.991: <09>Lane 00 nibble 0 adjusted value (post nibble): 0044
246.991: <09>Lane 01 nibble 0 raw readback: 0040
246.991: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0040
246.991: <09>Lane 01 nibble 0 adjusted value (post nibble): 0040
246.991: <09>Lane 02 nibble 0 raw readback: 003c
246.992: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003c
246.992: <09>Lane 02 nibble 0 adjusted value (post nibble): 003c
246.992: <09>Lane 03 nibble 0 raw readback: 003a
246.992: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003a
246.992: <09>Lane 03 nibble 0 adjusted value (post nibble): 003a
246.992: <09>Lane 04 nibble 0 raw readback: 0039
246.992: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
246.992: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
246.992: <09>Lane 05 nibble 0 raw readback: 003d
246.992: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
246.992: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
246.992: <09>Lane 06 nibble 0 raw readback: 0040
246.992: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
246.992: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
246.992: <09>Lane 07 nibble 0 raw readback: 0042
246.992: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0042
246.992: <09>Lane 07 nibble 0 adjusted value (post nibble): 0042
246.992: <09>Lane 08 nibble 0 raw readback: 0039
246.992: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0039
246.992: <09>Lane 08 nibble 0 adjusted value (post nibble): 0039
246.992: AgesaHwWlPhase1: training nibble 1
246.992: DIMM 1 RttNom: 3
246.992: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.992: DIMM 1 RttWr: 2
246.992: DIMM 1 RttWr: 2
246.992: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.992: DIMM 1 RttWr: 2
246.992: DIMM 1 RttNom: 3
246.992: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.992: DIMM 1 RttNom: 3
246.992: DIMM 1 RttWr: 2
246.992: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.992: DIMM 1 RttWr: 2
246.992: DIMM 0 RttNom: 3
246.992: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.992: DIMM 1 RttNom: 3
246.992: DIMM 0 RttWr: 2
246.992: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.992: DIMM 1 RttWr: 2
246.992: DIMM 0 RttNom: 3
246.992: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.992: DIMM 1 RttNom: 3
246.992: DIMM 0 RttWr: 2
246.992: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.992: DIMM 1 RttWr: 2
246.992: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
246.992: <09>Lane 00 initial seed: 0041
246.992: <09>Lane 01 initial seed: 0041
246.992: <09>Lane 02 initial seed: 0041
246.992: <09>Lane 03 initial seed: 0041
246.992: <09>Lane 04 initial seed: 0041
246.992: <09>Lane 05 initial seed: 0041
246.992: <09>Lane 06 initial seed: 0041
246.992: <09>Lane 07 initial seed: 0041
246.992: <09>Lane 08 initial seed: 0041
246.992: <09>Lane 00 nibble 1 raw readback: 0044
246.992: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0044
246.992: <09>Lane 00 nibble 1 adjusted value (post nibble): 0042
246.992: <09>Lane 01 nibble 1 raw readback: 0041
246.992: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0041
246.992: <09>Lane 01 nibble 1 adjusted value (post nibble): 0041
246.992: <09>Lane 02 nibble 1 raw readback: 003c
246.992: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003c
246.992: <09>Lane 02 nibble 1 adjusted value (post nibble): 003e
246.992: <09>Lane 03 nibble 1 raw readback: 003b
246.992: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
246.992: <09>Lane 03 nibble 1 adjusted value (post nibble): 003e
246.992: <09>Lane 04 nibble 1 raw readback: 0038
246.992: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
246.992: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
246.992: <09>Lane 05 nibble 1 raw readback: 003c
246.992: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
246.992: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
246.992: <09>Lane 06 nibble 1 raw readback: 003f
246.992: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
246.992: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
246.993: <09>Lane 07 nibble 1 raw readback: 0042
246.993: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
246.993: <09>Lane 07 nibble 1 adjusted value (post nibble): 0041
246.993: <09>Lane 08 nibble 1 raw readback: 0037
246.993: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
246.993: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
246.993: <09>original critical gross delay: 0
246.993: <09>new critical gross delay: 0
246.993: DIMM 1 RttNom: 3
246.993: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
246.993: DIMM 1 RttNom: 3
246.993: DIMM 1 RttWr: 2
246.993: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
246.993: DIMM 1 RttWr: 2
246.993: DIMM 1 RttNom: 3
246.993: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
246.993: DIMM 1 RttNom: 3
246.993: DIMM 1 RttWr: 2
246.993: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
246.993: DIMM 1 RttWr: 2
246.993: DIMM 0 RttNom: 3
246.993: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
246.993: DIMM 1 RttNom: 3
246.993: DIMM 0 RttWr: 2
246.993: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
246.993: DIMM 1 RttWr: 2
246.993: DIMM 0 RttNom: 3
246.993: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
246.993: DIMM 1 RttNom: 3
246.993: DIMM 0 RttWr: 2
246.993: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
246.993: DIMM 1 RttWr: 2
246.995: fam15_receiver_enable_training_seed: using seed: 0054
246.996: fam15_receiver_enable_training_seed: using seed: 0054
246.996: fam15_receiver_enable_training_seed: using seed: 0054
246.997: fam15_receiver_enable_training_seed: using seed: 0054
246.997: fam15_receiver_enable_training_seed: using seed: 0054
246.997: fam15_receiver_enable_training_seed: using seed: 0054
246.997: fam15_receiver_enable_training_seed: using seed: 0054
246.997: fam15_receiver_enable_training_seed: using seed: 0054
246.997: fam15_receiver_enable_training_seed: using seed: 004d
246.997: fam15_receiver_enable_training_seed: using seed: 004d
246.997: fam15_receiver_enable_training_seed: using seed: 004d
246.997: fam15_receiver_enable_training_seed: using seed: 004d
246.997: fam15_receiver_enable_training_seed: using seed: 004d
246.997: fam15_receiver_enable_training_seed: using seed: 004d
246.997: fam15_receiver_enable_training_seed: using seed: 004d
246.997: fam15_receiver_enable_training_seed: using seed: 004d
246.998: TrainRcvrEn: Status 2205
246.998: TrainRcvrEn: ErrStatus 0
246.998: TrainRcvrEn: ErrCode 0
246.998: TrainRcvrEn: Done
246.998: 
246.998: fam15_receiver_enable_training_seed: using seed: 0045
246.998: fam15_receiver_enable_training_seed: using seed: 0045
246.999: fam15_receiver_enable_training_seed: using seed: 0045
246.999: fam15_receiver_enable_training_seed: using seed: 0045
246.999: fam15_receiver_enable_training_seed: using seed: 0045
246.999: fam15_receiver_enable_training_seed: using seed: 0045
246.999: fam15_receiver_enable_training_seed: using seed: 0045
246.999: fam15_receiver_enable_training_seed: using seed: 0045
246.999: fam15_receiver_enable_training_seed: using seed: 0040
246.999: fam15_receiver_enable_training_seed: using seed: 0040
246.999: fam15_receiver_enable_training_seed: using seed: 0040
246.999: fam15_receiver_enable_training_seed: using seed: 0040
246.999: fam15_receiver_enable_training_seed: using seed: 0040
247.000: fam15_receiver_enable_training_seed: using seed: 0040
247.000: fam15_receiver_enable_training_seed: using seed: 0040
247.000: fam15_receiver_enable_training_seed: using seed: 0040
247.000: TrainRcvrEn: Status 2005
247.000: TrainRcvrEn: ErrStatus 0
247.000: TrainRcvrEn: ErrCode 0
247.000: TrainRcvrEn: Done
247.000: 
247.000: fam15_receiver_enable_training_seed: using seed: 0054
247.000: fam15_receiver_enable_training_seed: using seed: 0054
247.000: fam15_receiver_enable_training_seed: using seed: 0054
247.000: fam15_receiver_enable_training_seed: using seed: 0054
247.000: fam15_receiver_enable_training_seed: using seed: 0054
247.001: fam15_receiver_enable_training_seed: using seed: 0054
247.001: fam15_receiver_enable_training_seed: using seed: 0054
247.001: fam15_receiver_enable_training_seed: using seed: 0054
247.001: fam15_receiver_enable_training_seed: using seed: 004d
247.001: fam15_receiver_enable_training_seed: using seed: 004d
247.001: fam15_receiver_enable_training_seed: using seed: 004d
247.001: fam15_receiver_enable_training_seed: using seed: 004d
247.001: fam15_receiver_enable_training_seed: using seed: 004d
247.001: fam15_receiver_enable_training_seed: using seed: 004d
247.001: fam15_receiver_enable_training_seed: using seed: 004d
247.001: fam15_receiver_enable_training_seed: using seed: 004d
247.002: TrainRcvrEn: Status 2005
247.002: TrainRcvrEn: ErrStatus 0
247.002: TrainRcvrEn: ErrCode 0
247.002: TrainRcvrEn: Done
247.002: 
247.002: fam15_receiver_enable_training_seed: using seed: 0045
247.002: fam15_receiver_enable_training_seed: using seed: 0045
247.002: fam15_receiver_enable_training_seed: using seed: 0045
247.002: fam15_receiver_enable_training_seed: using seed: 0045
247.002: fam15_receiver_enable_training_seed: using seed: 0045
247.002: fam15_receiver_enable_training_seed: using seed: 0045
247.002: fam15_receiver_enable_training_seed: using seed: 0045
247.002: fam15_receiver_enable_training_seed: using seed: 0045
247.002: fam15_receiver_enable_training_seed: using seed: 0040
247.003: fam15_receiver_enable_training_seed: using seed: 0040
247.003: fam15_receiver_enable_training_seed: using seed: 0040
247.003: fam15_receiver_enable_training_seed: using seed: 0040
247.003: fam15_receiver_enable_training_seed: using seed: 0040
247.003: fam15_receiver_enable_training_seed: using seed: 0040
247.003: fam15_receiver_enable_training_seed: using seed: 0040
247.003: fam15_receiver_enable_training_seed: using seed: 0040
247.003: TrainRcvrEn: Status 2005
247.003: TrainRcvrEn: ErrStatus 0
247.003: TrainRcvrEn: ErrCode 0
247.003: TrainRcvrEn: Done
247.003: 
247.003: activate_spd_rom() for node 00
247.003: enable_spd_node0()
247.004: SetTargetFreq: Start
247.004: SetTargetFreq: Node 0: New frequency code: 0006
247.004: ChangeMemClk: Start
247.004: set_2t_configuration: Start
247.004: set_2t_configuration: Done
247.004: mct_BeforePlatformSpec: Start
247.004: mct_BeforePlatformSpec: Done
247.004: mct_PlatformSpec: Start
247.005: Programmed DCT 0 timing/termination pattern 00000000 20222222
247.005: mct_PlatformSpec: Done
247.005: set_2t_configuration: Start
247.005: set_2t_configuration: Done
247.005: mct_BeforePlatformSpec: Start
247.005: mct_BeforePlatformSpec: Done
247.005: mct_PlatformSpec: Start
247.005: Programmed DCT 1 timing/termination pattern 00000000 20222222
247.005: mct_PlatformSpec: Done
247.005: ChangeMemClk: Done
247.005: phyAssistedMemFnceTraining: Start
247.005: phyAssistedMemFnceTraining: training node 0 DCT 0
247.005: phyAssistedMemFnceTraining: done training node 0 DCT 0
247.005: phyAssistedMemFnceTraining: training node 0 DCT 1
247.005: phyAssistedMemFnceTraining: done training node 0 DCT 1
247.005: phyAssistedMemFnceTraining: Done
247.005: InitPhyCompensation: DCT 0: Start
247.005: Waiting for predriver calibration to be applied...done!
247.005: InitPhyCompensation: DCT 0: Done
247.005: phyAssistedMemFnceTraining: Start
247.005: phyAssistedMemFnceTraining: training node 0 DCT 0
247.006: phyAssistedMemFnceTraining: done training node 0 DCT 0
247.006: phyAssistedMemFnceTraining: training node 0 DCT 1
247.006: phyAssistedMemFnceTraining: done training node 0 DCT 1
247.006: phyAssistedMemFnceTraining: Done
247.006: InitPhyCompensation: DCT 1: Start
247.006: Waiting for predriver calibration to be applied...done!
247.006: InitPhyCompensation: DCT 1: Done
247.006: Preparing to send DCT 0 DIMM 0 RC10: 00 (F2xA8: 02000300)
247.006: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.006: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
247.006: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.006: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
247.006: Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 02000c00)
247.006: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.007: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
247.006: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.006: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
247.007: Preparing to send DCT 1 DIMM 0 RC10: 00 (F2xA8: 02000300)
247.007: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.007: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
247.007: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.007: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
247.007: Preparing to send DCT 1 DIMM 1 RC10: 00 (F2xA8: 02000c00)
247.007: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.007: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
247.007: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.007: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
247.007: SetTargetFreq: Done
247.007: SPD2ndTiming: Start
247.007: SPD2ndTiming: Done
247.007: mct_BeforeDramInit_Prod_D: Start
247.007: mct_ProgramODT_D: Start
247.007: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
247.007: mct_ProgramODT_D: Done
247.007: mct_BeforeDramInit_Prod_D: Done
247.007: mct_DramInit_Sw_D: Start
247.007: DIMM 0 RttWr: 2
247.007: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.008: mct_SendMrsCmd: Start
247.008: mct_SendMrsCmd: Done
247.008: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
247.008: mct_SendMrsCmd: Start
247.008: mct_SendMrsCmd: Done
247.008: DIMM 0 RttNom: 3
247.008: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.008: mct_SendMrsCmd: Start
247.008: mct_SendMrsCmd: Done
247.008: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001578
247.008: mct_SendMrsCmd: Start
247.008: mct_SendMrsCmd: Done
247.008: DIMM 0 RttWr: 2
247.008: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.008: mct_SendMrsCmd: Start
247.008: mct_SendMrsCmd: Done
247.008: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
247.008: mct_SendMrsCmd: Start
247.008: mct_SendMrsCmd: Done
247.008: DIMM 0 RttNom: 3
247.008: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.008: mct_SendMrsCmd: Start
247.008: mct_SendMrsCmd: Done
247.008: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201578
247.008: mct_SendMrsCmd: Start
247.008: mct_SendMrsCmd: Done
247.008: DIMM 1 RttWr: 2
247.008: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.008: mct_SendMrsCmd: Start
247.008: mct_SendMrsCmd: Done
247.008: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
247.008: mct_SendMrsCmd: Start
247.008: mct_SendMrsCmd: Done
247.008: DIMM 1 RttNom: 3
247.008: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.008: mct_SendMrsCmd: Start
247.008: mct_SendMrsCmd: Done
247.008: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401578
247.008: mct_SendMrsCmd: Start
247.008: mct_SendMrsCmd: Done
247.008: DIMM 1 RttWr: 2
247.008: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.008: mct_SendMrsCmd: Start
247.008: mct_SendMrsCmd: Done
247.008: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
247.008: mct_SendMrsCmd: Start
247.008: mct_SendMrsCmd: Done
247.008: DIMM 1 RttNom: 3
247.008: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.008: mct_SendMrsCmd: Start
247.008: mct_SendMrsCmd: Done
247.008: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601578
247.008: mct_SendMrsCmd: Start
247.008: mct_SendMrsCmd: Done
247.008: mct_DramInit_Sw_D: Done
247.009: AgesaHwWlPhase1: training nibble 0
247.009: DIMM 0 RttNom: 3
247.009: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.009: DIMM 0 RttWr: 2
247.009: DIMM 0 RttWr: 2
247.009: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.009: DIMM 0 RttWr: 2
247.009: DIMM 0 RttNom: 3
247.009: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.009: DIMM 0 RttNom: 3
247.009: DIMM 0 RttWr: 2
247.009: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.009: DIMM 0 RttWr: 2
247.009: DIMM 1 RttNom: 3
247.009: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.009: DIMM 0 RttNom: 3
247.009: DIMM 1 RttWr: 2
247.009: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.009: DIMM 0 RttWr: 2
247.009: DIMM 1 RttNom: 3
247.009: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.009: DIMM 0 RttNom: 3
247.009: DIMM 1 RttWr: 2
247.009: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.009: DIMM 0 RttWr: 2
247.009: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.010: <09>Lane 00 scaled delay: 0047
247.009: <09>Lane 00 new seed: 0047
247.010: <09>Lane 01 scaled delay: 0047
247.010: <09>Lane 01 new seed: 0047
247.010: <09>Lane 02 scaled delay: 0047
247.010: <09>Lane 02 new seed: 0047
247.010: <09>Lane 03 scaled delay: 0047
247.010: <09>Lane 03 new seed: 0047
247.010: <09>Lane 04 scaled delay: 0047
247.010: <09>Lane 04 new seed: 0047
247.010: <09>Lane 05 scaled delay: 0047
247.010: <09>Lane 05 new seed: 0047
247.010: <09>Lane 06 scaled delay: 0047
247.010: <09>Lane 06 new seed: 0047
247.010: <09>Lane 07 scaled delay: 0047
247.010: <09>Lane 07 new seed: 0047
247.010: <09>Lane 08 scaled delay: 0047
247.010: <09>Lane 08 new seed: 0047
247.010: <09>Lane 00 nibble 0 raw readback: 0050
247.010: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0050
247.010: <09>Lane 00 nibble 0 adjusted value (post nibble): 0050
247.010: <09>Lane 01 nibble 0 raw readback: 004a
247.010: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004a
247.010: <09>Lane 01 nibble 0 adjusted value (post nibble): 004a
247.010: <09>Lane 02 nibble 0 raw readback: 0048
247.010: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0048
247.010: <09>Lane 02 nibble 0 adjusted value (post nibble): 0048
247.010: <09>Lane 03 nibble 0 raw readback: 0044
247.010: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
247.010: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
247.010: <09>Lane 04 nibble 0 raw readback: 003a
247.010: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
247.010: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
247.010: <09>Lane 05 nibble 0 raw readback: 003e
247.010: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003e
247.010: <09>Lane 05 nibble 0 adjusted value (post nibble): 003e
247.010: <09>Lane 06 nibble 0 raw readback: 0040
247.010: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
247.010: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
247.010: <09>Lane 07 nibble 0 raw readback: 0043
247.010: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0043
247.010: <09>Lane 07 nibble 0 adjusted value (post nibble): 0043
247.010: <09>Lane 08 nibble 0 raw readback: 003c
247.010: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003c
247.010: <09>Lane 08 nibble 0 adjusted value (post nibble): 003c
247.010: AgesaHwWlPhase1: training nibble 1
247.010: DIMM 0 RttNom: 3
247.010: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.010: DIMM 0 RttWr: 2
247.010: DIMM 0 RttWr: 2
247.010: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.010: DIMM 0 RttWr: 2
247.010: DIMM 0 RttNom: 3
247.010: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.010: DIMM 0 RttNom: 3
247.010: DIMM 0 RttWr: 2
247.010: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.010: DIMM 0 RttWr: 2
247.010: DIMM 1 RttNom: 3
247.011: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.011: DIMM 0 RttNom: 3
247.011: DIMM 1 RttWr: 2
247.011: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.011: DIMM 0 RttWr: 2
247.011: DIMM 1 RttNom: 3
247.011: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.011: DIMM 0 RttNom: 3
247.011: DIMM 1 RttWr: 2
247.011: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.011: DIMM 0 RttWr: 2
247.011: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.011: <09>Lane 00 new seed: 0047
247.011: <09>Lane 01 new seed: 0047
247.011: <09>Lane 02 new seed: 0047
247.011: <09>Lane 03 new seed: 0047
247.011: <09>Lane 04 new seed: 0047
247.011: <09>Lane 05 new seed: 0047
247.011: <09>Lane 06 new seed: 0047
247.011: <09>Lane 07 new seed: 0047
247.011: <09>Lane 08 new seed: 0047
247.011: <09>Lane 00 nibble 1 raw readback: 004f
247.011: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004f
247.011: <09>Lane 00 nibble 1 adjusted value (post nibble): 004b
247.011: <09>Lane 01 nibble 1 raw readback: 004a
247.011: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004a
247.011: <09>Lane 01 nibble 1 adjusted value (post nibble): 0048
247.011: <09>Lane 02 nibble 1 raw readback: 0049
247.011: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0049
247.011: <09>Lane 02 nibble 1 adjusted value (post nibble): 0048
247.011: <09>Lane 03 nibble 1 raw readback: 0046
247.011: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0046
247.011: <09>Lane 03 nibble 1 adjusted value (post nibble): 0046
247.011: <09>Lane 04 nibble 1 raw readback: 003b
247.011: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003b
247.011: <09>Lane 04 nibble 1 adjusted value (post nibble): 0041
247.011: <09>Lane 05 nibble 1 raw readback: 003f
247.011: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003f
247.011: <09>Lane 05 nibble 1 adjusted value (post nibble): 0043
247.011: <09>Lane 06 nibble 1 raw readback: 0041
247.011: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0041
247.011: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
247.011: <09>Lane 07 nibble 1 raw readback: 0043
247.011: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0043
247.011: <09>Lane 07 nibble 1 adjusted value (post nibble): 0045
247.011: <09>Lane 08 nibble 1 raw readback: 003d
247.011: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003d
247.011: <09>Lane 08 nibble 1 adjusted value (post nibble): 0042
247.011: <09>original critical gross delay: 0
247.011: <09>new critical gross delay: 0
247.011: DIMM 0 RttNom: 3
247.011: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.011: DIMM 0 RttNom: 3
247.011: DIMM 0 RttWr: 2
247.011: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.011: DIMM 0 RttWr: 2
247.011: DIMM 0 RttNom: 3
247.011: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.011: DIMM 0 RttNom: 3
247.011: DIMM 0 RttWr: 2
247.012: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.012: DIMM 0 RttWr: 2
247.012: DIMM 1 RttNom: 3
247.012: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.012: DIMM 0 RttNom: 3
247.012: DIMM 1 RttWr: 2
247.012: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.012: DIMM 0 RttWr: 2
247.012: DIMM 1 RttNom: 3
247.012: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.012: DIMM 0 RttNom: 3
247.012: DIMM 1 RttWr: 2
247.012: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.012: DIMM 0 RttWr: 2
247.012: AgesaHwWlPhase1: training nibble 0
247.012: DIMM 1 RttNom: 3
247.012: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.012: DIMM 1 RttWr: 2
247.012: DIMM 1 RttWr: 2
247.012: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.012: DIMM 1 RttWr: 2
247.012: DIMM 1 RttNom: 3
247.012: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.012: DIMM 1 RttNom: 3
247.012: DIMM 1 RttWr: 2
247.012: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.012: DIMM 1 RttWr: 2
247.012: DIMM 0 RttNom: 3
247.012: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.012: DIMM 1 RttNom: 3
247.012: DIMM 0 RttWr: 2
247.012: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.012: DIMM 1 RttWr: 2
247.012: DIMM 0 RttNom: 3
247.012: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.012: DIMM 1 RttNom: 3
247.012: DIMM 0 RttWr: 2
247.012: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.012: DIMM 1 RttWr: 2
247.012: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.012: <09>Lane 00 scaled delay: 0047
247.012: <09>Lane 00 new seed: 0047
247.012: <09>Lane 01 scaled delay: 0047
247.012: <09>Lane 01 new seed: 0047
247.012: <09>Lane 02 scaled delay: 0047
247.012: <09>Lane 02 new seed: 0047
247.012: <09>Lane 03 scaled delay: 0047
247.012: <09>Lane 03 new seed: 0047
247.012: <09>Lane 04 scaled delay: 0047
247.012: <09>Lane 04 new seed: 0047
247.012: <09>Lane 05 scaled delay: 0047
247.012: <09>Lane 05 new seed: 0047
247.012: <09>Lane 06 scaled delay: 0047
247.012: <09>Lane 06 new seed: 0047
247.012: <09>Lane 07 scaled delay: 0047
247.012: <09>Lane 07 new seed: 0047
247.012: <09>Lane 08 scaled delay: 0047
247.012: <09>Lane 08 new seed: 0047
247.012: <09>Lane 00 nibble 0 raw readback: 0046
247.012: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0046
247.012: <09>Lane 00 nibble 0 adjusted value (post nibble): 0046
247.012: <09>Lane 01 nibble 0 raw readback: 003f
247.012: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003f
247.012: <09>Lane 01 nibble 0 adjusted value (post nibble): 003f
247.012: <09>Lane 02 nibble 0 raw readback: 003e
247.013: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003e
247.012: <09>Lane 02 nibble 0 adjusted value (post nibble): 003e
247.012: <09>Lane 03 nibble 0 raw readback: 003b
247.012: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
247.012: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
247.013: <09>Lane 04 nibble 0 raw readback: 0030
247.013: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0030
247.013: <09>Lane 04 nibble 0 adjusted value (post nibble): 0030
247.013: <09>Lane 05 nibble 0 raw readback: 0035
247.013: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0035
247.013: <09>Lane 05 nibble 0 adjusted value (post nibble): 0035
247.013: <09>Lane 06 nibble 0 raw readback: 0037
247.013: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0037
247.013: <09>Lane 06 nibble 0 adjusted value (post nibble): 0037
247.013: <09>Lane 07 nibble 0 raw readback: 003a
247.013: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003a
247.013: <09>Lane 07 nibble 0 adjusted value (post nibble): 003a
247.013: <09>Lane 08 nibble 0 raw readback: 0032
247.013: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0032
247.013: <09>Lane 08 nibble 0 adjusted value (post nibble): 0032
247.013: AgesaHwWlPhase1: training nibble 1
247.013: DIMM 1 RttNom: 3
247.013: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.013: DIMM 1 RttWr: 2
247.013: DIMM 1 RttWr: 2
247.013: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.013: DIMM 1 RttWr: 2
247.013: DIMM 1 RttNom: 3
247.013: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.013: DIMM 1 RttNom: 3
247.013: DIMM 1 RttWr: 2
247.013: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.013: DIMM 1 RttWr: 2
247.013: DIMM 0 RttNom: 3
247.013: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.013: DIMM 1 RttNom: 3
247.013: DIMM 0 RttWr: 2
247.013: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.013: DIMM 1 RttWr: 2
247.013: DIMM 0 RttNom: 3
247.013: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.013: DIMM 1 RttNom: 3
247.013: DIMM 0 RttWr: 2
247.013: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.013: DIMM 1 RttWr: 2
247.013: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.013: <09>Lane 00 new seed: 0047
247.013: <09>Lane 01 new seed: 0047
247.013: <09>Lane 02 new seed: 0047
247.013: <09>Lane 03 new seed: 0047
247.013: <09>Lane 04 new seed: 0047
247.013: <09>Lane 05 new seed: 0047
247.013: <09>Lane 06 new seed: 0047
247.013: <09>Lane 07 new seed: 0047
247.013: <09>Lane 08 new seed: 0047
247.013: <09>Lane 00 nibble 1 raw readback: 0046
247.013: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0046
247.013: <09>Lane 00 nibble 1 adjusted value (post nibble): 0046
247.013: <09>Lane 01 nibble 1 raw readback: 0040
247.013: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0040
247.013: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
247.013: <09>Lane 02 nibble 1 raw readback: 003f
247.013: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003f
247.013: <09>Lane 02 nibble 1 adjusted value (post nibble): 0043
247.013: <09>Lane 03 nibble 1 raw readback: 003b
247.013: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
247.013: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
247.013: <09>Lane 04 nibble 1 raw readback: 0030
247.013: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0030
247.013: <09>Lane 04 nibble 1 adjusted value (post nibble): 003b
247.013: <09>Lane 05 nibble 1 raw readback: 0035
247.013: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0035
247.013: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
247.013: <09>Lane 06 nibble 1 raw readback: 0036
247.013: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0036
247.013: <09>Lane 06 nibble 1 adjusted value (post nibble): 003e
247.013: <09>Lane 07 nibble 1 raw readback: 003a
247.013: <09>Lane 07 nibble 1 adjusted value (pre nibble): 003a
247.013: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
247.013: <09>Lane 08 nibble 1 raw readback: 0032
247.013: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0032
247.013: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
247.013: <09>original critical gross delay: 0
247.013: <09>new critical gross delay: 0
247.014: DIMM 1 RttNom: 3
247.014: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.014: DIMM 1 RttNom: 3
247.014: DIMM 1 RttWr: 2
247.014: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.014: DIMM 1 RttWr: 2
247.014: DIMM 1 RttNom: 3
247.014: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.014: DIMM 1 RttNom: 3
247.014: DIMM 1 RttWr: 2
247.014: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.014: DIMM 1 RttWr: 2
247.014: DIMM 0 RttNom: 3
247.014: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.014: DIMM 1 RttNom: 3
247.014: DIMM 0 RttWr: 2
247.014: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.014: DIMM 1 RttWr: 2
247.014: DIMM 0 RttNom: 3
247.014: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.014: DIMM 1 RttNom: 3
247.014: DIMM 0 RttWr: 2
247.014: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.014: DIMM 1 RttWr: 2
247.014: SPD2ndTiming: Start
247.015: SPD2ndTiming: Done
247.015: mct_BeforeDramInit_Prod_D: Start
247.015: mct_ProgramODT_D: Start
247.015: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
247.015: mct_ProgramODT_D: Done
247.015: mct_BeforeDramInit_Prod_D: Done
247.015: mct_DramInit_Sw_D: Start
247.015: DIMM 0 RttWr: 2
247.015: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.015: mct_SendMrsCmd: Start
247.015: mct_SendMrsCmd: Done
247.015: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
247.015: mct_SendMrsCmd: Start
247.015: mct_SendMrsCmd: Done
247.015: DIMM 0 RttNom: 3
247.015: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.015: mct_SendMrsCmd: Start
247.015: mct_SendMrsCmd: Done
247.015: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001578
247.015: mct_SendMrsCmd: Start
247.015: mct_SendMrsCmd: Done
247.015: DIMM 0 RttWr: 2
247.015: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.015: mct_SendMrsCmd: Start
247.015: mct_SendMrsCmd: Done
247.015: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
247.015: mct_SendMrsCmd: Start
247.015: mct_SendMrsCmd: Done
247.015: DIMM 0 RttNom: 3
247.015: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.015: mct_SendMrsCmd: Start
247.015: mct_SendMrsCmd: Done
247.015: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201578
247.015: mct_SendMrsCmd: Start
247.015: mct_SendMrsCmd: Done
247.015: DIMM 1 RttWr: 2
247.015: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.015: mct_SendMrsCmd: Start
247.015: mct_SendMrsCmd: Done
247.015: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
247.015: mct_SendMrsCmd: Start
247.015: mct_SendMrsCmd: Done
247.015: DIMM 1 RttNom: 3
247.015: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.015: mct_SendMrsCmd: Start
247.015: mct_SendMrsCmd: Done
247.015: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401578
247.015: mct_SendMrsCmd: Start
247.015: mct_SendMrsCmd: Done
247.015: DIMM 1 RttWr: 2
247.015: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.015: mct_SendMrsCmd: Start
247.015: mct_SendMrsCmd: Done
247.015: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
247.015: mct_SendMrsCmd: Start
247.015: mct_SendMrsCmd: Done
247.015: DIMM 1 RttNom: 3
247.015: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.015: mct_SendMrsCmd: Start
247.015: mct_SendMrsCmd: Done
247.015: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601578
247.016: mct_SendMrsCmd: Start
247.016: mct_SendMrsCmd: Done
247.016: mct_DramInit_Sw_D: Done
247.016: AgesaHwWlPhase1: training nibble 0
247.016: DIMM 0 RttNom: 3
247.016: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.016: DIMM 0 RttWr: 2
247.016: DIMM 0 RttWr: 2
247.016: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.016: DIMM 0 RttWr: 2
247.016: DIMM 0 RttNom: 3
247.016: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.016: DIMM 0 RttNom: 3
247.016: DIMM 0 RttWr: 2
247.016: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.016: DIMM 0 RttWr: 2
247.016: DIMM 1 RttNom: 3
247.016: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.016: DIMM 0 RttNom: 3
247.016: DIMM 1 RttWr: 2
247.016: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.016: DIMM 0 RttWr: 2
247.016: DIMM 1 RttNom: 3
247.016: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.016: DIMM 0 RttNom: 3
247.016: DIMM 1 RttWr: 2
247.016: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.016: DIMM 0 RttWr: 2
247.016: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.016: <09>Lane 00 scaled delay: 0047
247.016: <09>Lane 00 new seed: 0047
247.016: <09>Lane 01 scaled delay: 0047
247.016: <09>Lane 01 new seed: 0047
247.016: <09>Lane 02 scaled delay: 0047
247.016: <09>Lane 02 new seed: 0047
247.016: <09>Lane 03 scaled delay: 0047
247.016: <09>Lane 03 new seed: 0047
247.016: <09>Lane 04 scaled delay: 0047
247.016: <09>Lane 04 new seed: 0047
247.016: <09>Lane 05 scaled delay: 0047
247.016: <09>Lane 05 new seed: 0047
247.016: <09>Lane 06 scaled delay: 0047
247.016: <09>Lane 06 new seed: 0047
247.016: <09>Lane 07 scaled delay: 0047
247.016: <09>Lane 07 new seed: 0047
247.016: <09>Lane 08 scaled delay: 0047
247.016: <09>Lane 08 new seed: 0047
247.016: <09>Lane 00 nibble 0 raw readback: 004c
247.016: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004c
247.016: <09>Lane 00 nibble 0 adjusted value (post nibble): 004c
247.016: <09>Lane 01 nibble 0 raw readback: 0049
247.016: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0049
247.016: <09>Lane 01 nibble 0 adjusted value (post nibble): 0049
247.016: <09>Lane 02 nibble 0 raw readback: 0045
247.016: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0045
247.017: <09>Lane 02 nibble 0 adjusted value (post nibble): 0045
247.017: <09>Lane 03 nibble 0 raw readback: 0042
247.017: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0042
247.017: <09>Lane 03 nibble 0 adjusted value (post nibble): 0042
247.017: <09>Lane 04 nibble 0 raw readback: 0039
247.017: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
247.017: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
247.017: <09>Lane 05 nibble 0 raw readback: 003c
247.017: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003c
247.017: <09>Lane 05 nibble 0 adjusted value (post nibble): 003c
247.017: <09>Lane 06 nibble 0 raw readback: 003e
247.017: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003e
247.017: <09>Lane 06 nibble 0 adjusted value (post nibble): 003e
247.017: <09>Lane 07 nibble 0 raw readback: 0040
247.017: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0040
247.017: <09>Lane 07 nibble 0 adjusted value (post nibble): 0040
247.017: <09>Lane 08 nibble 0 raw readback: 003a
247.017: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003a
247.017: <09>Lane 08 nibble 0 adjusted value (post nibble): 003a
247.017: AgesaHwWlPhase1: training nibble 1
247.017: DIMM 0 RttNom: 3
247.017: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.017: DIMM 0 RttWr: 2
247.017: DIMM 0 RttWr: 2
247.017: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.017: DIMM 0 RttWr: 2
247.017: DIMM 0 RttNom: 3
247.017: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.017: DIMM 0 RttNom: 3
247.017: DIMM 0 RttWr: 2
247.017: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.017: DIMM 0 RttWr: 2
247.017: DIMM 1 RttNom: 3
247.017: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.017: DIMM 0 RttNom: 3
247.017: DIMM 1 RttWr: 2
247.017: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.017: DIMM 0 RttWr: 2
247.017: DIMM 1 RttNom: 3
247.017: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.017: DIMM 0 RttNom: 3
247.017: DIMM 1 RttWr: 2
247.017: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.017: DIMM 0 RttWr: 2
247.017: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.017: <09>Lane 00 new seed: 0047
247.017: <09>Lane 01 new seed: 0047
247.017: <09>Lane 02 new seed: 0047
247.017: <09>Lane 03 new seed: 0047
247.017: <09>Lane 04 new seed: 0047
247.017: <09>Lane 05 new seed: 0047
247.017: <09>Lane 06 new seed: 0047
247.017: <09>Lane 07 new seed: 0047
247.017: <09>Lane 08 new seed: 0047
247.017: <09>Lane 00 nibble 1 raw readback: 004d
247.017: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004d
247.017: <09>Lane 00 nibble 1 adjusted value (post nibble): 004a
247.017: <09>Lane 01 nibble 1 raw readback: 0049
247.017: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0049
247.017: <09>Lane 01 nibble 1 adjusted value (post nibble): 0048
247.017: <09>Lane 02 nibble 1 raw readback: 0046
247.017: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0046
247.017: <09>Lane 02 nibble 1 adjusted value (post nibble): 0046
247.017: <09>Lane 03 nibble 1 raw readback: 0043
247.017: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0043
247.017: <09>Lane 03 nibble 1 adjusted value (post nibble): 0045
247.017: <09>Lane 04 nibble 1 raw readback: 0038
247.017: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
247.017: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
247.017: <09>Lane 05 nibble 1 raw readback: 003b
247.017: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003b
247.017: <09>Lane 05 nibble 1 adjusted value (post nibble): 0041
247.017: <09>Lane 06 nibble 1 raw readback: 003f
247.018: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
247.018: <09>Lane 06 nibble 1 adjusted value (post nibble): 0043
247.018: <09>Lane 07 nibble 1 raw readback: 0041
247.018: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
247.018: <09>Lane 07 nibble 1 adjusted value (post nibble): 0044
247.018: <09>Lane 08 nibble 1 raw readback: 003a
247.018: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003a
247.018: <09>Lane 08 nibble 1 adjusted value (post nibble): 0040
247.018: <09>original critical gross delay: 0
247.018: <09>new critical gross delay: 0
247.018: DIMM 0 RttNom: 3
247.018: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.018: DIMM 0 RttNom: 3
247.018: DIMM 0 RttWr: 2
247.018: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.018: DIMM 0 RttWr: 2
247.018: DIMM 0 RttNom: 3
247.018: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.018: DIMM 0 RttNom: 3
247.018: DIMM 0 RttWr: 2
247.018: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.018: DIMM 0 RttWr: 2
247.018: DIMM 1 RttNom: 3
247.018: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.018: DIMM 0 RttNom: 3
247.018: DIMM 1 RttWr: 2
247.018: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.018: DIMM 0 RttWr: 2
247.018: DIMM 1 RttNom: 3
247.018: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.018: DIMM 0 RttNom: 3
247.018: DIMM 1 RttWr: 2
247.018: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.018: DIMM 0 RttWr: 2
247.018: AgesaHwWlPhase1: training nibble 0
247.018: DIMM 1 RttNom: 3
247.018: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.018: DIMM 1 RttWr: 2
247.018: DIMM 1 RttWr: 2
247.018: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.018: DIMM 1 RttWr: 2
247.018: DIMM 1 RttNom: 3
247.018: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.018: DIMM 1 RttNom: 3
247.018: DIMM 1 RttWr: 2
247.018: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.018: DIMM 1 RttWr: 2
247.018: DIMM 0 RttNom: 3
247.018: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.018: DIMM 1 RttNom: 3
247.018: DIMM 0 RttWr: 2
247.018: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.018: DIMM 1 RttWr: 2
247.018: DIMM 0 RttNom: 3
247.018: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.018: DIMM 1 RttNom: 3
247.019: DIMM 0 RttWr: 2
247.019: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.019: DIMM 1 RttWr: 2
247.019: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.019: <09>Lane 00 scaled delay: 0047
247.019: <09>Lane 00 new seed: 0047
247.019: <09>Lane 01 scaled delay: 0047
247.019: <09>Lane 01 new seed: 0047
247.019: <09>Lane 02 scaled delay: 0047
247.019: <09>Lane 02 new seed: 0047
247.019: <09>Lane 03 scaled delay: 0047
247.019: <09>Lane 03 new seed: 0047
247.019: <09>Lane 04 scaled delay: 0047
247.019: <09>Lane 04 new seed: 0047
247.019: <09>Lane 05 scaled delay: 0047
247.019: <09>Lane 05 new seed: 0047
247.019: <09>Lane 06 scaled delay: 0047
247.019: <09>Lane 06 new seed: 0047
247.019: <09>Lane 07 scaled delay: 0047
247.019: <09>Lane 07 new seed: 0047
247.019: <09>Lane 08 scaled delay: 0047
247.019: <09>Lane 08 new seed: 0047
247.019: <09>Lane 00 nibble 0 raw readback: 0045
247.019: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0045
247.019: <09>Lane 00 nibble 0 adjusted value (post nibble): 0045
247.019: <09>Lane 01 nibble 0 raw readback: 0042
247.019: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0042
247.019: <09>Lane 01 nibble 0 adjusted value (post nibble): 0042
247.019: <09>Lane 02 nibble 0 raw readback: 003e
247.019: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003e
247.019: <09>Lane 02 nibble 0 adjusted value (post nibble): 003e
247.019: <09>Lane 03 nibble 0 raw readback: 003b
247.019: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
247.019: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
247.019: <09>Lane 04 nibble 0 raw readback: 0031
247.019: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0031
247.019: <09>Lane 04 nibble 0 adjusted value (post nibble): 0031
247.019: <09>Lane 05 nibble 0 raw readback: 0034
247.019: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0034
247.019: <09>Lane 05 nibble 0 adjusted value (post nibble): 0034
247.019: <09>Lane 06 nibble 0 raw readback: 0037
247.019: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0037
247.019: <09>Lane 06 nibble 0 adjusted value (post nibble): 0037
247.019: <09>Lane 07 nibble 0 raw readback: 003a
247.019: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003a
247.019: <09>Lane 07 nibble 0 adjusted value (post nibble): 003a
247.019: <09>Lane 08 nibble 0 raw readback: 0033
247.019: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0033
247.019: <09>Lane 08 nibble 0 adjusted value (post nibble): 0033
247.019: AgesaHwWlPhase1: training nibble 1
247.019: DIMM 1 RttNom: 3
247.019: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.019: DIMM 1 RttWr: 2
247.019: DIMM 1 RttWr: 2
247.019: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.019: DIMM 1 RttWr: 2
247.019: DIMM 1 RttNom: 3
247.019: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.019: DIMM 1 RttNom: 3
247.019: DIMM 1 RttWr: 2
247.019: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.019: DIMM 1 RttWr: 2
247.019: DIMM 0 RttNom: 3
247.019: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.019: DIMM 1 RttNom: 3
247.019: DIMM 0 RttWr: 2
247.019: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.019: DIMM 1 RttWr: 2
247.019: DIMM 0 RttNom: 3
247.019: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.019: DIMM 1 RttNom: 3
247.019: DIMM 0 RttWr: 2
247.019: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.019: DIMM 1 RttWr: 2
247.019: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.019: <09>Lane 00 new seed: 0047
247.019: <09>Lane 01 new seed: 0047
247.020: <09>Lane 02 new seed: 0047
247.020: <09>Lane 03 new seed: 0047
247.020: <09>Lane 04 new seed: 0047
247.020: <09>Lane 05 new seed: 0047
247.020: <09>Lane 06 new seed: 0047
247.020: <09>Lane 07 new seed: 0047
247.020: <09>Lane 08 new seed: 0047
247.020: <09>Lane 00 nibble 1 raw readback: 0045
247.020: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0045
247.020: <09>Lane 00 nibble 1 adjusted value (post nibble): 0046
247.020: <09>Lane 01 nibble 1 raw readback: 0041
247.020: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0041
247.020: <09>Lane 01 nibble 1 adjusted value (post nibble): 0044
247.020: <09>Lane 02 nibble 1 raw readback: 003f
247.020: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003f
247.020: <09>Lane 02 nibble 1 adjusted value (post nibble): 0043
247.020: <09>Lane 03 nibble 1 raw readback: 003d
247.020: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003d
247.020: <09>Lane 03 nibble 1 adjusted value (post nibble): 0042
247.020: <09>Lane 04 nibble 1 raw readback: 0031
247.020: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0031
247.020: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
247.020: <09>Lane 05 nibble 1 raw readback: 0035
247.020: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0035
247.020: <09>Lane 05 nibble 1 adjusted value (post nibble): 003e
247.020: <09>Lane 06 nibble 1 raw readback: 0037
247.020: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0037
247.020: <09>Lane 06 nibble 1 adjusted value (post nibble): 003f
247.020: <09>Lane 07 nibble 1 raw readback: 0039
247.020: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0039
247.020: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
247.020: <09>Lane 08 nibble 1 raw readback: 0034
247.020: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0034
247.020: <09>Lane 08 nibble 1 adjusted value (post nibble): 003d
247.020: <09>original critical gross delay: 0
247.020: <09>new critical gross delay: 0
247.020: DIMM 1 RttNom: 3
247.020: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.020: DIMM 1 RttNom: 3
247.020: DIMM 1 RttWr: 2
247.020: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.020: DIMM 1 RttWr: 2
247.020: DIMM 1 RttNom: 3
247.020: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.020: DIMM 1 RttNom: 3
247.020: DIMM 1 RttWr: 2
247.020: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.020: DIMM 1 RttWr: 2
247.020: DIMM 0 RttNom: 3
247.020: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.020: DIMM 1 RttNom: 3
247.020: DIMM 0 RttWr: 2
247.020: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.020: DIMM 1 RttWr: 2
247.020: DIMM 0 RttNom: 3
247.020: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.020: DIMM 1 RttNom: 3
247.020: DIMM 0 RttWr: 2
247.020: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.020: DIMM 1 RttWr: 2
247.021: SetTargetFreq: Start
247.021: SetTargetFreq: Node 0: New frequency code: 000a
247.021: ChangeMemClk: Start
247.021: set_2t_configuration: Start
247.021: set_2t_configuration: Done
247.021: mct_BeforePlatformSpec: Start
247.021: mct_BeforePlatformSpec: Done
247.021: mct_PlatformSpec: Start
247.021: Programmed DCT 0 timing/termination pattern 003a3c3a 30222222
247.021: mct_PlatformSpec: Done
247.021: set_2t_configuration: Start
247.021: set_2t_configuration: Done
247.021: mct_BeforePlatformSpec: Start
247.021: mct_BeforePlatformSpec: Done
247.021: mct_PlatformSpec: Start
247.021: Programmed DCT 1 timing/termination pattern 003a3c3a 30222222
247.021: mct_PlatformSpec: Done
247.021: ChangeMemClk: Done
247.021: phyAssistedMemFnceTraining: Start
247.021: phyAssistedMemFnceTraining: training node 0 DCT 0
247.021: phyAssistedMemFnceTraining: done training node 0 DCT 0
247.021: phyAssistedMemFnceTraining: training node 0 DCT 1
247.021: phyAssistedMemFnceTraining: done training node 0 DCT 1
247.021: phyAssistedMemFnceTraining: Done
247.021: InitPhyCompensation: DCT 0: Start
247.022: Waiting for predriver calibration to be applied...done!
247.022: InitPhyCompensation: DCT 0: Done
247.022: phyAssistedMemFnceTraining: Start
247.022: phyAssistedMemFnceTraining: training node 0 DCT 0
247.022: phyAssistedMemFnceTraining: done training node 0 DCT 0
247.022: phyAssistedMemFnceTraining: training node 0 DCT 1
247.022: phyAssistedMemFnceTraining: done training node 0 DCT 1
247.022: phyAssistedMemFnceTraining: Done
247.022: InitPhyCompensation: DCT 1: Start
247.022: Waiting for predriver calibration to be applied...done!
247.022: InitPhyCompensation: DCT 1: Done
247.022: Preparing to send DCT 0 DIMM 0 RC10: 01 (F2xA8: 02000300)
247.022: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.022: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
247.022: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.022: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
247.022: Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 02000c00)
247.022: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.022: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
247.022: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.022: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
247.022: Preparing to send DCT 1 DIMM 0 RC10: 01 (F2xA8: 02000300)
247.022: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.022: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
247.022: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.022: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
247.023: Preparing to send DCT 1 DIMM 1 RC10: 01 (F2xA8: 02000c00)
247.023: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.023: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
247.023: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.023: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
247.023: SetTargetFreq: Done
247.023: SPD2ndTiming: Start
247.023: SPD2ndTiming: Done
247.023: mct_BeforeDramInit_Prod_D: Start
247.023: mct_ProgramODT_D: Start
247.023: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
247.023: mct_ProgramODT_D: Done
247.023: mct_BeforeDramInit_Prod_D: Done
247.023: mct_DramInit_Sw_D: Start
247.023: DIMM 0 RttWr: 1
247.023: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.023: mct_SendMrsCmd: Start
247.023: mct_SendMrsCmd: Done
247.023: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
247.023: mct_SendMrsCmd: Start
247.023: mct_SendMrsCmd: Done
247.023: DIMM 0 RttNom: 3
247.023: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.023: mct_SendMrsCmd: Start
247.023: mct_SendMrsCmd: Done
247.023: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001978
247.023: mct_SendMrsCmd: Start
247.023: mct_SendMrsCmd: Done
247.023: DIMM 0 RttWr: 1
247.023: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.023: mct_SendMrsCmd: Start
247.023: mct_SendMrsCmd: Done
247.023: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
247.023: mct_SendMrsCmd: Start
247.023: mct_SendMrsCmd: Done
247.023: DIMM 0 RttNom: 3
247.023: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.023: mct_SendMrsCmd: Start
247.023: mct_SendMrsCmd: Done
247.023: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201978
247.023: mct_SendMrsCmd: Start
247.024: mct_SendMrsCmd: Done
247.023: DIMM 1 RttWr: 1
247.024: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.024: mct_SendMrsCmd: Start
247.024: mct_SendMrsCmd: Done
247.024: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
247.024: mct_SendMrsCmd: Start
247.024: mct_SendMrsCmd: Done
247.024: DIMM 1 RttNom: 3
247.024: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.024: mct_SendMrsCmd: Start
247.024: mct_SendMrsCmd: Done
247.024: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401978
247.024: mct_SendMrsCmd: Start
247.024: mct_SendMrsCmd: Done
247.024: DIMM 1 RttWr: 1
247.024: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.024: mct_SendMrsCmd: Start
247.024: mct_SendMrsCmd: Done
247.024: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
247.024: mct_SendMrsCmd: Start
247.024: mct_SendMrsCmd: Done
247.024: DIMM 1 RttNom: 3
247.024: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.024: mct_SendMrsCmd: Start
247.024: mct_SendMrsCmd: Done
247.024: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601978
247.024: mct_SendMrsCmd: Start
247.024: mct_SendMrsCmd: Done
247.024: mct_DramInit_Sw_D: Done
247.024: AgesaHwWlPhase1: training nibble 0
247.024: DIMM 0 RttNom: 3
247.024: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.024: DIMM 0 RttWr: 1
247.024: DIMM 0 RttWr: 1
247.024: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.024: DIMM 0 RttWr: 1
247.024: DIMM 0 RttNom: 3
247.024: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.024: DIMM 0 RttNom: 3
247.024: DIMM 0 RttWr: 1
247.024: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.024: DIMM 0 RttWr: 1
247.024: DIMM 1 RttNom: 3
247.024: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.024: DIMM 0 RttNom: 3
247.024: DIMM 1 RttWr: 1
247.024: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.024: DIMM 0 RttWr: 1
247.024: DIMM 1 RttNom: 3
247.024: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.024: DIMM 0 RttNom: 3
247.024: DIMM 1 RttWr: 1
247.024: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.024: DIMM 0 RttWr: 1
247.024: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.025: <09>Lane 00 scaled delay: 0059
247.025: <09>Lane 00 new seed: 0059
247.025: <09>Lane 01 scaled delay: 0055
247.025: <09>Lane 01 new seed: 0055
247.025: <09>Lane 02 scaled delay: 0055
247.025: <09>Lane 02 new seed: 0055
247.025: <09>Lane 03 scaled delay: 0052
247.025: <09>Lane 03 new seed: 0052
247.025: <09>Lane 04 scaled delay: 004b
247.025: <09>Lane 04 new seed: 004b
247.025: <09>Lane 05 scaled delay: 004e
247.025: <09>Lane 05 new seed: 004e
247.025: <09>Lane 06 scaled delay: 004f
247.025: <09>Lane 06 new seed: 004f
247.025: <09>Lane 07 scaled delay: 0051
247.025: <09>Lane 07 new seed: 0051
247.025: <09>Lane 08 scaled delay: 004d
247.025: <09>Lane 08 new seed: 004d
247.025: <09>Lane 00 nibble 0 raw readback: 0060
247.025: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0060
247.025: <09>Lane 00 nibble 0 adjusted value (post nibble): 0060
247.025: <09>Lane 01 nibble 0 raw readback: 0058
247.025: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0058
247.025: <09>Lane 01 nibble 0 adjusted value (post nibble): 0058
247.025: <09>Lane 02 nibble 0 raw readback: 0055
247.025: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0055
247.025: <09>Lane 02 nibble 0 adjusted value (post nibble): 0055
247.025: <09>Lane 03 nibble 0 raw readback: 0050
247.025: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0050
247.025: <09>Lane 03 nibble 0 adjusted value (post nibble): 0050
247.025: <09>Lane 04 nibble 0 raw readback: 0042
247.025: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0042
247.025: <09>Lane 04 nibble 0 adjusted value (post nibble): 0042
247.025: <09>Lane 05 nibble 0 raw readback: 0049
247.025: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0049
247.025: <09>Lane 05 nibble 0 adjusted value (post nibble): 0049
247.025: <09>Lane 06 nibble 0 raw readback: 004d
247.025: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004d
247.025: <09>Lane 06 nibble 0 adjusted value (post nibble): 004d
247.025: <09>Lane 07 nibble 0 raw readback: 0050
247.025: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0050
247.025: <09>Lane 07 nibble 0 adjusted value (post nibble): 0050
247.025: <09>Lane 08 nibble 0 raw readback: 0046
247.025: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0046
247.025: <09>Lane 08 nibble 0 adjusted value (post nibble): 0046
247.025: AgesaHwWlPhase1: training nibble 1
247.025: DIMM 0 RttNom: 3
247.025: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.025: DIMM 0 RttWr: 1
247.025: DIMM 0 RttWr: 1
247.025: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.025: DIMM 0 RttWr: 1
247.025: DIMM 0 RttNom: 3
247.026: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.025: DIMM 0 RttNom: 3
247.025: DIMM 0 RttWr: 1
247.026: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.025: DIMM 0 RttWr: 1
247.026: DIMM 1 RttNom: 3
247.026: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.026: DIMM 0 RttNom: 3
247.026: DIMM 1 RttWr: 1
247.026: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.026: DIMM 0 RttWr: 1
247.026: DIMM 1 RttNom: 3
247.026: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.026: DIMM 0 RttNom: 3
247.026: DIMM 1 RttWr: 1
247.026: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.026: DIMM 0 RttWr: 1
247.026: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.026: <09>Lane 00 new seed: 0059
247.026: <09>Lane 01 new seed: 0055
247.026: <09>Lane 02 new seed: 0055
247.026: <09>Lane 03 new seed: 0052
247.026: <09>Lane 04 new seed: 004b
247.026: <09>Lane 05 new seed: 004e
247.026: <09>Lane 06 new seed: 004f
247.026: <09>Lane 07 new seed: 0051
247.026: <09>Lane 08 new seed: 004d
247.026: <09>Lane 00 nibble 1 raw readback: 0060
247.026: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0060
247.026: <09>Lane 00 nibble 1 adjusted value (post nibble): 005c
247.026: <09>Lane 01 nibble 1 raw readback: 0057
247.026: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0057
247.026: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
247.026: <09>Lane 02 nibble 1 raw readback: 0056
247.026: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0056
247.026: <09>Lane 02 nibble 1 adjusted value (post nibble): 0055
247.026: <09>Lane 03 nibble 1 raw readback: 0051
247.026: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0051
247.026: <09>Lane 03 nibble 1 adjusted value (post nibble): 0051
247.026: <09>Lane 04 nibble 1 raw readback: 0042
247.026: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0042
247.026: <09>Lane 04 nibble 1 adjusted value (post nibble): 0046
247.026: <09>Lane 05 nibble 1 raw readback: 0048
247.026: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0048
247.026: <09>Lane 05 nibble 1 adjusted value (post nibble): 004b
247.026: <09>Lane 06 nibble 1 raw readback: 004d
247.026: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004d
247.026: <09>Lane 06 nibble 1 adjusted value (post nibble): 004e
247.026: <09>Lane 07 nibble 1 raw readback: 004f
247.026: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004f
247.026: <09>Lane 07 nibble 1 adjusted value (post nibble): 0050
247.026: <09>Lane 08 nibble 1 raw readback: 0045
247.026: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0045
247.026: <09>Lane 08 nibble 1 adjusted value (post nibble): 0049
247.026: <09>original critical gross delay: 0
247.026: <09>new critical gross delay: 0
247.026: DIMM 0 RttNom: 3
247.026: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.026: DIMM 0 RttNom: 3
247.026: DIMM 0 RttWr: 1
247.026: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.026: DIMM 0 RttWr: 1
247.026: DIMM 0 RttNom: 3
247.026: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.026: DIMM 0 RttNom: 3
247.026: DIMM 0 RttWr: 1
247.026: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.026: DIMM 0 RttWr: 1
247.026: DIMM 1 RttNom: 3
247.027: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.027: DIMM 0 RttNom: 3
247.027: DIMM 1 RttWr: 1
247.027: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.027: DIMM 0 RttWr: 1
247.027: DIMM 1 RttNom: 3
247.027: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.027: DIMM 0 RttNom: 3
247.027: DIMM 1 RttWr: 1
247.027: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.027: DIMM 0 RttWr: 1
247.027: AgesaHwWlPhase1: training nibble 0
247.027: DIMM 1 RttNom: 3
247.027: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.027: DIMM 1 RttWr: 1
247.027: DIMM 1 RttWr: 1
247.027: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.027: DIMM 1 RttWr: 1
247.027: DIMM 1 RttNom: 3
247.027: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.027: DIMM 1 RttNom: 3
247.027: DIMM 1 RttWr: 1
247.027: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.027: DIMM 1 RttWr: 1
247.027: DIMM 0 RttNom: 3
247.027: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.027: DIMM 1 RttNom: 3
247.027: DIMM 0 RttWr: 1
247.027: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.027: DIMM 1 RttWr: 1
247.027: DIMM 0 RttNom: 3
247.027: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.027: DIMM 1 RttNom: 3
247.027: DIMM 0 RttWr: 1
247.027: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.027: DIMM 1 RttWr: 1
247.027: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.027: <09>Lane 00 scaled delay: 0052
247.027: <09>Lane 00 new seed: 0052
247.027: <09>Lane 01 scaled delay: 004e
247.027: <09>Lane 01 new seed: 004e
247.027: <09>Lane 02 scaled delay: 004e
247.027: <09>Lane 02 new seed: 004e
247.027: <09>Lane 03 scaled delay: 004b
247.027: <09>Lane 03 new seed: 004b
247.027: <09>Lane 04 scaled delay: 0043
247.027: <09>Lane 04 new seed: 0043
247.027: <09>Lane 05 scaled delay: 0047
247.027: <09>Lane 05 new seed: 0047
247.027: <09>Lane 06 scaled delay: 0047
247.027: <09>Lane 06 new seed: 0047
247.027: <09>Lane 07 scaled delay: 004a
247.027: <09>Lane 07 new seed: 004a
247.027: <09>Lane 08 scaled delay: 0045
247.027: <09>Lane 08 new seed: 0045
247.027: <09>Lane 00 nibble 0 raw readback: 0052
247.027: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0052
247.027: <09>Lane 00 nibble 0 adjusted value (post nibble): 0052
247.027: <09>Lane 01 nibble 0 raw readback: 004b
247.027: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004b
247.027: <09>Lane 01 nibble 0 adjusted value (post nibble): 004b
247.027: <09>Lane 02 nibble 0 raw readback: 0048
247.027: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0048
247.027: <09>Lane 02 nibble 0 adjusted value (post nibble): 0048
247.027: <09>Lane 03 nibble 0 raw readback: 0044
247.027: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
247.027: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
247.027: <09>Lane 04 nibble 0 raw readback: 0037
247.027: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0037
247.027: <09>Lane 04 nibble 0 adjusted value (post nibble): 0037
247.027: <09>Lane 05 nibble 0 raw readback: 003d
247.027: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
247.027: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
247.027: <09>Lane 06 nibble 0 raw readback: 0040
247.027: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
247.027: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
247.028: <09>Lane 07 nibble 0 raw readback: 0044
247.028: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0044
247.028: <09>Lane 07 nibble 0 adjusted value (post nibble): 0044
247.028: <09>Lane 08 nibble 0 raw readback: 0038
247.028: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0038
247.028: <09>Lane 08 nibble 0 adjusted value (post nibble): 0038
247.028: AgesaHwWlPhase1: training nibble 1
247.028: DIMM 1 RttNom: 3
247.028: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.028: DIMM 1 RttWr: 1
247.028: DIMM 1 RttWr: 1
247.028: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.028: DIMM 1 RttWr: 1
247.028: DIMM 1 RttNom: 3
247.028: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.028: DIMM 1 RttNom: 3
247.028: DIMM 1 RttWr: 1
247.028: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.028: DIMM 1 RttWr: 1
247.028: DIMM 0 RttNom: 3
247.028: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.028: DIMM 1 RttNom: 3
247.028: DIMM 0 RttWr: 1
247.028: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.028: DIMM 1 RttWr: 1
247.028: DIMM 0 RttNom: 3
247.028: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.028: DIMM 1 RttNom: 3
247.028: DIMM 0 RttWr: 1
247.028: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.028: DIMM 1 RttWr: 1
247.028: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.028: <09>Lane 00 new seed: 0052
247.028: <09>Lane 01 new seed: 004e
247.028: <09>Lane 02 new seed: 004e
247.028: <09>Lane 03 new seed: 004b
247.028: <09>Lane 04 new seed: 0043
247.028: <09>Lane 05 new seed: 0047
247.028: <09>Lane 06 new seed: 0047
247.028: <09>Lane 07 new seed: 004a
247.028: <09>Lane 08 new seed: 0045
247.028: <09>Lane 00 nibble 1 raw readback: 0053
247.028: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0053
247.028: <09>Lane 00 nibble 1 adjusted value (post nibble): 0052
247.028: <09>Lane 01 nibble 1 raw readback: 004c
247.028: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004c
247.028: <09>Lane 01 nibble 1 adjusted value (post nibble): 004d
247.028: <09>Lane 02 nibble 1 raw readback: 004a
247.028: <09>Lane 02 nibble 1 adjusted value (pre nibble): 004a
247.028: <09>Lane 02 nibble 1 adjusted value (post nibble): 004c
247.028: <09>Lane 03 nibble 1 raw readback: 0044
247.028: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0044
247.028: <09>Lane 03 nibble 1 adjusted value (post nibble): 0047
247.028: <09>Lane 04 nibble 1 raw readback: 0036
247.028: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0036
247.028: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
247.028: <09>Lane 05 nibble 1 raw readback: 003d
247.028: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003d
247.028: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
247.028: <09>Lane 06 nibble 1 raw readback: 0040
247.028: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0040
247.028: <09>Lane 06 nibble 1 adjusted value (post nibble): 0043
247.028: <09>Lane 07 nibble 1 raw readback: 0045
247.028: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0045
247.028: <09>Lane 07 nibble 1 adjusted value (post nibble): 0047
247.028: <09>Lane 08 nibble 1 raw readback: 0039
247.028: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0039
247.028: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
247.028: <09>original critical gross delay: 0
247.028: <09>new critical gross delay: 0
247.028: DIMM 1 RttNom: 3
247.028: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.028: DIMM 1 RttNom: 3
247.029: DIMM 1 RttWr: 1
247.029: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.029: DIMM 1 RttWr: 1
247.029: DIMM 1 RttNom: 3
247.029: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.029: DIMM 1 RttNom: 3
247.029: DIMM 1 RttWr: 1
247.029: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.029: DIMM 1 RttWr: 1
247.029: DIMM 0 RttNom: 3
247.029: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.029: DIMM 1 RttNom: 3
247.029: DIMM 0 RttWr: 1
247.029: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.029: DIMM 1 RttWr: 1
247.029: DIMM 0 RttNom: 3
247.029: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.029: DIMM 1 RttNom: 3
247.029: DIMM 0 RttWr: 1
247.029: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.029: DIMM 1 RttWr: 1
247.029: SPD2ndTiming: Start
247.029: SPD2ndTiming: Done
247.029: mct_BeforeDramInit_Prod_D: Start
247.029: mct_ProgramODT_D: Start
247.029: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
247.029: mct_ProgramODT_D: Done
247.029: mct_BeforeDramInit_Prod_D: Done
247.029: mct_DramInit_Sw_D: Start
247.029: DIMM 0 RttWr: 1
247.029: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.029: mct_SendMrsCmd: Start
247.029: mct_SendMrsCmd: Done
247.029: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
247.029: mct_SendMrsCmd: Start
247.030: mct_SendMrsCmd: Done
247.030: DIMM 0 RttNom: 3
247.030: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.030: mct_SendMrsCmd: Start
247.030: mct_SendMrsCmd: Done
247.030: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001978
247.030: mct_SendMrsCmd: Start
247.030: mct_SendMrsCmd: Done
247.030: DIMM 0 RttWr: 1
247.030: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.030: mct_SendMrsCmd: Start
247.030: mct_SendMrsCmd: Done
247.030: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
247.030: mct_SendMrsCmd: Start
247.030: mct_SendMrsCmd: Done
247.030: DIMM 0 RttNom: 3
247.030: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.030: mct_SendMrsCmd: Start
247.030: mct_SendMrsCmd: Done
247.030: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201978
247.030: mct_SendMrsCmd: Start
247.030: mct_SendMrsCmd: Done
247.030: DIMM 1 RttWr: 1
247.030: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.030: mct_SendMrsCmd: Start
247.030: mct_SendMrsCmd: Done
247.030: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
247.030: mct_SendMrsCmd: Start
247.030: mct_SendMrsCmd: Done
247.030: DIMM 1 RttNom: 3
247.030: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.030: mct_SendMrsCmd: Start
247.030: mct_SendMrsCmd: Done
247.030: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401978
247.030: mct_SendMrsCmd: Start
247.030: mct_SendMrsCmd: Done
247.030: DIMM 1 RttWr: 1
247.030: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.030: mct_SendMrsCmd: Start
247.030: mct_SendMrsCmd: Done
247.030: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
247.030: mct_SendMrsCmd: Start
247.030: mct_SendMrsCmd: Done
247.030: DIMM 1 RttNom: 3
247.030: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.030: mct_SendMrsCmd: Start
247.030: mct_SendMrsCmd: Done
247.030: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601978
247.030: mct_SendMrsCmd: Start
247.030: mct_SendMrsCmd: Done
247.030: mct_DramInit_Sw_D: Done
247.030: AgesaHwWlPhase1: training nibble 0
247.030: DIMM 0 RttNom: 3
247.030: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.030: DIMM 0 RttWr: 1
247.030: DIMM 0 RttWr: 1
247.030: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.030: DIMM 0 RttWr: 1
247.030: DIMM 0 RttNom: 3
247.030: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.030: DIMM 0 RttNom: 3
247.030: DIMM 0 RttWr: 1
247.030: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.030: DIMM 0 RttWr: 1
247.030: DIMM 1 RttNom: 3
247.030: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.030: DIMM 0 RttNom: 3
247.030: DIMM 1 RttWr: 1
247.030: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.030: DIMM 0 RttWr: 1
247.031: DIMM 1 RttNom: 3
247.031: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.031: DIMM 0 RttNom: 3
247.031: DIMM 1 RttWr: 1
247.031: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.031: DIMM 0 RttWr: 1
247.031: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.031: <09>Lane 00 scaled delay: 0057
247.031: <09>Lane 00 new seed: 0057
247.031: <09>Lane 01 scaled delay: 0055
247.031: <09>Lane 01 new seed: 0055
247.031: <09>Lane 02 scaled delay: 0052
247.031: <09>Lane 02 new seed: 0052
247.031: <09>Lane 03 scaled delay: 0051
247.031: <09>Lane 03 new seed: 0051
247.031: <09>Lane 04 scaled delay: 0049
247.031: <09>Lane 04 new seed: 0049
247.031: <09>Lane 05 scaled delay: 004b
247.031: <09>Lane 05 new seed: 004b
247.031: <09>Lane 06 scaled delay: 004e
247.031: <09>Lane 06 new seed: 004e
247.031: <09>Lane 07 scaled delay: 004f
247.031: <09>Lane 07 new seed: 004f
247.031: <09>Lane 08 scaled delay: 004a
247.031: <09>Lane 08 new seed: 004a
247.031: <09>Lane 00 nibble 0 raw readback: 005c
247.031: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005c
247.031: <09>Lane 00 nibble 0 adjusted value (post nibble): 005c
247.031: <09>Lane 01 nibble 0 raw readback: 0059
247.031: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0059
247.031: <09>Lane 01 nibble 0 adjusted value (post nibble): 0059
247.031: <09>Lane 02 nibble 0 raw readback: 0054
247.031: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0054
247.031: <09>Lane 02 nibble 0 adjusted value (post nibble): 0054
247.031: <09>Lane 03 nibble 0 raw readback: 0050
247.031: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0050
247.031: <09>Lane 03 nibble 0 adjusted value (post nibble): 0050
247.031: <09>Lane 04 nibble 0 raw readback: 0043
247.031: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0043
247.031: <09>Lane 04 nibble 0 adjusted value (post nibble): 0043
247.031: <09>Lane 05 nibble 0 raw readback: 0046
247.031: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0046
247.031: <09>Lane 05 nibble 0 adjusted value (post nibble): 0046
247.031: <09>Lane 06 nibble 0 raw readback: 0049
247.031: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0049
247.031: <09>Lane 06 nibble 0 adjusted value (post nibble): 0049
247.031: <09>Lane 07 nibble 0 raw readback: 004d
247.031: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004d
247.031: <09>Lane 07 nibble 0 adjusted value (post nibble): 004d
247.031: <09>Lane 08 nibble 0 raw readback: 0045
247.031: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0045
247.031: <09>Lane 08 nibble 0 adjusted value (post nibble): 0045
247.031: AgesaHwWlPhase1: training nibble 1
247.031: DIMM 0 RttNom: 3
247.031: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.031: DIMM 0 RttWr: 1
247.031: DIMM 0 RttWr: 1
247.031: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.031: DIMM 0 RttWr: 1
247.031: DIMM 0 RttNom: 3
247.031: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.031: DIMM 0 RttNom: 3
247.031: DIMM 0 RttWr: 1
247.031: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.031: DIMM 0 RttWr: 1
247.032: DIMM 1 RttNom: 3
247.032: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.032: DIMM 0 RttNom: 3
247.032: DIMM 1 RttWr: 1
247.032: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.032: DIMM 0 RttWr: 1
247.032: DIMM 1 RttNom: 3
247.032: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.032: DIMM 0 RttNom: 3
247.032: DIMM 1 RttWr: 1
247.032: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.032: DIMM 0 RttWr: 1
247.032: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.032: <09>Lane 00 new seed: 0057
247.032: <09>Lane 01 new seed: 0055
247.032: <09>Lane 02 new seed: 0052
247.032: <09>Lane 03 new seed: 0051
247.032: <09>Lane 04 new seed: 0049
247.032: <09>Lane 05 new seed: 004b
247.032: <09>Lane 06 new seed: 004e
247.032: <09>Lane 07 new seed: 004f
247.032: <09>Lane 08 new seed: 004a
247.032: <09>Lane 00 nibble 1 raw readback: 005d
247.032: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005d
247.032: <09>Lane 00 nibble 1 adjusted value (post nibble): 005a
247.032: <09>Lane 01 nibble 1 raw readback: 0056
247.032: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0056
247.032: <09>Lane 01 nibble 1 adjusted value (post nibble): 0055
247.032: <09>Lane 02 nibble 1 raw readback: 0055
247.032: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0055
247.032: <09>Lane 02 nibble 1 adjusted value (post nibble): 0053
247.032: <09>Lane 03 nibble 1 raw readback: 0050
247.032: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0050
247.032: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
247.032: <09>Lane 04 nibble 1 raw readback: 0041
247.032: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0041
247.032: <09>Lane 04 nibble 1 adjusted value (post nibble): 0045
247.032: <09>Lane 05 nibble 1 raw readback: 0044
247.032: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0044
247.032: <09>Lane 05 nibble 1 adjusted value (post nibble): 0047
247.032: <09>Lane 06 nibble 1 raw readback: 004a
247.032: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004a
247.032: <09>Lane 06 nibble 1 adjusted value (post nibble): 004c
247.032: <09>Lane 07 nibble 1 raw readback: 004d
247.032: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004d
247.032: <09>Lane 07 nibble 1 adjusted value (post nibble): 004e
247.032: <09>Lane 08 nibble 1 raw readback: 0045
247.032: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0045
247.032: <09>Lane 08 nibble 1 adjusted value (post nibble): 0047
247.032: <09>original critical gross delay: 0
247.032: <09>new critical gross delay: 0
247.032: DIMM 0 RttNom: 3
247.032: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.032: DIMM 0 RttNom: 3
247.032: DIMM 0 RttWr: 1
247.032: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.032: DIMM 0 RttWr: 1
247.032: DIMM 0 RttNom: 3
247.032: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.032: DIMM 0 RttNom: 3
247.032: DIMM 0 RttWr: 1
247.032: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.032: DIMM 0 RttWr: 1
247.032: DIMM 1 RttNom: 3
247.032: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.033: DIMM 0 RttNom: 3
247.033: DIMM 1 RttWr: 1
247.033: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.033: DIMM 0 RttWr: 1
247.033: DIMM 1 RttNom: 3
247.033: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.033: DIMM 0 RttNom: 3
247.033: DIMM 1 RttWr: 1
247.033: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.033: DIMM 0 RttWr: 1
247.033: AgesaHwWlPhase1: training nibble 0
247.033: DIMM 1 RttNom: 3
247.033: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.033: DIMM 1 RttWr: 1
247.033: DIMM 1 RttWr: 1
247.033: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.033: DIMM 1 RttWr: 1
247.033: DIMM 1 RttNom: 3
247.033: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.033: DIMM 1 RttNom: 3
247.033: DIMM 1 RttWr: 1
247.033: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.033: DIMM 1 RttWr: 1
247.033: DIMM 0 RttNom: 3
247.033: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.033: DIMM 1 RttNom: 3
247.033: DIMM 0 RttWr: 1
247.033: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.033: DIMM 1 RttWr: 1
247.033: DIMM 0 RttNom: 3
247.033: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.033: DIMM 1 RttNom: 3
247.033: DIMM 0 RttWr: 1
247.033: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.033: DIMM 1 RttWr: 1
247.033: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.033: <09>Lane 00 scaled delay: 0052
247.033: <09>Lane 00 new seed: 0052
247.033: <09>Lane 01 scaled delay: 004f
247.033: <09>Lane 01 new seed: 004f
247.033: <09>Lane 02 scaled delay: 004e
247.033: <09>Lane 02 new seed: 004e
247.033: <09>Lane 03 scaled delay: 004d
247.033: <09>Lane 03 new seed: 004d
247.033: <09>Lane 04 scaled delay: 0045
247.033: <09>Lane 04 new seed: 0045
247.033: <09>Lane 05 scaled delay: 0047
247.033: <09>Lane 05 new seed: 0047
247.033: <09>Lane 06 scaled delay: 0049
247.033: <09>Lane 06 new seed: 0049
247.033: <09>Lane 07 scaled delay: 004a
247.033: <09>Lane 07 new seed: 004a
247.033: <09>Lane 08 scaled delay: 0046
247.033: <09>Lane 08 new seed: 0046
247.033: <09>Lane 00 nibble 0 raw readback: 0052
247.033: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0052
247.033: <09>Lane 00 nibble 0 adjusted value (post nibble): 0052
247.033: <09>Lane 01 nibble 0 raw readback: 004e
247.033: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004e
247.033: <09>Lane 01 nibble 0 adjusted value (post nibble): 004e
247.033: <09>Lane 02 nibble 0 raw readback: 0049
247.033: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0049
247.033: <09>Lane 02 nibble 0 adjusted value (post nibble): 0049
247.033: <09>Lane 03 nibble 0 raw readback: 0045
247.033: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0045
247.033: <09>Lane 03 nibble 0 adjusted value (post nibble): 0045
247.033: <09>Lane 04 nibble 0 raw readback: 0038
247.033: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0038
247.033: <09>Lane 04 nibble 0 adjusted value (post nibble): 0038
247.033: <09>Lane 05 nibble 0 raw readback: 003b
247.033: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003b
247.034: <09>Lane 05 nibble 0 adjusted value (post nibble): 003b
247.033: <09>Lane 06 nibble 0 raw readback: 0041
247.034: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0041
247.034: <09>Lane 06 nibble 0 adjusted value (post nibble): 0041
247.034: <09>Lane 07 nibble 0 raw readback: 0044
247.034: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0044
247.034: <09>Lane 07 nibble 0 adjusted value (post nibble): 0044
247.034: <09>Lane 08 nibble 0 raw readback: 003b
247.034: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003b
247.034: <09>Lane 08 nibble 0 adjusted value (post nibble): 003b
247.034: AgesaHwWlPhase1: training nibble 1
247.034: DIMM 1 RttNom: 3
247.034: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.034: DIMM 1 RttWr: 1
247.034: DIMM 1 RttWr: 1
247.034: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.034: DIMM 1 RttWr: 1
247.034: DIMM 1 RttNom: 3
247.034: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.034: DIMM 1 RttNom: 3
247.034: DIMM 1 RttWr: 1
247.034: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.034: DIMM 1 RttWr: 1
247.034: DIMM 0 RttNom: 3
247.034: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.034: DIMM 1 RttNom: 3
247.034: DIMM 0 RttWr: 1
247.034: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.034: DIMM 1 RttWr: 1
247.034: DIMM 0 RttNom: 3
247.034: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.034: DIMM 1 RttNom: 3
247.034: DIMM 0 RttWr: 1
247.034: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.034: DIMM 1 RttWr: 1
247.034: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.034: <09>Lane 00 new seed: 0052
247.034: <09>Lane 01 new seed: 004f
247.034: <09>Lane 02 new seed: 004e
247.034: <09>Lane 03 new seed: 004d
247.034: <09>Lane 04 new seed: 0045
247.034: <09>Lane 05 new seed: 0047
247.034: <09>Lane 06 new seed: 0049
247.034: <09>Lane 07 new seed: 004a
247.034: <09>Lane 08 new seed: 0046
247.034: <09>Lane 00 nibble 1 raw readback: 0052
247.034: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0052
247.034: <09>Lane 00 nibble 1 adjusted value (post nibble): 0052
247.034: <09>Lane 01 nibble 1 raw readback: 004d
247.034: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004d
247.034: <09>Lane 01 nibble 1 adjusted value (post nibble): 004e
247.034: <09>Lane 02 nibble 1 raw readback: 0049
247.034: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0049
247.034: <09>Lane 02 nibble 1 adjusted value (post nibble): 004b
247.034: <09>Lane 03 nibble 1 raw readback: 0047
247.034: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0047
247.034: <09>Lane 03 nibble 1 adjusted value (post nibble): 004a
247.034: <09>Lane 04 nibble 1 raw readback: 0037
247.034: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0037
247.034: <09>Lane 04 nibble 1 adjusted value (post nibble): 003e
247.034: <09>Lane 05 nibble 1 raw readback: 003d
247.034: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003d
247.034: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
247.034: <09>Lane 06 nibble 1 raw readback: 0040
247.034: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0040
247.034: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
247.034: <09>Lane 07 nibble 1 raw readback: 0043
247.034: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0043
247.034: <09>Lane 07 nibble 1 adjusted value (post nibble): 0046
247.034: <09>Lane 08 nibble 1 raw readback: 003c
247.034: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003c
247.034: <09>Lane 08 nibble 1 adjusted value (post nibble): 0041
247.034: <09>original critical gross delay: 0
247.034: <09>new critical gross delay: 0
247.035: DIMM 1 RttNom: 3
247.035: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.035: DIMM 1 RttNom: 3
247.035: DIMM 1 RttWr: 1
247.035: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.035: DIMM 1 RttWr: 1
247.035: DIMM 1 RttNom: 3
247.035: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.035: DIMM 1 RttNom: 3
247.035: DIMM 1 RttWr: 1
247.035: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.035: DIMM 1 RttWr: 1
247.035: DIMM 0 RttNom: 3
247.035: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.035: DIMM 1 RttNom: 3
247.035: DIMM 0 RttWr: 1
247.035: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.035: DIMM 1 RttWr: 1
247.035: DIMM 0 RttNom: 3
247.035: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.035: DIMM 1 RttNom: 3
247.035: DIMM 0 RttWr: 1
247.035: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.035: DIMM 1 RttWr: 1
247.035: SetTargetFreq: Start
247.035: SetTargetFreq: Node 0: New frequency code: 000e
247.035: ChangeMemClk: Start
247.035: set_2t_configuration: Start
247.035: set_2t_configuration: Done
247.035: mct_BeforePlatformSpec: Start
247.035: mct_BeforePlatformSpec: Done
247.035: mct_PlatformSpec: Start
247.035: Programmed DCT 0 timing/termination pattern 00383a38 30222222
247.035: mct_PlatformSpec: Done
247.035: set_2t_configuration: Start
247.036: set_2t_configuration: Done
247.035: mct_BeforePlatformSpec: Start
247.035: mct_BeforePlatformSpec: Done
247.036: mct_PlatformSpec: Start
247.036: Programmed DCT 1 timing/termination pattern 00383a38 30222222
247.036: mct_PlatformSpec: Done
247.036: ChangeMemClk: Done
247.036: phyAssistedMemFnceTraining: Start
247.036: phyAssistedMemFnceTraining: training node 0 DCT 0
247.036: phyAssistedMemFnceTraining: done training node 0 DCT 0
247.036: phyAssistedMemFnceTraining: training node 0 DCT 1
247.036: phyAssistedMemFnceTraining: done training node 0 DCT 1
247.036: phyAssistedMemFnceTraining: Done
247.036: InitPhyCompensation: DCT 0: Start
247.036: Waiting for predriver calibration to be applied...done!
247.036: InitPhyCompensation: DCT 0: Done
247.036: phyAssistedMemFnceTraining: Start
247.036: phyAssistedMemFnceTraining: training node 0 DCT 0
247.036: phyAssistedMemFnceTraining: done training node 0 DCT 0
247.036: phyAssistedMemFnceTraining: training node 0 DCT 1
247.036: phyAssistedMemFnceTraining: done training node 0 DCT 1
247.036: phyAssistedMemFnceTraining: Done
247.036: InitPhyCompensation: DCT 1: Start
247.036: Waiting for predriver calibration to be applied...done!
247.036: InitPhyCompensation: DCT 1: Done
247.036: Preparing to send DCT 0 DIMM 0 RC10: 02 (F2xA8: 02000300)
247.037: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.037: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
247.037: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.037: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
247.037: Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 02000c00)
247.037: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.037: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
247.037: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.037: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
247.037: Preparing to send DCT 1 DIMM 0 RC10: 02 (F2xA8: 02000300)
247.037: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.037: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
247.037: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.037: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
247.037: Preparing to send DCT 1 DIMM 1 RC10: 02 (F2xA8: 02000c00)
247.037: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.037: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
247.037: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.037: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
247.037: SetTargetFreq: Done
247.037: SPD2ndTiming: Start
247.037: SPD2ndTiming: Done
247.037: mct_BeforeDramInit_Prod_D: Start
247.037: mct_ProgramODT_D: Start
247.037: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
247.037: mct_ProgramODT_D: Done
247.037: mct_BeforeDramInit_Prod_D: Done
247.037: mct_DramInit_Sw_D: Start
247.037: DIMM 0 RttWr: 2
247.037: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.037: mct_SendMrsCmd: Start
247.037: mct_SendMrsCmd: Done
247.037: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
247.037: mct_SendMrsCmd: Start
247.037: mct_SendMrsCmd: Done
247.038: DIMM 0 RttNom: 5
247.038: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.038: mct_SendMrsCmd: Start
247.038: mct_SendMrsCmd: Done
247.038: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001b78
247.038: mct_SendMrsCmd: Start
247.038: mct_SendMrsCmd: Done
247.038: DIMM 0 RttWr: 2
247.038: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.038: mct_SendMrsCmd: Start
247.038: mct_SendMrsCmd: Done
247.038: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
247.038: mct_SendMrsCmd: Start
247.038: mct_SendMrsCmd: Done
247.038: DIMM 0 RttNom: 5
247.038: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.038: mct_SendMrsCmd: Start
247.038: mct_SendMrsCmd: Done
247.038: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201b78
247.038: mct_SendMrsCmd: Start
247.038: mct_SendMrsCmd: Done
247.038: DIMM 1 RttWr: 2
247.038: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.038: mct_SendMrsCmd: Start
247.038: mct_SendMrsCmd: Done
247.038: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
247.038: mct_SendMrsCmd: Start
247.038: mct_SendMrsCmd: Done
247.038: DIMM 1 RttNom: 5
247.038: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.038: mct_SendMrsCmd: Start
247.038: mct_SendMrsCmd: Done
247.038: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b78
247.038: mct_SendMrsCmd: Start
247.038: mct_SendMrsCmd: Done
247.038: DIMM 1 RttWr: 2
247.038: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.038: mct_SendMrsCmd: Start
247.038: mct_SendMrsCmd: Done
247.038: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
247.038: mct_SendMrsCmd: Start
247.038: mct_SendMrsCmd: Done
247.038: DIMM 1 RttNom: 5
247.038: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.038: mct_SendMrsCmd: Start
247.038: mct_SendMrsCmd: Done
247.038: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b78
247.038: mct_SendMrsCmd: Start
247.038: mct_SendMrsCmd: Done
247.038: mct_DramInit_Sw_D: Done
247.039: AgesaHwWlPhase1: training nibble 0
247.039: DIMM 0 RttNom: 5
247.039: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.039: DIMM 0 RttWr: 2
247.039: DIMM 0 RttWr: 2
247.039: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.039: DIMM 0 RttWr: 2
247.039: DIMM 0 RttNom: 5
247.039: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.039: DIMM 0 RttNom: 5
247.039: DIMM 0 RttWr: 2
247.039: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.039: DIMM 0 RttWr: 2
247.039: DIMM 1 RttNom: 5
247.039: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.039: DIMM 0 RttNom: 5
247.039: DIMM 1 RttWr: 2
247.039: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.039: DIMM 0 RttWr: 2
247.039: DIMM 1 RttNom: 5
247.039: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.039: DIMM 0 RttNom: 5
247.039: DIMM 1 RttWr: 2
247.039: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.039: DIMM 0 RttWr: 2
247.039: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.039: <09>Lane 00 scaled delay: 006b
247.039: <09>Lane 00 new seed: 006b
247.039: <09>Lane 01 scaled delay: 0063
247.039: <09>Lane 01 new seed: 0063
247.039: <09>Lane 02 scaled delay: 0062
247.039: <09>Lane 02 new seed: 0062
247.039: <09>Lane 03 scaled delay: 005d
247.039: <09>Lane 03 new seed: 005d
247.039: <09>Lane 04 scaled delay: 004f
247.039: <09>Lane 04 new seed: 004f
247.039: <09>Lane 05 scaled delay: 0055
247.039: <09>Lane 05 new seed: 0055
247.039: <09>Lane 06 scaled delay: 0059
247.039: <09>Lane 06 new seed: 0059
247.039: <09>Lane 07 scaled delay: 005c
247.039: <09>Lane 07 new seed: 005c
247.039: <09>Lane 08 scaled delay: 0053
247.039: <09>Lane 08 new seed: 0053
247.039: <09>Lane 00 nibble 0 raw readback: 0030
247.039: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0070
247.040: <09>Lane 00 nibble 0 adjusted value (post nibble): 0070
247.039: <09>Lane 01 nibble 0 raw readback: 0026
247.039: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0066
247.039: <09>Lane 01 nibble 0 adjusted value (post nibble): 0066
247.040: <09>Lane 02 nibble 0 raw readback: 0022
247.040: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0062
247.040: <09>Lane 02 nibble 0 adjusted value (post nibble): 0062
247.040: <09>Lane 03 nibble 0 raw readback: 005c
247.040: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005c
247.040: <09>Lane 03 nibble 0 adjusted value (post nibble): 005c
247.040: <09>Lane 04 nibble 0 raw readback: 004a
247.040: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004a
247.040: <09>Lane 04 nibble 0 adjusted value (post nibble): 004a
247.040: <09>Lane 05 nibble 0 raw readback: 0053
247.040: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0053
247.040: <09>Lane 05 nibble 0 adjusted value (post nibble): 0053
247.040: <09>Lane 06 nibble 0 raw readback: 0058
247.040: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0058
247.040: <09>Lane 06 nibble 0 adjusted value (post nibble): 0058
247.040: <09>Lane 07 nibble 0 raw readback: 005b
247.040: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005b
247.040: <09>Lane 07 nibble 0 adjusted value (post nibble): 005b
247.040: <09>Lane 08 nibble 0 raw readback: 004f
247.040: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004f
247.040: <09>Lane 08 nibble 0 adjusted value (post nibble): 004f
247.040: AgesaHwWlPhase1: training nibble 1
247.040: DIMM 0 RttNom: 5
247.040: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.040: DIMM 0 RttWr: 2
247.040: DIMM 0 RttWr: 2
247.040: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.040: DIMM 0 RttWr: 2
247.040: DIMM 0 RttNom: 5
247.040: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.040: DIMM 0 RttNom: 5
247.040: DIMM 0 RttWr: 2
247.040: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.040: DIMM 0 RttWr: 2
247.040: DIMM 1 RttNom: 5
247.040: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.040: DIMM 0 RttNom: 5
247.040: DIMM 1 RttWr: 2
247.040: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.040: DIMM 0 RttWr: 2
247.040: DIMM 1 RttNom: 5
247.040: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.040: DIMM 0 RttNom: 5
247.040: DIMM 1 RttWr: 2
247.040: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.040: DIMM 0 RttWr: 2
247.040: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.040: <09>Lane 00 new seed: 006b
247.040: <09>Lane 01 new seed: 0063
247.040: <09>Lane 02 new seed: 0062
247.040: <09>Lane 03 new seed: 005d
247.040: <09>Lane 04 new seed: 004f
247.040: <09>Lane 05 new seed: 0055
247.040: <09>Lane 06 new seed: 0059
247.040: <09>Lane 07 new seed: 005c
247.040: <09>Lane 08 new seed: 0053
247.040: <09>Lane 00 nibble 1 raw readback: 002f
247.040: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006f
247.040: <09>Lane 00 nibble 1 adjusted value (post nibble): 006d
247.040: <09>Lane 01 nibble 1 raw readback: 0026
247.040: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0066
247.040: <09>Lane 01 nibble 1 adjusted value (post nibble): 0064
247.040: <09>Lane 02 nibble 1 raw readback: 0022
247.040: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0062
247.040: <09>Lane 02 nibble 1 adjusted value (post nibble): 0062
247.040: <09>Lane 03 nibble 1 raw readback: 005d
247.040: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005d
247.040: <09>Lane 03 nibble 1 adjusted value (post nibble): 005d
247.040: <09>Lane 04 nibble 1 raw readback: 004a
247.040: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004a
247.040: <09>Lane 04 nibble 1 adjusted value (post nibble): 004c
247.040: <09>Lane 05 nibble 1 raw readback: 0053
247.040: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0053
247.041: <09>Lane 05 nibble 1 adjusted value (post nibble): 0054
247.041: <09>Lane 06 nibble 1 raw readback: 0058
247.041: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0058
247.041: <09>Lane 06 nibble 1 adjusted value (post nibble): 0058
247.041: <09>Lane 07 nibble 1 raw readback: 005a
247.041: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005a
247.041: <09>Lane 07 nibble 1 adjusted value (post nibble): 005b
247.041: <09>Lane 08 nibble 1 raw readback: 004e
247.041: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004e
247.041: <09>Lane 08 nibble 1 adjusted value (post nibble): 0050
247.041: <09>original critical gross delay: 0
247.041: <09>new critical gross delay: 0
247.041: DIMM 0 RttNom: 5
247.041: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.041: DIMM 0 RttNom: 5
247.041: DIMM 0 RttWr: 2
247.041: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.041: DIMM 0 RttWr: 2
247.041: DIMM 0 RttNom: 5
247.041: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.041: DIMM 0 RttNom: 5
247.041: DIMM 0 RttWr: 2
247.041: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.041: DIMM 0 RttWr: 2
247.041: DIMM 1 RttNom: 5
247.041: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.041: DIMM 0 RttNom: 5
247.041: DIMM 1 RttWr: 2
247.041: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.041: DIMM 0 RttWr: 2
247.041: DIMM 1 RttNom: 5
247.041: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.041: DIMM 0 RttNom: 5
247.041: DIMM 1 RttWr: 2
247.041: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.041: DIMM 0 RttWr: 2
247.041: AgesaHwWlPhase1: training nibble 0
247.041: DIMM 1 RttNom: 5
247.041: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.041: DIMM 1 RttWr: 2
247.041: DIMM 1 RttWr: 2
247.041: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.041: DIMM 1 RttWr: 2
247.041: DIMM 1 RttNom: 5
247.041: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.041: DIMM 1 RttNom: 5
247.041: DIMM 1 RttWr: 2
247.041: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.041: DIMM 1 RttWr: 2
247.041: DIMM 0 RttNom: 5
247.041: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.041: DIMM 1 RttNom: 5
247.041: DIMM 0 RttWr: 2
247.041: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.041: DIMM 1 RttWr: 2
247.041: DIMM 0 RttNom: 5
247.041: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.041: DIMM 1 RttNom: 5
247.041: DIMM 0 RttWr: 2
247.041: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.041: DIMM 1 RttWr: 2
247.042: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.041: <09>Lane 00 scaled delay: 005e
247.041: <09>Lane 00 new seed: 005e
247.042: <09>Lane 01 scaled delay: 0058
247.042: <09>Lane 01 new seed: 0058
247.042: <09>Lane 02 scaled delay: 0057
247.042: <09>Lane 02 new seed: 0057
247.042: <09>Lane 03 scaled delay: 0050
247.042: <09>Lane 03 new seed: 0050
247.042: <09>Lane 04 scaled delay: 0043
247.042: <09>Lane 04 new seed: 0043
247.042: <09>Lane 05 scaled delay: 004a
247.042: <09>Lane 05 new seed: 004a
247.042: <09>Lane 06 scaled delay: 004b
247.042: <09>Lane 06 new seed: 004b
247.042: <09>Lane 07 scaled delay: 0050
247.042: <09>Lane 07 new seed: 0050
247.042: <09>Lane 08 scaled delay: 0046
247.042: <09>Lane 08 new seed: 0046
247.042: <09>Lane 00 nibble 0 raw readback: 0060
247.042: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0060
247.042: <09>Lane 00 nibble 0 adjusted value (post nibble): 0060
247.042: <09>Lane 01 nibble 0 raw readback: 0056
247.042: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0056
247.042: <09>Lane 01 nibble 0 adjusted value (post nibble): 0056
247.042: <09>Lane 02 nibble 0 raw readback: 0051
247.042: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0051
247.042: <09>Lane 02 nibble 0 adjusted value (post nibble): 0051
247.042: <09>Lane 03 nibble 0 raw readback: 004d
247.042: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004d
247.042: <09>Lane 03 nibble 0 adjusted value (post nibble): 004d
247.042: <09>Lane 04 nibble 0 raw readback: 003c
247.042: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003c
247.042: <09>Lane 04 nibble 0 adjusted value (post nibble): 003c
247.042: <09>Lane 05 nibble 0 raw readback: 0045
247.042: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0045
247.042: <09>Lane 05 nibble 0 adjusted value (post nibble): 0045
247.042: <09>Lane 06 nibble 0 raw readback: 0047
247.042: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0047
247.042: <09>Lane 06 nibble 0 adjusted value (post nibble): 0047
247.042: <09>Lane 07 nibble 0 raw readback: 004c
247.042: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004c
247.042: <09>Lane 07 nibble 0 adjusted value (post nibble): 004c
247.042: <09>Lane 08 nibble 0 raw readback: 003f
247.042: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003f
247.042: <09>Lane 08 nibble 0 adjusted value (post nibble): 003f
247.042: AgesaHwWlPhase1: training nibble 1
247.042: DIMM 1 RttNom: 5
247.042: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.042: DIMM 1 RttWr: 2
247.042: DIMM 1 RttWr: 2
247.042: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.042: DIMM 1 RttWr: 2
247.042: DIMM 1 RttNom: 5
247.042: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.042: DIMM 1 RttNom: 5
247.042: DIMM 1 RttWr: 2
247.042: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.042: DIMM 1 RttWr: 2
247.042: DIMM 0 RttNom: 5
247.042: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.042: DIMM 1 RttNom: 5
247.042: DIMM 0 RttWr: 2
247.042: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.042: DIMM 1 RttWr: 2
247.042: DIMM 0 RttNom: 5
247.042: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.042: DIMM 1 RttNom: 5
247.042: DIMM 0 RttWr: 2
247.042: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.042: DIMM 1 RttWr: 2
247.042: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.042: <09>Lane 00 new seed: 005e
247.042: <09>Lane 01 new seed: 0058
247.042: <09>Lane 02 new seed: 0057
247.042: <09>Lane 03 new seed: 0050
247.042: <09>Lane 04 new seed: 0043
247.042: <09>Lane 05 new seed: 004a
247.042: <09>Lane 06 new seed: 004b
247.043: <09>Lane 07 new seed: 0050
247.043: <09>Lane 08 new seed: 0046
247.043: <09>Lane 00 nibble 1 raw readback: 005f
247.043: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005f
247.043: <09>Lane 00 nibble 1 adjusted value (post nibble): 005e
247.043: <09>Lane 01 nibble 1 raw readback: 0057
247.043: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0057
247.043: <09>Lane 01 nibble 1 adjusted value (post nibble): 0057
247.043: <09>Lane 02 nibble 1 raw readback: 0054
247.043: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0054
247.043: <09>Lane 02 nibble 1 adjusted value (post nibble): 0055
247.043: <09>Lane 03 nibble 1 raw readback: 004e
247.043: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004e
247.043: <09>Lane 03 nibble 1 adjusted value (post nibble): 004f
247.043: <09>Lane 04 nibble 1 raw readback: 003c
247.043: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003c
247.043: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
247.043: <09>Lane 05 nibble 1 raw readback: 0044
247.043: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0044
247.043: <09>Lane 05 nibble 1 adjusted value (post nibble): 0047
247.043: <09>Lane 06 nibble 1 raw readback: 0049
247.043: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0049
247.043: <09>Lane 06 nibble 1 adjusted value (post nibble): 004a
247.043: <09>Lane 07 nibble 1 raw readback: 004d
247.043: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004d
247.043: <09>Lane 07 nibble 1 adjusted value (post nibble): 004e
247.043: <09>Lane 08 nibble 1 raw readback: 003f
247.043: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003f
247.043: <09>Lane 08 nibble 1 adjusted value (post nibble): 0042
247.043: <09>original critical gross delay: 0
247.043: <09>new critical gross delay: 0
247.043: DIMM 1 RttNom: 5
247.043: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.043: DIMM 1 RttNom: 5
247.043: DIMM 1 RttWr: 2
247.043: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.043: DIMM 1 RttWr: 2
247.043: DIMM 1 RttNom: 5
247.043: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.043: DIMM 1 RttNom: 5
247.043: DIMM 1 RttWr: 2
247.043: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.043: DIMM 1 RttWr: 2
247.043: DIMM 0 RttNom: 5
247.043: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.043: DIMM 1 RttNom: 5
247.043: DIMM 0 RttWr: 2
247.043: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.043: DIMM 1 RttWr: 2
247.043: DIMM 0 RttNom: 5
247.043: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.043: DIMM 1 RttNom: 5
247.043: DIMM 0 RttWr: 2
247.043: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.043: DIMM 1 RttWr: 2
247.043: SPD2ndTiming: Start
247.044: SPD2ndTiming: Done
247.044: mct_BeforeDramInit_Prod_D: Start
247.044: mct_ProgramODT_D: Start
247.044: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
247.044: mct_ProgramODT_D: Done
247.044: mct_BeforeDramInit_Prod_D: Done
247.044: mct_DramInit_Sw_D: Start
247.044: DIMM 0 RttWr: 2
247.044: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.044: mct_SendMrsCmd: Start
247.044: mct_SendMrsCmd: Done
247.044: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
247.044: mct_SendMrsCmd: Start
247.044: mct_SendMrsCmd: Done
247.044: DIMM 0 RttNom: 5
247.044: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.044: mct_SendMrsCmd: Start
247.044: mct_SendMrsCmd: Done
247.044: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001b78
247.044: mct_SendMrsCmd: Start
247.044: mct_SendMrsCmd: Done
247.044: DIMM 0 RttWr: 2
247.044: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.044: mct_SendMrsCmd: Start
247.044: mct_SendMrsCmd: Done
247.044: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
247.044: mct_SendMrsCmd: Start
247.044: mct_SendMrsCmd: Done
247.044: DIMM 0 RttNom: 5
247.044: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.044: mct_SendMrsCmd: Start
247.044: mct_SendMrsCmd: Done
247.044: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201b78
247.044: mct_SendMrsCmd: Start
247.044: mct_SendMrsCmd: Done
247.044: DIMM 1 RttWr: 2
247.044: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.044: mct_SendMrsCmd: Start
247.044: mct_SendMrsCmd: Done
247.044: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
247.044: mct_SendMrsCmd: Start
247.044: mct_SendMrsCmd: Done
247.045: DIMM 1 RttNom: 5
247.045: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.045: mct_SendMrsCmd: Start
247.045: mct_SendMrsCmd: Done
247.045: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401b78
247.045: mct_SendMrsCmd: Start
247.045: mct_SendMrsCmd: Done
247.045: DIMM 1 RttWr: 2
247.045: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.045: mct_SendMrsCmd: Start
247.045: mct_SendMrsCmd: Done
247.045: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
247.045: mct_SendMrsCmd: Start
247.045: mct_SendMrsCmd: Done
247.045: DIMM 1 RttNom: 5
247.045: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.045: mct_SendMrsCmd: Start
247.045: mct_SendMrsCmd: Done
247.045: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601b78
247.045: mct_SendMrsCmd: Start
247.045: mct_SendMrsCmd: Done
247.045: mct_DramInit_Sw_D: Done
247.045: AgesaHwWlPhase1: training nibble 0
247.045: DIMM 0 RttNom: 5
247.045: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.045: DIMM 0 RttWr: 2
247.045: DIMM 0 RttWr: 2
247.045: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.045: DIMM 0 RttWr: 2
247.045: DIMM 0 RttNom: 5
247.045: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.045: DIMM 0 RttNom: 5
247.045: DIMM 0 RttWr: 2
247.045: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.045: DIMM 0 RttWr: 2
247.045: DIMM 1 RttNom: 5
247.045: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.045: DIMM 0 RttNom: 5
247.045: DIMM 1 RttWr: 2
247.045: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.045: DIMM 0 RttWr: 2
247.045: DIMM 1 RttNom: 5
247.045: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.045: DIMM 0 RttNom: 5
247.045: DIMM 1 RttWr: 2
247.045: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.045: DIMM 0 RttWr: 2
247.045: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.045: <09>Lane 00 scaled delay: 0068
247.045: <09>Lane 00 new seed: 0068
247.045: <09>Lane 01 scaled delay: 0062
247.045: <09>Lane 01 new seed: 0062
247.045: <09>Lane 02 scaled delay: 005f
247.045: <09>Lane 02 new seed: 005f
247.045: <09>Lane 03 scaled delay: 005c
247.045: <09>Lane 03 new seed: 005c
247.045: <09>Lane 04 scaled delay: 004e
247.045: <09>Lane 04 new seed: 004e
247.045: <09>Lane 05 scaled delay: 0050
247.045: <09>Lane 05 new seed: 0050
247.045: <09>Lane 06 scaled delay: 0057
247.045: <09>Lane 06 new seed: 0057
247.045: <09>Lane 07 scaled delay: 0059
247.046: <09>Lane 07 new seed: 0059
247.045: <09>Lane 08 scaled delay: 0050
247.046: <09>Lane 08 new seed: 0050
247.046: <09>Lane 00 nibble 0 raw readback: 002b
247.046: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006b
247.046: <09>Lane 00 nibble 0 adjusted value (post nibble): 006b
247.046: <09>Lane 01 nibble 0 raw readback: 0025
247.046: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0065
247.046: <09>Lane 01 nibble 0 adjusted value (post nibble): 0065
247.046: <09>Lane 02 nibble 0 raw readback: 0060
247.046: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0060
247.046: <09>Lane 02 nibble 0 adjusted value (post nibble): 0060
247.046: <09>Lane 03 nibble 0 raw readback: 005b
247.046: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005b
247.046: <09>Lane 03 nibble 0 adjusted value (post nibble): 005b
247.046: <09>Lane 04 nibble 0 raw readback: 004a
247.046: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004a
247.046: <09>Lane 04 nibble 0 adjusted value (post nibble): 004a
247.046: <09>Lane 05 nibble 0 raw readback: 0050
247.046: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0050
247.046: <09>Lane 05 nibble 0 adjusted value (post nibble): 0050
247.046: <09>Lane 06 nibble 0 raw readback: 0053
247.046: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0053
247.046: <09>Lane 06 nibble 0 adjusted value (post nibble): 0053
247.046: <09>Lane 07 nibble 0 raw readback: 0058
247.046: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0058
247.046: <09>Lane 07 nibble 0 adjusted value (post nibble): 0058
247.046: <09>Lane 08 nibble 0 raw readback: 004d
247.046: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004d
247.046: <09>Lane 08 nibble 0 adjusted value (post nibble): 004d
247.046: AgesaHwWlPhase1: training nibble 1
247.046: DIMM 0 RttNom: 5
247.046: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.046: DIMM 0 RttWr: 2
247.046: DIMM 0 RttWr: 2
247.046: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.046: DIMM 0 RttWr: 2
247.046: DIMM 0 RttNom: 5
247.046: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.046: DIMM 0 RttNom: 5
247.046: DIMM 0 RttWr: 2
247.046: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.046: DIMM 0 RttWr: 2
247.046: DIMM 1 RttNom: 5
247.046: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.046: DIMM 0 RttNom: 5
247.046: DIMM 1 RttWr: 2
247.046: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.046: DIMM 0 RttWr: 2
247.046: DIMM 1 RttNom: 5
247.046: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.046: DIMM 0 RttNom: 5
247.046: DIMM 1 RttWr: 2
247.046: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.046: DIMM 0 RttWr: 2
247.046: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.046: <09>Lane 00 new seed: 0068
247.046: <09>Lane 01 new seed: 0062
247.046: <09>Lane 02 new seed: 005f
247.046: <09>Lane 03 new seed: 005c
247.046: <09>Lane 04 new seed: 004e
247.046: <09>Lane 05 new seed: 0050
247.046: <09>Lane 06 new seed: 0057
247.046: <09>Lane 07 new seed: 0059
247.046: <09>Lane 08 new seed: 0050
247.047: <09>Lane 00 nibble 1 raw readback: 002c
247.047: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006c
247.047: <09>Lane 00 nibble 1 adjusted value (post nibble): 006a
247.047: <09>Lane 01 nibble 1 raw readback: 0024
247.047: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0064
247.047: <09>Lane 01 nibble 1 adjusted value (post nibble): 0063
247.047: <09>Lane 02 nibble 1 raw readback: 0061
247.047: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0061
247.047: <09>Lane 02 nibble 1 adjusted value (post nibble): 0060
247.047: <09>Lane 03 nibble 1 raw readback: 005b
247.047: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005b
247.047: <09>Lane 03 nibble 1 adjusted value (post nibble): 005b
247.047: <09>Lane 04 nibble 1 raw readback: 0049
247.047: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0049
247.047: <09>Lane 04 nibble 1 adjusted value (post nibble): 004b
247.047: <09>Lane 05 nibble 1 raw readback: 004f
247.047: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004f
247.047: <09>Lane 05 nibble 1 adjusted value (post nibble): 004f
247.047: <09>Lane 06 nibble 1 raw readback: 0055
247.047: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0055
247.047: <09>Lane 06 nibble 1 adjusted value (post nibble): 0056
247.047: <09>Lane 07 nibble 1 raw readback: 0059
247.047: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0059
247.047: <09>Lane 07 nibble 1 adjusted value (post nibble): 0059
247.047: <09>Lane 08 nibble 1 raw readback: 004d
247.047: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004d
247.047: <09>Lane 08 nibble 1 adjusted value (post nibble): 004e
247.047: <09>original critical gross delay: 0
247.047: <09>new critical gross delay: 0
247.047: DIMM 0 RttNom: 5
247.047: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.047: DIMM 0 RttNom: 5
247.047: DIMM 0 RttWr: 2
247.047: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.047: DIMM 0 RttWr: 2
247.047: DIMM 0 RttNom: 5
247.047: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.047: DIMM 0 RttNom: 5
247.047: DIMM 0 RttWr: 2
247.047: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.047: DIMM 0 RttWr: 2
247.047: DIMM 1 RttNom: 5
247.047: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.047: DIMM 0 RttNom: 5
247.047: DIMM 1 RttWr: 2
247.047: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.047: DIMM 0 RttWr: 2
247.047: DIMM 1 RttNom: 5
247.047: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.047: DIMM 0 RttNom: 5
247.047: DIMM 1 RttWr: 2
247.047: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.047: DIMM 0 RttWr: 2
247.047: AgesaHwWlPhase1: training nibble 0
247.047: DIMM 1 RttNom: 5
247.047: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.047: DIMM 1 RttWr: 2
247.047: DIMM 1 RttWr: 2
247.047: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.047: DIMM 1 RttWr: 2
247.047: DIMM 1 RttNom: 5
247.047: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.047: DIMM 1 RttNom: 5
247.047: DIMM 1 RttWr: 2
247.047: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.047: DIMM 1 RttWr: 2
247.047: DIMM 0 RttNom: 5
247.047: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.047: DIMM 1 RttNom: 5
247.047: DIMM 0 RttWr: 2
247.048: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.048: DIMM 1 RttWr: 2
247.048: DIMM 0 RttNom: 5
247.048: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.048: DIMM 1 RttNom: 5
247.048: DIMM 0 RttWr: 2
247.048: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.048: DIMM 1 RttWr: 2
247.048: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.048: <09>Lane 00 scaled delay: 005e
247.048: <09>Lane 00 new seed: 005e
247.048: <09>Lane 01 scaled delay: 0059
247.048: <09>Lane 01 new seed: 0059
247.048: <09>Lane 02 scaled delay: 0055
247.048: <09>Lane 02 new seed: 0055
247.048: <09>Lane 03 scaled delay: 0054
247.048: <09>Lane 03 new seed: 0054
247.048: <09>Lane 04 scaled delay: 0045
247.048: <09>Lane 04 new seed: 0045
247.048: <09>Lane 05 scaled delay: 004a
247.048: <09>Lane 05 new seed: 004a
247.048: <09>Lane 06 scaled delay: 004d
247.048: <09>Lane 06 new seed: 004d
247.048: <09>Lane 07 scaled delay: 004f
247.048: <09>Lane 07 new seed: 004f
247.048: <09>Lane 08 scaled delay: 0049
247.048: <09>Lane 08 new seed: 0049
247.048: <09>Lane 00 nibble 0 raw readback: 005e
247.048: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005e
247.048: <09>Lane 00 nibble 0 adjusted value (post nibble): 005e
247.048: <09>Lane 01 nibble 0 raw readback: 0059
247.048: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0059
247.048: <09>Lane 01 nibble 0 adjusted value (post nibble): 0059
247.048: <09>Lane 02 nibble 0 raw readback: 0051
247.048: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0051
247.048: <09>Lane 02 nibble 0 adjusted value (post nibble): 0051
247.048: <09>Lane 03 nibble 0 raw readback: 004d
247.048: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004d
247.048: <09>Lane 03 nibble 0 adjusted value (post nibble): 004d
247.048: <09>Lane 04 nibble 0 raw readback: 003d
247.048: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003d
247.048: <09>Lane 04 nibble 0 adjusted value (post nibble): 003d
247.048: <09>Lane 05 nibble 0 raw readback: 0041
247.048: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0041
247.048: <09>Lane 05 nibble 0 adjusted value (post nibble): 0041
247.048: <09>Lane 06 nibble 0 raw readback: 0048
247.048: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0048
247.048: <09>Lane 06 nibble 0 adjusted value (post nibble): 0048
247.048: <09>Lane 07 nibble 0 raw readback: 004d
247.048: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004d
247.048: <09>Lane 07 nibble 0 adjusted value (post nibble): 004d
247.048: <09>Lane 08 nibble 0 raw readback: 0041
247.048: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0041
247.048: <09>Lane 08 nibble 0 adjusted value (post nibble): 0041
247.048: AgesaHwWlPhase1: training nibble 1
247.048: DIMM 1 RttNom: 5
247.048: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.048: DIMM 1 RttWr: 2
247.048: DIMM 1 RttWr: 2
247.048: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.048: DIMM 1 RttWr: 2
247.048: DIMM 1 RttNom: 5
247.048: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.048: DIMM 1 RttNom: 5
247.048: DIMM 1 RttWr: 2
247.048: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.048: DIMM 1 RttWr: 2
247.048: DIMM 0 RttNom: 5
247.048: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.048: DIMM 1 RttNom: 5
247.048: DIMM 0 RttWr: 2
247.048: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.048: DIMM 1 RttWr: 2
247.048: DIMM 0 RttNom: 5
247.048: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.049: DIMM 1 RttNom: 5
247.049: DIMM 0 RttWr: 2
247.049: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.049: DIMM 1 RttWr: 2
247.049: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.049: <09>Lane 00 new seed: 005e
247.049: <09>Lane 01 new seed: 0059
247.049: <09>Lane 02 new seed: 0055
247.049: <09>Lane 03 new seed: 0054
247.049: <09>Lane 04 new seed: 0045
247.049: <09>Lane 05 new seed: 004a
247.049: <09>Lane 06 new seed: 004d
247.049: <09>Lane 07 new seed: 004f
247.049: <09>Lane 08 new seed: 0049
247.049: <09>Lane 00 nibble 1 raw readback: 005e
247.049: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005e
247.049: <09>Lane 00 nibble 1 adjusted value (post nibble): 005e
247.049: <09>Lane 01 nibble 1 raw readback: 0059
247.049: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0059
247.049: <09>Lane 01 nibble 1 adjusted value (post nibble): 0059
247.049: <09>Lane 02 nibble 1 raw readback: 0052
247.049: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0052
247.049: <09>Lane 02 nibble 1 adjusted value (post nibble): 0053
247.049: <09>Lane 03 nibble 1 raw readback: 0050
247.049: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0050
247.049: <09>Lane 03 nibble 1 adjusted value (post nibble): 0052
247.049: <09>Lane 04 nibble 1 raw readback: 003d
247.049: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003d
247.049: <09>Lane 04 nibble 1 adjusted value (post nibble): 0041
247.049: <09>Lane 05 nibble 1 raw readback: 0045
247.049: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0045
247.049: <09>Lane 05 nibble 1 adjusted value (post nibble): 0047
247.049: <09>Lane 06 nibble 1 raw readback: 0048
247.049: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0048
247.049: <09>Lane 06 nibble 1 adjusted value (post nibble): 004a
247.049: <09>Lane 07 nibble 1 raw readback: 004c
247.049: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004c
247.049: <09>Lane 07 nibble 1 adjusted value (post nibble): 004d
247.049: <09>Lane 08 nibble 1 raw readback: 0042
247.049: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0042
247.049: <09>Lane 08 nibble 1 adjusted value (post nibble): 0045
247.049: <09>original critical gross delay: 0
247.049: <09>new critical gross delay: 0
247.049: DIMM 1 RttNom: 5
247.049: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.049: DIMM 1 RttNom: 5
247.049: DIMM 1 RttWr: 2
247.049: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.049: DIMM 1 RttWr: 2
247.049: DIMM 1 RttNom: 5
247.049: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.049: DIMM 1 RttNom: 5
247.049: DIMM 1 RttWr: 2
247.049: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.049: DIMM 1 RttWr: 2
247.049: DIMM 0 RttNom: 5
247.049: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.049: DIMM 1 RttNom: 5
247.049: DIMM 0 RttWr: 2
247.049: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.049: DIMM 1 RttWr: 2
247.049: DIMM 0 RttNom: 5
247.049: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.049: DIMM 1 RttNom: 5
247.049: DIMM 0 RttWr: 2
247.049: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.049: DIMM 1 RttWr: 2
247.050: SetTargetFreq: Start
247.050: SetTargetFreq: Node 0: New frequency code: 0012
247.050: ChangeMemClk: Start
247.050: set_2t_configuration: Start
247.050: set_2t_configuration: Done
247.050: mct_BeforePlatformSpec: Start
247.050: mct_BeforePlatformSpec: Done
247.050: mct_PlatformSpec: Start
247.050: Programmed DCT 0 timing/termination pattern 00353935 30222222
247.050: mct_PlatformSpec: Done
247.050: set_2t_configuration: Start
247.050: set_2t_configuration: Done
247.050: mct_BeforePlatformSpec: Start
247.050: mct_BeforePlatformSpec: Done
247.050: mct_PlatformSpec: Start
247.050: Programmed DCT 1 timing/termination pattern 00353935 30222222
247.050: mct_PlatformSpec: Done
247.050: ChangeMemClk: Done
247.050: phyAssistedMemFnceTraining: Start
247.050: phyAssistedMemFnceTraining: training node 0 DCT 0
247.050: phyAssistedMemFnceTraining: done training node 0 DCT 0
247.050: phyAssistedMemFnceTraining: training node 0 DCT 1
247.050: phyAssistedMemFnceTraining: done training node 0 DCT 1
247.050: phyAssistedMemFnceTraining: Done
247.050: InitPhyCompensation: DCT 0: Start
247.050: Waiting for predriver calibration to be applied...done!
247.050: InitPhyCompensation: DCT 0: Done
247.051: phyAssistedMemFnceTraining: Start
247.051: phyAssistedMemFnceTraining: training node 0 DCT 0
247.051: phyAssistedMemFnceTraining: done training node 0 DCT 0
247.051: phyAssistedMemFnceTraining: training node 0 DCT 1
247.051: phyAssistedMemFnceTraining: done training node 0 DCT 1
247.051: phyAssistedMemFnceTraining: Done
247.051: InitPhyCompensation: DCT 1: Start
247.051: Waiting for predriver calibration to be applied...done!
247.051: InitPhyCompensation: DCT 1: Done
247.051: Preparing to send DCT 0 DIMM 0 RC10: 03 (F2xA8: 02000300)
247.051: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.051: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
247.051: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.051: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
247.051: Preparing to send DCT 0 DIMM 1 RC10: 03 (F2xA8: 02000c00)
247.051: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.051: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
247.051: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.051: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
247.051: Preparing to send DCT 1 DIMM 0 RC10: 03 (F2xA8: 02000300)
247.051: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.051: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
247.051: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.051: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
247.051: Preparing to send DCT 1 DIMM 1 RC10: 03 (F2xA8: 02000c00)
247.051: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.051: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
247.051: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.051: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
247.051: SetTargetFreq: Done
247.051: SPD2ndTiming: Start
247.052: SPD2ndTiming: Done
247.052: mct_BeforeDramInit_Prod_D: Start
247.052: mct_ProgramODT_D: Start
247.052: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
247.052: mct_ProgramODT_D: Done
247.052: mct_BeforeDramInit_Prod_D: Done
247.052: mct_DramInit_Sw_D: Start
247.052: DIMM 0 RttWr: 1
247.052: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.052: mct_SendMrsCmd: Start
247.052: mct_SendMrsCmd: Done
247.052: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
247.052: mct_SendMrsCmd: Start
247.052: mct_SendMrsCmd: Done
247.052: DIMM 0 RttNom: 4
247.052: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.052: mct_SendMrsCmd: Start
247.052: mct_SendMrsCmd: Done
247.052: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001d78
247.052: mct_SendMrsCmd: Start
247.052: mct_SendMrsCmd: Done
247.052: DIMM 0 RttWr: 1
247.052: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.052: mct_SendMrsCmd: Start
247.052: mct_SendMrsCmd: Done
247.052: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
247.052: mct_SendMrsCmd: Start
247.052: mct_SendMrsCmd: Done
247.052: DIMM 0 RttNom: 4
247.052: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.052: mct_SendMrsCmd: Start
247.052: mct_SendMrsCmd: Done
247.052: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201d78
247.052: mct_SendMrsCmd: Start
247.053: mct_SendMrsCmd: Done
247.052: DIMM 1 RttWr: 1
247.052: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.052: mct_SendMrsCmd: Start
247.052: mct_SendMrsCmd: Done
247.052: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
247.053: mct_SendMrsCmd: Start
247.053: mct_SendMrsCmd: Done
247.053: DIMM 1 RttNom: 4
247.053: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.053: mct_SendMrsCmd: Start
247.053: mct_SendMrsCmd: Done
247.053: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401d78
247.053: mct_SendMrsCmd: Start
247.053: mct_SendMrsCmd: Done
247.053: DIMM 1 RttWr: 1
247.053: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.053: mct_SendMrsCmd: Start
247.053: mct_SendMrsCmd: Done
247.053: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
247.053: mct_SendMrsCmd: Start
247.053: mct_SendMrsCmd: Done
247.053: DIMM 1 RttNom: 4
247.053: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.053: mct_SendMrsCmd: Start
247.053: mct_SendMrsCmd: Done
247.053: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601d78
247.053: mct_SendMrsCmd: Start
247.053: mct_SendMrsCmd: Done
247.053: mct_DramInit_Sw_D: Done
247.053: AgesaHwWlPhase1: training nibble 0
247.053: DIMM 0 RttNom: 4
247.053: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.053: DIMM 0 RttWr: 1
247.053: DIMM 0 RttWr: 1
247.053: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.053: DIMM 0 RttWr: 1
247.053: DIMM 0 RttNom: 4
247.053: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.053: DIMM 0 RttNom: 4
247.053: DIMM 0 RttWr: 1
247.053: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.053: DIMM 0 RttWr: 1
247.053: DIMM 1 RttNom: 4
247.053: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.053: DIMM 0 RttNom: 4
247.053: DIMM 1 RttWr: 1
247.053: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.053: DIMM 0 RttWr: 1
247.053: DIMM 1 RttNom: 4
247.053: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.053: DIMM 0 RttNom: 4
247.053: DIMM 1 RttWr: 1
247.053: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.053: DIMM 0 RttWr: 1
247.053: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.054: <09>Lane 00 scaled delay: 007c
247.054: <09>Lane 00 new seed: 007c
247.054: <09>Lane 01 scaled delay: 0071
247.054: <09>Lane 01 new seed: 0071
247.054: <09>Lane 02 scaled delay: 006f
247.054: <09>Lane 02 new seed: 006f
247.054: <09>Lane 03 scaled delay: 0069
247.054: <09>Lane 03 new seed: 0069
247.054: <09>Lane 04 scaled delay: 0054
247.054: <09>Lane 04 new seed: 0054
247.054: <09>Lane 05 scaled delay: 005e
247.054: <09>Lane 05 new seed: 005e
247.054: <09>Lane 06 scaled delay: 0063
247.054: <09>Lane 06 new seed: 0063
247.054: <09>Lane 07 scaled delay: 0066
247.054: <09>Lane 07 new seed: 0066
247.054: <09>Lane 08 scaled delay: 0059
247.054: <09>Lane 08 new seed: 0059
247.054: <09>Lane 00 nibble 0 raw readback: 0042
247.054: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0082
247.054: <09>Lane 00 nibble 0 adjusted value (post nibble): 0082
247.054: <09>Lane 01 nibble 0 raw readback: 0036
247.054: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0076
247.054: <09>Lane 01 nibble 0 adjusted value (post nibble): 0076
247.054: <09>Lane 02 nibble 0 raw readback: 0031
247.054: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0071
247.054: <09>Lane 02 nibble 0 adjusted value (post nibble): 0071
247.054: <09>Lane 03 nibble 0 raw readback: 002a
247.054: <09>Lane 03 nibble 0 adjusted value (pre nibble): 006a
247.054: <09>Lane 03 nibble 0 adjusted value (post nibble): 006a
247.054: <09>Lane 04 nibble 0 raw readback: 0057
247.054: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0057
247.054: <09>Lane 04 nibble 0 adjusted value (post nibble): 0057
247.054: <09>Lane 05 nibble 0 raw readback: 005f
247.054: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005f
247.054: <09>Lane 05 nibble 0 adjusted value (post nibble): 005f
247.054: <09>Lane 06 nibble 0 raw readback: 0025
247.054: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0065
247.054: <09>Lane 06 nibble 0 adjusted value (post nibble): 0065
247.054: <09>Lane 07 nibble 0 raw readback: 0029
247.054: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0069
247.054: <09>Lane 07 nibble 0 adjusted value (post nibble): 0069
247.054: <09>Lane 08 nibble 0 raw readback: 005b
247.054: <09>Lane 08 nibble 0 adjusted value (pre nibble): 005b
247.054: <09>Lane 08 nibble 0 adjusted value (post nibble): 005b
247.054: AgesaHwWlPhase1: training nibble 1
247.054: DIMM 0 RttNom: 4
247.054: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.054: DIMM 0 RttWr: 1
247.054: DIMM 0 RttWr: 1
247.054: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.054: DIMM 0 RttWr: 1
247.054: DIMM 0 RttNom: 4
247.054: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.054: DIMM 0 RttNom: 4
247.055: DIMM 0 RttWr: 1
247.055: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.055: DIMM 0 RttWr: 1
247.055: DIMM 1 RttNom: 4
247.055: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.055: DIMM 0 RttNom: 4
247.055: DIMM 1 RttWr: 1
247.055: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.055: DIMM 0 RttWr: 1
247.055: DIMM 1 RttNom: 4
247.055: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.055: DIMM 0 RttNom: 4
247.055: DIMM 1 RttWr: 1
247.055: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.055: DIMM 0 RttWr: 1
247.055: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.055: <09>Lane 00 new seed: 007c
247.055: <09>Lane 01 new seed: 0071
247.055: <09>Lane 02 new seed: 006f
247.055: <09>Lane 03 new seed: 0069
247.055: <09>Lane 04 new seed: 0054
247.055: <09>Lane 05 new seed: 005e
247.055: <09>Lane 06 new seed: 0063
247.055: <09>Lane 07 new seed: 0066
247.055: <09>Lane 08 new seed: 0059
247.055: <09>Lane 00 nibble 1 raw readback: 0040
247.055: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0080
247.055: <09>Lane 00 nibble 1 adjusted value (post nibble): 007e
247.055: <09>Lane 01 nibble 1 raw readback: 0036
247.055: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0076
247.055: <09>Lane 01 nibble 1 adjusted value (post nibble): 0073
247.055: <09>Lane 02 nibble 1 raw readback: 0032
247.055: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0072
247.055: <09>Lane 02 nibble 1 adjusted value (post nibble): 0070
247.055: <09>Lane 03 nibble 1 raw readback: 002c
247.055: <09>Lane 03 nibble 1 adjusted value (pre nibble): 006c
247.055: <09>Lane 03 nibble 1 adjusted value (post nibble): 006a
247.055: <09>Lane 04 nibble 1 raw readback: 0056
247.055: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0056
247.055: <09>Lane 04 nibble 1 adjusted value (post nibble): 0055
247.055: <09>Lane 05 nibble 1 raw readback: 005f
247.055: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005f
247.055: <09>Lane 05 nibble 1 adjusted value (post nibble): 005e
247.055: <09>Lane 06 nibble 1 raw readback: 0025
247.055: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0065
247.055: <09>Lane 06 nibble 1 adjusted value (post nibble): 0064
247.055: <09>Lane 07 nibble 1 raw readback: 0029
247.055: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0069
247.055: <09>Lane 07 nibble 1 adjusted value (post nibble): 0067
247.055: <09>Lane 08 nibble 1 raw readback: 005c
247.055: <09>Lane 08 nibble 1 adjusted value (pre nibble): 005c
247.055: <09>Lane 08 nibble 1 adjusted value (post nibble): 005a
247.055: <09>original critical gross delay: 0
247.055: <09>new critical gross delay: 0
247.055: DIMM 0 RttNom: 4
247.055: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.055: DIMM 0 RttNom: 4
247.055: DIMM 0 RttWr: 1
247.055: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.055: DIMM 0 RttWr: 1
247.055: DIMM 0 RttNom: 4
247.055: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.055: DIMM 0 RttNom: 4
247.056: DIMM 0 RttWr: 1
247.055: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.055: DIMM 0 RttWr: 1
247.056: DIMM 1 RttNom: 4
247.056: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.056: DIMM 0 RttNom: 4
247.056: DIMM 1 RttWr: 1
247.056: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.056: DIMM 0 RttWr: 1
247.056: DIMM 1 RttNom: 4
247.056: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.056: DIMM 0 RttNom: 4
247.056: DIMM 1 RttWr: 1
247.056: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.056: DIMM 0 RttWr: 1
247.056: AgesaHwWlPhase1: training nibble 0
247.056: DIMM 1 RttNom: 4
247.056: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.056: DIMM 1 RttWr: 1
247.056: DIMM 1 RttWr: 1
247.056: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.056: DIMM 1 RttWr: 1
247.056: DIMM 1 RttNom: 4
247.056: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.056: DIMM 1 RttNom: 4
247.056: DIMM 1 RttWr: 1
247.056: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.056: DIMM 1 RttWr: 1
247.056: DIMM 0 RttNom: 4
247.056: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.056: DIMM 1 RttNom: 4
247.056: DIMM 0 RttWr: 1
247.056: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.056: DIMM 1 RttWr: 1
247.056: DIMM 0 RttNom: 4
247.056: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.056: DIMM 1 RttNom: 4
247.056: DIMM 0 RttWr: 1
247.056: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.056: DIMM 1 RttWr: 1
247.056: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.056: <09>Lane 00 scaled delay: 006a
247.056: <09>Lane 00 new seed: 006a
247.056: <09>Lane 01 scaled delay: 0061
247.056: <09>Lane 01 new seed: 0061
247.056: <09>Lane 02 scaled delay: 005f
247.056: <09>Lane 02 new seed: 005f
247.056: <09>Lane 03 scaled delay: 0058
247.056: <09>Lane 03 new seed: 0058
247.056: <09>Lane 04 scaled delay: 0045
247.056: <09>Lane 04 new seed: 0045
247.056: <09>Lane 05 scaled delay: 004e
247.056: <09>Lane 05 new seed: 004e
247.056: <09>Lane 06 scaled delay: 0052
247.056: <09>Lane 06 new seed: 0052
247.056: <09>Lane 07 scaled delay: 0057
247.056: <09>Lane 07 new seed: 0057
247.056: <09>Lane 08 scaled delay: 0048
247.056: <09>Lane 08 new seed: 0048
247.056: <09>Lane 00 nibble 0 raw readback: 0030
247.056: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0070
247.056: <09>Lane 00 nibble 0 adjusted value (post nibble): 0070
247.056: <09>Lane 01 nibble 0 raw readback: 0025
247.056: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0065
247.056: <09>Lane 01 nibble 0 adjusted value (post nibble): 0065
247.056: <09>Lane 02 nibble 0 raw readback: 0060
247.056: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0060
247.056: <09>Lane 02 nibble 0 adjusted value (post nibble): 0060
247.056: <09>Lane 03 nibble 0 raw readback: 005b
247.056: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005b
247.056: <09>Lane 03 nibble 0 adjusted value (post nibble): 005b
247.056: <09>Lane 04 nibble 0 raw readback: 0047
247.056: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0047
247.056: <09>Lane 04 nibble 0 adjusted value (post nibble): 0047
247.056: <09>Lane 05 nibble 0 raw readback: 0050
247.057: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0050
247.056: <09>Lane 05 nibble 0 adjusted value (post nibble): 0050
247.057: <09>Lane 06 nibble 0 raw readback: 0054
247.057: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0054
247.057: <09>Lane 06 nibble 0 adjusted value (post nibble): 0054
247.057: <09>Lane 07 nibble 0 raw readback: 005a
247.057: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005a
247.057: <09>Lane 07 nibble 0 adjusted value (post nibble): 005a
247.057: <09>Lane 08 nibble 0 raw readback: 004a
247.057: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004a
247.057: <09>Lane 08 nibble 0 adjusted value (post nibble): 004a
247.057: AgesaHwWlPhase1: training nibble 1
247.057: DIMM 1 RttNom: 4
247.057: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.057: DIMM 1 RttWr: 1
247.057: DIMM 1 RttWr: 1
247.057: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.057: DIMM 1 RttWr: 1
247.057: DIMM 1 RttNom: 4
247.057: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.057: DIMM 1 RttNom: 4
247.057: DIMM 1 RttWr: 1
247.057: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.057: DIMM 1 RttWr: 1
247.057: DIMM 0 RttNom: 4
247.057: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.057: DIMM 1 RttNom: 4
247.057: DIMM 0 RttWr: 1
247.057: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.057: DIMM 1 RttWr: 1
247.057: DIMM 0 RttNom: 4
247.057: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.057: DIMM 1 RttNom: 4
247.057: DIMM 0 RttWr: 1
247.057: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.057: DIMM 1 RttWr: 1
247.057: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.057: <09>Lane 00 new seed: 006a
247.057: <09>Lane 01 new seed: 0061
247.057: <09>Lane 02 new seed: 005f
247.057: <09>Lane 03 new seed: 0058
247.057: <09>Lane 04 new seed: 0045
247.057: <09>Lane 05 new seed: 004e
247.057: <09>Lane 06 new seed: 0052
247.057: <09>Lane 07 new seed: 0057
247.057: <09>Lane 08 new seed: 0048
247.057: <09>Lane 00 nibble 1 raw readback: 0031
247.057: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0071
247.057: <09>Lane 00 nibble 1 adjusted value (post nibble): 006d
247.057: <09>Lane 01 nibble 1 raw readback: 0027
247.057: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0067
247.057: <09>Lane 01 nibble 1 adjusted value (post nibble): 0064
247.057: <09>Lane 02 nibble 1 raw readback: 0062
247.057: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0062
247.057: <09>Lane 02 nibble 1 adjusted value (post nibble): 0060
247.057: <09>Lane 03 nibble 1 raw readback: 005c
247.057: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005c
247.057: <09>Lane 03 nibble 1 adjusted value (post nibble): 005a
247.057: <09>Lane 04 nibble 1 raw readback: 0047
247.057: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0047
247.057: <09>Lane 04 nibble 1 adjusted value (post nibble): 0046
247.057: <09>Lane 05 nibble 1 raw readback: 0050
247.057: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0050
247.057: <09>Lane 05 nibble 1 adjusted value (post nibble): 004f
247.057: <09>Lane 06 nibble 1 raw readback: 0055
247.057: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0055
247.057: <09>Lane 06 nibble 1 adjusted value (post nibble): 0053
247.057: <09>Lane 07 nibble 1 raw readback: 005c
247.057: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005c
247.057: <09>Lane 07 nibble 1 adjusted value (post nibble): 0059
247.057: <09>Lane 08 nibble 1 raw readback: 004a
247.057: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004a
247.057: <09>Lane 08 nibble 1 adjusted value (post nibble): 0049
247.057: <09>original critical gross delay: 0
247.057: <09>new critical gross delay: 0
247.058: DIMM 1 RttNom: 4
247.058: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.058: DIMM 1 RttNom: 4
247.058: DIMM 1 RttWr: 1
247.058: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.058: DIMM 1 RttWr: 1
247.058: DIMM 1 RttNom: 4
247.058: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.058: DIMM 1 RttNom: 4
247.058: DIMM 1 RttWr: 1
247.058: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.058: DIMM 1 RttWr: 1
247.058: DIMM 0 RttNom: 4
247.058: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.058: DIMM 1 RttNom: 4
247.058: DIMM 0 RttWr: 1
247.058: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.058: DIMM 1 RttWr: 1
247.058: DIMM 0 RttNom: 4
247.058: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.058: DIMM 1 RttNom: 4
247.058: DIMM 0 RttWr: 1
247.058: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.058: DIMM 1 RttWr: 1
247.058: SPD2ndTiming: Start
247.058: SPD2ndTiming: Done
247.058: mct_BeforeDramInit_Prod_D: Start
247.058: mct_ProgramODT_D: Start
247.058: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
247.058: mct_ProgramODT_D: Done
247.058: mct_BeforeDramInit_Prod_D: Done
247.059: mct_DramInit_Sw_D: Start
247.059: DIMM 0 RttWr: 1
247.059: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.059: mct_SendMrsCmd: Start
247.059: mct_SendMrsCmd: Done
247.059: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
247.059: mct_SendMrsCmd: Start
247.059: mct_SendMrsCmd: Done
247.059: DIMM 0 RttNom: 4
247.059: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.059: mct_SendMrsCmd: Start
247.059: mct_SendMrsCmd: Done
247.059: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001d78
247.059: mct_SendMrsCmd: Start
247.059: mct_SendMrsCmd: Done
247.059: DIMM 0 RttWr: 1
247.059: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.059: mct_SendMrsCmd: Start
247.059: mct_SendMrsCmd: Done
247.059: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
247.059: mct_SendMrsCmd: Start
247.059: mct_SendMrsCmd: Done
247.059: DIMM 0 RttNom: 4
247.059: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.059: mct_SendMrsCmd: Start
247.059: mct_SendMrsCmd: Done
247.059: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201d78
247.059: mct_SendMrsCmd: Start
247.059: mct_SendMrsCmd: Done
247.059: DIMM 1 RttWr: 1
247.059: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.059: mct_SendMrsCmd: Start
247.059: mct_SendMrsCmd: Done
247.059: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
247.059: mct_SendMrsCmd: Start
247.059: mct_SendMrsCmd: Done
247.059: DIMM 1 RttNom: 4
247.059: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.059: mct_SendMrsCmd: Start
247.059: mct_SendMrsCmd: Done
247.059: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401d78
247.059: mct_SendMrsCmd: Start
247.059: mct_SendMrsCmd: Done
247.059: DIMM 1 RttWr: 1
247.059: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.059: mct_SendMrsCmd: Start
247.059: mct_SendMrsCmd: Done
247.059: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
247.059: mct_SendMrsCmd: Start
247.059: mct_SendMrsCmd: Done
247.059: DIMM 1 RttNom: 4
247.059: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.059: mct_SendMrsCmd: Start
247.059: mct_SendMrsCmd: Done
247.059: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601d78
247.059: mct_SendMrsCmd: Start
247.059: mct_SendMrsCmd: Done
247.059: mct_DramInit_Sw_D: Done
247.059: AgesaHwWlPhase1: training nibble 0
247.059: DIMM 0 RttNom: 4
247.059: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.059: DIMM 0 RttWr: 1
247.059: DIMM 0 RttWr: 1
247.059: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.059: DIMM 0 RttWr: 1
247.059: DIMM 0 RttNom: 4
247.059: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.060: DIMM 0 RttNom: 4
247.059: DIMM 0 RttWr: 1
247.059: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.060: DIMM 0 RttWr: 1
247.060: DIMM 1 RttNom: 4
247.060: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.060: DIMM 0 RttNom: 4
247.060: DIMM 1 RttWr: 1
247.060: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.060: DIMM 0 RttWr: 1
247.060: DIMM 1 RttNom: 4
247.060: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.060: DIMM 0 RttNom: 4
247.060: DIMM 1 RttWr: 1
247.060: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.060: DIMM 0 RttWr: 1
247.060: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.060: <09>Lane 00 scaled delay: 0078
247.060: <09>Lane 00 new seed: 0078
247.060: <09>Lane 01 scaled delay: 0070
247.060: <09>Lane 01 new seed: 0070
247.060: <09>Lane 02 scaled delay: 006c
247.060: <09>Lane 02 new seed: 006c
247.060: <09>Lane 03 scaled delay: 0066
247.060: <09>Lane 03 new seed: 0066
247.060: <09>Lane 04 scaled delay: 0053
247.060: <09>Lane 04 new seed: 0053
247.060: <09>Lane 05 scaled delay: 0058
247.060: <09>Lane 05 new seed: 0058
247.060: <09>Lane 06 scaled delay: 0060
247.060: <09>Lane 06 new seed: 0060
247.060: <09>Lane 07 scaled delay: 0064
247.060: <09>Lane 07 new seed: 0064
247.060: <09>Lane 08 scaled delay: 0057
247.060: <09>Lane 08 new seed: 0057
247.060: <09>Lane 00 nibble 0 raw readback: 003d
247.060: <09>Lane 00 nibble 0 adjusted value (pre nibble): 007d
247.060: <09>Lane 00 nibble 0 adjusted value (post nibble): 007d
247.060: <09>Lane 01 nibble 0 raw readback: 0037
247.060: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0077
247.060: <09>Lane 01 nibble 0 adjusted value (post nibble): 0077
247.060: <09>Lane 02 nibble 0 raw readback: 002e
247.060: <09>Lane 02 nibble 0 adjusted value (pre nibble): 006e
247.060: <09>Lane 02 nibble 0 adjusted value (post nibble): 006e
247.060: <09>Lane 03 nibble 0 raw readback: 0029
247.060: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0069
247.060: <09>Lane 03 nibble 0 adjusted value (post nibble): 0069
247.060: <09>Lane 04 nibble 0 raw readback: 0057
247.060: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0057
247.060: <09>Lane 04 nibble 0 adjusted value (post nibble): 0057
247.060: <09>Lane 05 nibble 0 raw readback: 005d
247.060: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005d
247.060: <09>Lane 05 nibble 0 adjusted value (post nibble): 005d
247.060: <09>Lane 06 nibble 0 raw readback: 0020
247.060: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0060
247.060: <09>Lane 06 nibble 0 adjusted value (post nibble): 0060
247.060: <09>Lane 07 nibble 0 raw readback: 0025
247.060: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0065
247.060: <09>Lane 07 nibble 0 adjusted value (post nibble): 0065
247.060: <09>Lane 08 nibble 0 raw readback: 0059
247.060: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0059
247.060: <09>Lane 08 nibble 0 adjusted value (post nibble): 0059
247.060: AgesaHwWlPhase1: training nibble 1
247.060: DIMM 0 RttNom: 4
247.060: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.061: DIMM 0 RttWr: 1
247.061: DIMM 0 RttWr: 1
247.061: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.061: DIMM 0 RttWr: 1
247.061: DIMM 0 RttNom: 4
247.061: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.061: DIMM 0 RttNom: 4
247.061: DIMM 0 RttWr: 1
247.061: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.061: DIMM 0 RttWr: 1
247.061: DIMM 1 RttNom: 4
247.061: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.061: DIMM 0 RttNom: 4
247.061: DIMM 1 RttWr: 1
247.061: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.061: DIMM 0 RttWr: 1
247.061: DIMM 1 RttNom: 4
247.061: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.061: DIMM 0 RttNom: 4
247.061: DIMM 1 RttWr: 1
247.061: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.061: DIMM 0 RttWr: 1
247.061: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.061: <09>Lane 00 new seed: 0078
247.061: <09>Lane 01 new seed: 0070
247.061: <09>Lane 02 new seed: 006c
247.061: <09>Lane 03 new seed: 0066
247.061: <09>Lane 04 new seed: 0053
247.061: <09>Lane 05 new seed: 0058
247.061: <09>Lane 06 new seed: 0060
247.061: <09>Lane 07 new seed: 0064
247.061: <09>Lane 08 new seed: 0057
247.061: <09>Lane 00 nibble 1 raw readback: 003c
247.061: <09>Lane 00 nibble 1 adjusted value (pre nibble): 007c
247.061: <09>Lane 00 nibble 1 adjusted value (post nibble): 007a
247.061: <09>Lane 01 nibble 1 raw readback: 0035
247.061: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0075
247.061: <09>Lane 01 nibble 1 adjusted value (post nibble): 0072
247.061: <09>Lane 02 nibble 1 raw readback: 002f
247.061: <09>Lane 02 nibble 1 adjusted value (pre nibble): 006f
247.061: <09>Lane 02 nibble 1 adjusted value (post nibble): 006d
247.061: <09>Lane 03 nibble 1 raw readback: 0029
247.061: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0069
247.061: <09>Lane 03 nibble 1 adjusted value (post nibble): 0067
247.061: <09>Lane 04 nibble 1 raw readback: 0054
247.061: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0054
247.061: <09>Lane 04 nibble 1 adjusted value (post nibble): 0053
247.061: <09>Lane 05 nibble 1 raw readback: 005b
247.061: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005b
247.061: <09>Lane 05 nibble 1 adjusted value (post nibble): 0059
247.061: <09>Lane 06 nibble 1 raw readback: 0022
247.061: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0062
247.061: <09>Lane 06 nibble 1 adjusted value (post nibble): 0061
247.061: <09>Lane 07 nibble 1 raw readback: 0026
247.061: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0066
247.061: <09>Lane 07 nibble 1 adjusted value (post nibble): 0065
247.061: <09>Lane 08 nibble 1 raw readback: 0059
247.061: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0059
247.061: <09>Lane 08 nibble 1 adjusted value (post nibble): 0058
247.061: <09>original critical gross delay: 0
247.061: <09>new critical gross delay: 0
247.061: DIMM 0 RttNom: 4
247.061: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.061: DIMM 0 RttNom: 4
247.061: DIMM 0 RttWr: 1
247.061: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.062: DIMM 0 RttWr: 1
247.062: DIMM 0 RttNom: 4
247.062: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.062: DIMM 0 RttNom: 4
247.062: DIMM 0 RttWr: 1
247.062: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.062: DIMM 0 RttWr: 1
247.062: DIMM 1 RttNom: 4
247.062: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.062: DIMM 0 RttNom: 4
247.062: DIMM 1 RttWr: 1
247.062: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.062: DIMM 0 RttWr: 1
247.062: DIMM 1 RttNom: 4
247.062: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.062: DIMM 0 RttNom: 4
247.062: DIMM 1 RttWr: 1
247.062: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.062: DIMM 0 RttWr: 1
247.062: AgesaHwWlPhase1: training nibble 0
247.062: DIMM 1 RttNom: 4
247.062: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.062: DIMM 1 RttWr: 1
247.062: DIMM 1 RttWr: 1
247.062: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.062: DIMM 1 RttWr: 1
247.062: DIMM 1 RttNom: 4
247.062: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.062: DIMM 1 RttNom: 4
247.062: DIMM 1 RttWr: 1
247.062: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.062: DIMM 1 RttWr: 1
247.062: DIMM 0 RttNom: 4
247.062: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.062: DIMM 1 RttNom: 4
247.062: DIMM 0 RttWr: 1
247.062: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.062: DIMM 1 RttWr: 1
247.062: DIMM 0 RttNom: 4
247.062: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.062: DIMM 1 RttNom: 4
247.062: DIMM 0 RttWr: 1
247.062: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.062: DIMM 1 RttWr: 1
247.062: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.062: <09>Lane 00 scaled delay: 006a
247.062: <09>Lane 00 new seed: 006a
247.062: <09>Lane 01 scaled delay: 0064
247.062: <09>Lane 01 new seed: 0064
247.062: <09>Lane 02 scaled delay: 005d
247.062: <09>Lane 02 new seed: 005d
247.062: <09>Lane 03 scaled delay: 005b
247.062: <09>Lane 03 new seed: 005b
247.062: <09>Lane 04 scaled delay: 0047
247.062: <09>Lane 04 new seed: 0047
247.062: <09>Lane 05 scaled delay: 004e
247.062: <09>Lane 05 new seed: 004e
247.062: <09>Lane 06 scaled delay: 0052
247.062: <09>Lane 06 new seed: 0052
247.062: <09>Lane 07 scaled delay: 0055
247.062: <09>Lane 07 new seed: 0055
247.062: <09>Lane 08 scaled delay: 004c
247.062: <09>Lane 08 new seed: 004c
247.062: <09>Lane 00 nibble 0 raw readback: 002f
247.062: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006f
247.062: <09>Lane 00 nibble 0 adjusted value (post nibble): 006f
247.062: <09>Lane 01 nibble 0 raw readback: 002a
247.062: <09>Lane 01 nibble 0 adjusted value (pre nibble): 006a
247.062: <09>Lane 01 nibble 0 adjusted value (post nibble): 006a
247.062: <09>Lane 02 nibble 0 raw readback: 0060
247.062: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0060
247.062: <09>Lane 02 nibble 0 adjusted value (post nibble): 0060
247.062: <09>Lane 03 nibble 0 raw readback: 005b
247.063: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005b
247.063: <09>Lane 03 nibble 0 adjusted value (post nibble): 005b
247.063: <09>Lane 04 nibble 0 raw readback: 0049
247.063: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0049
247.063: <09>Lane 04 nibble 0 adjusted value (post nibble): 0049
247.063: <09>Lane 05 nibble 0 raw readback: 004d
247.063: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004d
247.063: <09>Lane 05 nibble 0 adjusted value (post nibble): 004d
247.063: <09>Lane 06 nibble 0 raw readback: 0054
247.063: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0054
247.063: <09>Lane 06 nibble 0 adjusted value (post nibble): 0054
247.063: <09>Lane 07 nibble 0 raw readback: 0059
247.063: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0059
247.063: <09>Lane 07 nibble 0 adjusted value (post nibble): 0059
247.063: <09>Lane 08 nibble 0 raw readback: 004b
247.063: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004b
247.063: <09>Lane 08 nibble 0 adjusted value (post nibble): 004b
247.063: AgesaHwWlPhase1: training nibble 1
247.063: DIMM 1 RttNom: 4
247.063: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.063: DIMM 1 RttWr: 1
247.063: DIMM 1 RttWr: 1
247.063: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.063: DIMM 1 RttWr: 1
247.063: DIMM 1 RttNom: 4
247.063: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.063: DIMM 1 RttNom: 4
247.063: DIMM 1 RttWr: 1
247.063: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.063: DIMM 1 RttWr: 1
247.063: DIMM 0 RttNom: 4
247.063: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.063: DIMM 1 RttNom: 4
247.063: DIMM 0 RttWr: 1
247.063: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.063: DIMM 1 RttWr: 1
247.063: DIMM 0 RttNom: 4
247.063: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.063: DIMM 1 RttNom: 4
247.063: DIMM 0 RttWr: 1
247.063: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.063: DIMM 1 RttWr: 1
247.063: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.063: <09>Lane 00 new seed: 006a
247.063: <09>Lane 01 new seed: 0064
247.063: <09>Lane 02 new seed: 005d
247.063: <09>Lane 03 new seed: 005b
247.063: <09>Lane 04 new seed: 0047
247.063: <09>Lane 05 new seed: 004e
247.063: <09>Lane 06 new seed: 0052
247.063: <09>Lane 07 new seed: 0055
247.063: <09>Lane 08 new seed: 004c
247.063: <09>Lane 00 nibble 1 raw readback: 002e
247.063: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006e
247.063: <09>Lane 00 nibble 1 adjusted value (post nibble): 006c
247.063: <09>Lane 01 nibble 1 raw readback: 0027
247.063: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0067
247.063: <09>Lane 01 nibble 1 adjusted value (post nibble): 0065
247.063: <09>Lane 02 nibble 1 raw readback: 005f
247.063: <09>Lane 02 nibble 1 adjusted value (pre nibble): 005f
247.063: <09>Lane 02 nibble 1 adjusted value (post nibble): 005e
247.063: <09>Lane 03 nibble 1 raw readback: 005d
247.063: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005d
247.063: <09>Lane 03 nibble 1 adjusted value (post nibble): 005c
247.063: <09>Lane 04 nibble 1 raw readback: 0046
247.063: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0046
247.063: <09>Lane 04 nibble 1 adjusted value (post nibble): 0046
247.063: <09>Lane 05 nibble 1 raw readback: 004f
247.063: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004f
247.063: <09>Lane 05 nibble 1 adjusted value (post nibble): 004e
247.063: <09>Lane 06 nibble 1 raw readback: 0053
247.063: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0053
247.063: <09>Lane 06 nibble 1 adjusted value (post nibble): 0052
247.063: <09>Lane 07 nibble 1 raw readback: 0057
247.063: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0057
247.063: <09>Lane 07 nibble 1 adjusted value (post nibble): 0056
247.063: <09>Lane 08 nibble 1 raw readback: 004c
247.063: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004c
247.063: <09>Lane 08 nibble 1 adjusted value (post nibble): 004c
247.063: <09>original critical gross delay: 0
247.064: <09>new critical gross delay: 0
247.064: DIMM 1 RttNom: 4
247.064: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.064: DIMM 1 RttNom: 4
247.064: DIMM 1 RttWr: 1
247.064: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.064: DIMM 1 RttWr: 1
247.064: DIMM 1 RttNom: 4
247.064: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.064: DIMM 1 RttNom: 4
247.064: DIMM 1 RttWr: 1
247.064: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.064: DIMM 1 RttWr: 1
247.064: DIMM 0 RttNom: 4
247.064: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.064: DIMM 1 RttNom: 4
247.064: DIMM 0 RttWr: 1
247.064: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.064: DIMM 1 RttWr: 1
247.064: DIMM 0 RttNom: 4
247.064: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.064: DIMM 1 RttNom: 4
247.064: DIMM 0 RttWr: 1
247.064: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.064: DIMM 1 RttWr: 1
247.064: activate_spd_rom() for node 01
247.064: enable_spd_node1()
247.064: SetTargetFreq: Start
247.065: SetTargetFreq: Node 1: New frequency code: 0006
247.065: ChangeMemClk: Start
247.065: set_2t_configuration: Start
247.065: set_2t_configuration: Done
247.065: mct_BeforePlatformSpec: Start
247.065: mct_BeforePlatformSpec: Done
247.065: mct_PlatformSpec: Start
247.065: Programmed DCT 0 timing/termination pattern 00000000 20222222
247.065: mct_PlatformSpec: Done
247.065: set_2t_configuration: Start
247.065: set_2t_configuration: Done
247.065: mct_BeforePlatformSpec: Start
247.065: mct_BeforePlatformSpec: Done
247.065: mct_PlatformSpec: Start
247.065: Programmed DCT 1 timing/termination pattern 00000000 20222222
247.065: mct_PlatformSpec: Done
247.065: ChangeMemClk: Done
247.065: phyAssistedMemFnceTraining: Start
247.065: phyAssistedMemFnceTraining: training node 1 DCT 0
247.065: phyAssistedMemFnceTraining: done training node 1 DCT 0
247.065: phyAssistedMemFnceTraining: training node 1 DCT 1
247.065: phyAssistedMemFnceTraining: done training node 1 DCT 1
247.065: phyAssistedMemFnceTraining: Done
247.065: InitPhyCompensation: DCT 0: Start
247.065: Waiting for predriver calibration to be applied...done!
247.065: InitPhyCompensation: DCT 0: Done
247.066: phyAssistedMemFnceTraining: Start
247.066: phyAssistedMemFnceTraining: training node 1 DCT 0
247.066: phyAssistedMemFnceTraining: done training node 1 DCT 0
247.066: phyAssistedMemFnceTraining: training node 1 DCT 1
247.066: phyAssistedMemFnceTraining: done training node 1 DCT 1
247.066: phyAssistedMemFnceTraining: Done
247.066: InitPhyCompensation: DCT 1: Start
247.066: Waiting for predriver calibration to be applied...done!
247.066: InitPhyCompensation: DCT 1: Done
247.066: Preparing to send DCT 0 DIMM 0 RC10: 00 (F2xA8: 02000300)
247.066: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.066: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
247.066: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.066: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
247.066: Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 02000c00)
247.066: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.066: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
247.066: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.066: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
247.066: Preparing to send DCT 1 DIMM 0 RC10: 00 (F2xA8: 02000300)
247.066: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.066: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
247.066: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.066: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
247.066: Preparing to send DCT 1 DIMM 1 RC10: 00 (F2xA8: 02000c00)
247.066: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.066: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
247.066: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.067: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
247.067: SetTargetFreq: Done
247.067: SPD2ndTiming: Start
247.067: SPD2ndTiming: Done
247.067: mct_BeforeDramInit_Prod_D: Start
247.067: mct_ProgramODT_D: Start
247.067: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
247.067: mct_ProgramODT_D: Done
247.067: mct_BeforeDramInit_Prod_D: Done
247.067: mct_DramInit_Sw_D: Start
247.067: DIMM 0 RttWr: 2
247.067: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.067: mct_SendMrsCmd: Start
247.067: mct_SendMrsCmd: Done
247.067: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
247.067: mct_SendMrsCmd: Start
247.067: mct_SendMrsCmd: Done
247.067: DIMM 0 RttNom: 3
247.067: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.067: mct_SendMrsCmd: Start
247.067: mct_SendMrsCmd: Done
247.067: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001578
247.067: mct_SendMrsCmd: Start
247.067: mct_SendMrsCmd: Done
247.067: DIMM 0 RttWr: 2
247.067: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.067: mct_SendMrsCmd: Start
247.067: mct_SendMrsCmd: Done
247.067: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
247.067: mct_SendMrsCmd: Start
247.067: mct_SendMrsCmd: Done
247.067: DIMM 0 RttNom: 3
247.067: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.067: mct_SendMrsCmd: Start
247.067: mct_SendMrsCmd: Done
247.068: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201578
247.068: mct_SendMrsCmd: Start
247.068: mct_SendMrsCmd: Done
247.068: DIMM 1 RttWr: 2
247.068: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.068: mct_SendMrsCmd: Start
247.068: mct_SendMrsCmd: Done
247.068: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
247.068: mct_SendMrsCmd: Start
247.068: mct_SendMrsCmd: Done
247.068: DIMM 1 RttNom: 3
247.068: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.068: mct_SendMrsCmd: Start
247.068: mct_SendMrsCmd: Done
247.068: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401578
247.068: mct_SendMrsCmd: Start
247.068: mct_SendMrsCmd: Done
247.068: DIMM 1 RttWr: 2
247.068: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.068: mct_SendMrsCmd: Start
247.068: mct_SendMrsCmd: Done
247.068: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
247.068: mct_SendMrsCmd: Start
247.068: mct_SendMrsCmd: Done
247.068: DIMM 1 RttNom: 3
247.068: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.068: mct_SendMrsCmd: Start
247.068: mct_SendMrsCmd: Done
247.068: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601578
247.068: mct_SendMrsCmd: Start
247.068: mct_SendMrsCmd: Done
247.068: mct_DramInit_Sw_D: Done
247.068: AgesaHwWlPhase1: training nibble 0
247.068: DIMM 0 RttNom: 3
247.068: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.068: DIMM 0 RttWr: 2
247.068: DIMM 0 RttWr: 2
247.068: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.068: DIMM 0 RttWr: 2
247.068: DIMM 0 RttNom: 3
247.068: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.068: DIMM 0 RttNom: 3
247.068: DIMM 0 RttWr: 2
247.068: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.068: DIMM 0 RttWr: 2
247.068: DIMM 1 RttNom: 3
247.068: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.068: DIMM 0 RttNom: 3
247.068: DIMM 1 RttWr: 2
247.068: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.068: DIMM 0 RttWr: 2
247.068: DIMM 1 RttNom: 3
247.068: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.068: DIMM 0 RttNom: 3
247.068: DIMM 1 RttWr: 2
247.068: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.069: DIMM 0 RttWr: 2
247.069: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.069: <09>Lane 00 scaled delay: 0047
247.069: <09>Lane 00 new seed: 0047
247.069: <09>Lane 01 scaled delay: 0047
247.069: <09>Lane 01 new seed: 0047
247.069: <09>Lane 02 scaled delay: 0047
247.069: <09>Lane 02 new seed: 0047
247.069: <09>Lane 03 scaled delay: 0047
247.069: <09>Lane 03 new seed: 0047
247.069: <09>Lane 04 scaled delay: 0047
247.069: <09>Lane 04 new seed: 0047
247.069: <09>Lane 05 scaled delay: 0047
247.069: <09>Lane 05 new seed: 0047
247.069: <09>Lane 06 scaled delay: 0047
247.069: <09>Lane 06 new seed: 0047
247.069: <09>Lane 07 scaled delay: 0047
247.069: <09>Lane 07 new seed: 0047
247.069: <09>Lane 08 scaled delay: 0047
247.069: <09>Lane 08 new seed: 0047
247.069: <09>Lane 00 nibble 0 raw readback: 0040
247.069: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0040
247.069: <09>Lane 00 nibble 0 adjusted value (post nibble): 0040
247.069: <09>Lane 01 nibble 0 raw readback: 003c
247.069: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003c
247.069: <09>Lane 01 nibble 0 adjusted value (post nibble): 003c
247.069: <09>Lane 02 nibble 0 raw readback: 0038
247.069: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0038
247.069: <09>Lane 02 nibble 0 adjusted value (post nibble): 0038
247.069: <09>Lane 03 nibble 0 raw readback: 0036
247.069: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0036
247.069: <09>Lane 03 nibble 0 adjusted value (post nibble): 0036
247.069: <09>Lane 04 nibble 0 raw readback: 0033
247.069: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0033
247.069: <09>Lane 04 nibble 0 adjusted value (post nibble): 0033
247.069: <09>Lane 05 nibble 0 raw readback: 0037
247.069: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0037
247.069: <09>Lane 05 nibble 0 adjusted value (post nibble): 0037
247.069: <09>Lane 06 nibble 0 raw readback: 0039
247.069: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0039
247.069: <09>Lane 06 nibble 0 adjusted value (post nibble): 0039
247.069: <09>Lane 07 nibble 0 raw readback: 003d
247.069: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003d
247.069: <09>Lane 07 nibble 0 adjusted value (post nibble): 003d
247.069: <09>Lane 08 nibble 0 raw readback: 0031
247.069: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0031
247.069: <09>Lane 08 nibble 0 adjusted value (post nibble): 0031
247.069: AgesaHwWlPhase1: training nibble 1
247.070: DIMM 0 RttNom: 3
247.070: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.070: DIMM 0 RttWr: 2
247.070: DIMM 0 RttWr: 2
247.070: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.070: DIMM 0 RttWr: 2
247.070: DIMM 0 RttNom: 3
247.070: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.070: DIMM 0 RttNom: 3
247.070: DIMM 0 RttWr: 2
247.070: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.070: DIMM 0 RttWr: 2
247.070: DIMM 1 RttNom: 3
247.070: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.070: DIMM 0 RttNom: 3
247.070: DIMM 1 RttWr: 2
247.070: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.070: DIMM 0 RttWr: 2
247.070: DIMM 1 RttNom: 3
247.070: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.070: DIMM 0 RttNom: 3
247.070: DIMM 1 RttWr: 2
247.070: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.070: DIMM 0 RttWr: 2
247.070: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.070: <09>Lane 00 new seed: 0047
247.070: <09>Lane 01 new seed: 0047
247.070: <09>Lane 02 new seed: 0047
247.070: <09>Lane 03 new seed: 0047
247.070: <09>Lane 04 new seed: 0047
247.070: <09>Lane 05 new seed: 0047
247.070: <09>Lane 06 new seed: 0047
247.070: <09>Lane 07 new seed: 0047
247.070: <09>Lane 08 new seed: 0047
247.070: <09>Lane 00 nibble 1 raw readback: 003f
247.070: <09>Lane 00 nibble 1 adjusted value (pre nibble): 003f
247.070: <09>Lane 00 nibble 1 adjusted value (post nibble): 0043
247.070: <09>Lane 01 nibble 1 raw readback: 003c
247.070: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003c
247.070: <09>Lane 01 nibble 1 adjusted value (post nibble): 0041
247.070: <09>Lane 02 nibble 1 raw readback: 0039
247.070: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0039
247.070: <09>Lane 02 nibble 1 adjusted value (post nibble): 0040
247.070: <09>Lane 03 nibble 1 raw readback: 0037
247.070: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0037
247.070: <09>Lane 03 nibble 1 adjusted value (post nibble): 003f
247.070: <09>Lane 04 nibble 1 raw readback: 0032
247.070: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0032
247.070: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
247.070: <09>Lane 05 nibble 1 raw readback: 0037
247.070: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0037
247.070: <09>Lane 05 nibble 1 adjusted value (post nibble): 003f
247.070: <09>Lane 06 nibble 1 raw readback: 003a
247.070: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003a
247.070: <09>Lane 06 nibble 1 adjusted value (post nibble): 0040
247.070: <09>Lane 07 nibble 1 raw readback: 003d
247.070: <09>Lane 07 nibble 1 adjusted value (pre nibble): 003d
247.070: <09>Lane 07 nibble 1 adjusted value (post nibble): 0042
247.070: <09>Lane 08 nibble 1 raw readback: 0031
247.070: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0031
247.070: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
247.070: <09>original critical gross delay: 0
247.070: <09>new critical gross delay: 0
247.071: DIMM 0 RttNom: 3
247.071: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.071: DIMM 0 RttNom: 3
247.071: DIMM 0 RttWr: 2
247.071: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.071: DIMM 0 RttWr: 2
247.071: DIMM 0 RttNom: 3
247.071: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.071: DIMM 0 RttNom: 3
247.071: DIMM 0 RttWr: 2
247.071: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.071: DIMM 0 RttWr: 2
247.071: DIMM 1 RttNom: 3
247.071: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.071: DIMM 0 RttNom: 3
247.071: DIMM 1 RttWr: 2
247.071: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.071: DIMM 0 RttWr: 2
247.071: DIMM 1 RttNom: 3
247.071: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.071: DIMM 0 RttNom: 3
247.071: DIMM 1 RttWr: 2
247.071: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.071: DIMM 0 RttWr: 2
247.071: AgesaHwWlPhase1: training nibble 0
247.071: DIMM 1 RttNom: 3
247.071: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.071: DIMM 1 RttWr: 2
247.071: DIMM 1 RttWr: 2
247.071: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.071: DIMM 1 RttWr: 2
247.071: DIMM 1 RttNom: 3
247.071: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.071: DIMM 1 RttNom: 3
247.071: DIMM 1 RttWr: 2
247.071: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.071: DIMM 1 RttWr: 2
247.071: DIMM 0 RttNom: 3
247.071: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.071: DIMM 1 RttNom: 3
247.071: DIMM 0 RttWr: 2
247.071: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.071: DIMM 1 RttWr: 2
247.071: DIMM 0 RttNom: 3
247.071: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.071: DIMM 1 RttNom: 3
247.071: DIMM 0 RttWr: 2
247.071: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.071: DIMM 1 RttWr: 2
247.071: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.071: <09>Lane 00 scaled delay: 0047
247.071: <09>Lane 00 new seed: 0047
247.071: <09>Lane 01 scaled delay: 0047
247.071: <09>Lane 01 new seed: 0047
247.071: <09>Lane 02 scaled delay: 0047
247.071: <09>Lane 02 new seed: 0047
247.071: <09>Lane 03 scaled delay: 0047
247.071: <09>Lane 03 new seed: 0047
247.071: <09>Lane 04 scaled delay: 0047
247.071: <09>Lane 04 new seed: 0047
247.071: <09>Lane 05 scaled delay: 0047
247.071: <09>Lane 05 new seed: 0047
247.071: <09>Lane 06 scaled delay: 0047
247.072: <09>Lane 06 new seed: 0047
247.072: <09>Lane 07 scaled delay: 0047
247.072: <09>Lane 07 new seed: 0047
247.072: <09>Lane 08 scaled delay: 0047
247.072: <09>Lane 08 new seed: 0047
247.072: <09>Lane 00 nibble 0 raw readback: 0045
247.072: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0045
247.072: <09>Lane 00 nibble 0 adjusted value (post nibble): 0045
247.072: <09>Lane 01 nibble 0 raw readback: 0040
247.072: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0040
247.072: <09>Lane 01 nibble 0 adjusted value (post nibble): 0040
247.072: <09>Lane 02 nibble 0 raw readback: 003c
247.072: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003c
247.072: <09>Lane 02 nibble 0 adjusted value (post nibble): 003c
247.072: <09>Lane 03 nibble 0 raw readback: 003b
247.072: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
247.072: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
247.072: <09>Lane 04 nibble 0 raw readback: 0038
247.072: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0038
247.072: <09>Lane 04 nibble 0 adjusted value (post nibble): 0038
247.072: <09>Lane 05 nibble 0 raw readback: 003d
247.072: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
247.072: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
247.072: <09>Lane 06 nibble 0 raw readback: 003d
247.072: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003d
247.072: <09>Lane 06 nibble 0 adjusted value (post nibble): 003d
247.072: <09>Lane 07 nibble 0 raw readback: 0042
247.072: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0042
247.072: <09>Lane 07 nibble 0 adjusted value (post nibble): 0042
247.072: <09>Lane 08 nibble 0 raw readback: 0036
247.072: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
247.072: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
247.072: AgesaHwWlPhase1: training nibble 1
247.072: DIMM 1 RttNom: 3
247.072: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.072: DIMM 1 RttWr: 2
247.072: DIMM 1 RttWr: 2
247.072: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.072: DIMM 1 RttWr: 2
247.072: DIMM 1 RttNom: 3
247.072: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.072: DIMM 1 RttNom: 3
247.072: DIMM 1 RttWr: 2
247.072: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.072: DIMM 1 RttWr: 2
247.072: DIMM 0 RttNom: 3
247.072: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.072: DIMM 1 RttNom: 3
247.072: DIMM 0 RttWr: 2
247.072: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.072: DIMM 1 RttWr: 2
247.072: DIMM 0 RttNom: 3
247.072: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.072: DIMM 1 RttNom: 3
247.072: DIMM 0 RttWr: 2
247.072: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.072: DIMM 1 RttWr: 2
247.072: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.072: <09>Lane 00 new seed: 0047
247.072: <09>Lane 01 new seed: 0047
247.072: <09>Lane 02 new seed: 0047
247.072: <09>Lane 03 new seed: 0047
247.072: <09>Lane 04 new seed: 0047
247.072: <09>Lane 05 new seed: 0047
247.072: <09>Lane 06 new seed: 0047
247.072: <09>Lane 07 new seed: 0047
247.072: <09>Lane 08 new seed: 0047
247.072: <09>Lane 00 nibble 1 raw readback: 0046
247.072: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0046
247.072: <09>Lane 00 nibble 1 adjusted value (post nibble): 0046
247.072: <09>Lane 01 nibble 1 raw readback: 003f
247.073: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003f
247.073: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
247.073: <09>Lane 02 nibble 1 raw readback: 003d
247.073: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003d
247.073: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
247.073: <09>Lane 03 nibble 1 raw readback: 003b
247.073: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
247.073: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
247.073: <09>Lane 04 nibble 1 raw readback: 0037
247.073: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0037
247.073: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
247.073: <09>Lane 05 nibble 1 raw readback: 003c
247.073: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
247.073: <09>Lane 05 nibble 1 adjusted value (post nibble): 0041
247.073: <09>Lane 06 nibble 1 raw readback: 003f
247.073: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003f
247.073: <09>Lane 06 nibble 1 adjusted value (post nibble): 0043
247.073: <09>Lane 07 nibble 1 raw readback: 0042
247.073: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
247.073: <09>Lane 07 nibble 1 adjusted value (post nibble): 0044
247.073: <09>Lane 08 nibble 1 raw readback: 0037
247.073: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
247.073: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
247.073: <09>original critical gross delay: 0
247.073: <09>new critical gross delay: 0
247.073: DIMM 1 RttNom: 3
247.073: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.073: DIMM 1 RttNom: 3
247.073: DIMM 1 RttWr: 2
247.073: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.073: DIMM 1 RttWr: 2
247.073: DIMM 1 RttNom: 3
247.073: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.073: DIMM 1 RttNom: 3
247.073: DIMM 1 RttWr: 2
247.073: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.073: DIMM 1 RttWr: 2
247.073: DIMM 0 RttNom: 3
247.073: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.073: DIMM 1 RttNom: 3
247.073: DIMM 0 RttWr: 2
247.073: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.073: DIMM 1 RttWr: 2
247.073: DIMM 0 RttNom: 3
247.073: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.073: DIMM 1 RttNom: 3
247.073: DIMM 0 RttWr: 2
247.073: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.073: DIMM 1 RttWr: 2
247.073: SPD2ndTiming: Start
247.074: SPD2ndTiming: Done
247.074: mct_BeforeDramInit_Prod_D: Start
247.074: mct_ProgramODT_D: Start
247.074: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
247.074: mct_ProgramODT_D: Done
247.074: mct_BeforeDramInit_Prod_D: Done
247.074: mct_DramInit_Sw_D: Start
247.074: DIMM 0 RttWr: 2
247.074: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.074: mct_SendMrsCmd: Start
247.074: mct_SendMrsCmd: Done
247.074: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
247.074: mct_SendMrsCmd: Start
247.074: mct_SendMrsCmd: Done
247.074: DIMM 0 RttNom: 3
247.074: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.074: mct_SendMrsCmd: Start
247.074: mct_SendMrsCmd: Done
247.074: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001578
247.074: mct_SendMrsCmd: Start
247.074: mct_SendMrsCmd: Done
247.074: DIMM 0 RttWr: 2
247.074: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.074: mct_SendMrsCmd: Start
247.074: mct_SendMrsCmd: Done
247.074: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
247.074: mct_SendMrsCmd: Start
247.074: mct_SendMrsCmd: Done
247.074: DIMM 0 RttNom: 3
247.074: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.074: mct_SendMrsCmd: Start
247.074: mct_SendMrsCmd: Done
247.074: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201578
247.074: mct_SendMrsCmd: Start
247.074: mct_SendMrsCmd: Done
247.074: DIMM 1 RttWr: 2
247.074: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.074: mct_SendMrsCmd: Start
247.074: mct_SendMrsCmd: Done
247.074: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
247.074: mct_SendMrsCmd: Start
247.074: mct_SendMrsCmd: Done
247.074: DIMM 1 RttNom: 3
247.074: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.074: mct_SendMrsCmd: Start
247.074: mct_SendMrsCmd: Done
247.074: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401578
247.074: mct_SendMrsCmd: Start
247.074: mct_SendMrsCmd: Done
247.074: DIMM 1 RttWr: 2
247.074: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.074: mct_SendMrsCmd: Start
247.075: mct_SendMrsCmd: Done
247.075: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
247.075: mct_SendMrsCmd: Start
247.075: mct_SendMrsCmd: Done
247.075: DIMM 1 RttNom: 3
247.075: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.075: mct_SendMrsCmd: Start
247.075: mct_SendMrsCmd: Done
247.075: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601578
247.075: mct_SendMrsCmd: Start
247.075: mct_SendMrsCmd: Done
247.075: mct_DramInit_Sw_D: Done
247.075: AgesaHwWlPhase1: training nibble 0
247.075: DIMM 0 RttNom: 3
247.075: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.075: DIMM 0 RttWr: 2
247.075: DIMM 0 RttWr: 2
247.075: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.075: DIMM 0 RttWr: 2
247.075: DIMM 0 RttNom: 3
247.075: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.075: DIMM 0 RttNom: 3
247.075: DIMM 0 RttWr: 2
247.075: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.075: DIMM 0 RttWr: 2
247.075: DIMM 1 RttNom: 3
247.075: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.075: DIMM 0 RttNom: 3
247.075: DIMM 1 RttWr: 2
247.075: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.075: DIMM 0 RttWr: 2
247.075: DIMM 1 RttNom: 3
247.075: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.075: DIMM 0 RttNom: 3
247.075: DIMM 1 RttWr: 2
247.075: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.075: DIMM 0 RttWr: 2
247.075: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.075: <09>Lane 00 scaled delay: 0047
247.075: <09>Lane 00 new seed: 0047
247.075: <09>Lane 01 scaled delay: 0047
247.075: <09>Lane 01 new seed: 0047
247.075: <09>Lane 02 scaled delay: 0047
247.075: <09>Lane 02 new seed: 0047
247.075: <09>Lane 03 scaled delay: 0047
247.075: <09>Lane 03 new seed: 0047
247.075: <09>Lane 04 scaled delay: 0047
247.075: <09>Lane 04 new seed: 0047
247.075: <09>Lane 05 scaled delay: 0047
247.075: <09>Lane 05 new seed: 0047
247.075: <09>Lane 06 scaled delay: 0047
247.075: <09>Lane 06 new seed: 0047
247.075: <09>Lane 07 scaled delay: 0047
247.075: <09>Lane 07 new seed: 0047
247.075: <09>Lane 08 scaled delay: 0047
247.075: <09>Lane 08 new seed: 0047
247.076: <09>Lane 00 nibble 0 raw readback: 0041
247.076: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0041
247.076: <09>Lane 00 nibble 0 adjusted value (post nibble): 0041
247.076: <09>Lane 01 nibble 0 raw readback: 003c
247.076: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003c
247.076: <09>Lane 01 nibble 0 adjusted value (post nibble): 003c
247.076: <09>Lane 02 nibble 0 raw readback: 0039
247.076: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0039
247.076: <09>Lane 02 nibble 0 adjusted value (post nibble): 0039
247.076: <09>Lane 03 nibble 0 raw readback: 0036
247.076: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0036
247.076: <09>Lane 03 nibble 0 adjusted value (post nibble): 0036
247.076: <09>Lane 04 nibble 0 raw readback: 0034
247.076: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0034
247.076: <09>Lane 04 nibble 0 adjusted value (post nibble): 0034
247.076: <09>Lane 05 nibble 0 raw readback: 0038
247.076: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0038
247.076: <09>Lane 05 nibble 0 adjusted value (post nibble): 0038
247.076: <09>Lane 06 nibble 0 raw readback: 003a
247.076: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003a
247.076: <09>Lane 06 nibble 0 adjusted value (post nibble): 003a
247.076: <09>Lane 07 nibble 0 raw readback: 003e
247.076: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003e
247.076: <09>Lane 07 nibble 0 adjusted value (post nibble): 003e
247.076: <09>Lane 08 nibble 0 raw readback: 0032
247.076: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0032
247.076: <09>Lane 08 nibble 0 adjusted value (post nibble): 0032
247.076: AgesaHwWlPhase1: training nibble 1
247.076: DIMM 0 RttNom: 3
247.076: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.076: DIMM 0 RttWr: 2
247.076: DIMM 0 RttWr: 2
247.076: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.076: DIMM 0 RttWr: 2
247.076: DIMM 0 RttNom: 3
247.076: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.076: DIMM 0 RttNom: 3
247.076: DIMM 0 RttWr: 2
247.076: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.076: DIMM 0 RttWr: 2
247.076: DIMM 1 RttNom: 3
247.076: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.076: DIMM 0 RttNom: 3
247.076: DIMM 1 RttWr: 2
247.076: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.076: DIMM 0 RttWr: 2
247.076: DIMM 1 RttNom: 3
247.076: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.076: DIMM 0 RttNom: 3
247.076: DIMM 1 RttWr: 2
247.076: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.076: DIMM 0 RttWr: 2
247.076: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.076: <09>Lane 00 new seed: 0047
247.076: <09>Lane 01 new seed: 0047
247.076: <09>Lane 02 new seed: 0047
247.076: <09>Lane 03 new seed: 0047
247.076: <09>Lane 04 new seed: 0047
247.076: <09>Lane 05 new seed: 0047
247.076: <09>Lane 06 new seed: 0047
247.076: <09>Lane 07 new seed: 0047
247.076: <09>Lane 08 new seed: 0047
247.076: <09>Lane 00 nibble 1 raw readback: 0040
247.076: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0040
247.076: <09>Lane 00 nibble 1 adjusted value (post nibble): 0043
247.076: <09>Lane 01 nibble 1 raw readback: 003d
247.076: <09>Lane 01 nibble 1 adjusted value (pre nibble): 003d
247.076: <09>Lane 01 nibble 1 adjusted value (post nibble): 0042
247.077: <09>Lane 02 nibble 1 raw readback: 0039
247.077: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0039
247.077: <09>Lane 02 nibble 1 adjusted value (post nibble): 0040
247.077: <09>Lane 03 nibble 1 raw readback: 0036
247.077: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0036
247.077: <09>Lane 03 nibble 1 adjusted value (post nibble): 003e
247.077: <09>Lane 04 nibble 1 raw readback: 0034
247.077: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0034
247.077: <09>Lane 04 nibble 1 adjusted value (post nibble): 003d
247.077: <09>Lane 05 nibble 1 raw readback: 0037
247.077: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0037
247.077: <09>Lane 05 nibble 1 adjusted value (post nibble): 003f
247.077: <09>Lane 06 nibble 1 raw readback: 003b
247.077: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003b
247.077: <09>Lane 06 nibble 1 adjusted value (post nibble): 0041
247.077: <09>Lane 07 nibble 1 raw readback: 003f
247.077: <09>Lane 07 nibble 1 adjusted value (pre nibble): 003f
247.077: <09>Lane 07 nibble 1 adjusted value (post nibble): 0043
247.077: <09>Lane 08 nibble 1 raw readback: 0031
247.077: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0031
247.077: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
247.077: <09>original critical gross delay: 0
247.077: <09>new critical gross delay: 0
247.077: DIMM 0 RttNom: 3
247.077: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.077: DIMM 0 RttNom: 3
247.077: DIMM 0 RttWr: 2
247.077: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.077: DIMM 0 RttWr: 2
247.077: DIMM 0 RttNom: 3
247.077: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.077: DIMM 0 RttNom: 3
247.077: DIMM 0 RttWr: 2
247.077: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.077: DIMM 0 RttWr: 2
247.077: DIMM 1 RttNom: 3
247.077: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.077: DIMM 0 RttNom: 3
247.077: DIMM 1 RttWr: 2
247.077: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.077: DIMM 0 RttWr: 2
247.077: DIMM 1 RttNom: 3
247.077: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.077: DIMM 0 RttNom: 3
247.077: DIMM 1 RttWr: 2
247.077: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.077: DIMM 0 RttWr: 2
247.077: AgesaHwWlPhase1: training nibble 0
247.077: DIMM 1 RttNom: 3
247.077: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.077: DIMM 1 RttWr: 2
247.077: DIMM 1 RttWr: 2
247.077: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.077: DIMM 1 RttWr: 2
247.077: DIMM 1 RttNom: 3
247.077: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.077: DIMM 1 RttNom: 3
247.077: DIMM 1 RttWr: 2
247.077: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.077: DIMM 1 RttWr: 2
247.077: DIMM 0 RttNom: 3
247.077: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.078: DIMM 1 RttNom: 3
247.078: DIMM 0 RttWr: 2
247.078: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.078: DIMM 1 RttWr: 2
247.078: DIMM 0 RttNom: 3
247.078: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.078: DIMM 1 RttNom: 3
247.078: DIMM 0 RttWr: 2
247.078: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.078: DIMM 1 RttWr: 2
247.078: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.078: <09>Lane 00 scaled delay: 0047
247.078: <09>Lane 00 new seed: 0047
247.078: <09>Lane 01 scaled delay: 0047
247.078: <09>Lane 01 new seed: 0047
247.078: <09>Lane 02 scaled delay: 0047
247.078: <09>Lane 02 new seed: 0047
247.078: <09>Lane 03 scaled delay: 0047
247.078: <09>Lane 03 new seed: 0047
247.078: <09>Lane 04 scaled delay: 0047
247.078: <09>Lane 04 new seed: 0047
247.078: <09>Lane 05 scaled delay: 0047
247.078: <09>Lane 05 new seed: 0047
247.078: <09>Lane 06 scaled delay: 0047
247.078: <09>Lane 06 new seed: 0047
247.078: <09>Lane 07 scaled delay: 0047
247.078: <09>Lane 07 new seed: 0047
247.078: <09>Lane 08 scaled delay: 0047
247.078: <09>Lane 08 new seed: 0047
247.078: <09>Lane 00 nibble 0 raw readback: 0044
247.078: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0044
247.078: <09>Lane 00 nibble 0 adjusted value (post nibble): 0044
247.078: <09>Lane 01 nibble 0 raw readback: 0043
247.078: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0043
247.078: <09>Lane 01 nibble 0 adjusted value (post nibble): 0043
247.078: <09>Lane 02 nibble 0 raw readback: 003e
247.078: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003e
247.078: <09>Lane 02 nibble 0 adjusted value (post nibble): 003e
247.078: <09>Lane 03 nibble 0 raw readback: 003a
247.078: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003a
247.078: <09>Lane 03 nibble 0 adjusted value (post nibble): 003a
247.078: <09>Lane 04 nibble 0 raw readback: 0039
247.078: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
247.078: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
247.078: <09>Lane 05 nibble 0 raw readback: 003d
247.078: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
247.078: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
247.078: <09>Lane 06 nibble 0 raw readback: 0041
247.078: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0041
247.078: <09>Lane 06 nibble 0 adjusted value (post nibble): 0041
247.078: <09>Lane 07 nibble 0 raw readback: 0044
247.078: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0044
247.078: <09>Lane 07 nibble 0 adjusted value (post nibble): 0044
247.078: <09>Lane 08 nibble 0 raw readback: 0036
247.078: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0036
247.078: <09>Lane 08 nibble 0 adjusted value (post nibble): 0036
247.078: AgesaHwWlPhase1: training nibble 1
247.078: DIMM 1 RttNom: 3
247.078: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.078: DIMM 1 RttWr: 2
247.078: DIMM 1 RttWr: 2
247.078: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.078: DIMM 1 RttWr: 2
247.078: DIMM 1 RttNom: 3
247.078: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.078: DIMM 1 RttNom: 3
247.078: DIMM 1 RttWr: 2
247.078: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.078: DIMM 1 RttWr: 2
247.078: DIMM 0 RttNom: 3
247.078: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.078: DIMM 1 RttNom: 3
247.079: DIMM 0 RttWr: 2
247.079: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.079: DIMM 1 RttWr: 2
247.079: DIMM 0 RttNom: 3
247.079: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.079: DIMM 1 RttNom: 3
247.079: DIMM 0 RttWr: 2
247.079: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.079: DIMM 1 RttWr: 2
247.079: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.079: <09>Lane 00 new seed: 0047
247.079: <09>Lane 01 new seed: 0047
247.079: <09>Lane 02 new seed: 0047
247.079: <09>Lane 03 new seed: 0047
247.079: <09>Lane 04 new seed: 0047
247.079: <09>Lane 05 new seed: 0047
247.079: <09>Lane 06 new seed: 0047
247.079: <09>Lane 07 new seed: 0047
247.079: <09>Lane 08 new seed: 0047
247.079: <09>Lane 00 nibble 1 raw readback: 0046
247.079: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0046
247.079: <09>Lane 00 nibble 1 adjusted value (post nibble): 0046
247.079: <09>Lane 01 nibble 1 raw readback: 0042
247.079: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0042
247.079: <09>Lane 01 nibble 1 adjusted value (post nibble): 0044
247.079: <09>Lane 02 nibble 1 raw readback: 003e
247.079: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003e
247.079: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
247.079: <09>Lane 03 nibble 1 raw readback: 003b
247.079: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
247.079: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
247.079: <09>Lane 04 nibble 1 raw readback: 0038
247.079: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
247.079: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
247.079: <09>Lane 05 nibble 1 raw readback: 003b
247.079: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003b
247.079: <09>Lane 05 nibble 1 adjusted value (post nibble): 0041
247.079: <09>Lane 06 nibble 1 raw readback: 0040
247.079: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0040
247.079: <09>Lane 06 nibble 1 adjusted value (post nibble): 0043
247.079: <09>Lane 07 nibble 1 raw readback: 0044
247.079: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0044
247.079: <09>Lane 07 nibble 1 adjusted value (post nibble): 0045
247.079: <09>Lane 08 nibble 1 raw readback: 0037
247.079: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
247.079: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
247.079: <09>original critical gross delay: 0
247.079: <09>new critical gross delay: 0
247.079: DIMM 1 RttNom: 3
247.079: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.079: DIMM 1 RttNom: 3
247.079: DIMM 1 RttWr: 2
247.079: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.079: DIMM 1 RttWr: 2
247.079: DIMM 1 RttNom: 3
247.079: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.079: DIMM 1 RttNom: 3
247.079: DIMM 1 RttWr: 2
247.079: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.079: DIMM 1 RttWr: 2
247.079: DIMM 0 RttNom: 3
247.079: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.079: DIMM 1 RttNom: 3
247.079: DIMM 0 RttWr: 2
247.080: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.080: DIMM 1 RttWr: 2
247.080: DIMM 0 RttNom: 3
247.080: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.080: DIMM 1 RttNom: 3
247.080: DIMM 0 RttWr: 2
247.080: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.080: DIMM 1 RttWr: 2
247.080: SetTargetFreq: Start
247.080: SetTargetFreq: Node 1: New frequency code: 000a
247.080: ChangeMemClk: Start
247.080: set_2t_configuration: Start
247.080: set_2t_configuration: Done
247.080: mct_BeforePlatformSpec: Start
247.080: mct_BeforePlatformSpec: Done
247.080: mct_PlatformSpec: Start
247.080: Programmed DCT 0 timing/termination pattern 003a3c3a 30222222
247.080: mct_PlatformSpec: Done
247.080: set_2t_configuration: Start
247.080: set_2t_configuration: Done
247.080: mct_BeforePlatformSpec: Start
247.080: mct_BeforePlatformSpec: Done
247.080: mct_PlatformSpec: Start
247.080: Programmed DCT 1 timing/termination pattern 003a3c3a 30222222
247.080: mct_PlatformSpec: Done
247.080: ChangeMemClk: Done
247.080: phyAssistedMemFnceTraining: Start
247.080: phyAssistedMemFnceTraining: training node 1 DCT 0
247.080: phyAssistedMemFnceTraining: done training node 1 DCT 0
247.080: phyAssistedMemFnceTraining: training node 1 DCT 1
247.081: phyAssistedMemFnceTraining: done training node 1 DCT 1
247.081: phyAssistedMemFnceTraining: Done
247.081: InitPhyCompensation: DCT 0: Start
247.081: Waiting for predriver calibration to be applied...done!
247.081: InitPhyCompensation: DCT 0: Done
247.081: phyAssistedMemFnceTraining: Start
247.081: phyAssistedMemFnceTraining: training node 1 DCT 0
247.081: phyAssistedMemFnceTraining: done training node 1 DCT 0
247.081: phyAssistedMemFnceTraining: training node 1 DCT 1
247.081: phyAssistedMemFnceTraining: done training node 1 DCT 1
247.081: phyAssistedMemFnceTraining: Done
247.081: InitPhyCompensation: DCT 1: Start
247.081: Waiting for predriver calibration to be applied...done!
247.081: InitPhyCompensation: DCT 1: Done
247.081: Preparing to send DCT 0 DIMM 0 RC10: 01 (F2xA8: 02000300)
247.081: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.081: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
247.081: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.081: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
247.082: Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 02000c00)
247.082: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.082: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
247.082: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.082: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
247.082: Preparing to send DCT 1 DIMM 0 RC10: 01 (F2xA8: 02000300)
247.082: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.082: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
247.082: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.082: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
247.082: Preparing to send DCT 1 DIMM 1 RC10: 01 (F2xA8: 02000c00)
247.082: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.082: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
247.082: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.082: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
247.082: SetTargetFreq: Done
247.082: SPD2ndTiming: Start
247.082: SPD2ndTiming: Done
247.082: mct_BeforeDramInit_Prod_D: Start
247.082: mct_ProgramODT_D: Start
247.082: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
247.082: mct_ProgramODT_D: Done
247.082: mct_BeforeDramInit_Prod_D: Done
247.082: mct_DramInit_Sw_D: Start
247.082: DIMM 0 RttWr: 1
247.082: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.082: mct_SendMrsCmd: Start
247.082: mct_SendMrsCmd: Done
247.082: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
247.082: mct_SendMrsCmd: Start
247.082: mct_SendMrsCmd: Done
247.082: DIMM 0 RttNom: 3
247.082: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.082: mct_SendMrsCmd: Start
247.082: mct_SendMrsCmd: Done
247.082: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001978
247.082: mct_SendMrsCmd: Start
247.082: mct_SendMrsCmd: Done
247.082: DIMM 0 RttWr: 1
247.082: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.082: mct_SendMrsCmd: Start
247.082: mct_SendMrsCmd: Done
247.082: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
247.083: mct_SendMrsCmd: Start
247.083: mct_SendMrsCmd: Done
247.083: DIMM 0 RttNom: 3
247.083: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.083: mct_SendMrsCmd: Start
247.083: mct_SendMrsCmd: Done
247.083: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201978
247.083: mct_SendMrsCmd: Start
247.083: mct_SendMrsCmd: Done
247.083: DIMM 1 RttWr: 1
247.083: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.083: mct_SendMrsCmd: Start
247.083: mct_SendMrsCmd: Done
247.083: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
247.083: mct_SendMrsCmd: Start
247.083: mct_SendMrsCmd: Done
247.083: DIMM 1 RttNom: 3
247.083: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.083: mct_SendMrsCmd: Start
247.083: mct_SendMrsCmd: Done
247.083: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401978
247.083: mct_SendMrsCmd: Start
247.083: mct_SendMrsCmd: Done
247.083: DIMM 1 RttWr: 1
247.083: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.083: mct_SendMrsCmd: Start
247.083: mct_SendMrsCmd: Done
247.083: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
247.083: mct_SendMrsCmd: Start
247.083: mct_SendMrsCmd: Done
247.083: DIMM 1 RttNom: 3
247.083: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.083: mct_SendMrsCmd: Start
247.083: mct_SendMrsCmd: Done
247.083: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601978
247.083: mct_SendMrsCmd: Start
247.083: mct_SendMrsCmd: Done
247.083: mct_DramInit_Sw_D: Done
247.083: AgesaHwWlPhase1: training nibble 0
247.083: DIMM 0 RttNom: 3
247.083: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.083: DIMM 0 RttWr: 1
247.083: DIMM 0 RttWr: 1
247.083: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.083: DIMM 0 RttWr: 1
247.083: DIMM 0 RttNom: 3
247.083: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.083: DIMM 0 RttNom: 3
247.083: DIMM 0 RttWr: 1
247.083: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.083: DIMM 0 RttWr: 1
247.084: DIMM 1 RttNom: 3
247.084: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.084: DIMM 0 RttNom: 3
247.084: DIMM 1 RttWr: 1
247.084: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.084: DIMM 0 RttWr: 1
247.084: DIMM 1 RttNom: 3
247.084: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.084: DIMM 0 RttNom: 3
247.084: DIMM 1 RttWr: 1
247.084: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.084: DIMM 0 RttWr: 1
247.084: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.084: <09>Lane 00 scaled delay: 004e
247.084: <09>Lane 00 new seed: 004e
247.084: <09>Lane 01 scaled delay: 004b
247.084: <09>Lane 01 new seed: 004b
247.084: <09>Lane 02 scaled delay: 004a
247.084: <09>Lane 02 new seed: 004a
247.084: <09>Lane 03 scaled delay: 0049
247.084: <09>Lane 03 new seed: 0049
247.084: <09>Lane 04 scaled delay: 0045
247.084: <09>Lane 04 new seed: 0045
247.084: <09>Lane 05 scaled delay: 0049
247.084: <09>Lane 05 new seed: 0049
247.084: <09>Lane 06 scaled delay: 004a
247.084: <09>Lane 06 new seed: 004a
247.084: <09>Lane 07 scaled delay: 004d
247.084: <09>Lane 07 new seed: 004d
247.084: <09>Lane 08 scaled delay: 0045
247.084: <09>Lane 08 new seed: 0045
247.084: <09>Lane 00 nibble 0 raw readback: 004a
247.084: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004a
247.084: <09>Lane 00 nibble 0 adjusted value (post nibble): 004a
247.084: <09>Lane 01 nibble 0 raw readback: 0043
247.084: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0043
247.084: <09>Lane 01 nibble 0 adjusted value (post nibble): 0043
247.084: <09>Lane 02 nibble 0 raw readback: 0040
247.084: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0040
247.084: <09>Lane 02 nibble 0 adjusted value (post nibble): 0040
247.084: <09>Lane 03 nibble 0 raw readback: 003d
247.084: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003d
247.084: <09>Lane 03 nibble 0 adjusted value (post nibble): 003d
247.084: <09>Lane 04 nibble 0 raw readback: 003a
247.084: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
247.084: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
247.084: <09>Lane 05 nibble 0 raw readback: 003e
247.084: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003e
247.084: <09>Lane 05 nibble 0 adjusted value (post nibble): 003e
247.084: <09>Lane 06 nibble 0 raw readback: 0041
247.084: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0041
247.084: <09>Lane 06 nibble 0 adjusted value (post nibble): 0041
247.084: <09>Lane 07 nibble 0 raw readback: 0045
247.084: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0045
247.084: <09>Lane 07 nibble 0 adjusted value (post nibble): 0045
247.085: <09>Lane 08 nibble 0 raw readback: 0037
247.085: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0037
247.085: <09>Lane 08 nibble 0 adjusted value (post nibble): 0037
247.085: AgesaHwWlPhase1: training nibble 1
247.085: DIMM 0 RttNom: 3
247.085: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.085: DIMM 0 RttWr: 1
247.085: DIMM 0 RttWr: 1
247.085: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.085: DIMM 0 RttWr: 1
247.085: DIMM 0 RttNom: 3
247.085: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.085: DIMM 0 RttNom: 3
247.085: DIMM 0 RttWr: 1
247.085: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.085: DIMM 0 RttWr: 1
247.085: DIMM 1 RttNom: 3
247.085: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.085: DIMM 0 RttNom: 3
247.085: DIMM 1 RttWr: 1
247.085: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.085: DIMM 0 RttWr: 1
247.085: DIMM 1 RttNom: 3
247.085: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.085: DIMM 0 RttNom: 3
247.085: DIMM 1 RttWr: 1
247.085: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.085: DIMM 0 RttWr: 1
247.085: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.085: <09>Lane 00 new seed: 004e
247.085: <09>Lane 01 new seed: 004b
247.085: <09>Lane 02 new seed: 004a
247.085: <09>Lane 03 new seed: 0049
247.085: <09>Lane 04 new seed: 0045
247.085: <09>Lane 05 new seed: 0049
247.085: <09>Lane 06 new seed: 004a
247.085: <09>Lane 07 new seed: 004d
247.085: <09>Lane 08 new seed: 0045
247.085: <09>Lane 00 nibble 1 raw readback: 0048
247.085: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0048
247.085: <09>Lane 00 nibble 1 adjusted value (post nibble): 004b
247.085: <09>Lane 01 nibble 1 raw readback: 0043
247.085: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0043
247.085: <09>Lane 01 nibble 1 adjusted value (post nibble): 0047
247.085: <09>Lane 02 nibble 1 raw readback: 003f
247.085: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003f
247.085: <09>Lane 02 nibble 1 adjusted value (post nibble): 0044
247.085: <09>Lane 03 nibble 1 raw readback: 003e
247.085: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003e
247.085: <09>Lane 03 nibble 1 adjusted value (post nibble): 0043
247.085: <09>Lane 04 nibble 1 raw readback: 0039
247.085: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
247.085: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
247.085: <09>Lane 05 nibble 1 raw readback: 003f
247.085: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003f
247.085: <09>Lane 05 nibble 1 adjusted value (post nibble): 0044
247.085: <09>Lane 06 nibble 1 raw readback: 0042
247.085: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0042
247.085: <09>Lane 06 nibble 1 adjusted value (post nibble): 0046
247.085: <09>Lane 07 nibble 1 raw readback: 0045
247.085: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0045
247.085: <09>Lane 07 nibble 1 adjusted value (post nibble): 0049
247.085: <09>Lane 08 nibble 1 raw readback: 0036
247.085: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0036
247.085: <09>Lane 08 nibble 1 adjusted value (post nibble): 003d
247.085: <09>original critical gross delay: 0
247.085: <09>new critical gross delay: 0
247.086: DIMM 0 RttNom: 3
247.086: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.086: DIMM 0 RttNom: 3
247.086: DIMM 0 RttWr: 1
247.086: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.086: DIMM 0 RttWr: 1
247.086: DIMM 0 RttNom: 3
247.086: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.086: DIMM 0 RttNom: 3
247.086: DIMM 0 RttWr: 1
247.086: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.086: DIMM 0 RttWr: 1
247.086: DIMM 1 RttNom: 3
247.086: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.086: DIMM 0 RttNom: 3
247.086: DIMM 1 RttWr: 1
247.086: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.086: DIMM 0 RttWr: 1
247.086: DIMM 1 RttNom: 3
247.086: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.086: DIMM 0 RttNom: 3
247.086: DIMM 1 RttWr: 1
247.086: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.086: DIMM 0 RttWr: 1
247.086: AgesaHwWlPhase1: training nibble 0
247.086: DIMM 1 RttNom: 3
247.086: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.086: DIMM 1 RttWr: 1
247.086: DIMM 1 RttWr: 1
247.086: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.086: DIMM 1 RttWr: 1
247.086: DIMM 1 RttNom: 3
247.086: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.086: DIMM 1 RttNom: 3
247.086: DIMM 1 RttWr: 1
247.086: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.086: DIMM 1 RttWr: 1
247.086: DIMM 0 RttNom: 3
247.086: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.086: DIMM 1 RttNom: 3
247.086: DIMM 0 RttWr: 1
247.086: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.086: DIMM 1 RttWr: 1
247.086: DIMM 0 RttNom: 3
247.086: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.086: DIMM 1 RttNom: 3
247.086: DIMM 0 RttWr: 1
247.086: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.086: DIMM 1 RttWr: 1
247.086: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.086: <09>Lane 00 scaled delay: 0052
247.086: <09>Lane 00 new seed: 0052
247.086: <09>Lane 01 scaled delay: 004e
247.086: <09>Lane 01 new seed: 004e
247.086: <09>Lane 02 scaled delay: 004d
247.086: <09>Lane 02 new seed: 004d
247.086: <09>Lane 03 scaled delay: 004b
247.087: <09>Lane 03 new seed: 004b
247.086: <09>Lane 04 scaled delay: 0049
247.087: <09>Lane 04 new seed: 0049
247.087: <09>Lane 05 scaled delay: 004b
247.087: <09>Lane 05 new seed: 004b
247.087: <09>Lane 06 scaled delay: 004e
247.087: <09>Lane 06 new seed: 004e
247.087: <09>Lane 07 scaled delay: 004f
247.087: <09>Lane 07 new seed: 004f
247.087: <09>Lane 08 scaled delay: 0049
247.087: <09>Lane 08 new seed: 0049
247.087: <09>Lane 00 nibble 0 raw readback: 0051
247.087: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0051
247.087: <09>Lane 00 nibble 0 adjusted value (post nibble): 0051
247.087: <09>Lane 01 nibble 0 raw readback: 004b
247.087: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004b
247.087: <09>Lane 01 nibble 0 adjusted value (post nibble): 004b
247.087: <09>Lane 02 nibble 0 raw readback: 0046
247.087: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0046
247.087: <09>Lane 02 nibble 0 adjusted value (post nibble): 0046
247.087: <09>Lane 03 nibble 0 raw readback: 0046
247.087: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0046
247.087: <09>Lane 03 nibble 0 adjusted value (post nibble): 0046
247.087: <09>Lane 04 nibble 0 raw readback: 0042
247.087: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0042
247.087: <09>Lane 04 nibble 0 adjusted value (post nibble): 0042
247.087: <09>Lane 05 nibble 0 raw readback: 0048
247.087: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0048
247.087: <09>Lane 05 nibble 0 adjusted value (post nibble): 0048
247.087: <09>Lane 06 nibble 0 raw readback: 0049
247.087: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0049
247.087: <09>Lane 06 nibble 0 adjusted value (post nibble): 0049
247.087: <09>Lane 07 nibble 0 raw readback: 004e
247.087: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004e
247.087: <09>Lane 07 nibble 0 adjusted value (post nibble): 004e
247.087: <09>Lane 08 nibble 0 raw readback: 003f
247.087: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003f
247.087: <09>Lane 08 nibble 0 adjusted value (post nibble): 003f
247.087: AgesaHwWlPhase1: training nibble 1
247.087: DIMM 1 RttNom: 3
247.087: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.087: DIMM 1 RttWr: 1
247.087: DIMM 1 RttWr: 1
247.087: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.087: DIMM 1 RttWr: 1
247.087: DIMM 1 RttNom: 3
247.087: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.087: DIMM 1 RttNom: 3
247.087: DIMM 1 RttWr: 1
247.087: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.087: DIMM 1 RttWr: 1
247.087: DIMM 0 RttNom: 3
247.087: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.087: DIMM 1 RttNom: 3
247.087: DIMM 0 RttWr: 1
247.087: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.087: DIMM 1 RttWr: 1
247.087: DIMM 0 RttNom: 3
247.087: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.087: DIMM 1 RttNom: 3
247.087: DIMM 0 RttWr: 1
247.087: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.087: DIMM 1 RttWr: 1
247.087: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.087: <09>Lane 00 new seed: 0052
247.087: <09>Lane 01 new seed: 004e
247.087: <09>Lane 02 new seed: 004d
247.087: <09>Lane 03 new seed: 004b
247.087: <09>Lane 04 new seed: 0049
247.087: <09>Lane 05 new seed: 004b
247.087: <09>Lane 06 new seed: 004e
247.087: <09>Lane 07 new seed: 004f
247.087: <09>Lane 08 new seed: 0049
247.088: <09>Lane 00 nibble 1 raw readback: 0051
247.088: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0051
247.088: <09>Lane 00 nibble 1 adjusted value (post nibble): 0051
247.088: <09>Lane 01 nibble 1 raw readback: 004b
247.088: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004b
247.088: <09>Lane 01 nibble 1 adjusted value (post nibble): 004c
247.088: <09>Lane 02 nibble 1 raw readback: 0047
247.088: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0047
247.088: <09>Lane 02 nibble 1 adjusted value (post nibble): 004a
247.088: <09>Lane 03 nibble 1 raw readback: 0045
247.088: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
247.088: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
247.088: <09>Lane 04 nibble 1 raw readback: 0040
247.088: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0040
247.088: <09>Lane 04 nibble 1 adjusted value (post nibble): 0044
247.088: <09>Lane 05 nibble 1 raw readback: 0045
247.088: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0045
247.088: <09>Lane 05 nibble 1 adjusted value (post nibble): 0048
247.088: <09>Lane 06 nibble 1 raw readback: 0049
247.088: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0049
247.088: <09>Lane 06 nibble 1 adjusted value (post nibble): 004b
247.088: <09>Lane 07 nibble 1 raw readback: 004e
247.088: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004e
247.088: <09>Lane 07 nibble 1 adjusted value (post nibble): 004e
247.088: <09>Lane 08 nibble 1 raw readback: 003f
247.088: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003f
247.088: <09>Lane 08 nibble 1 adjusted value (post nibble): 0044
247.088: <09>original critical gross delay: 0
247.088: <09>new critical gross delay: 0
247.088: DIMM 1 RttNom: 3
247.088: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.088: DIMM 1 RttNom: 3
247.088: DIMM 1 RttWr: 1
247.088: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.088: DIMM 1 RttWr: 1
247.088: DIMM 1 RttNom: 3
247.088: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.088: DIMM 1 RttNom: 3
247.088: DIMM 1 RttWr: 1
247.088: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.088: DIMM 1 RttWr: 1
247.088: DIMM 0 RttNom: 3
247.088: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.088: DIMM 1 RttNom: 3
247.088: DIMM 0 RttWr: 1
247.088: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.088: DIMM 1 RttWr: 1
247.088: DIMM 0 RttNom: 3
247.088: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.088: DIMM 1 RttNom: 3
247.088: DIMM 0 RttWr: 1
247.088: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.088: DIMM 1 RttWr: 1
247.088: SPD2ndTiming: Start
247.089: SPD2ndTiming: Done
247.089: mct_BeforeDramInit_Prod_D: Start
247.089: mct_ProgramODT_D: Start
247.089: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
247.089: mct_ProgramODT_D: Done
247.089: mct_BeforeDramInit_Prod_D: Done
247.089: mct_DramInit_Sw_D: Start
247.089: DIMM 0 RttWr: 1
247.089: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.089: mct_SendMrsCmd: Start
247.089: mct_SendMrsCmd: Done
247.089: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
247.089: mct_SendMrsCmd: Start
247.089: mct_SendMrsCmd: Done
247.089: DIMM 0 RttNom: 3
247.089: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.089: mct_SendMrsCmd: Start
247.089: mct_SendMrsCmd: Done
247.089: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001978
247.089: mct_SendMrsCmd: Start
247.089: mct_SendMrsCmd: Done
247.089: DIMM 0 RttWr: 1
247.089: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.089: mct_SendMrsCmd: Start
247.089: mct_SendMrsCmd: Done
247.089: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
247.089: mct_SendMrsCmd: Start
247.089: mct_SendMrsCmd: Done
247.089: DIMM 0 RttNom: 3
247.089: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.089: mct_SendMrsCmd: Start
247.089: mct_SendMrsCmd: Done
247.089: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201978
247.089: mct_SendMrsCmd: Start
247.089: mct_SendMrsCmd: Done
247.089: DIMM 1 RttWr: 1
247.089: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.089: mct_SendMrsCmd: Start
247.089: mct_SendMrsCmd: Done
247.089: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
247.089: mct_SendMrsCmd: Start
247.089: mct_SendMrsCmd: Done
247.089: DIMM 1 RttNom: 3
247.089: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.089: mct_SendMrsCmd: Start
247.089: mct_SendMrsCmd: Done
247.089: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401978
247.089: mct_SendMrsCmd: Start
247.089: mct_SendMrsCmd: Done
247.089: DIMM 1 RttWr: 1
247.089: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.089: mct_SendMrsCmd: Start
247.089: mct_SendMrsCmd: Done
247.090: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
247.090: mct_SendMrsCmd: Start
247.090: mct_SendMrsCmd: Done
247.090: DIMM 1 RttNom: 3
247.090: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.090: mct_SendMrsCmd: Start
247.090: mct_SendMrsCmd: Done
247.090: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601978
247.090: mct_SendMrsCmd: Start
247.090: mct_SendMrsCmd: Done
247.090: mct_DramInit_Sw_D: Done
247.090: AgesaHwWlPhase1: training nibble 0
247.090: DIMM 0 RttNom: 3
247.090: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.090: DIMM 0 RttWr: 1
247.090: DIMM 0 RttWr: 1
247.090: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.090: DIMM 0 RttWr: 1
247.090: DIMM 0 RttNom: 3
247.090: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.090: DIMM 0 RttNom: 3
247.090: DIMM 0 RttWr: 1
247.090: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.090: DIMM 0 RttWr: 1
247.090: DIMM 1 RttNom: 3
247.090: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.090: DIMM 0 RttNom: 3
247.090: DIMM 1 RttWr: 1
247.090: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.090: DIMM 0 RttWr: 1
247.090: DIMM 1 RttNom: 3
247.090: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.090: DIMM 0 RttNom: 3
247.090: DIMM 1 RttWr: 1
247.090: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.090: DIMM 0 RttWr: 1
247.090: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.090: <09>Lane 00 scaled delay: 004e
247.090: <09>Lane 00 new seed: 004e
247.090: <09>Lane 01 scaled delay: 004d
247.090: <09>Lane 01 new seed: 004d
247.090: <09>Lane 02 scaled delay: 004a
247.090: <09>Lane 02 new seed: 004a
247.090: <09>Lane 03 scaled delay: 0047
247.090: <09>Lane 03 new seed: 0047
247.090: <09>Lane 04 scaled delay: 0046
247.090: <09>Lane 04 new seed: 0046
247.090: <09>Lane 05 scaled delay: 0049
247.090: <09>Lane 05 new seed: 0049
247.090: <09>Lane 06 scaled delay: 004b
247.090: <09>Lane 06 new seed: 004b
247.090: <09>Lane 07 scaled delay: 004e
247.090: <09>Lane 07 new seed: 004e
247.090: <09>Lane 08 scaled delay: 0045
247.090: <09>Lane 08 new seed: 0045
247.091: <09>Lane 00 nibble 0 raw readback: 004d
247.091: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004d
247.091: <09>Lane 00 nibble 0 adjusted value (post nibble): 004d
247.091: <09>Lane 01 nibble 0 raw readback: 0047
247.091: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0047
247.091: <09>Lane 01 nibble 0 adjusted value (post nibble): 0047
247.091: <09>Lane 02 nibble 0 raw readback: 0042
247.091: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0042
247.091: <09>Lane 02 nibble 0 adjusted value (post nibble): 0042
247.091: <09>Lane 03 nibble 0 raw readback: 003f
247.091: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003f
247.091: <09>Lane 03 nibble 0 adjusted value (post nibble): 003f
247.091: <09>Lane 04 nibble 0 raw readback: 003c
247.091: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003c
247.091: <09>Lane 04 nibble 0 adjusted value (post nibble): 003c
247.091: <09>Lane 05 nibble 0 raw readback: 0041
247.091: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0041
247.091: <09>Lane 05 nibble 0 adjusted value (post nibble): 0041
247.091: <09>Lane 06 nibble 0 raw readback: 0044
247.091: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0044
247.091: <09>Lane 06 nibble 0 adjusted value (post nibble): 0044
247.091: <09>Lane 07 nibble 0 raw readback: 004a
247.091: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004a
247.091: <09>Lane 07 nibble 0 adjusted value (post nibble): 004a
247.091: <09>Lane 08 nibble 0 raw readback: 0039
247.091: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0039
247.091: <09>Lane 08 nibble 0 adjusted value (post nibble): 0039
247.091: AgesaHwWlPhase1: training nibble 1
247.091: DIMM 0 RttNom: 3
247.091: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.091: DIMM 0 RttWr: 1
247.091: DIMM 0 RttWr: 1
247.091: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.091: DIMM 0 RttWr: 1
247.091: DIMM 0 RttNom: 3
247.091: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.091: DIMM 0 RttNom: 3
247.091: DIMM 0 RttWr: 1
247.091: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.091: DIMM 0 RttWr: 1
247.091: DIMM 1 RttNom: 3
247.091: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.091: DIMM 0 RttNom: 3
247.091: DIMM 1 RttWr: 1
247.091: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.091: DIMM 0 RttWr: 1
247.091: DIMM 1 RttNom: 3
247.091: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.091: DIMM 0 RttNom: 3
247.091: DIMM 1 RttWr: 1
247.091: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.091: DIMM 0 RttWr: 1
247.091: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.091: <09>Lane 00 new seed: 004e
247.091: <09>Lane 01 new seed: 004d
247.091: <09>Lane 02 new seed: 004a
247.091: <09>Lane 03 new seed: 0047
247.091: <09>Lane 04 new seed: 0046
247.091: <09>Lane 05 new seed: 0049
247.091: <09>Lane 06 new seed: 004b
247.091: <09>Lane 07 new seed: 004e
247.091: <09>Lane 08 new seed: 0045
247.091: <09>Lane 00 nibble 1 raw readback: 004d
247.091: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004d
247.091: <09>Lane 00 nibble 1 adjusted value (post nibble): 004d
247.091: <09>Lane 01 nibble 1 raw readback: 0048
247.091: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0048
247.092: <09>Lane 01 nibble 1 adjusted value (post nibble): 004a
247.091: <09>Lane 02 nibble 1 raw readback: 0042
247.092: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0042
247.092: <09>Lane 02 nibble 1 adjusted value (post nibble): 0046
247.092: <09>Lane 03 nibble 1 raw readback: 003e
247.092: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003e
247.092: <09>Lane 03 nibble 1 adjusted value (post nibble): 0042
247.092: <09>Lane 04 nibble 1 raw readback: 003b
247.092: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003b
247.092: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
247.092: <09>Lane 05 nibble 1 raw readback: 0040
247.092: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0040
247.092: <09>Lane 05 nibble 1 adjusted value (post nibble): 0044
247.092: <09>Lane 06 nibble 1 raw readback: 0045
247.092: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0045
247.092: <09>Lane 06 nibble 1 adjusted value (post nibble): 0048
247.092: <09>Lane 07 nibble 1 raw readback: 004b
247.092: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004b
247.092: <09>Lane 07 nibble 1 adjusted value (post nibble): 004c
247.092: <09>Lane 08 nibble 1 raw readback: 0039
247.092: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0039
247.092: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
247.092: <09>original critical gross delay: 0
247.092: <09>new critical gross delay: 0
247.092: DIMM 0 RttNom: 3
247.092: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.092: DIMM 0 RttNom: 3
247.092: DIMM 0 RttWr: 1
247.092: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.092: DIMM 0 RttWr: 1
247.092: DIMM 0 RttNom: 3
247.092: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.092: DIMM 0 RttNom: 3
247.092: DIMM 0 RttWr: 1
247.092: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.092: DIMM 0 RttWr: 1
247.092: DIMM 1 RttNom: 3
247.092: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.092: DIMM 0 RttNom: 3
247.092: DIMM 1 RttWr: 1
247.092: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.092: DIMM 0 RttWr: 1
247.092: DIMM 1 RttNom: 3
247.092: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.092: DIMM 0 RttNom: 3
247.092: DIMM 1 RttWr: 1
247.092: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.092: DIMM 0 RttWr: 1
247.092: AgesaHwWlPhase1: training nibble 0
247.092: DIMM 1 RttNom: 3
247.092: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.092: DIMM 1 RttWr: 1
247.092: DIMM 1 RttWr: 1
247.092: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.092: DIMM 1 RttWr: 1
247.092: DIMM 1 RttNom: 3
247.092: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.092: DIMM 1 RttNom: 3
247.092: DIMM 1 RttWr: 1
247.092: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.092: DIMM 1 RttWr: 1
247.092: DIMM 0 RttNom: 3
247.092: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.092: DIMM 1 RttNom: 3
247.093: DIMM 0 RttWr: 1
247.093: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.093: DIMM 1 RttWr: 1
247.093: DIMM 0 RttNom: 3
247.093: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.093: DIMM 1 RttNom: 3
247.093: DIMM 0 RttWr: 1
247.093: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.093: DIMM 1 RttWr: 1
247.093: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.093: <09>Lane 00 scaled delay: 0052
247.093: <09>Lane 00 new seed: 0052
247.093: <09>Lane 01 scaled delay: 004f
247.093: <09>Lane 01 new seed: 004f
247.093: <09>Lane 02 scaled delay: 004d
247.093: <09>Lane 02 new seed: 004d
247.093: <09>Lane 03 scaled delay: 004b
247.093: <09>Lane 03 new seed: 004b
247.093: <09>Lane 04 scaled delay: 0049
247.093: <09>Lane 04 new seed: 0049
247.093: <09>Lane 05 scaled delay: 004b
247.093: <09>Lane 05 new seed: 004b
247.093: <09>Lane 06 scaled delay: 004e
247.093: <09>Lane 06 new seed: 004e
247.093: <09>Lane 07 scaled delay: 0051
247.093: <09>Lane 07 new seed: 0051
247.093: <09>Lane 08 scaled delay: 0049
247.093: <09>Lane 08 new seed: 0049
247.093: <09>Lane 00 nibble 0 raw readback: 0050
247.093: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0050
247.093: <09>Lane 00 nibble 0 adjusted value (post nibble): 0050
247.093: <09>Lane 01 nibble 0 raw readback: 004e
247.093: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004e
247.093: <09>Lane 01 nibble 0 adjusted value (post nibble): 004e
247.093: <09>Lane 02 nibble 0 raw readback: 0049
247.093: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0049
247.093: <09>Lane 02 nibble 0 adjusted value (post nibble): 0049
247.093: <09>Lane 03 nibble 0 raw readback: 0044
247.093: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
247.093: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
247.093: <09>Lane 04 nibble 0 raw readback: 0042
247.093: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0042
247.093: <09>Lane 04 nibble 0 adjusted value (post nibble): 0042
247.093: <09>Lane 05 nibble 0 raw readback: 0047
247.093: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0047
247.093: <09>Lane 05 nibble 0 adjusted value (post nibble): 0047
247.093: <09>Lane 06 nibble 0 raw readback: 004d
247.093: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004d
247.093: <09>Lane 06 nibble 0 adjusted value (post nibble): 004d
247.093: <09>Lane 07 nibble 0 raw readback: 0050
247.093: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0050
247.093: <09>Lane 07 nibble 0 adjusted value (post nibble): 0050
247.093: <09>Lane 08 nibble 0 raw readback: 003e
247.093: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003e
247.093: <09>Lane 08 nibble 0 adjusted value (post nibble): 003e
247.093: AgesaHwWlPhase1: training nibble 1
247.093: DIMM 1 RttNom: 3
247.093: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.093: DIMM 1 RttWr: 1
247.093: DIMM 1 RttWr: 1
247.093: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.093: DIMM 1 RttWr: 1
247.093: DIMM 1 RttNom: 3
247.093: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.093: DIMM 1 RttNom: 3
247.093: DIMM 1 RttWr: 1
247.093: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.093: DIMM 1 RttWr: 1
247.093: DIMM 0 RttNom: 3
247.093: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.093: DIMM 1 RttNom: 3
247.094: DIMM 0 RttWr: 1
247.094: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.094: DIMM 1 RttWr: 1
247.094: DIMM 0 RttNom: 3
247.094: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.094: DIMM 1 RttNom: 3
247.094: DIMM 0 RttWr: 1
247.094: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.094: DIMM 1 RttWr: 1
247.094: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.094: <09>Lane 00 new seed: 0052
247.094: <09>Lane 01 new seed: 004f
247.094: <09>Lane 02 new seed: 004d
247.094: <09>Lane 03 new seed: 004b
247.094: <09>Lane 04 new seed: 0049
247.094: <09>Lane 05 new seed: 004b
247.094: <09>Lane 06 new seed: 004e
247.094: <09>Lane 07 new seed: 0051
247.094: <09>Lane 08 new seed: 0049
247.094: <09>Lane 00 nibble 1 raw readback: 0054
247.094: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0054
247.094: <09>Lane 00 nibble 1 adjusted value (post nibble): 0053
247.094: <09>Lane 01 nibble 1 raw readback: 004e
247.094: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004e
247.094: <09>Lane 01 nibble 1 adjusted value (post nibble): 004e
247.094: <09>Lane 02 nibble 1 raw readback: 0049
247.094: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0049
247.094: <09>Lane 02 nibble 1 adjusted value (post nibble): 004b
247.094: <09>Lane 03 nibble 1 raw readback: 0045
247.094: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
247.094: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
247.094: <09>Lane 04 nibble 1 raw readback: 0040
247.094: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0040
247.094: <09>Lane 04 nibble 1 adjusted value (post nibble): 0044
247.094: <09>Lane 05 nibble 1 raw readback: 0046
247.094: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0046
247.094: <09>Lane 05 nibble 1 adjusted value (post nibble): 0048
247.094: <09>Lane 06 nibble 1 raw readback: 004c
247.094: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004c
247.094: <09>Lane 06 nibble 1 adjusted value (post nibble): 004d
247.094: <09>Lane 07 nibble 1 raw readback: 0051
247.094: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0051
247.094: <09>Lane 07 nibble 1 adjusted value (post nibble): 0051
247.094: <09>Lane 08 nibble 1 raw readback: 0040
247.094: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0040
247.094: <09>Lane 08 nibble 1 adjusted value (post nibble): 0044
247.094: <09>original critical gross delay: 0
247.094: <09>new critical gross delay: 0
247.094: DIMM 1 RttNom: 3
247.094: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.094: DIMM 1 RttNom: 3
247.094: DIMM 1 RttWr: 1
247.094: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.094: DIMM 1 RttWr: 1
247.094: DIMM 1 RttNom: 3
247.094: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.094: DIMM 1 RttNom: 3
247.094: DIMM 1 RttWr: 1
247.094: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.094: DIMM 1 RttWr: 1
247.094: DIMM 0 RttNom: 3
247.094: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.094: DIMM 1 RttNom: 3
247.094: DIMM 0 RttWr: 1
247.094: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.094: DIMM 1 RttWr: 1
247.095: DIMM 0 RttNom: 3
247.095: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.095: DIMM 1 RttNom: 3
247.095: DIMM 0 RttWr: 1
247.095: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.095: DIMM 1 RttWr: 1
247.095: SetTargetFreq: Start
247.095: SetTargetFreq: Node 1: New frequency code: 000e
247.095: ChangeMemClk: Start
247.095: set_2t_configuration: Start
247.095: set_2t_configuration: Done
247.095: mct_BeforePlatformSpec: Start
247.095: mct_BeforePlatformSpec: Done
247.095: mct_PlatformSpec: Start
247.095: Programmed DCT 0 timing/termination pattern 00383a38 30222222
247.095: mct_PlatformSpec: Done
247.095: set_2t_configuration: Start
247.095: set_2t_configuration: Done
247.095: mct_BeforePlatformSpec: Start
247.095: mct_BeforePlatformSpec: Done
247.095: mct_PlatformSpec: Start
247.095: Programmed DCT 1 timing/termination pattern 00383a38 30222222
247.095: mct_PlatformSpec: Done
247.095: ChangeMemClk: Done
247.095: phyAssistedMemFnceTraining: Start
247.095: phyAssistedMemFnceTraining: training node 1 DCT 0
247.095: phyAssistedMemFnceTraining: done training node 1 DCT 0
247.095: phyAssistedMemFnceTraining: training node 1 DCT 1
247.095: phyAssistedMemFnceTraining: done training node 1 DCT 1
247.096: phyAssistedMemFnceTraining: Done
247.096: InitPhyCompensation: DCT 0: Start
247.096: Waiting for predriver calibration to be applied...done!
247.096: InitPhyCompensation: DCT 0: Done
247.096: phyAssistedMemFnceTraining: Start
247.096: phyAssistedMemFnceTraining: training node 1 DCT 0
247.096: phyAssistedMemFnceTraining: done training node 1 DCT 0
247.096: phyAssistedMemFnceTraining: training node 1 DCT 1
247.096: phyAssistedMemFnceTraining: done training node 1 DCT 1
247.096: phyAssistedMemFnceTraining: Done
247.096: InitPhyCompensation: DCT 1: Start
247.096: Waiting for predriver calibration to be applied...done!
247.096: InitPhyCompensation: DCT 1: Done
247.096: Preparing to send DCT 0 DIMM 0 RC10: 02 (F2xA8: 02000300)
247.096: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.096: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
247.096: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.096: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
247.096: Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 02000c00)
247.096: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.096: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
247.096: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.096: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
247.097: Preparing to send DCT 1 DIMM 0 RC10: 02 (F2xA8: 02000300)
247.097: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.097: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
247.097: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.097: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
247.097: Preparing to send DCT 1 DIMM 1 RC10: 02 (F2xA8: 02000c00)
247.097: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.097: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
247.097: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.097: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
247.097: SetTargetFreq: Done
247.097: SPD2ndTiming: Start
247.097: SPD2ndTiming: Done
247.097: mct_BeforeDramInit_Prod_D: Start
247.097: mct_ProgramODT_D: Start
247.097: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
247.097: mct_ProgramODT_D: Done
247.097: mct_BeforeDramInit_Prod_D: Done
247.097: mct_DramInit_Sw_D: Start
247.097: DIMM 0 RttWr: 2
247.097: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.097: mct_SendMrsCmd: Start
247.097: mct_SendMrsCmd: Done
247.097: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
247.097: mct_SendMrsCmd: Start
247.097: mct_SendMrsCmd: Done
247.097: DIMM 0 RttNom: 5
247.097: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.097: mct_SendMrsCmd: Start
247.097: mct_SendMrsCmd: Done
247.097: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001b78
247.097: mct_SendMrsCmd: Start
247.097: mct_SendMrsCmd: Done
247.097: DIMM 0 RttWr: 2
247.097: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.097: mct_SendMrsCmd: Start
247.097: mct_SendMrsCmd: Done
247.098: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
247.097: mct_SendMrsCmd: Start
247.098: mct_SendMrsCmd: Done
247.098: DIMM 0 RttNom: 5
247.098: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.098: mct_SendMrsCmd: Start
247.098: mct_SendMrsCmd: Done
247.098: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201b78
247.098: mct_SendMrsCmd: Start
247.098: mct_SendMrsCmd: Done
247.098: DIMM 1 RttWr: 2
247.098: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.098: mct_SendMrsCmd: Start
247.098: mct_SendMrsCmd: Done
247.098: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
247.098: mct_SendMrsCmd: Start
247.098: mct_SendMrsCmd: Done
247.098: DIMM 1 RttNom: 5
247.098: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.098: mct_SendMrsCmd: Start
247.098: mct_SendMrsCmd: Done
247.098: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b78
247.098: mct_SendMrsCmd: Start
247.098: mct_SendMrsCmd: Done
247.098: DIMM 1 RttWr: 2
247.098: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.098: mct_SendMrsCmd: Start
247.098: mct_SendMrsCmd: Done
247.098: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
247.098: mct_SendMrsCmd: Start
247.098: mct_SendMrsCmd: Done
247.098: DIMM 1 RttNom: 5
247.098: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.098: mct_SendMrsCmd: Start
247.098: mct_SendMrsCmd: Done
247.098: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b78
247.098: mct_SendMrsCmd: Start
247.098: mct_SendMrsCmd: Done
247.098: mct_DramInit_Sw_D: Done
247.098: AgesaHwWlPhase1: training nibble 0
247.098: DIMM 0 RttNom: 5
247.098: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.098: DIMM 0 RttWr: 2
247.098: DIMM 0 RttWr: 2
247.098: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.098: DIMM 0 RttWr: 2
247.098: DIMM 0 RttNom: 5
247.098: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.098: DIMM 0 RttNom: 5
247.098: DIMM 0 RttWr: 2
247.098: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.098: DIMM 0 RttWr: 2
247.098: DIMM 1 RttNom: 5
247.098: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.098: DIMM 0 RttNom: 5
247.098: DIMM 1 RttWr: 2
247.098: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.098: DIMM 0 RttWr: 2
247.098: DIMM 1 RttNom: 5
247.098: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.099: DIMM 0 RttNom: 5
247.099: DIMM 1 RttWr: 2
247.099: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.099: DIMM 0 RttWr: 2
247.099: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.099: <09>Lane 00 scaled delay: 0055
247.099: <09>Lane 00 new seed: 0055
247.099: <09>Lane 01 scaled delay: 0050
247.099: <09>Lane 01 new seed: 0050
247.099: <09>Lane 02 scaled delay: 004d
247.099: <09>Lane 02 new seed: 004d
247.099: <09>Lane 03 scaled delay: 004b
247.099: <09>Lane 03 new seed: 004b
247.099: <09>Lane 04 scaled delay: 0046
247.099: <09>Lane 04 new seed: 0046
247.099: <09>Lane 05 scaled delay: 004d
247.099: <09>Lane 05 new seed: 004d
247.099: <09>Lane 06 scaled delay: 004f
247.099: <09>Lane 06 new seed: 004f
247.099: <09>Lane 07 scaled delay: 0053
247.099: <09>Lane 07 new seed: 0053
247.099: <09>Lane 08 scaled delay: 0044
247.099: <09>Lane 08 new seed: 0044
247.099: <09>Lane 00 nibble 0 raw readback: 0056
247.099: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0056
247.099: <09>Lane 00 nibble 0 adjusted value (post nibble): 0056
247.099: <09>Lane 01 nibble 0 raw readback: 004f
247.099: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004f
247.099: <09>Lane 01 nibble 0 adjusted value (post nibble): 004f
247.099: <09>Lane 02 nibble 0 raw readback: 0049
247.099: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0049
247.099: <09>Lane 02 nibble 0 adjusted value (post nibble): 0049
247.099: <09>Lane 03 nibble 0 raw readback: 0047
247.099: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0047
247.099: <09>Lane 03 nibble 0 adjusted value (post nibble): 0047
247.099: <09>Lane 04 nibble 0 raw readback: 0042
247.099: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0042
247.099: <09>Lane 04 nibble 0 adjusted value (post nibble): 0042
247.099: <09>Lane 05 nibble 0 raw readback: 0048
247.099: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0048
247.099: <09>Lane 05 nibble 0 adjusted value (post nibble): 0048
247.099: <09>Lane 06 nibble 0 raw readback: 004b
247.099: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004b
247.099: <09>Lane 06 nibble 0 adjusted value (post nibble): 004b
247.099: <09>Lane 07 nibble 0 raw readback: 0050
247.099: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0050
247.099: <09>Lane 07 nibble 0 adjusted value (post nibble): 0050
247.099: <09>Lane 08 nibble 0 raw readback: 003e
247.099: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003e
247.099: <09>Lane 08 nibble 0 adjusted value (post nibble): 003e
247.099: AgesaHwWlPhase1: training nibble 1
247.099: DIMM 0 RttNom: 5
247.099: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.099: DIMM 0 RttWr: 2
247.100: DIMM 0 RttWr: 2
247.100: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.100: DIMM 0 RttWr: 2
247.100: DIMM 0 RttNom: 5
247.100: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.100: DIMM 0 RttNom: 5
247.100: DIMM 0 RttWr: 2
247.100: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.100: DIMM 0 RttWr: 2
247.100: DIMM 1 RttNom: 5
247.100: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.100: DIMM 0 RttNom: 5
247.100: DIMM 1 RttWr: 2
247.100: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.100: DIMM 0 RttWr: 2
247.100: DIMM 1 RttNom: 5
247.100: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.100: DIMM 0 RttNom: 5
247.100: DIMM 1 RttWr: 2
247.100: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.100: DIMM 0 RttWr: 2
247.100: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.100: <09>Lane 00 new seed: 0055
247.100: <09>Lane 01 new seed: 0050
247.100: <09>Lane 02 new seed: 004d
247.100: <09>Lane 03 new seed: 004b
247.100: <09>Lane 04 new seed: 0046
247.100: <09>Lane 05 new seed: 004d
247.100: <09>Lane 06 new seed: 004f
247.100: <09>Lane 07 new seed: 0053
247.100: <09>Lane 08 new seed: 0044
247.100: <09>Lane 00 nibble 1 raw readback: 0054
247.100: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0054
247.100: <09>Lane 00 nibble 1 adjusted value (post nibble): 0054
247.100: <09>Lane 01 nibble 1 raw readback: 004e
247.100: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004e
247.100: <09>Lane 01 nibble 1 adjusted value (post nibble): 004f
247.100: <09>Lane 02 nibble 1 raw readback: 0049
247.100: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0049
247.100: <09>Lane 02 nibble 1 adjusted value (post nibble): 004b
247.100: <09>Lane 03 nibble 1 raw readback: 0047
247.100: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0047
247.100: <09>Lane 03 nibble 1 adjusted value (post nibble): 0049
247.100: <09>Lane 04 nibble 1 raw readback: 0041
247.100: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0041
247.100: <09>Lane 04 nibble 1 adjusted value (post nibble): 0043
247.100: <09>Lane 05 nibble 1 raw readback: 0047
247.100: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0047
247.100: <09>Lane 05 nibble 1 adjusted value (post nibble): 004a
247.100: <09>Lane 06 nibble 1 raw readback: 004a
247.100: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004a
247.100: <09>Lane 06 nibble 1 adjusted value (post nibble): 004c
247.100: <09>Lane 07 nibble 1 raw readback: 004f
247.100: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004f
247.100: <09>Lane 07 nibble 1 adjusted value (post nibble): 0051
247.100: <09>Lane 08 nibble 1 raw readback: 003d
247.100: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003d
247.100: <09>Lane 08 nibble 1 adjusted value (post nibble): 0040
247.100: <09>original critical gross delay: 0
247.100: <09>new critical gross delay: 0
247.101: DIMM 0 RttNom: 5
247.100: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.101: DIMM 0 RttNom: 5
247.101: DIMM 0 RttWr: 2
247.101: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.101: DIMM 0 RttWr: 2
247.101: DIMM 0 RttNom: 5
247.101: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.101: DIMM 0 RttNom: 5
247.101: DIMM 0 RttWr: 2
247.101: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.101: DIMM 0 RttWr: 2
247.101: DIMM 1 RttNom: 5
247.101: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.101: DIMM 0 RttNom: 5
247.101: DIMM 1 RttWr: 2
247.101: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.101: DIMM 0 RttWr: 2
247.101: DIMM 1 RttNom: 5
247.101: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.101: DIMM 0 RttNom: 5
247.101: DIMM 1 RttWr: 2
247.101: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.101: DIMM 0 RttWr: 2
247.101: AgesaHwWlPhase1: training nibble 0
247.101: DIMM 1 RttNom: 5
247.101: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.101: DIMM 1 RttWr: 2
247.101: DIMM 1 RttWr: 2
247.101: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.101: DIMM 1 RttWr: 2
247.101: DIMM 1 RttNom: 5
247.101: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.101: DIMM 1 RttNom: 5
247.101: DIMM 1 RttWr: 2
247.101: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.101: DIMM 1 RttWr: 2
247.101: DIMM 0 RttNom: 5
247.101: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.101: DIMM 1 RttNom: 5
247.101: DIMM 0 RttWr: 2
247.101: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.101: DIMM 1 RttWr: 2
247.101: DIMM 0 RttNom: 5
247.101: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.101: DIMM 1 RttNom: 5
247.101: DIMM 0 RttWr: 2
247.101: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.101: DIMM 1 RttWr: 2
247.101: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.101: <09>Lane 00 scaled delay: 005d
247.101: <09>Lane 00 new seed: 005d
247.101: <09>Lane 01 scaled delay: 0057
247.101: <09>Lane 01 new seed: 0057
247.101: <09>Lane 02 scaled delay: 0054
247.101: <09>Lane 02 new seed: 0054
247.101: <09>Lane 03 scaled delay: 0052
247.101: <09>Lane 03 new seed: 0052
247.101: <09>Lane 04 scaled delay: 004d
247.101: <09>Lane 04 new seed: 004d
247.101: <09>Lane 05 scaled delay: 0052
247.101: <09>Lane 05 new seed: 0052
247.101: <09>Lane 06 scaled delay: 0055
247.101: <09>Lane 06 new seed: 0055
247.101: <09>Lane 07 scaled delay: 0059
247.101: <09>Lane 07 new seed: 0059
247.101: <09>Lane 08 scaled delay: 004d
247.101: <09>Lane 08 new seed: 004d
247.102: <09>Lane 00 nibble 0 raw readback: 005e
247.102: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005e
247.102: <09>Lane 00 nibble 0 adjusted value (post nibble): 005e
247.102: <09>Lane 01 nibble 0 raw readback: 0056
247.102: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0056
247.102: <09>Lane 01 nibble 0 adjusted value (post nibble): 0056
247.102: <09>Lane 02 nibble 0 raw readback: 004f
247.102: <09>Lane 02 nibble 0 adjusted value (pre nibble): 004f
247.102: <09>Lane 02 nibble 0 adjusted value (post nibble): 004f
247.102: <09>Lane 03 nibble 0 raw readback: 004e
247.102: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004e
247.102: <09>Lane 03 nibble 0 adjusted value (post nibble): 004e
247.102: <09>Lane 04 nibble 0 raw readback: 004a
247.102: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004a
247.102: <09>Lane 04 nibble 0 adjusted value (post nibble): 004a
247.102: <09>Lane 05 nibble 0 raw readback: 0051
247.102: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0051
247.102: <09>Lane 05 nibble 0 adjusted value (post nibble): 0051
247.102: <09>Lane 06 nibble 0 raw readback: 0051
247.102: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0051
247.102: <09>Lane 06 nibble 0 adjusted value (post nibble): 0051
247.102: <09>Lane 07 nibble 0 raw readback: 0059
247.102: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0059
247.102: <09>Lane 07 nibble 0 adjusted value (post nibble): 0059
247.102: <09>Lane 08 nibble 0 raw readback: 0045
247.102: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0045
247.102: <09>Lane 08 nibble 0 adjusted value (post nibble): 0045
247.102: AgesaHwWlPhase1: training nibble 1
247.102: DIMM 1 RttNom: 5
247.102: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.102: DIMM 1 RttWr: 2
247.102: DIMM 1 RttWr: 2
247.102: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.102: DIMM 1 RttWr: 2
247.102: DIMM 1 RttNom: 5
247.102: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.102: DIMM 1 RttNom: 5
247.102: DIMM 1 RttWr: 2
247.102: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.102: DIMM 1 RttWr: 2
247.102: DIMM 0 RttNom: 5
247.102: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.102: DIMM 1 RttNom: 5
247.102: DIMM 0 RttWr: 2
247.102: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.102: DIMM 1 RttWr: 2
247.102: DIMM 0 RttNom: 5
247.102: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.102: DIMM 1 RttNom: 5
247.102: DIMM 0 RttWr: 2
247.102: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.102: DIMM 1 RttWr: 2
247.102: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.102: <09>Lane 00 new seed: 005d
247.102: <09>Lane 01 new seed: 0057
247.102: <09>Lane 02 new seed: 0054
247.102: <09>Lane 03 new seed: 0052
247.102: <09>Lane 04 new seed: 004d
247.102: <09>Lane 05 new seed: 0052
247.102: <09>Lane 06 new seed: 0055
247.102: <09>Lane 07 new seed: 0059
247.102: <09>Lane 08 new seed: 004d
247.102: <09>Lane 00 nibble 1 raw readback: 005e
247.102: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005e
247.102: <09>Lane 00 nibble 1 adjusted value (post nibble): 005d
247.102: <09>Lane 01 nibble 1 raw readback: 0055
247.102: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0055
247.102: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
247.102: <09>Lane 02 nibble 1 raw readback: 004f
247.103: <09>Lane 02 nibble 1 adjusted value (pre nibble): 004f
247.102: <09>Lane 02 nibble 1 adjusted value (post nibble): 0051
247.103: <09>Lane 03 nibble 1 raw readback: 004d
247.102: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004d
247.103: <09>Lane 03 nibble 1 adjusted value (post nibble): 004f
247.103: <09>Lane 04 nibble 1 raw readback: 0048
247.103: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0048
247.103: <09>Lane 04 nibble 1 adjusted value (post nibble): 004a
247.103: <09>Lane 05 nibble 1 raw readback: 004e
247.103: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004e
247.103: <09>Lane 05 nibble 1 adjusted value (post nibble): 0050
247.103: <09>Lane 06 nibble 1 raw readback: 0051
247.103: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0051
247.103: <09>Lane 06 nibble 1 adjusted value (post nibble): 0053
247.103: <09>Lane 07 nibble 1 raw readback: 0058
247.103: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0058
247.103: <09>Lane 07 nibble 1 adjusted value (post nibble): 0058
247.103: <09>Lane 08 nibble 1 raw readback: 0047
247.103: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0047
247.103: <09>Lane 08 nibble 1 adjusted value (post nibble): 004a
247.103: <09>original critical gross delay: 0
247.103: <09>new critical gross delay: 0
247.103: DIMM 1 RttNom: 5
247.103: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.103: DIMM 1 RttNom: 5
247.103: DIMM 1 RttWr: 2
247.103: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.103: DIMM 1 RttWr: 2
247.103: DIMM 1 RttNom: 5
247.103: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.103: DIMM 1 RttNom: 5
247.103: DIMM 1 RttWr: 2
247.103: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.103: DIMM 1 RttWr: 2
247.103: DIMM 0 RttNom: 5
247.103: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.103: DIMM 1 RttNom: 5
247.103: DIMM 0 RttWr: 2
247.103: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.103: DIMM 1 RttWr: 2
247.103: DIMM 0 RttNom: 5
247.103: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.103: DIMM 1 RttNom: 5
247.103: DIMM 0 RttWr: 2
247.103: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.103: DIMM 1 RttWr: 2
247.103: SPD2ndTiming: Start
247.104: SPD2ndTiming: Done
247.104: mct_BeforeDramInit_Prod_D: Start
247.104: mct_ProgramODT_D: Start
247.104: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
247.104: mct_ProgramODT_D: Done
247.104: mct_BeforeDramInit_Prod_D: Done
247.104: mct_DramInit_Sw_D: Start
247.104: DIMM 0 RttWr: 2
247.104: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.104: mct_SendMrsCmd: Start
247.104: mct_SendMrsCmd: Done
247.104: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
247.104: mct_SendMrsCmd: Start
247.104: mct_SendMrsCmd: Done
247.104: DIMM 0 RttNom: 5
247.104: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.104: mct_SendMrsCmd: Start
247.104: mct_SendMrsCmd: Done
247.104: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001b78
247.104: mct_SendMrsCmd: Start
247.104: mct_SendMrsCmd: Done
247.104: DIMM 0 RttWr: 2
247.104: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.104: mct_SendMrsCmd: Start
247.104: mct_SendMrsCmd: Done
247.104: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
247.104: mct_SendMrsCmd: Start
247.104: mct_SendMrsCmd: Done
247.104: DIMM 0 RttNom: 5
247.104: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.104: mct_SendMrsCmd: Start
247.104: mct_SendMrsCmd: Done
247.104: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201b78
247.104: mct_SendMrsCmd: Start
247.104: mct_SendMrsCmd: Done
247.104: DIMM 1 RttWr: 2
247.104: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.104: mct_SendMrsCmd: Start
247.104: mct_SendMrsCmd: Done
247.104: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
247.104: mct_SendMrsCmd: Start
247.104: mct_SendMrsCmd: Done
247.104: DIMM 1 RttNom: 5
247.104: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.104: mct_SendMrsCmd: Start
247.104: mct_SendMrsCmd: Done
247.104: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401b78
247.104: mct_SendMrsCmd: Start
247.104: mct_SendMrsCmd: Done
247.104: DIMM 1 RttWr: 2
247.104: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.104: mct_SendMrsCmd: Start
247.104: mct_SendMrsCmd: Done
247.104: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
247.104: mct_SendMrsCmd: Start
247.104: mct_SendMrsCmd: Done
247.104: DIMM 1 RttNom: 5
247.104: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.104: mct_SendMrsCmd: Start
247.104: mct_SendMrsCmd: Done
247.104: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601b78
247.105: mct_SendMrsCmd: Start
247.105: mct_SendMrsCmd: Done
247.105: mct_DramInit_Sw_D: Done
247.105: AgesaHwWlPhase1: training nibble 0
247.105: DIMM 0 RttNom: 5
247.105: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.105: DIMM 0 RttWr: 2
247.105: DIMM 0 RttWr: 2
247.105: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.105: DIMM 0 RttWr: 2
247.105: DIMM 0 RttNom: 5
247.105: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.105: DIMM 0 RttNom: 5
247.105: DIMM 0 RttWr: 2
247.105: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.105: DIMM 0 RttWr: 2
247.105: DIMM 1 RttNom: 5
247.105: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.105: DIMM 0 RttNom: 5
247.105: DIMM 1 RttWr: 2
247.105: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.105: DIMM 0 RttWr: 2
247.105: DIMM 1 RttNom: 5
247.105: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.105: DIMM 0 RttNom: 5
247.105: DIMM 1 RttWr: 2
247.105: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.105: DIMM 0 RttWr: 2
247.105: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.105: <09>Lane 00 scaled delay: 0058
247.105: <09>Lane 00 new seed: 0058
247.105: <09>Lane 01 scaled delay: 0054
247.105: <09>Lane 01 new seed: 0054
247.105: <09>Lane 02 scaled delay: 004f
247.105: <09>Lane 02 new seed: 004f
247.105: <09>Lane 03 scaled delay: 004a
247.105: <09>Lane 03 new seed: 004a
247.105: <09>Lane 04 scaled delay: 0048
247.105: <09>Lane 04 new seed: 0048
247.105: <09>Lane 05 scaled delay: 004d
247.105: <09>Lane 05 new seed: 004d
247.105: <09>Lane 06 scaled delay: 0052
247.105: <09>Lane 06 new seed: 0052
247.105: <09>Lane 07 scaled delay: 0057
247.105: <09>Lane 07 new seed: 0057
247.105: <09>Lane 08 scaled delay: 0046
247.105: <09>Lane 08 new seed: 0046
247.105: <09>Lane 00 nibble 0 raw readback: 0058
247.105: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0058
247.105: <09>Lane 00 nibble 0 adjusted value (post nibble): 0058
247.106: <09>Lane 01 nibble 0 raw readback: 0050
247.106: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0050
247.106: <09>Lane 01 nibble 0 adjusted value (post nibble): 0050
247.106: <09>Lane 02 nibble 0 raw readback: 004d
247.106: <09>Lane 02 nibble 0 adjusted value (pre nibble): 004d
247.106: <09>Lane 02 nibble 0 adjusted value (post nibble): 004d
247.106: <09>Lane 03 nibble 0 raw readback: 0047
247.106: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0047
247.106: <09>Lane 03 nibble 0 adjusted value (post nibble): 0047
247.106: <09>Lane 04 nibble 0 raw readback: 0043
247.106: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0043
247.106: <09>Lane 04 nibble 0 adjusted value (post nibble): 0043
247.106: <09>Lane 05 nibble 0 raw readback: 004b
247.106: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004b
247.106: <09>Lane 05 nibble 0 adjusted value (post nibble): 004b
247.106: <09>Lane 06 nibble 0 raw readback: 004e
247.106: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004e
247.106: <09>Lane 06 nibble 0 adjusted value (post nibble): 004e
247.106: <09>Lane 07 nibble 0 raw readback: 0055
247.106: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0055
247.106: <09>Lane 07 nibble 0 adjusted value (post nibble): 0055
247.106: <09>Lane 08 nibble 0 raw readback: 0041
247.106: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0041
247.106: <09>Lane 08 nibble 0 adjusted value (post nibble): 0041
247.106: AgesaHwWlPhase1: training nibble 1
247.106: DIMM 0 RttNom: 5
247.106: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.106: DIMM 0 RttWr: 2
247.106: DIMM 0 RttWr: 2
247.106: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.106: DIMM 0 RttWr: 2
247.106: DIMM 0 RttNom: 5
247.106: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.106: DIMM 0 RttNom: 5
247.106: DIMM 0 RttWr: 2
247.106: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.106: DIMM 0 RttWr: 2
247.106: DIMM 1 RttNom: 5
247.106: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.106: DIMM 0 RttNom: 5
247.106: DIMM 1 RttWr: 2
247.106: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.106: DIMM 0 RttWr: 2
247.106: DIMM 1 RttNom: 5
247.106: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.106: DIMM 0 RttNom: 5
247.106: DIMM 1 RttWr: 2
247.106: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.106: DIMM 0 RttWr: 2
247.106: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.106: <09>Lane 00 new seed: 0058
247.106: <09>Lane 01 new seed: 0054
247.106: <09>Lane 02 new seed: 004f
247.106: <09>Lane 03 new seed: 004a
247.106: <09>Lane 04 new seed: 0048
247.106: <09>Lane 05 new seed: 004d
247.106: <09>Lane 06 new seed: 0052
247.106: <09>Lane 07 new seed: 0057
247.106: <09>Lane 08 new seed: 0046
247.106: <09>Lane 00 nibble 1 raw readback: 0058
247.106: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0058
247.106: <09>Lane 00 nibble 1 adjusted value (post nibble): 0058
247.106: <09>Lane 01 nibble 1 raw readback: 0051
247.106: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0051
247.106: <09>Lane 01 nibble 1 adjusted value (post nibble): 0052
247.106: <09>Lane 02 nibble 1 raw readback: 004c
247.106: <09>Lane 02 nibble 1 adjusted value (pre nibble): 004c
247.106: <09>Lane 02 nibble 1 adjusted value (post nibble): 004d
247.107: <09>Lane 03 nibble 1 raw readback: 0048
247.106: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0048
247.106: <09>Lane 03 nibble 1 adjusted value (post nibble): 0049
247.106: <09>Lane 04 nibble 1 raw readback: 0042
247.107: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0042
247.107: <09>Lane 04 nibble 1 adjusted value (post nibble): 0045
247.107: <09>Lane 05 nibble 1 raw readback: 004a
247.107: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004a
247.107: <09>Lane 05 nibble 1 adjusted value (post nibble): 004b
247.107: <09>Lane 06 nibble 1 raw readback: 004f
247.107: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004f
247.107: <09>Lane 06 nibble 1 adjusted value (post nibble): 0050
247.107: <09>Lane 07 nibble 1 raw readback: 0056
247.107: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0056
247.107: <09>Lane 07 nibble 1 adjusted value (post nibble): 0056
247.107: <09>Lane 08 nibble 1 raw readback: 0040
247.107: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0040
247.107: <09>Lane 08 nibble 1 adjusted value (post nibble): 0043
247.107: <09>original critical gross delay: 0
247.107: <09>new critical gross delay: 0
247.107: DIMM 0 RttNom: 5
247.107: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.107: DIMM 0 RttNom: 5
247.107: DIMM 0 RttWr: 2
247.107: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.107: DIMM 0 RttWr: 2
247.107: DIMM 0 RttNom: 5
247.107: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.107: DIMM 0 RttNom: 5
247.107: DIMM 0 RttWr: 2
247.107: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.107: DIMM 0 RttWr: 2
247.107: DIMM 1 RttNom: 5
247.107: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.107: DIMM 0 RttNom: 5
247.107: DIMM 1 RttWr: 2
247.107: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.107: DIMM 0 RttWr: 2
247.107: DIMM 1 RttNom: 5
247.107: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.107: DIMM 0 RttNom: 5
247.107: DIMM 1 RttWr: 2
247.107: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.107: DIMM 0 RttWr: 2
247.107: AgesaHwWlPhase1: training nibble 0
247.107: DIMM 1 RttNom: 5
247.107: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.107: DIMM 1 RttWr: 2
247.107: DIMM 1 RttWr: 2
247.107: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.107: DIMM 1 RttWr: 2
247.107: DIMM 1 RttNom: 5
247.107: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.107: DIMM 1 RttNom: 5
247.107: DIMM 1 RttWr: 2
247.107: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.107: DIMM 1 RttWr: 2
247.107: DIMM 0 RttNom: 5
247.107: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.107: DIMM 1 RttNom: 5
247.107: DIMM 0 RttWr: 2
247.107: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.107: DIMM 1 RttWr: 2
247.108: DIMM 0 RttNom: 5
247.108: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.108: DIMM 1 RttNom: 5
247.108: DIMM 0 RttWr: 2
247.108: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.108: DIMM 1 RttWr: 2
247.108: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.108: <09>Lane 00 scaled delay: 005f
247.108: <09>Lane 00 new seed: 005f
247.108: <09>Lane 01 scaled delay: 0059
247.108: <09>Lane 01 new seed: 0059
247.108: <09>Lane 02 scaled delay: 0055
247.108: <09>Lane 02 new seed: 0055
247.108: <09>Lane 03 scaled delay: 0052
247.108: <09>Lane 03 new seed: 0052
247.108: <09>Lane 04 scaled delay: 004d
247.108: <09>Lane 04 new seed: 004d
247.108: <09>Lane 05 scaled delay: 0052
247.108: <09>Lane 05 new seed: 0052
247.108: <09>Lane 06 scaled delay: 0058
247.108: <09>Lane 06 new seed: 0058
247.108: <09>Lane 07 scaled delay: 005d
247.108: <09>Lane 07 new seed: 005d
247.108: <09>Lane 08 scaled delay: 004d
247.108: <09>Lane 08 new seed: 004d
247.108: <09>Lane 00 nibble 0 raw readback: 005c
247.108: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005c
247.108: <09>Lane 00 nibble 0 adjusted value (post nibble): 005c
247.108: <09>Lane 01 nibble 0 raw readback: 0059
247.108: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0059
247.108: <09>Lane 01 nibble 0 adjusted value (post nibble): 0059
247.108: <09>Lane 02 nibble 0 raw readback: 0053
247.108: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0053
247.108: <09>Lane 02 nibble 0 adjusted value (post nibble): 0053
247.108: <09>Lane 03 nibble 0 raw readback: 004d
247.108: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004d
247.108: <09>Lane 03 nibble 0 adjusted value (post nibble): 004d
247.108: <09>Lane 04 nibble 0 raw readback: 004a
247.108: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004a
247.108: <09>Lane 04 nibble 0 adjusted value (post nibble): 004a
247.108: <09>Lane 05 nibble 0 raw readback: 0051
247.108: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0051
247.108: <09>Lane 05 nibble 0 adjusted value (post nibble): 0051
247.108: <09>Lane 06 nibble 0 raw readback: 0058
247.108: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0058
247.108: <09>Lane 06 nibble 0 adjusted value (post nibble): 0058
247.108: <09>Lane 07 nibble 0 raw readback: 005b
247.108: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005b
247.108: <09>Lane 07 nibble 0 adjusted value (post nibble): 005b
247.108: <09>Lane 08 nibble 0 raw readback: 0047
247.108: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0047
247.108: <09>Lane 08 nibble 0 adjusted value (post nibble): 0047
247.108: AgesaHwWlPhase1: training nibble 1
247.108: DIMM 1 RttNom: 5
247.108: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.108: DIMM 1 RttWr: 2
247.108: DIMM 1 RttWr: 2
247.108: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.108: DIMM 1 RttWr: 2
247.108: DIMM 1 RttNom: 5
247.108: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.108: DIMM 1 RttNom: 5
247.108: DIMM 1 RttWr: 2
247.108: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.108: DIMM 1 RttWr: 2
247.108: DIMM 0 RttNom: 5
247.108: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.108: DIMM 1 RttNom: 5
247.108: DIMM 0 RttWr: 2
247.108: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.108: DIMM 1 RttWr: 2
247.108: DIMM 0 RttNom: 5
247.108: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.109: DIMM 1 RttNom: 5
247.109: DIMM 0 RttWr: 2
247.109: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.109: DIMM 1 RttWr: 2
247.109: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.109: <09>Lane 00 new seed: 005f
247.109: <09>Lane 01 new seed: 0059
247.109: <09>Lane 02 new seed: 0055
247.109: <09>Lane 03 new seed: 0052
247.109: <09>Lane 04 new seed: 004d
247.109: <09>Lane 05 new seed: 0052
247.109: <09>Lane 06 new seed: 0058
247.109: <09>Lane 07 new seed: 005d
247.109: <09>Lane 08 new seed: 004d
247.109: <09>Lane 00 nibble 1 raw readback: 005f
247.109: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005f
247.109: <09>Lane 00 nibble 1 adjusted value (post nibble): 005f
247.109: <09>Lane 01 nibble 1 raw readback: 005a
247.109: <09>Lane 01 nibble 1 adjusted value (pre nibble): 005a
247.109: <09>Lane 01 nibble 1 adjusted value (post nibble): 0059
247.109: <09>Lane 02 nibble 1 raw readback: 0053
247.109: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0053
247.109: <09>Lane 02 nibble 1 adjusted value (post nibble): 0054
247.109: <09>Lane 03 nibble 1 raw readback: 004e
247.109: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004e
247.109: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
247.109: <09>Lane 04 nibble 1 raw readback: 0049
247.109: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0049
247.109: <09>Lane 04 nibble 1 adjusted value (post nibble): 004b
247.109: <09>Lane 05 nibble 1 raw readback: 004f
247.109: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004f
247.109: <09>Lane 05 nibble 1 adjusted value (post nibble): 0050
247.109: <09>Lane 06 nibble 1 raw readback: 0057
247.109: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0057
247.109: <09>Lane 06 nibble 1 adjusted value (post nibble): 0057
247.109: <09>Lane 07 nibble 1 raw readback: 005d
247.109: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005d
247.109: <09>Lane 07 nibble 1 adjusted value (post nibble): 005d
247.109: <09>Lane 08 nibble 1 raw readback: 0048
247.109: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0048
247.109: <09>Lane 08 nibble 1 adjusted value (post nibble): 004a
247.109: <09>original critical gross delay: 0
247.109: <09>new critical gross delay: 0
247.109: DIMM 1 RttNom: 5
247.109: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.109: DIMM 1 RttNom: 5
247.109: DIMM 1 RttWr: 2
247.109: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.109: DIMM 1 RttWr: 2
247.109: DIMM 1 RttNom: 5
247.109: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.109: DIMM 1 RttNom: 5
247.109: DIMM 1 RttWr: 2
247.109: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.109: DIMM 1 RttWr: 2
247.109: DIMM 0 RttNom: 5
247.109: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.109: DIMM 1 RttNom: 5
247.109: DIMM 0 RttWr: 2
247.109: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.109: DIMM 1 RttWr: 2
247.109: DIMM 0 RttNom: 5
247.109: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.109: DIMM 1 RttNom: 5
247.109: DIMM 0 RttWr: 2
247.110: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.110: DIMM 1 RttWr: 2
247.110: SetTargetFreq: Start
247.110: SetTargetFreq: Node 1: New frequency code: 0012
247.110: ChangeMemClk: Start
247.110: set_2t_configuration: Start
247.110: set_2t_configuration: Done
247.110: mct_BeforePlatformSpec: Start
247.110: mct_BeforePlatformSpec: Done
247.110: mct_PlatformSpec: Start
247.110: Programmed DCT 0 timing/termination pattern 00353935 30222222
247.110: mct_PlatformSpec: Done
247.110: set_2t_configuration: Start
247.110: set_2t_configuration: Done
247.110: mct_BeforePlatformSpec: Start
247.110: mct_BeforePlatformSpec: Done
247.110: mct_PlatformSpec: Start
247.110: Programmed DCT 1 timing/termination pattern 00353935 30222222
247.110: mct_PlatformSpec: Done
247.110: ChangeMemClk: Done
247.110: phyAssistedMemFnceTraining: Start
247.110: phyAssistedMemFnceTraining: training node 1 DCT 0
247.110: phyAssistedMemFnceTraining: done training node 1 DCT 0
247.110: phyAssistedMemFnceTraining: training node 1 DCT 1
247.110: phyAssistedMemFnceTraining: done training node 1 DCT 1
247.110: phyAssistedMemFnceTraining: Done
247.110: InitPhyCompensation: DCT 0: Start
247.111: Waiting for predriver calibration to be applied...done!
247.111: InitPhyCompensation: DCT 0: Done
247.111: phyAssistedMemFnceTraining: Start
247.111: phyAssistedMemFnceTraining: training node 1 DCT 0
247.111: phyAssistedMemFnceTraining: done training node 1 DCT 0
247.111: phyAssistedMemFnceTraining: training node 1 DCT 1
247.111: phyAssistedMemFnceTraining: done training node 1 DCT 1
247.111: phyAssistedMemFnceTraining: Done
247.111: InitPhyCompensation: DCT 1: Start
247.111: Waiting for predriver calibration to be applied...done!
247.111: InitPhyCompensation: DCT 1: Done
247.111: Preparing to send DCT 0 DIMM 0 RC10: 03 (F2xA8: 02000300)
247.111: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.111: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
247.111: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.111: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
247.111: Preparing to send DCT 0 DIMM 1 RC10: 03 (F2xA8: 02000c00)
247.111: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.111: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
247.111: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.111: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
247.111: Preparing to send DCT 1 DIMM 0 RC10: 03 (F2xA8: 02000300)
247.111: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.111: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
247.111: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.111: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
247.111: Preparing to send DCT 1 DIMM 1 RC10: 03 (F2xA8: 02000c00)
247.111: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.111: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
247.111: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.111: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
247.112: SetTargetFreq: Done
247.112: SPD2ndTiming: Start
247.112: SPD2ndTiming: Done
247.112: mct_BeforeDramInit_Prod_D: Start
247.112: mct_ProgramODT_D: Start
247.112: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
247.112: mct_ProgramODT_D: Done
247.112: mct_BeforeDramInit_Prod_D: Done
247.112: mct_DramInit_Sw_D: Start
247.112: DIMM 0 RttWr: 1
247.112: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.112: mct_SendMrsCmd: Start
247.112: mct_SendMrsCmd: Done
247.112: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
247.112: mct_SendMrsCmd: Start
247.112: mct_SendMrsCmd: Done
247.112: DIMM 0 RttNom: 4
247.112: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.112: mct_SendMrsCmd: Start
247.112: mct_SendMrsCmd: Done
247.112: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001d78
247.112: mct_SendMrsCmd: Start
247.112: mct_SendMrsCmd: Done
247.112: DIMM 0 RttWr: 1
247.112: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.112: mct_SendMrsCmd: Start
247.112: mct_SendMrsCmd: Done
247.112: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
247.112: mct_SendMrsCmd: Start
247.112: mct_SendMrsCmd: Done
247.112: DIMM 0 RttNom: 4
247.112: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.112: mct_SendMrsCmd: Start
247.112: mct_SendMrsCmd: Done
247.112: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201d78
247.112: mct_SendMrsCmd: Start
247.112: mct_SendMrsCmd: Done
247.112: DIMM 1 RttWr: 1
247.113: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.112: mct_SendMrsCmd: Start
247.112: mct_SendMrsCmd: Done
247.112: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
247.113: mct_SendMrsCmd: Start
247.113: mct_SendMrsCmd: Done
247.113: DIMM 1 RttNom: 4
247.113: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.113: mct_SendMrsCmd: Start
247.113: mct_SendMrsCmd: Done
247.113: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401d78
247.113: mct_SendMrsCmd: Start
247.113: mct_SendMrsCmd: Done
247.113: DIMM 1 RttWr: 1
247.113: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.113: mct_SendMrsCmd: Start
247.113: mct_SendMrsCmd: Done
247.113: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
247.113: mct_SendMrsCmd: Start
247.113: mct_SendMrsCmd: Done
247.113: DIMM 1 RttNom: 4
247.113: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.113: mct_SendMrsCmd: Start
247.113: mct_SendMrsCmd: Done
247.113: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601d78
247.113: mct_SendMrsCmd: Start
247.113: mct_SendMrsCmd: Done
247.113: mct_DramInit_Sw_D: Done
247.113: AgesaHwWlPhase1: training nibble 0
247.113: DIMM 0 RttNom: 4
247.113: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.113: DIMM 0 RttWr: 1
247.113: DIMM 0 RttWr: 1
247.113: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.113: DIMM 0 RttWr: 1
247.113: DIMM 0 RttNom: 4
247.113: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.113: DIMM 0 RttNom: 4
247.113: DIMM 0 RttWr: 1
247.113: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.113: DIMM 0 RttWr: 1
247.113: DIMM 1 RttNom: 4
247.113: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.113: DIMM 0 RttNom: 4
247.113: DIMM 1 RttWr: 1
247.113: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.113: DIMM 0 RttWr: 1
247.113: DIMM 1 RttNom: 4
247.113: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.113: DIMM 0 RttNom: 4
247.113: DIMM 1 RttWr: 1
247.113: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.113: DIMM 0 RttWr: 1
247.113: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.114: <09>Lane 00 scaled delay: 005e
247.114: <09>Lane 00 new seed: 005e
247.114: <09>Lane 01 scaled delay: 0058
247.114: <09>Lane 01 new seed: 0058
247.114: <09>Lane 02 scaled delay: 0053
247.114: <09>Lane 02 new seed: 0053
247.114: <09>Lane 03 scaled delay: 0051
247.114: <09>Lane 03 new seed: 0051
247.114: <09>Lane 04 scaled delay: 0049
247.114: <09>Lane 04 new seed: 0049
247.114: <09>Lane 05 scaled delay: 0052
247.114: <09>Lane 05 new seed: 0052
247.114: <09>Lane 06 scaled delay: 0054
247.114: <09>Lane 06 new seed: 0054
247.114: <09>Lane 07 scaled delay: 005a
247.114: <09>Lane 07 new seed: 005a
247.114: <09>Lane 08 scaled delay: 0046
247.114: <09>Lane 08 new seed: 0046
247.114: <09>Lane 00 nibble 0 raw readback: 0066
247.114: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0066
247.114: <09>Lane 00 nibble 0 adjusted value (post nibble): 0066
247.114: <09>Lane 01 nibble 0 raw readback: 005e
247.114: <09>Lane 01 nibble 0 adjusted value (pre nibble): 005e
247.114: <09>Lane 01 nibble 0 adjusted value (post nibble): 005e
247.114: <09>Lane 02 nibble 0 raw readback: 0055
247.114: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0055
247.114: <09>Lane 02 nibble 0 adjusted value (post nibble): 0055
247.114: <09>Lane 03 nibble 0 raw readback: 0051
247.114: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0051
247.114: <09>Lane 03 nibble 0 adjusted value (post nibble): 0051
247.114: <09>Lane 04 nibble 0 raw readback: 004d
247.114: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004d
247.114: <09>Lane 04 nibble 0 adjusted value (post nibble): 004d
247.114: <09>Lane 05 nibble 0 raw readback: 0053
247.114: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0053
247.114: <09>Lane 05 nibble 0 adjusted value (post nibble): 0053
247.114: <09>Lane 06 nibble 0 raw readback: 0057
247.114: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0057
247.114: <09>Lane 06 nibble 0 adjusted value (post nibble): 0057
247.114: <09>Lane 07 nibble 0 raw readback: 0060
247.114: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0060
247.114: <09>Lane 07 nibble 0 adjusted value (post nibble): 0060
247.114: <09>Lane 08 nibble 0 raw readback: 004a
247.114: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004a
247.114: <09>Lane 08 nibble 0 adjusted value (post nibble): 004a
247.114: AgesaHwWlPhase1: training nibble 1
247.114: DIMM 0 RttNom: 4
247.114: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.114: DIMM 0 RttWr: 1
247.114: DIMM 0 RttWr: 1
247.114: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.114: DIMM 0 RttWr: 1
247.114: DIMM 0 RttNom: 4
247.114: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.114: DIMM 0 RttNom: 4
247.115: DIMM 0 RttWr: 1
247.115: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.115: DIMM 0 RttWr: 1
247.115: DIMM 1 RttNom: 4
247.115: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.115: DIMM 0 RttNom: 4
247.115: DIMM 1 RttWr: 1
247.115: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.115: DIMM 0 RttWr: 1
247.115: DIMM 1 RttNom: 4
247.115: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.115: DIMM 0 RttNom: 4
247.115: DIMM 1 RttWr: 1
247.115: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.115: DIMM 0 RttWr: 1
247.115: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.115: <09>Lane 00 new seed: 005e
247.115: <09>Lane 01 new seed: 0058
247.115: <09>Lane 02 new seed: 0053
247.115: <09>Lane 03 new seed: 0051
247.115: <09>Lane 04 new seed: 0049
247.115: <09>Lane 05 new seed: 0052
247.115: <09>Lane 06 new seed: 0054
247.115: <09>Lane 07 new seed: 005a
247.115: <09>Lane 08 new seed: 0046
247.115: <09>Lane 00 nibble 1 raw readback: 0064
247.115: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0064
247.115: <09>Lane 00 nibble 1 adjusted value (post nibble): 0061
247.115: <09>Lane 01 nibble 1 raw readback: 005d
247.115: <09>Lane 01 nibble 1 adjusted value (pre nibble): 005d
247.115: <09>Lane 01 nibble 1 adjusted value (post nibble): 005a
247.115: <09>Lane 02 nibble 1 raw readback: 0055
247.115: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0055
247.115: <09>Lane 02 nibble 1 adjusted value (post nibble): 0054
247.115: <09>Lane 03 nibble 1 raw readback: 0052
247.115: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0052
247.115: <09>Lane 03 nibble 1 adjusted value (post nibble): 0051
247.115: <09>Lane 04 nibble 1 raw readback: 004b
247.115: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004b
247.115: <09>Lane 04 nibble 1 adjusted value (post nibble): 004a
247.115: <09>Lane 05 nibble 1 raw readback: 0052
247.115: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0052
247.115: <09>Lane 05 nibble 1 adjusted value (post nibble): 0052
247.115: <09>Lane 06 nibble 1 raw readback: 0058
247.115: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0058
247.115: <09>Lane 06 nibble 1 adjusted value (post nibble): 0056
247.115: <09>Lane 07 nibble 1 raw readback: 005f
247.115: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005f
247.115: <09>Lane 07 nibble 1 adjusted value (post nibble): 005c
247.115: <09>Lane 08 nibble 1 raw readback: 0048
247.115: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0048
247.115: <09>Lane 08 nibble 1 adjusted value (post nibble): 0047
247.115: <09>original critical gross delay: 0
247.115: <09>new critical gross delay: 0
247.115: DIMM 0 RttNom: 4
247.115: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.115: DIMM 0 RttNom: 4
247.115: DIMM 0 RttWr: 1
247.115: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.115: DIMM 0 RttWr: 1
247.115: DIMM 0 RttNom: 4
247.117: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.116: DIMM 0 RttNom: 4
247.116: DIMM 0 RttWr: 1
247.116: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.116: DIMM 0 RttWr: 1
247.116: DIMM 1 RttNom: 4
247.116: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.116: DIMM 0 RttNom: 4
247.116: DIMM 1 RttWr: 1
247.116: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.116: DIMM 0 RttWr: 1
247.116: DIMM 1 RttNom: 4
247.116: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.116: DIMM 0 RttNom: 4
247.116: DIMM 1 RttWr: 1
247.116: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.116: DIMM 0 RttWr: 1
247.116: AgesaHwWlPhase1: training nibble 0
247.116: DIMM 1 RttNom: 4
247.116: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.116: DIMM 1 RttWr: 1
247.116: DIMM 1 RttWr: 1
247.116: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.116: DIMM 1 RttWr: 1
247.116: DIMM 1 RttNom: 4
247.116: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.116: DIMM 1 RttNom: 4
247.116: DIMM 1 RttWr: 1
247.116: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.116: DIMM 1 RttWr: 1
247.116: DIMM 0 RttNom: 4
247.116: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.116: DIMM 1 RttNom: 4
247.116: DIMM 0 RttWr: 1
247.116: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.116: DIMM 1 RttWr: 1
247.116: DIMM 0 RttNom: 4
247.116: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.116: DIMM 1 RttNom: 4
247.116: DIMM 0 RttWr: 1
247.116: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.116: DIMM 1 RttWr: 1
247.116: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.116: <09>Lane 00 scaled delay: 0069
247.116: <09>Lane 00 new seed: 0069
247.116: <09>Lane 01 scaled delay: 0060
247.116: <09>Lane 01 new seed: 0060
247.116: <09>Lane 02 scaled delay: 005a
247.116: <09>Lane 02 new seed: 005a
247.116: <09>Lane 03 scaled delay: 0058
247.116: <09>Lane 03 new seed: 0058
247.116: <09>Lane 04 scaled delay: 0052
247.116: <09>Lane 04 new seed: 0052
247.116: <09>Lane 05 scaled delay: 0059
247.116: <09>Lane 05 new seed: 0059
247.116: <09>Lane 06 scaled delay: 005d
247.116: <09>Lane 06 new seed: 005d
247.116: <09>Lane 07 scaled delay: 0063
247.116: <09>Lane 07 new seed: 0063
247.116: <09>Lane 08 scaled delay: 0052
247.116: <09>Lane 08 new seed: 0052
247.116: <09>Lane 00 nibble 0 raw readback: 002f
247.116: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006f
247.116: <09>Lane 00 nibble 0 adjusted value (post nibble): 006f
247.116: <09>Lane 01 nibble 0 raw readback: 0025
247.117: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0065
247.117: <09>Lane 01 nibble 0 adjusted value (post nibble): 0065
247.117: <09>Lane 02 nibble 0 raw readback: 005d
247.117: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005d
247.117: <09>Lane 02 nibble 0 adjusted value (post nibble): 005d
247.117: <09>Lane 03 nibble 0 raw readback: 005c
247.117: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005c
247.117: <09>Lane 03 nibble 0 adjusted value (post nibble): 005c
247.117: <09>Lane 04 nibble 0 raw readback: 0057
247.117: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0057
247.117: <09>Lane 04 nibble 0 adjusted value (post nibble): 0057
247.117: <09>Lane 05 nibble 0 raw readback: 0060
247.117: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0060
247.117: <09>Lane 05 nibble 0 adjusted value (post nibble): 0060
247.117: <09>Lane 06 nibble 0 raw readback: 0061
247.117: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0061
247.117: <09>Lane 06 nibble 0 adjusted value (post nibble): 0061
247.117: <09>Lane 07 nibble 0 raw readback: 0029
247.117: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0069
247.117: <09>Lane 07 nibble 0 adjusted value (post nibble): 0069
247.117: <09>Lane 08 nibble 0 raw readback: 0052
247.117: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0052
247.117: <09>Lane 08 nibble 0 adjusted value (post nibble): 0052
247.117: AgesaHwWlPhase1: training nibble 1
247.117: DIMM 1 RttNom: 4
247.117: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.117: DIMM 1 RttWr: 1
247.117: DIMM 1 RttWr: 1
247.117: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.117: DIMM 1 RttWr: 1
247.117: DIMM 1 RttNom: 4
247.117: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.117: DIMM 1 RttNom: 4
247.117: DIMM 1 RttWr: 1
247.117: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.117: DIMM 1 RttWr: 1
247.117: DIMM 0 RttNom: 4
247.117: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.117: DIMM 1 RttNom: 4
247.117: DIMM 0 RttWr: 1
247.117: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.117: DIMM 1 RttWr: 1
247.117: DIMM 0 RttNom: 4
247.117: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.117: DIMM 1 RttNom: 4
247.117: DIMM 0 RttWr: 1
247.117: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.117: DIMM 1 RttWr: 1
247.117: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.117: <09>Lane 00 new seed: 0069
247.117: <09>Lane 01 new seed: 0060
247.117: <09>Lane 02 new seed: 005a
247.117: <09>Lane 03 new seed: 0058
247.117: <09>Lane 04 new seed: 0052
247.117: <09>Lane 05 new seed: 0059
247.117: <09>Lane 06 new seed: 005d
247.117: <09>Lane 07 new seed: 0063
247.117: <09>Lane 08 new seed: 0052
247.117: <09>Lane 00 nibble 1 raw readback: 002f
247.117: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006f
247.117: <09>Lane 00 nibble 1 adjusted value (post nibble): 006c
247.117: <09>Lane 01 nibble 1 raw readback: 0025
247.117: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0065
247.117: <09>Lane 01 nibble 1 adjusted value (post nibble): 0062
247.117: <09>Lane 02 nibble 1 raw readback: 005c
247.117: <09>Lane 02 nibble 1 adjusted value (pre nibble): 005c
247.117: <09>Lane 02 nibble 1 adjusted value (post nibble): 005b
247.118: <09>Lane 03 nibble 1 raw readback: 005a
247.117: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005a
247.117: <09>Lane 03 nibble 1 adjusted value (post nibble): 0059
247.117: <09>Lane 04 nibble 1 raw readback: 0053
247.117: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0053
247.117: <09>Lane 04 nibble 1 adjusted value (post nibble): 0052
247.117: <09>Lane 05 nibble 1 raw readback: 005c
247.118: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005c
247.117: <09>Lane 05 nibble 1 adjusted value (post nibble): 005a
247.117: <09>Lane 06 nibble 1 raw readback: 0061
247.118: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0061
247.118: <09>Lane 06 nibble 1 adjusted value (post nibble): 005f
247.118: <09>Lane 07 nibble 1 raw readback: 0028
247.118: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0068
247.118: <09>Lane 07 nibble 1 adjusted value (post nibble): 0065
247.118: <09>Lane 08 nibble 1 raw readback: 0053
247.118: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0053
247.118: <09>Lane 08 nibble 1 adjusted value (post nibble): 0052
247.118: <09>original critical gross delay: 0
247.118: <09>new critical gross delay: 0
247.118: DIMM 1 RttNom: 4
247.118: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.118: DIMM 1 RttNom: 4
247.118: DIMM 1 RttWr: 1
247.118: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.118: DIMM 1 RttWr: 1
247.118: DIMM 1 RttNom: 4
247.118: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.118: DIMM 1 RttNom: 4
247.118: DIMM 1 RttWr: 1
247.118: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.118: DIMM 1 RttWr: 1
247.118: DIMM 0 RttNom: 4
247.118: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.118: DIMM 1 RttNom: 4
247.118: DIMM 0 RttWr: 1
247.118: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.118: DIMM 1 RttWr: 1
247.118: DIMM 0 RttNom: 4
247.118: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.118: DIMM 1 RttNom: 4
247.118: DIMM 0 RttWr: 1
247.118: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.118: DIMM 1 RttWr: 1
247.118: SPD2ndTiming: Start
247.119: SPD2ndTiming: Done
247.119: mct_BeforeDramInit_Prod_D: Start
247.119: mct_ProgramODT_D: Start
247.119: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
247.119: mct_ProgramODT_D: Done
247.119: mct_BeforeDramInit_Prod_D: Done
247.119: mct_DramInit_Sw_D: Start
247.119: DIMM 0 RttWr: 1
247.119: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.119: mct_SendMrsCmd: Start
247.119: mct_SendMrsCmd: Done
247.119: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
247.119: mct_SendMrsCmd: Start
247.119: mct_SendMrsCmd: Done
247.119: DIMM 0 RttNom: 4
247.119: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.119: mct_SendMrsCmd: Start
247.119: mct_SendMrsCmd: Done
247.119: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001d78
247.119: mct_SendMrsCmd: Start
247.119: mct_SendMrsCmd: Done
247.119: DIMM 0 RttWr: 1
247.119: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.119: mct_SendMrsCmd: Start
247.119: mct_SendMrsCmd: Done
247.119: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
247.119: mct_SendMrsCmd: Start
247.119: mct_SendMrsCmd: Done
247.119: DIMM 0 RttNom: 4
247.119: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.119: mct_SendMrsCmd: Start
247.119: mct_SendMrsCmd: Done
247.119: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201d78
247.119: mct_SendMrsCmd: Start
247.119: mct_SendMrsCmd: Done
247.119: DIMM 1 RttWr: 1
247.119: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.119: mct_SendMrsCmd: Start
247.119: mct_SendMrsCmd: Done
247.119: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
247.119: mct_SendMrsCmd: Start
247.119: mct_SendMrsCmd: Done
247.119: DIMM 1 RttNom: 4
247.119: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.119: mct_SendMrsCmd: Start
247.119: mct_SendMrsCmd: Done
247.119: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401d78
247.119: mct_SendMrsCmd: Start
247.119: mct_SendMrsCmd: Done
247.119: DIMM 1 RttWr: 1
247.119: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.119: mct_SendMrsCmd: Start
247.119: mct_SendMrsCmd: Done
247.119: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
247.119: mct_SendMrsCmd: Start
247.119: mct_SendMrsCmd: Done
247.119: DIMM 1 RttNom: 4
247.119: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.119: mct_SendMrsCmd: Start
247.119: mct_SendMrsCmd: Done
247.119: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601d78
247.119: mct_SendMrsCmd: Start
247.119: mct_SendMrsCmd: Done
247.119: mct_DramInit_Sw_D: Done
247.120: AgesaHwWlPhase1: training nibble 0
247.120: DIMM 0 RttNom: 4
247.120: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.120: DIMM 0 RttWr: 1
247.120: DIMM 0 RttWr: 1
247.120: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.120: DIMM 0 RttWr: 1
247.120: DIMM 0 RttNom: 4
247.120: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.120: DIMM 0 RttNom: 4
247.120: DIMM 0 RttWr: 1
247.120: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.120: DIMM 0 RttWr: 1
247.120: DIMM 1 RttNom: 4
247.120: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.120: DIMM 0 RttNom: 4
247.120: DIMM 1 RttWr: 1
247.120: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.120: DIMM 0 RttWr: 1
247.120: DIMM 1 RttNom: 4
247.120: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.120: DIMM 0 RttNom: 4
247.120: DIMM 1 RttWr: 1
247.120: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.120: DIMM 0 RttWr: 1
247.120: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.120: <09>Lane 00 scaled delay: 0063
247.120: <09>Lane 00 new seed: 0063
247.120: <09>Lane 01 scaled delay: 005b
247.120: <09>Lane 01 new seed: 005b
247.120: <09>Lane 02 scaled delay: 0055
247.120: <09>Lane 02 new seed: 0055
247.120: <09>Lane 03 scaled delay: 0051
247.120: <09>Lane 03 new seed: 0051
247.120: <09>Lane 04 scaled delay: 004c
247.120: <09>Lane 04 new seed: 004c
247.120: <09>Lane 05 scaled delay: 0053
247.120: <09>Lane 05 new seed: 0053
247.120: <09>Lane 06 scaled delay: 0059
247.120: <09>Lane 06 new seed: 0059
247.120: <09>Lane 07 scaled delay: 0060
247.120: <09>Lane 07 new seed: 0060
247.120: <09>Lane 08 scaled delay: 0049
247.120: <09>Lane 08 new seed: 0049
247.120: <09>Lane 00 nibble 0 raw readback: 0027
247.120: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0067
247.120: <09>Lane 00 nibble 0 adjusted value (post nibble): 0067
247.120: <09>Lane 01 nibble 0 raw readback: 005d
247.120: <09>Lane 01 nibble 0 adjusted value (pre nibble): 005d
247.120: <09>Lane 01 nibble 0 adjusted value (post nibble): 005d
247.120: <09>Lane 02 nibble 0 raw readback: 0056
247.120: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0056
247.121: <09>Lane 02 nibble 0 adjusted value (post nibble): 0056
247.120: <09>Lane 03 nibble 0 raw readback: 004f
247.121: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004f
247.121: <09>Lane 03 nibble 0 adjusted value (post nibble): 004f
247.121: <09>Lane 04 nibble 0 raw readback: 004d
247.121: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004d
247.121: <09>Lane 04 nibble 0 adjusted value (post nibble): 004d
247.121: <09>Lane 05 nibble 0 raw readback: 0055
247.121: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0055
247.121: <09>Lane 05 nibble 0 adjusted value (post nibble): 0055
247.121: <09>Lane 06 nibble 0 raw readback: 005a
247.121: <09>Lane 06 nibble 0 adjusted value (pre nibble): 005a
247.121: <09>Lane 06 nibble 0 adjusted value (post nibble): 005a
247.121: <09>Lane 07 nibble 0 raw readback: 0021
247.121: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0061
247.121: <09>Lane 07 nibble 0 adjusted value (post nibble): 0061
247.121: <09>Lane 08 nibble 0 raw readback: 004a
247.121: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004a
247.121: <09>Lane 08 nibble 0 adjusted value (post nibble): 004a
247.121: AgesaHwWlPhase1: training nibble 1
247.121: DIMM 0 RttNom: 4
247.121: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.121: DIMM 0 RttWr: 1
247.121: DIMM 0 RttWr: 1
247.121: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.121: DIMM 0 RttWr: 1
247.121: DIMM 0 RttNom: 4
247.121: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.121: DIMM 0 RttNom: 4
247.121: DIMM 0 RttWr: 1
247.121: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.121: DIMM 0 RttWr: 1
247.121: DIMM 1 RttNom: 4
247.121: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.121: DIMM 0 RttNom: 4
247.121: DIMM 1 RttWr: 1
247.121: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.121: DIMM 0 RttWr: 1
247.121: DIMM 1 RttNom: 4
247.121: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.121: DIMM 0 RttNom: 4
247.121: DIMM 1 RttWr: 1
247.121: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.121: DIMM 0 RttWr: 1
247.121: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.121: <09>Lane 00 new seed: 0063
247.121: <09>Lane 01 new seed: 005b
247.121: <09>Lane 02 new seed: 0055
247.121: <09>Lane 03 new seed: 0051
247.121: <09>Lane 04 new seed: 004c
247.121: <09>Lane 05 new seed: 0053
247.121: <09>Lane 06 new seed: 0059
247.121: <09>Lane 07 new seed: 0060
247.121: <09>Lane 08 new seed: 0049
247.121: <09>Lane 00 nibble 1 raw readback: 0024
247.121: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0064
247.121: <09>Lane 00 nibble 1 adjusted value (post nibble): 0063
247.121: <09>Lane 01 nibble 1 raw readback: 005e
247.121: <09>Lane 01 nibble 1 adjusted value (pre nibble): 005e
247.121: <09>Lane 01 nibble 1 adjusted value (post nibble): 005c
247.121: <09>Lane 02 nibble 1 raw readback: 0055
247.121: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0055
247.121: <09>Lane 02 nibble 1 adjusted value (post nibble): 0055
247.121: <09>Lane 03 nibble 1 raw readback: 004f
247.121: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004f
247.121: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
247.121: <09>Lane 04 nibble 1 raw readback: 004c
247.121: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004c
247.121: <09>Lane 04 nibble 1 adjusted value (post nibble): 004c
247.121: <09>Lane 05 nibble 1 raw readback: 0053
247.121: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0053
247.121: <09>Lane 05 nibble 1 adjusted value (post nibble): 0053
247.121: <09>Lane 06 nibble 1 raw readback: 005a
247.122: <09>Lane 06 nibble 1 adjusted value (pre nibble): 005a
247.122: <09>Lane 06 nibble 1 adjusted value (post nibble): 0059
247.122: <09>Lane 07 nibble 1 raw readback: 0022
247.122: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0062
247.122: <09>Lane 07 nibble 1 adjusted value (post nibble): 0061
247.122: <09>Lane 08 nibble 1 raw readback: 0047
247.122: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0047
247.122: <09>Lane 08 nibble 1 adjusted value (post nibble): 0048
247.122: <09>original critical gross delay: 0
247.122: <09>new critical gross delay: 0
247.122: DIMM 0 RttNom: 4
247.122: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.122: DIMM 0 RttNom: 4
247.122: DIMM 0 RttWr: 1
247.122: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.122: DIMM 0 RttWr: 1
247.122: DIMM 0 RttNom: 4
247.122: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.122: DIMM 0 RttNom: 4
247.122: DIMM 0 RttWr: 1
247.122: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.122: DIMM 0 RttWr: 1
247.122: DIMM 1 RttNom: 4
247.122: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.122: DIMM 0 RttNom: 4
247.122: DIMM 1 RttWr: 1
247.122: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.122: DIMM 0 RttWr: 1
247.122: DIMM 1 RttNom: 4
247.122: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.122: DIMM 0 RttNom: 4
247.122: DIMM 1 RttWr: 1
247.122: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.122: DIMM 0 RttWr: 1
247.122: AgesaHwWlPhase1: training nibble 0
247.122: DIMM 1 RttNom: 4
247.122: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.122: DIMM 1 RttWr: 1
247.122: DIMM 1 RttWr: 1
247.122: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.122: DIMM 1 RttWr: 1
247.122: DIMM 1 RttNom: 4
247.122: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.122: DIMM 1 RttNom: 4
247.122: DIMM 1 RttWr: 1
247.122: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.122: DIMM 1 RttWr: 1
247.122: DIMM 0 RttNom: 4
247.122: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.122: DIMM 1 RttNom: 4
247.122: DIMM 0 RttWr: 1
247.122: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.122: DIMM 1 RttWr: 1
247.122: DIMM 0 RttNom: 4
247.122: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.122: DIMM 1 RttNom: 4
247.122: DIMM 0 RttWr: 1
247.122: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.123: DIMM 1 RttWr: 1
247.123: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.123: <09>Lane 00 scaled delay: 006b
247.123: <09>Lane 00 new seed: 006b
247.123: <09>Lane 01 scaled delay: 0064
247.123: <09>Lane 01 new seed: 0064
247.123: <09>Lane 02 scaled delay: 005e
247.123: <09>Lane 02 new seed: 005e
247.123: <09>Lane 03 scaled delay: 0059
247.123: <09>Lane 03 new seed: 0059
247.123: <09>Lane 04 scaled delay: 0053
247.123: <09>Lane 04 new seed: 0053
247.123: <09>Lane 05 scaled delay: 0059
247.123: <09>Lane 05 new seed: 0059
247.123: <09>Lane 06 scaled delay: 0061
247.123: <09>Lane 06 new seed: 0061
247.123: <09>Lane 07 scaled delay: 0069
247.123: <09>Lane 07 new seed: 0069
247.123: <09>Lane 08 scaled delay: 0052
247.123: <09>Lane 08 new seed: 0052
247.123: <09>Lane 00 nibble 0 raw readback: 002a
247.123: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006a
247.123: <09>Lane 00 nibble 0 adjusted value (post nibble): 006a
247.123: <09>Lane 01 nibble 0 raw readback: 0028
247.123: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0068
247.123: <09>Lane 01 nibble 0 adjusted value (post nibble): 0068
247.123: <09>Lane 02 nibble 0 raw readback: 005f
247.123: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005f
247.123: <09>Lane 02 nibble 0 adjusted value (post nibble): 005f
247.123: <09>Lane 03 nibble 0 raw readback: 0058
247.123: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0058
247.123: <09>Lane 03 nibble 0 adjusted value (post nibble): 0058
247.123: <09>Lane 04 nibble 0 raw readback: 0055
247.123: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0055
247.123: <09>Lane 04 nibble 0 adjusted value (post nibble): 0055
247.123: <09>Lane 05 nibble 0 raw readback: 005e
247.123: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005e
247.123: <09>Lane 05 nibble 0 adjusted value (post nibble): 005e
247.123: <09>Lane 06 nibble 0 raw readback: 0025
247.123: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0065
247.123: <09>Lane 06 nibble 0 adjusted value (post nibble): 0065
247.123: <09>Lane 07 nibble 0 raw readback: 0029
247.123: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0069
247.123: <09>Lane 07 nibble 0 adjusted value (post nibble): 0069
247.123: <09>Lane 08 nibble 0 raw readback: 0051
247.123: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0051
247.123: <09>Lane 08 nibble 0 adjusted value (post nibble): 0051
247.123: AgesaHwWlPhase1: training nibble 1
247.123: DIMM 1 RttNom: 4
247.123: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.123: DIMM 1 RttWr: 1
247.123: DIMM 1 RttWr: 1
247.123: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.123: DIMM 1 RttWr: 1
247.123: DIMM 1 RttNom: 4
247.123: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.123: DIMM 1 RttNom: 4
247.123: DIMM 1 RttWr: 1
247.123: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.123: DIMM 1 RttWr: 1
247.123: DIMM 0 RttNom: 4
247.123: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.123: DIMM 1 RttNom: 4
247.123: DIMM 0 RttWr: 1
247.123: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.123: DIMM 1 RttWr: 1
247.123: DIMM 0 RttNom: 4
247.123: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.123: DIMM 1 RttNom: 4
247.123: DIMM 0 RttWr: 1
247.123: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.123: DIMM 1 RttWr: 1
247.124: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.124: <09>Lane 00 new seed: 006b
247.124: <09>Lane 01 new seed: 0064
247.124: <09>Lane 02 new seed: 005e
247.124: <09>Lane 03 new seed: 0059
247.124: <09>Lane 04 new seed: 0053
247.124: <09>Lane 05 new seed: 0059
247.124: <09>Lane 06 new seed: 0061
247.124: <09>Lane 07 new seed: 0069
247.124: <09>Lane 08 new seed: 0052
247.124: <09>Lane 00 nibble 1 raw readback: 002f
247.124: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006f
247.124: <09>Lane 00 nibble 1 adjusted value (post nibble): 006d
247.124: <09>Lane 01 nibble 1 raw readback: 0027
247.124: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0067
247.124: <09>Lane 01 nibble 1 adjusted value (post nibble): 0065
247.124: <09>Lane 02 nibble 1 raw readback: 005e
247.124: <09>Lane 02 nibble 1 adjusted value (pre nibble): 005e
247.124: <09>Lane 02 nibble 1 adjusted value (post nibble): 005e
247.124: <09>Lane 03 nibble 1 raw readback: 0059
247.124: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0059
247.124: <09>Lane 03 nibble 1 adjusted value (post nibble): 0059
247.124: <09>Lane 04 nibble 1 raw readback: 0053
247.124: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0053
247.124: <09>Lane 04 nibble 1 adjusted value (post nibble): 0053
247.124: <09>Lane 05 nibble 1 raw readback: 005a
247.124: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005a
247.124: <09>Lane 05 nibble 1 adjusted value (post nibble): 0059
247.124: <09>Lane 06 nibble 1 raw readback: 0023
247.124: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0063
247.124: <09>Lane 06 nibble 1 adjusted value (post nibble): 0062
247.124: <09>Lane 07 nibble 1 raw readback: 002b
247.124: <09>Lane 07 nibble 1 adjusted value (pre nibble): 006b
247.124: <09>Lane 07 nibble 1 adjusted value (post nibble): 006a
247.124: <09>Lane 08 nibble 1 raw readback: 0052
247.124: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0052
247.124: <09>Lane 08 nibble 1 adjusted value (post nibble): 0052
247.124: <09>original critical gross delay: 0
247.124: <09>new critical gross delay: 0
247.124: DIMM 1 RttNom: 4
247.124: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.124: DIMM 1 RttNom: 4
247.124: DIMM 1 RttWr: 1
247.124: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.124: DIMM 1 RttWr: 1
247.124: DIMM 1 RttNom: 4
247.124: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.124: DIMM 1 RttNom: 4
247.124: DIMM 1 RttWr: 1
247.124: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.124: DIMM 1 RttWr: 1
247.124: DIMM 0 RttNom: 4
247.124: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.124: DIMM 1 RttNom: 4
247.124: DIMM 0 RttWr: 1
247.124: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.124: DIMM 1 RttWr: 1
247.124: DIMM 0 RttNom: 4
247.124: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.124: DIMM 1 RttNom: 4
247.124: DIMM 0 RttWr: 1
247.124: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.124: DIMM 1 RttWr: 1
247.125: activate_spd_rom() for node 02
247.125: enable_spd_node2()
247.125: SetTargetFreq: Start
247.125: SetTargetFreq: Node 2: New frequency code: 0006
247.125: ChangeMemClk: Start
247.125: set_2t_configuration: Start
247.125: set_2t_configuration: Done
247.125: mct_BeforePlatformSpec: Start
247.125: mct_BeforePlatformSpec: Done
247.125: mct_PlatformSpec: Start
247.125: Programmed DCT 0 timing/termination pattern 00000000 20222222
247.125: mct_PlatformSpec: Done
247.125: set_2t_configuration: Start
247.125: set_2t_configuration: Done
247.125: mct_BeforePlatformSpec: Start
247.125: mct_BeforePlatformSpec: Done
247.125: mct_PlatformSpec: Start
247.125: Programmed DCT 1 timing/termination pattern 00000000 20222222
247.125: mct_PlatformSpec: Done
247.125: ChangeMemClk: Done
247.125: phyAssistedMemFnceTraining: Start
247.126: phyAssistedMemFnceTraining: training node 2 DCT 0
247.126: phyAssistedMemFnceTraining: done training node 2 DCT 0
247.126: phyAssistedMemFnceTraining: training node 2 DCT 1
247.126: phyAssistedMemFnceTraining: done training node 2 DCT 1
247.126: phyAssistedMemFnceTraining: Done
247.126: InitPhyCompensation: DCT 0: Start
247.126: Waiting for predriver calibration to be applied...done!
247.126: InitPhyCompensation: DCT 0: Done
247.126: phyAssistedMemFnceTraining: Start
247.126: phyAssistedMemFnceTraining: training node 2 DCT 0
247.126: phyAssistedMemFnceTraining: done training node 2 DCT 0
247.126: phyAssistedMemFnceTraining: training node 2 DCT 1
247.126: phyAssistedMemFnceTraining: done training node 2 DCT 1
247.126: phyAssistedMemFnceTraining: Done
247.126: InitPhyCompensation: DCT 1: Start
247.126: Waiting for predriver calibration to be applied...done!
247.126: InitPhyCompensation: DCT 1: Done
247.127: Preparing to send DCT 0 DIMM 0 RC10: 00 (F2xA8: 02000300)
247.127: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.127: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
247.127: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.127: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
247.127: Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 02000c00)
247.127: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.127: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
247.127: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.127: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
247.127: Preparing to send DCT 1 DIMM 0 RC10: 00 (F2xA8: 02000300)
247.127: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.127: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
247.127: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.127: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
247.127: Preparing to send DCT 1 DIMM 1 RC10: 00 (F2xA8: 02000c00)
247.127: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.127: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
247.127: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.127: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
247.127: SetTargetFreq: Done
247.127: SPD2ndTiming: Start
247.128: SPD2ndTiming: Done
247.127: mct_BeforeDramInit_Prod_D: Start
247.127: mct_ProgramODT_D: Start
247.127: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
247.128: mct_ProgramODT_D: Done
247.128: mct_BeforeDramInit_Prod_D: Done
247.128: mct_DramInit_Sw_D: Start
247.128: DIMM 0 RttWr: 2
247.128: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.128: mct_SendMrsCmd: Start
247.128: mct_SendMrsCmd: Done
247.128: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
247.128: mct_SendMrsCmd: Start
247.128: mct_SendMrsCmd: Done
247.128: DIMM 0 RttNom: 3
247.128: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.128: mct_SendMrsCmd: Start
247.128: mct_SendMrsCmd: Done
247.128: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001578
247.128: mct_SendMrsCmd: Start
247.128: mct_SendMrsCmd: Done
247.128: DIMM 0 RttWr: 2
247.128: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.128: mct_SendMrsCmd: Start
247.128: mct_SendMrsCmd: Done
247.128: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
247.128: mct_SendMrsCmd: Start
247.128: mct_SendMrsCmd: Done
247.128: DIMM 0 RttNom: 3
247.128: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.128: mct_SendMrsCmd: Start
247.128: mct_SendMrsCmd: Done
247.128: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201578
247.128: mct_SendMrsCmd: Start
247.128: mct_SendMrsCmd: Done
247.128: DIMM 1 RttWr: 2
247.128: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.128: mct_SendMrsCmd: Start
247.128: mct_SendMrsCmd: Done
247.128: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
247.128: mct_SendMrsCmd: Start
247.128: mct_SendMrsCmd: Done
247.128: DIMM 1 RttNom: 3
247.128: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.128: mct_SendMrsCmd: Start
247.128: mct_SendMrsCmd: Done
247.128: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401578
247.128: mct_SendMrsCmd: Start
247.128: mct_SendMrsCmd: Done
247.128: DIMM 1 RttWr: 2
247.128: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.128: mct_SendMrsCmd: Start
247.128: mct_SendMrsCmd: Done
247.128: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
247.128: mct_SendMrsCmd: Start
247.128: mct_SendMrsCmd: Done
247.128: DIMM 1 RttNom: 3
247.128: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.128: mct_SendMrsCmd: Start
247.128: mct_SendMrsCmd: Done
247.128: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601578
247.128: mct_SendMrsCmd: Start
247.128: mct_SendMrsCmd: Done
247.128: mct_DramInit_Sw_D: Done
247.129: AgesaHwWlPhase1: training nibble 0
247.129: DIMM 0 RttNom: 3
247.129: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.129: DIMM 0 RttWr: 2
247.129: DIMM 0 RttWr: 2
247.129: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.129: DIMM 0 RttWr: 2
247.129: DIMM 0 RttNom: 3
247.129: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.129: DIMM 0 RttNom: 3
247.129: DIMM 0 RttWr: 2
247.129: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.129: DIMM 0 RttWr: 2
247.129: DIMM 1 RttNom: 3
247.129: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.129: DIMM 0 RttNom: 3
247.129: DIMM 1 RttWr: 2
247.129: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.129: DIMM 0 RttWr: 2
247.129: DIMM 1 RttNom: 3
247.129: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.129: DIMM 0 RttNom: 3
247.129: DIMM 1 RttWr: 2
247.129: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.129: DIMM 0 RttWr: 2
247.129: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.129: <09>Lane 00 scaled delay: 0047
247.129: <09>Lane 00 new seed: 0047
247.129: <09>Lane 01 scaled delay: 0047
247.129: <09>Lane 01 new seed: 0047
247.129: <09>Lane 02 scaled delay: 0047
247.129: <09>Lane 02 new seed: 0047
247.129: <09>Lane 03 scaled delay: 0047
247.129: <09>Lane 03 new seed: 0047
247.129: <09>Lane 04 scaled delay: 0047
247.129: <09>Lane 04 new seed: 0047
247.129: <09>Lane 05 scaled delay: 0047
247.129: <09>Lane 05 new seed: 0047
247.129: <09>Lane 06 scaled delay: 0047
247.129: <09>Lane 06 new seed: 0047
247.129: <09>Lane 07 scaled delay: 0047
247.129: <09>Lane 07 new seed: 0047
247.129: <09>Lane 08 scaled delay: 0047
247.129: <09>Lane 08 new seed: 0047
247.130: <09>Lane 00 nibble 0 raw readback: 0050
247.130: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0050
247.130: <09>Lane 00 nibble 0 adjusted value (post nibble): 0050
247.130: <09>Lane 01 nibble 0 raw readback: 0049
247.130: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0049
247.130: <09>Lane 01 nibble 0 adjusted value (post nibble): 0049
247.130: <09>Lane 02 nibble 0 raw readback: 0048
247.130: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0048
247.130: <09>Lane 02 nibble 0 adjusted value (post nibble): 0048
247.130: <09>Lane 03 nibble 0 raw readback: 0045
247.130: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0045
247.130: <09>Lane 03 nibble 0 adjusted value (post nibble): 0045
247.130: <09>Lane 04 nibble 0 raw readback: 003b
247.130: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003b
247.130: <09>Lane 04 nibble 0 adjusted value (post nibble): 003b
247.130: <09>Lane 05 nibble 0 raw readback: 003f
247.130: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003f
247.130: <09>Lane 05 nibble 0 adjusted value (post nibble): 003f
247.130: <09>Lane 06 nibble 0 raw readback: 0041
247.130: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0041
247.130: <09>Lane 06 nibble 0 adjusted value (post nibble): 0041
247.130: <09>Lane 07 nibble 0 raw readback: 0043
247.130: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0043
247.130: <09>Lane 07 nibble 0 adjusted value (post nibble): 0043
247.130: <09>Lane 08 nibble 0 raw readback: 003d
247.130: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003d
247.130: <09>Lane 08 nibble 0 adjusted value (post nibble): 003d
247.130: AgesaHwWlPhase1: training nibble 1
247.130: DIMM 0 RttNom: 3
247.130: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.130: DIMM 0 RttWr: 2
247.130: DIMM 0 RttWr: 2
247.130: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.130: DIMM 0 RttWr: 2
247.130: DIMM 0 RttNom: 3
247.130: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.130: DIMM 0 RttNom: 3
247.130: DIMM 0 RttWr: 2
247.130: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.130: DIMM 0 RttWr: 2
247.130: DIMM 1 RttNom: 3
247.130: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.130: DIMM 0 RttNom: 3
247.130: DIMM 1 RttWr: 2
247.130: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.130: DIMM 0 RttWr: 2
247.130: DIMM 1 RttNom: 3
247.130: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.130: DIMM 0 RttNom: 3
247.130: DIMM 1 RttWr: 2
247.130: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.130: DIMM 0 RttWr: 2
247.130: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.130: <09>Lane 00 new seed: 0047
247.130: <09>Lane 01 new seed: 0047
247.130: <09>Lane 02 new seed: 0047
247.130: <09>Lane 03 new seed: 0047
247.130: <09>Lane 04 new seed: 0047
247.130: <09>Lane 05 new seed: 0047
247.130: <09>Lane 06 new seed: 0047
247.130: <09>Lane 07 new seed: 0047
247.130: <09>Lane 08 new seed: 0047
247.131: <09>Lane 00 nibble 1 raw readback: 004e
247.131: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004e
247.131: <09>Lane 00 nibble 1 adjusted value (post nibble): 004a
247.131: <09>Lane 01 nibble 1 raw readback: 004a
247.131: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004a
247.131: <09>Lane 01 nibble 1 adjusted value (post nibble): 0048
247.131: <09>Lane 02 nibble 1 raw readback: 0047
247.131: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0047
247.131: <09>Lane 02 nibble 1 adjusted value (post nibble): 0047
247.131: <09>Lane 03 nibble 1 raw readback: 0045
247.131: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
247.131: <09>Lane 03 nibble 1 adjusted value (post nibble): 0046
247.131: <09>Lane 04 nibble 1 raw readback: 003b
247.131: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003b
247.131: <09>Lane 04 nibble 1 adjusted value (post nibble): 0041
247.131: <09>Lane 05 nibble 1 raw readback: 003d
247.131: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003d
247.131: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
247.131: <09>Lane 06 nibble 1 raw readback: 0041
247.131: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0041
247.131: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
247.131: <09>Lane 07 nibble 1 raw readback: 0042
247.131: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
247.131: <09>Lane 07 nibble 1 adjusted value (post nibble): 0044
247.131: <09>Lane 08 nibble 1 raw readback: 003b
247.131: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003b
247.131: <09>Lane 08 nibble 1 adjusted value (post nibble): 0041
247.131: <09>original critical gross delay: 0
247.131: <09>new critical gross delay: 0
247.131: DIMM 0 RttNom: 3
247.131: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.131: DIMM 0 RttNom: 3
247.131: DIMM 0 RttWr: 2
247.131: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.131: DIMM 0 RttWr: 2
247.131: DIMM 0 RttNom: 3
247.131: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.131: DIMM 0 RttNom: 3
247.131: DIMM 0 RttWr: 2
247.131: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.131: DIMM 0 RttWr: 2
247.131: DIMM 1 RttNom: 3
247.131: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.131: DIMM 0 RttNom: 3
247.131: DIMM 1 RttWr: 2
247.131: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.131: DIMM 0 RttWr: 2
247.131: DIMM 1 RttNom: 3
247.131: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.131: DIMM 0 RttNom: 3
247.131: DIMM 1 RttWr: 2
247.131: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.131: DIMM 0 RttWr: 2
247.131: AgesaHwWlPhase1: training nibble 0
247.131: DIMM 1 RttNom: 3
247.131: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.131: DIMM 1 RttWr: 2
247.131: DIMM 1 RttWr: 2
247.131: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.131: DIMM 1 RttWr: 2
247.131: DIMM 1 RttNom: 3
247.131: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.131: DIMM 1 RttNom: 3
247.131: DIMM 1 RttWr: 2
247.132: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.132: DIMM 1 RttWr: 2
247.132: DIMM 0 RttNom: 3
247.132: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.132: DIMM 1 RttNom: 3
247.132: DIMM 0 RttWr: 2
247.132: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.132: DIMM 1 RttWr: 2
247.132: DIMM 0 RttNom: 3
247.132: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.132: DIMM 1 RttNom: 3
247.132: DIMM 0 RttWr: 2
247.132: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.132: DIMM 1 RttWr: 2
247.132: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.132: <09>Lane 00 scaled delay: 0047
247.132: <09>Lane 00 new seed: 0047
247.132: <09>Lane 01 scaled delay: 0047
247.132: <09>Lane 01 new seed: 0047
247.132: <09>Lane 02 scaled delay: 0047
247.132: <09>Lane 02 new seed: 0047
247.132: <09>Lane 03 scaled delay: 0047
247.132: <09>Lane 03 new seed: 0047
247.132: <09>Lane 04 scaled delay: 0047
247.132: <09>Lane 04 new seed: 0047
247.132: <09>Lane 05 scaled delay: 0047
247.132: <09>Lane 05 new seed: 0047
247.132: <09>Lane 06 scaled delay: 0047
247.132: <09>Lane 06 new seed: 0047
247.132: <09>Lane 07 scaled delay: 0047
247.132: <09>Lane 07 new seed: 0047
247.132: <09>Lane 08 scaled delay: 0047
247.132: <09>Lane 08 new seed: 0047
247.132: <09>Lane 00 nibble 0 raw readback: 0046
247.132: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0046
247.132: <09>Lane 00 nibble 0 adjusted value (post nibble): 0046
247.132: <09>Lane 01 nibble 0 raw readback: 003f
247.132: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003f
247.132: <09>Lane 01 nibble 0 adjusted value (post nibble): 003f
247.132: <09>Lane 02 nibble 0 raw readback: 003e
247.132: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003e
247.132: <09>Lane 02 nibble 0 adjusted value (post nibble): 003e
247.132: <09>Lane 03 nibble 0 raw readback: 003b
247.132: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
247.132: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
247.132: <09>Lane 04 nibble 0 raw readback: 0030
247.132: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0030
247.132: <09>Lane 04 nibble 0 adjusted value (post nibble): 0030
247.132: <09>Lane 05 nibble 0 raw readback: 0035
247.132: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0035
247.132: <09>Lane 05 nibble 0 adjusted value (post nibble): 0035
247.132: <09>Lane 06 nibble 0 raw readback: 0038
247.132: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0038
247.132: <09>Lane 06 nibble 0 adjusted value (post nibble): 0038
247.132: <09>Lane 07 nibble 0 raw readback: 003a
247.132: <09>Lane 07 nibble 0 adjusted value (pre nibble): 003a
247.132: <09>Lane 07 nibble 0 adjusted value (post nibble): 003a
247.132: <09>Lane 08 nibble 0 raw readback: 0033
247.132: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0033
247.132: <09>Lane 08 nibble 0 adjusted value (post nibble): 0033
247.132: AgesaHwWlPhase1: training nibble 1
247.132: DIMM 1 RttNom: 3
247.132: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.132: DIMM 1 RttWr: 2
247.132: DIMM 1 RttWr: 2
247.132: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.132: DIMM 1 RttWr: 2
247.132: DIMM 1 RttNom: 3
247.132: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.132: DIMM 1 RttNom: 3
247.133: DIMM 1 RttWr: 2
247.133: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.133: DIMM 1 RttWr: 2
247.133: DIMM 0 RttNom: 3
247.133: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.133: DIMM 1 RttNom: 3
247.133: DIMM 0 RttWr: 2
247.133: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.133: DIMM 1 RttWr: 2
247.133: DIMM 0 RttNom: 3
247.133: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.133: DIMM 1 RttNom: 3
247.133: DIMM 0 RttWr: 2
247.133: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.133: DIMM 1 RttWr: 2
247.133: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.133: <09>Lane 00 new seed: 0047
247.133: <09>Lane 01 new seed: 0047
247.133: <09>Lane 02 new seed: 0047
247.133: <09>Lane 03 new seed: 0047
247.133: <09>Lane 04 new seed: 0047
247.133: <09>Lane 05 new seed: 0047
247.133: <09>Lane 06 new seed: 0047
247.133: <09>Lane 07 new seed: 0047
247.133: <09>Lane 08 new seed: 0047
247.133: <09>Lane 00 nibble 1 raw readback: 0044
247.133: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0044
247.133: <09>Lane 00 nibble 1 adjusted value (post nibble): 0045
247.133: <09>Lane 01 nibble 1 raw readback: 0040
247.133: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0040
247.133: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
247.133: <09>Lane 02 nibble 1 raw readback: 0040
247.133: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0040
247.133: <09>Lane 02 nibble 1 adjusted value (post nibble): 0043
247.133: <09>Lane 03 nibble 1 raw readback: 003d
247.133: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003d
247.133: <09>Lane 03 nibble 1 adjusted value (post nibble): 0042
247.133: <09>Lane 04 nibble 1 raw readback: 0031
247.133: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0031
247.133: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
247.133: <09>Lane 05 nibble 1 raw readback: 0034
247.133: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0034
247.133: <09>Lane 05 nibble 1 adjusted value (post nibble): 003d
247.133: <09>Lane 06 nibble 1 raw readback: 0037
247.133: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0037
247.133: <09>Lane 06 nibble 1 adjusted value (post nibble): 003f
247.133: <09>Lane 07 nibble 1 raw readback: 003a
247.133: <09>Lane 07 nibble 1 adjusted value (pre nibble): 003a
247.133: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
247.133: <09>Lane 08 nibble 1 raw readback: 0033
247.133: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0033
247.133: <09>Lane 08 nibble 1 adjusted value (post nibble): 003d
247.133: <09>original critical gross delay: 0
247.133: <09>new critical gross delay: 0
247.133: DIMM 1 RttNom: 3
247.133: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.133: DIMM 1 RttNom: 3
247.133: DIMM 1 RttWr: 2
247.133: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.133: DIMM 1 RttWr: 2
247.133: DIMM 1 RttNom: 3
247.133: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.133: DIMM 1 RttNom: 3
247.134: DIMM 1 RttWr: 2
247.133: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.133: DIMM 1 RttWr: 2
247.134: DIMM 0 RttNom: 3
247.134: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.134: DIMM 1 RttNom: 3
247.134: DIMM 0 RttWr: 2
247.134: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.134: DIMM 1 RttWr: 2
247.134: DIMM 0 RttNom: 3
247.134: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.134: DIMM 1 RttNom: 3
247.134: DIMM 0 RttWr: 2
247.134: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.134: DIMM 1 RttWr: 2
247.134: SPD2ndTiming: Start
247.134: SPD2ndTiming: Done
247.134: mct_BeforeDramInit_Prod_D: Start
247.134: mct_ProgramODT_D: Start
247.134: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
247.134: mct_ProgramODT_D: Done
247.134: mct_BeforeDramInit_Prod_D: Done
247.134: mct_DramInit_Sw_D: Start
247.134: DIMM 0 RttWr: 2
247.134: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.134: mct_SendMrsCmd: Start
247.134: mct_SendMrsCmd: Done
247.134: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
247.134: mct_SendMrsCmd: Start
247.135: mct_SendMrsCmd: Done
247.135: DIMM 0 RttNom: 3
247.135: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.135: mct_SendMrsCmd: Start
247.135: mct_SendMrsCmd: Done
247.135: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001578
247.135: mct_SendMrsCmd: Start
247.135: mct_SendMrsCmd: Done
247.135: DIMM 0 RttWr: 2
247.135: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.135: mct_SendMrsCmd: Start
247.135: mct_SendMrsCmd: Done
247.135: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
247.135: mct_SendMrsCmd: Start
247.135: mct_SendMrsCmd: Done
247.135: DIMM 0 RttNom: 3
247.135: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.135: mct_SendMrsCmd: Start
247.135: mct_SendMrsCmd: Done
247.135: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201578
247.135: mct_SendMrsCmd: Start
247.135: mct_SendMrsCmd: Done
247.135: DIMM 1 RttWr: 2
247.135: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.135: mct_SendMrsCmd: Start
247.135: mct_SendMrsCmd: Done
247.135: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
247.135: mct_SendMrsCmd: Start
247.135: mct_SendMrsCmd: Done
247.135: DIMM 1 RttNom: 3
247.135: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.135: mct_SendMrsCmd: Start
247.135: mct_SendMrsCmd: Done
247.135: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401578
247.135: mct_SendMrsCmd: Start
247.135: mct_SendMrsCmd: Done
247.135: DIMM 1 RttWr: 2
247.135: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.135: mct_SendMrsCmd: Start
247.135: mct_SendMrsCmd: Done
247.135: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
247.135: mct_SendMrsCmd: Start
247.135: mct_SendMrsCmd: Done
247.135: DIMM 1 RttNom: 3
247.135: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.135: mct_SendMrsCmd: Start
247.135: mct_SendMrsCmd: Done
247.135: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601578
247.135: mct_SendMrsCmd: Start
247.135: mct_SendMrsCmd: Done
247.135: mct_DramInit_Sw_D: Done
247.135: AgesaHwWlPhase1: training nibble 0
247.135: DIMM 0 RttNom: 3
247.135: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.135: DIMM 0 RttWr: 2
247.135: DIMM 0 RttWr: 2
247.135: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.135: DIMM 0 RttWr: 2
247.135: DIMM 0 RttNom: 3
247.135: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.135: DIMM 0 RttNom: 3
247.135: DIMM 0 RttWr: 2
247.135: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.135: DIMM 0 RttWr: 2
247.135: DIMM 1 RttNom: 3
247.135: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.135: DIMM 0 RttNom: 3
247.135: DIMM 1 RttWr: 2
247.135: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.135: DIMM 0 RttWr: 2
247.135: DIMM 1 RttNom: 3
247.135: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.136: DIMM 0 RttNom: 3
247.136: DIMM 1 RttWr: 2
247.136: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.136: DIMM 0 RttWr: 2
247.136: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.136: <09>Lane 00 scaled delay: 0047
247.136: <09>Lane 00 new seed: 0047
247.136: <09>Lane 01 scaled delay: 0047
247.136: <09>Lane 01 new seed: 0047
247.136: <09>Lane 02 scaled delay: 0047
247.136: <09>Lane 02 new seed: 0047
247.136: <09>Lane 03 scaled delay: 0047
247.136: <09>Lane 03 new seed: 0047
247.136: <09>Lane 04 scaled delay: 0047
247.136: <09>Lane 04 new seed: 0047
247.136: <09>Lane 05 scaled delay: 0047
247.136: <09>Lane 05 new seed: 0047
247.136: <09>Lane 06 scaled delay: 0047
247.136: <09>Lane 06 new seed: 0047
247.136: <09>Lane 07 scaled delay: 0047
247.136: <09>Lane 07 new seed: 0047
247.136: <09>Lane 08 scaled delay: 0047
247.136: <09>Lane 08 new seed: 0047
247.136: <09>Lane 00 nibble 0 raw readback: 004d
247.136: <09>Lane 00 nibble 0 adjusted value (pre nibble): 004d
247.136: <09>Lane 00 nibble 0 adjusted value (post nibble): 004d
247.136: <09>Lane 01 nibble 0 raw readback: 004a
247.136: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004a
247.136: <09>Lane 01 nibble 0 adjusted value (post nibble): 004a
247.136: <09>Lane 02 nibble 0 raw readback: 0046
247.136: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0046
247.136: <09>Lane 02 nibble 0 adjusted value (post nibble): 0046
247.136: <09>Lane 03 nibble 0 raw readback: 0044
247.136: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
247.136: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
247.136: <09>Lane 04 nibble 0 raw readback: 0039
247.136: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
247.136: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
247.136: <09>Lane 05 nibble 0 raw readback: 003d
247.136: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
247.136: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
247.136: <09>Lane 06 nibble 0 raw readback: 0040
247.136: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
247.136: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
247.136: <09>Lane 07 nibble 0 raw readback: 0041
247.136: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0041
247.136: <09>Lane 07 nibble 0 adjusted value (post nibble): 0041
247.136: <09>Lane 08 nibble 0 raw readback: 003b
247.136: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003b
247.136: <09>Lane 08 nibble 0 adjusted value (post nibble): 003b
247.136: AgesaHwWlPhase1: training nibble 1
247.136: DIMM 0 RttNom: 3
247.136: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.136: DIMM 0 RttWr: 2
247.136: DIMM 0 RttWr: 2
247.137: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.136: DIMM 0 RttWr: 2
247.137: DIMM 0 RttNom: 3
247.137: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.137: DIMM 0 RttNom: 3
247.137: DIMM 0 RttWr: 2
247.137: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.137: DIMM 0 RttWr: 2
247.137: DIMM 1 RttNom: 3
247.137: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.137: DIMM 0 RttNom: 3
247.137: DIMM 1 RttWr: 2
247.137: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.137: DIMM 0 RttWr: 2
247.137: DIMM 1 RttNom: 3
247.137: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.137: DIMM 0 RttNom: 3
247.137: DIMM 1 RttWr: 2
247.137: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.137: DIMM 0 RttWr: 2
247.137: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.137: <09>Lane 00 new seed: 0047
247.137: <09>Lane 01 new seed: 0047
247.137: <09>Lane 02 new seed: 0047
247.137: <09>Lane 03 new seed: 0047
247.137: <09>Lane 04 new seed: 0047
247.137: <09>Lane 05 new seed: 0047
247.137: <09>Lane 06 new seed: 0047
247.137: <09>Lane 07 new seed: 0047
247.137: <09>Lane 08 new seed: 0047
247.137: <09>Lane 00 nibble 1 raw readback: 004e
247.137: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004e
247.137: <09>Lane 00 nibble 1 adjusted value (post nibble): 004a
247.137: <09>Lane 01 nibble 1 raw readback: 004a
247.137: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004a
247.137: <09>Lane 01 nibble 1 adjusted value (post nibble): 0048
247.137: <09>Lane 02 nibble 1 raw readback: 0047
247.137: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0047
247.137: <09>Lane 02 nibble 1 adjusted value (post nibble): 0047
247.137: <09>Lane 03 nibble 1 raw readback: 0044
247.137: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0044
247.137: <09>Lane 03 nibble 1 adjusted value (post nibble): 0045
247.137: <09>Lane 04 nibble 1 raw readback: 0039
247.137: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
247.137: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
247.137: <09>Lane 05 nibble 1 raw readback: 003e
247.137: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003e
247.137: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
247.137: <09>Lane 06 nibble 1 raw readback: 0040
247.137: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0040
247.137: <09>Lane 06 nibble 1 adjusted value (post nibble): 0043
247.137: <09>Lane 07 nibble 1 raw readback: 0041
247.137: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0041
247.137: <09>Lane 07 nibble 1 adjusted value (post nibble): 0044
247.137: <09>Lane 08 nibble 1 raw readback: 003b
247.137: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003b
247.137: <09>Lane 08 nibble 1 adjusted value (post nibble): 0041
247.137: <09>original critical gross delay: 0
247.137: <09>new critical gross delay: 0
247.137: DIMM 0 RttNom: 3
247.137: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.137: DIMM 0 RttNom: 3
247.137: DIMM 0 RttWr: 2
247.137: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.137: DIMM 0 RttWr: 2
247.137: DIMM 0 RttNom: 3
247.138: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.138: DIMM 0 RttNom: 3
247.138: DIMM 0 RttWr: 2
247.138: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.138: DIMM 0 RttWr: 2
247.138: DIMM 1 RttNom: 3
247.138: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.138: DIMM 0 RttNom: 3
247.138: DIMM 1 RttWr: 2
247.138: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.138: DIMM 0 RttWr: 2
247.138: DIMM 1 RttNom: 3
247.138: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.138: DIMM 0 RttNom: 3
247.138: DIMM 1 RttWr: 2
247.138: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.138: DIMM 0 RttWr: 2
247.138: AgesaHwWlPhase1: training nibble 0
247.138: DIMM 1 RttNom: 3
247.138: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.138: DIMM 1 RttWr: 2
247.138: DIMM 1 RttWr: 2
247.138: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.138: DIMM 1 RttWr: 2
247.138: DIMM 1 RttNom: 3
247.138: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.138: DIMM 1 RttNom: 3
247.138: DIMM 1 RttWr: 2
247.138: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.138: DIMM 1 RttWr: 2
247.138: DIMM 0 RttNom: 3
247.138: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.138: DIMM 1 RttNom: 3
247.138: DIMM 0 RttWr: 2
247.138: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.138: DIMM 1 RttWr: 2
247.138: DIMM 0 RttNom: 3
247.138: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.138: DIMM 1 RttNom: 3
247.138: DIMM 0 RttWr: 2
247.138: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.138: DIMM 1 RttWr: 2
247.138: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.138: <09>Lane 00 scaled delay: 0047
247.138: <09>Lane 00 new seed: 0047
247.138: <09>Lane 01 scaled delay: 0047
247.138: <09>Lane 01 new seed: 0047
247.138: <09>Lane 02 scaled delay: 0047
247.138: <09>Lane 02 new seed: 0047
247.138: <09>Lane 03 scaled delay: 0047
247.138: <09>Lane 03 new seed: 0047
247.138: <09>Lane 04 scaled delay: 0047
247.138: <09>Lane 04 new seed: 0047
247.138: <09>Lane 05 scaled delay: 0047
247.138: <09>Lane 05 new seed: 0047
247.138: <09>Lane 06 scaled delay: 0047
247.138: <09>Lane 06 new seed: 0047
247.138: <09>Lane 07 scaled delay: 0047
247.138: <09>Lane 07 new seed: 0047
247.138: <09>Lane 08 scaled delay: 0047
247.138: <09>Lane 08 new seed: 0047
247.138: <09>Lane 00 nibble 0 raw readback: 0044
247.138: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0044
247.138: <09>Lane 00 nibble 0 adjusted value (post nibble): 0044
247.139: <09>Lane 01 nibble 0 raw readback: 0040
247.138: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0040
247.139: <09>Lane 01 nibble 0 adjusted value (post nibble): 0040
247.139: <09>Lane 02 nibble 0 raw readback: 003d
247.139: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003d
247.139: <09>Lane 02 nibble 0 adjusted value (post nibble): 003d
247.139: <09>Lane 03 nibble 0 raw readback: 003a
247.139: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003a
247.139: <09>Lane 03 nibble 0 adjusted value (post nibble): 003a
247.139: <09>Lane 04 nibble 0 raw readback: 002f
247.139: <09>Lane 04 nibble 0 adjusted value (pre nibble): 002f
247.139: <09>Lane 04 nibble 0 adjusted value (post nibble): 002f
247.139: <09>Lane 05 nibble 0 raw readback: 0033
247.139: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0033
247.139: <09>Lane 05 nibble 0 adjusted value (post nibble): 0033
247.139: <09>Lane 06 nibble 0 raw readback: 0036
247.139: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0036
247.139: <09>Lane 06 nibble 0 adjusted value (post nibble): 0036
247.139: <09>Lane 07 nibble 0 raw readback: 0039
247.139: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0039
247.139: <09>Lane 07 nibble 0 adjusted value (post nibble): 0039
247.139: <09>Lane 08 nibble 0 raw readback: 0032
247.139: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0032
247.139: <09>Lane 08 nibble 0 adjusted value (post nibble): 0032
247.139: AgesaHwWlPhase1: training nibble 1
247.139: DIMM 1 RttNom: 3
247.139: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.139: DIMM 1 RttWr: 2
247.139: DIMM 1 RttWr: 2
247.139: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.139: DIMM 1 RttWr: 2
247.139: DIMM 1 RttNom: 3
247.139: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.139: DIMM 1 RttNom: 3
247.139: DIMM 1 RttWr: 2
247.139: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.139: DIMM 1 RttWr: 2
247.139: DIMM 0 RttNom: 3
247.139: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.139: DIMM 1 RttNom: 3
247.139: DIMM 0 RttWr: 2
247.139: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.139: DIMM 1 RttWr: 2
247.139: DIMM 0 RttNom: 3
247.139: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.139: DIMM 1 RttNom: 3
247.139: DIMM 0 RttWr: 2
247.139: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.139: DIMM 1 RttWr: 2
247.139: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.139: <09>Lane 00 new seed: 0047
247.139: <09>Lane 01 new seed: 0047
247.139: <09>Lane 02 new seed: 0047
247.139: <09>Lane 03 new seed: 0047
247.139: <09>Lane 04 new seed: 0047
247.139: <09>Lane 05 new seed: 0047
247.139: <09>Lane 06 new seed: 0047
247.139: <09>Lane 07 new seed: 0047
247.139: <09>Lane 08 new seed: 0047
247.139: <09>Lane 00 nibble 1 raw readback: 0043
247.139: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0043
247.139: <09>Lane 00 nibble 1 adjusted value (post nibble): 0045
247.139: <09>Lane 01 nibble 1 raw readback: 0040
247.139: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0040
247.139: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
247.139: <09>Lane 02 nibble 1 raw readback: 003d
247.139: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003d
247.139: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
247.139: <09>Lane 03 nibble 1 raw readback: 003b
247.139: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
247.139: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
247.139: <09>Lane 04 nibble 1 raw readback: 0030
247.139: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0030
247.139: <09>Lane 04 nibble 1 adjusted value (post nibble): 003b
247.139: <09>Lane 05 nibble 1 raw readback: 0033
247.140: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0033
247.140: <09>Lane 05 nibble 1 adjusted value (post nibble): 003d
247.140: <09>Lane 06 nibble 1 raw readback: 0036
247.140: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0036
247.140: <09>Lane 06 nibble 1 adjusted value (post nibble): 003e
247.140: <09>Lane 07 nibble 1 raw readback: 0039
247.140: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0039
247.140: <09>Lane 07 nibble 1 adjusted value (post nibble): 0040
247.140: <09>Lane 08 nibble 1 raw readback: 0032
247.140: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0032
247.140: <09>Lane 08 nibble 1 adjusted value (post nibble): 003c
247.140: <09>original critical gross delay: 0
247.140: <09>new critical gross delay: 0
247.140: DIMM 1 RttNom: 3
247.140: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.140: DIMM 1 RttNom: 3
247.140: DIMM 1 RttWr: 2
247.140: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.140: DIMM 1 RttWr: 2
247.140: DIMM 1 RttNom: 3
247.140: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.140: DIMM 1 RttNom: 3
247.140: DIMM 1 RttWr: 2
247.140: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.140: DIMM 1 RttWr: 2
247.140: DIMM 0 RttNom: 3
247.140: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.140: DIMM 1 RttNom: 3
247.140: DIMM 0 RttWr: 2
247.140: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.140: DIMM 1 RttWr: 2
247.140: DIMM 0 RttNom: 3
247.140: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.140: DIMM 1 RttNom: 3
247.140: DIMM 0 RttWr: 2
247.140: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.140: DIMM 1 RttWr: 2
247.140: SetTargetFreq: Start
247.140: SetTargetFreq: Node 2: New frequency code: 000a
247.140: ChangeMemClk: Start
247.140: set_2t_configuration: Start
247.140: set_2t_configuration: Done
247.140: mct_BeforePlatformSpec: Start
247.140: mct_BeforePlatformSpec: Done
247.141: mct_PlatformSpec: Start
247.141: Programmed DCT 0 timing/termination pattern 003a3c3a 30222222
247.141: mct_PlatformSpec: Done
247.141: set_2t_configuration: Start
247.141: set_2t_configuration: Done
247.141: mct_BeforePlatformSpec: Start
247.141: mct_BeforePlatformSpec: Done
247.141: mct_PlatformSpec: Start
247.141: Programmed DCT 1 timing/termination pattern 003a3c3a 30222222
247.141: mct_PlatformSpec: Done
247.141: ChangeMemClk: Done
247.141: phyAssistedMemFnceTraining: Start
247.141: phyAssistedMemFnceTraining: training node 2 DCT 0
247.141: phyAssistedMemFnceTraining: done training node 2 DCT 0
247.141: phyAssistedMemFnceTraining: training node 2 DCT 1
247.141: phyAssistedMemFnceTraining: done training node 2 DCT 1
247.141: phyAssistedMemFnceTraining: Done
247.141: InitPhyCompensation: DCT 0: Start
247.141: Waiting for predriver calibration to be applied...done!
247.141: InitPhyCompensation: DCT 0: Done
247.141: phyAssistedMemFnceTraining: Start
247.141: phyAssistedMemFnceTraining: training node 2 DCT 0
247.141: phyAssistedMemFnceTraining: done training node 2 DCT 0
247.141: phyAssistedMemFnceTraining: training node 2 DCT 1
247.141: phyAssistedMemFnceTraining: done training node 2 DCT 1
247.141: phyAssistedMemFnceTraining: Done
247.141: InitPhyCompensation: DCT 1: Start
247.142: Waiting for predriver calibration to be applied...done!
247.142: InitPhyCompensation: DCT 1: Done
247.142: Preparing to send DCT 0 DIMM 0 RC10: 01 (F2xA8: 02000300)
247.142: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.142: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
247.142: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.142: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
247.142: Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 02000c00)
247.142: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.142: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
247.142: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.142: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
247.142: Preparing to send DCT 1 DIMM 0 RC10: 01 (F2xA8: 02000300)
247.142: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.142: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
247.142: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.142: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
247.142: Preparing to send DCT 1 DIMM 1 RC10: 01 (F2xA8: 02000c00)
247.142: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.142: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
247.142: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.142: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
247.142: SetTargetFreq: Done
247.142: SPD2ndTiming: Start
247.143: SPD2ndTiming: Done
247.143: mct_BeforeDramInit_Prod_D: Start
247.143: mct_ProgramODT_D: Start
247.143: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
247.143: mct_ProgramODT_D: Done
247.143: mct_BeforeDramInit_Prod_D: Done
247.143: mct_DramInit_Sw_D: Start
247.143: DIMM 0 RttWr: 1
247.143: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.143: mct_SendMrsCmd: Start
247.143: mct_SendMrsCmd: Done
247.143: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
247.143: mct_SendMrsCmd: Start
247.143: mct_SendMrsCmd: Done
247.143: DIMM 0 RttNom: 3
247.143: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.143: mct_SendMrsCmd: Start
247.143: mct_SendMrsCmd: Done
247.143: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001978
247.143: mct_SendMrsCmd: Start
247.143: mct_SendMrsCmd: Done
247.143: DIMM 0 RttWr: 1
247.143: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.143: mct_SendMrsCmd: Start
247.143: mct_SendMrsCmd: Done
247.143: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
247.143: mct_SendMrsCmd: Start
247.143: mct_SendMrsCmd: Done
247.143: DIMM 0 RttNom: 3
247.143: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.143: mct_SendMrsCmd: Start
247.143: mct_SendMrsCmd: Done
247.143: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201978
247.143: mct_SendMrsCmd: Start
247.143: mct_SendMrsCmd: Done
247.143: DIMM 1 RttWr: 1
247.143: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.143: mct_SendMrsCmd: Start
247.143: mct_SendMrsCmd: Done
247.143: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
247.143: mct_SendMrsCmd: Start
247.143: mct_SendMrsCmd: Done
247.143: DIMM 1 RttNom: 3
247.143: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.143: mct_SendMrsCmd: Start
247.143: mct_SendMrsCmd: Done
247.143: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401978
247.143: mct_SendMrsCmd: Start
247.143: mct_SendMrsCmd: Done
247.143: DIMM 1 RttWr: 1
247.143: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.143: mct_SendMrsCmd: Start
247.143: mct_SendMrsCmd: Done
247.143: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
247.144: mct_SendMrsCmd: Start
247.143: mct_SendMrsCmd: Done
247.143: DIMM 1 RttNom: 3
247.143: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.143: mct_SendMrsCmd: Start
247.143: mct_SendMrsCmd: Done
247.143: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601978
247.143: mct_SendMrsCmd: Start
247.143: mct_SendMrsCmd: Done
247.143: mct_DramInit_Sw_D: Done
247.144: AgesaHwWlPhase1: training nibble 0
247.144: DIMM 0 RttNom: 3
247.144: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.144: DIMM 0 RttWr: 1
247.144: DIMM 0 RttWr: 1
247.144: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.144: DIMM 0 RttWr: 1
247.144: DIMM 0 RttNom: 3
247.144: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.144: DIMM 0 RttNom: 3
247.144: DIMM 0 RttWr: 1
247.144: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.144: DIMM 0 RttWr: 1
247.144: DIMM 1 RttNom: 3
247.144: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.144: DIMM 0 RttNom: 3
247.144: DIMM 1 RttWr: 1
247.144: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.144: DIMM 0 RttWr: 1
247.144: DIMM 1 RttNom: 3
247.144: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.144: DIMM 0 RttNom: 3
247.144: DIMM 1 RttWr: 1
247.144: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.144: DIMM 0 RttWr: 1
247.144: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.144: <09>Lane 00 scaled delay: 0057
247.144: <09>Lane 00 new seed: 0057
247.144: <09>Lane 01 scaled delay: 0055
247.144: <09>Lane 01 new seed: 0055
247.144: <09>Lane 02 scaled delay: 0053
247.144: <09>Lane 02 new seed: 0053
247.144: <09>Lane 03 scaled delay: 0052
247.144: <09>Lane 03 new seed: 0052
247.144: <09>Lane 04 scaled delay: 004b
247.144: <09>Lane 04 new seed: 004b
247.144: <09>Lane 05 scaled delay: 004d
247.144: <09>Lane 05 new seed: 004d
247.144: <09>Lane 06 scaled delay: 004f
247.144: <09>Lane 06 new seed: 004f
247.144: <09>Lane 07 scaled delay: 004f
247.144: <09>Lane 07 new seed: 004f
247.145: <09>Lane 08 scaled delay: 004b
247.145: <09>Lane 08 new seed: 004b
247.145: <09>Lane 00 nibble 0 raw readback: 0060
247.145: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0060
247.145: <09>Lane 00 nibble 0 adjusted value (post nibble): 0060
247.145: <09>Lane 01 nibble 0 raw readback: 0057
247.145: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0057
247.145: <09>Lane 01 nibble 0 adjusted value (post nibble): 0057
247.145: <09>Lane 02 nibble 0 raw readback: 0055
247.145: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0055
247.145: <09>Lane 02 nibble 0 adjusted value (post nibble): 0055
247.145: <09>Lane 03 nibble 0 raw readback: 0051
247.145: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0051
247.145: <09>Lane 03 nibble 0 adjusted value (post nibble): 0051
247.145: <09>Lane 04 nibble 0 raw readback: 0044
247.145: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0044
247.145: <09>Lane 04 nibble 0 adjusted value (post nibble): 0044
247.145: <09>Lane 05 nibble 0 raw readback: 0049
247.145: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0049
247.145: <09>Lane 05 nibble 0 adjusted value (post nibble): 0049
247.145: <09>Lane 06 nibble 0 raw readback: 004d
247.145: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004d
247.145: <09>Lane 06 nibble 0 adjusted value (post nibble): 004d
247.145: <09>Lane 07 nibble 0 raw readback: 0051
247.145: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0051
247.145: <09>Lane 07 nibble 0 adjusted value (post nibble): 0051
247.145: <09>Lane 08 nibble 0 raw readback: 0046
247.145: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0046
247.145: <09>Lane 08 nibble 0 adjusted value (post nibble): 0046
247.145: AgesaHwWlPhase1: training nibble 1
247.145: DIMM 0 RttNom: 3
247.145: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.145: DIMM 0 RttWr: 1
247.145: DIMM 0 RttWr: 1
247.145: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.145: DIMM 0 RttWr: 1
247.145: DIMM 0 RttNom: 3
247.145: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.145: DIMM 0 RttNom: 3
247.145: DIMM 0 RttWr: 1
247.145: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.145: DIMM 0 RttWr: 1
247.145: DIMM 1 RttNom: 3
247.145: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.145: DIMM 0 RttNom: 3
247.145: DIMM 1 RttWr: 1
247.145: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.145: DIMM 0 RttWr: 1
247.145: DIMM 1 RttNom: 3
247.145: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.145: DIMM 0 RttNom: 3
247.145: DIMM 1 RttWr: 1
247.145: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.145: DIMM 0 RttWr: 1
247.145: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.145: <09>Lane 00 new seed: 0057
247.145: <09>Lane 01 new seed: 0055
247.145: <09>Lane 02 new seed: 0053
247.145: <09>Lane 03 new seed: 0052
247.145: <09>Lane 04 new seed: 004b
247.145: <09>Lane 05 new seed: 004d
247.145: <09>Lane 06 new seed: 004f
247.146: <09>Lane 07 new seed: 004f
247.146: <09>Lane 08 new seed: 004b
247.146: <09>Lane 00 nibble 1 raw readback: 005f
247.146: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005f
247.146: <09>Lane 00 nibble 1 adjusted value (post nibble): 005b
247.146: <09>Lane 01 nibble 1 raw readback: 0059
247.146: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0059
247.146: <09>Lane 01 nibble 1 adjusted value (post nibble): 0057
247.146: <09>Lane 02 nibble 1 raw readback: 0056
247.146: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0056
247.146: <09>Lane 02 nibble 1 adjusted value (post nibble): 0054
247.146: <09>Lane 03 nibble 1 raw readback: 0052
247.146: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0052
247.146: <09>Lane 03 nibble 1 adjusted value (post nibble): 0052
247.146: <09>Lane 04 nibble 1 raw readback: 0043
247.146: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0043
247.146: <09>Lane 04 nibble 1 adjusted value (post nibble): 0047
247.146: <09>Lane 05 nibble 1 raw readback: 0048
247.146: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0048
247.146: <09>Lane 05 nibble 1 adjusted value (post nibble): 004a
247.146: <09>Lane 06 nibble 1 raw readback: 004e
247.146: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004e
247.146: <09>Lane 06 nibble 1 adjusted value (post nibble): 004e
247.146: <09>Lane 07 nibble 1 raw readback: 0050
247.146: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0050
247.146: <09>Lane 07 nibble 1 adjusted value (post nibble): 004f
247.146: <09>Lane 08 nibble 1 raw readback: 0045
247.146: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0045
247.146: <09>Lane 08 nibble 1 adjusted value (post nibble): 0048
247.146: <09>original critical gross delay: 0
247.146: <09>new critical gross delay: 0
247.146: DIMM 0 RttNom: 3
247.146: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.146: DIMM 0 RttNom: 3
247.146: DIMM 0 RttWr: 1
247.146: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.146: DIMM 0 RttWr: 1
247.146: DIMM 0 RttNom: 3
247.146: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.146: DIMM 0 RttNom: 3
247.146: DIMM 0 RttWr: 1
247.146: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.146: DIMM 0 RttWr: 1
247.146: DIMM 1 RttNom: 3
247.146: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.146: DIMM 0 RttNom: 3
247.146: DIMM 1 RttWr: 1
247.146: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.146: DIMM 0 RttWr: 1
247.146: DIMM 1 RttNom: 3
247.146: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.146: DIMM 0 RttNom: 3
247.146: DIMM 1 RttWr: 1
247.146: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.146: DIMM 0 RttWr: 1
247.146: AgesaHwWlPhase1: training nibble 0
247.146: DIMM 1 RttNom: 3
247.146: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.146: DIMM 1 RttWr: 1
247.147: DIMM 1 RttWr: 1
247.146: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.146: DIMM 1 RttWr: 1
247.147: DIMM 1 RttNom: 3
247.147: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.147: DIMM 1 RttNom: 3
247.147: DIMM 1 RttWr: 1
247.147: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.147: DIMM 1 RttWr: 1
247.147: DIMM 0 RttNom: 3
247.147: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.147: DIMM 1 RttNom: 3
247.147: DIMM 0 RttWr: 1
247.147: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.147: DIMM 1 RttWr: 1
247.147: DIMM 0 RttNom: 3
247.147: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.147: DIMM 1 RttNom: 3
247.147: DIMM 0 RttWr: 1
247.147: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.147: DIMM 1 RttWr: 1
247.147: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.147: <09>Lane 00 scaled delay: 0051
247.147: <09>Lane 00 new seed: 0051
247.147: <09>Lane 01 scaled delay: 004e
247.147: <09>Lane 01 new seed: 004e
247.147: <09>Lane 02 scaled delay: 004e
247.147: <09>Lane 02 new seed: 004e
247.147: <09>Lane 03 scaled delay: 004d
247.147: <09>Lane 03 new seed: 004d
247.147: <09>Lane 04 scaled delay: 0045
247.147: <09>Lane 04 new seed: 0045
247.147: <09>Lane 05 scaled delay: 0046
247.147: <09>Lane 05 new seed: 0046
247.147: <09>Lane 06 scaled delay: 0049
247.147: <09>Lane 06 new seed: 0049
247.147: <09>Lane 07 scaled delay: 004a
247.147: <09>Lane 07 new seed: 004a
247.147: <09>Lane 08 scaled delay: 0046
247.147: <09>Lane 08 new seed: 0046
247.147: <09>Lane 00 nibble 0 raw readback: 0054
247.147: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0054
247.147: <09>Lane 00 nibble 0 adjusted value (post nibble): 0054
247.147: <09>Lane 01 nibble 0 raw readback: 004b
247.147: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004b
247.147: <09>Lane 01 nibble 0 adjusted value (post nibble): 004b
247.147: <09>Lane 02 nibble 0 raw readback: 0048
247.147: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0048
247.147: <09>Lane 02 nibble 0 adjusted value (post nibble): 0048
247.147: <09>Lane 03 nibble 0 raw readback: 0044
247.147: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
247.147: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
247.147: <09>Lane 04 nibble 0 raw readback: 0035
247.147: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0035
247.147: <09>Lane 04 nibble 0 adjusted value (post nibble): 0035
247.147: <09>Lane 05 nibble 0 raw readback: 003d
247.147: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003d
247.147: <09>Lane 05 nibble 0 adjusted value (post nibble): 003d
247.147: <09>Lane 06 nibble 0 raw readback: 0040
247.147: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
247.147: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
247.147: <09>Lane 07 nibble 0 raw readback: 0044
247.147: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0044
247.147: <09>Lane 07 nibble 0 adjusted value (post nibble): 0044
247.147: <09>Lane 08 nibble 0 raw readback: 0039
247.147: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0039
247.147: <09>Lane 08 nibble 0 adjusted value (post nibble): 0039
247.147: AgesaHwWlPhase1: training nibble 1
247.147: DIMM 1 RttNom: 3
247.147: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.147: DIMM 1 RttWr: 1
247.147: DIMM 1 RttWr: 1
247.147: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.147: DIMM 1 RttWr: 1
247.147: DIMM 1 RttNom: 3
247.148: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.148: DIMM 1 RttNom: 3
247.148: DIMM 1 RttWr: 1
247.148: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.148: DIMM 1 RttWr: 1
247.148: DIMM 0 RttNom: 3
247.148: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.148: DIMM 1 RttNom: 3
247.148: DIMM 0 RttWr: 1
247.148: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.148: DIMM 1 RttWr: 1
247.148: DIMM 0 RttNom: 3
247.148: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.148: DIMM 1 RttNom: 3
247.148: DIMM 0 RttWr: 1
247.148: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.148: DIMM 1 RttWr: 1
247.148: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.148: <09>Lane 00 new seed: 0051
247.148: <09>Lane 01 new seed: 004e
247.148: <09>Lane 02 new seed: 004e
247.148: <09>Lane 03 new seed: 004d
247.148: <09>Lane 04 new seed: 0045
247.148: <09>Lane 05 new seed: 0046
247.148: <09>Lane 06 new seed: 0049
247.148: <09>Lane 07 new seed: 004a
247.148: <09>Lane 08 new seed: 0046
247.148: <09>Lane 00 nibble 1 raw readback: 0052
247.148: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0052
247.148: <09>Lane 00 nibble 1 adjusted value (post nibble): 0051
247.148: <09>Lane 01 nibble 1 raw readback: 004b
247.148: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004b
247.148: <09>Lane 01 nibble 1 adjusted value (post nibble): 004c
247.148: <09>Lane 02 nibble 1 raw readback: 004b
247.148: <09>Lane 02 nibble 1 adjusted value (pre nibble): 004b
247.148: <09>Lane 02 nibble 1 adjusted value (post nibble): 004c
247.148: <09>Lane 03 nibble 1 raw readback: 0046
247.148: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0046
247.148: <09>Lane 03 nibble 1 adjusted value (post nibble): 0049
247.148: <09>Lane 04 nibble 1 raw readback: 0038
247.148: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0038
247.148: <09>Lane 04 nibble 1 adjusted value (post nibble): 003e
247.148: <09>Lane 05 nibble 1 raw readback: 003c
247.148: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
247.148: <09>Lane 05 nibble 1 adjusted value (post nibble): 0041
247.148: <09>Lane 06 nibble 1 raw readback: 0040
247.148: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0040
247.148: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
247.148: <09>Lane 07 nibble 1 raw readback: 0045
247.148: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0045
247.148: <09>Lane 07 nibble 1 adjusted value (post nibble): 0047
247.148: <09>Lane 08 nibble 1 raw readback: 003a
247.148: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003a
247.148: <09>Lane 08 nibble 1 adjusted value (post nibble): 0040
247.148: <09>original critical gross delay: 0
247.148: <09>new critical gross delay: 0
247.148: DIMM 1 RttNom: 3
247.148: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.148: DIMM 1 RttNom: 3
247.148: DIMM 1 RttWr: 1
247.148: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.148: DIMM 1 RttWr: 1
247.148: DIMM 1 RttNom: 3
247.148: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.148: DIMM 1 RttNom: 3
247.149: DIMM 1 RttWr: 1
247.149: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.149: DIMM 1 RttWr: 1
247.149: DIMM 0 RttNom: 3
247.149: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.149: DIMM 1 RttNom: 3
247.149: DIMM 0 RttWr: 1
247.149: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.149: DIMM 1 RttWr: 1
247.149: DIMM 0 RttNom: 3
247.149: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.149: DIMM 1 RttNom: 3
247.149: DIMM 0 RttWr: 1
247.149: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.149: DIMM 1 RttWr: 1
247.149: SPD2ndTiming: Start
247.149: SPD2ndTiming: Done
247.149: mct_BeforeDramInit_Prod_D: Start
247.149: mct_ProgramODT_D: Start
247.149: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
247.149: mct_ProgramODT_D: Done
247.149: mct_BeforeDramInit_Prod_D: Done
247.149: mct_DramInit_Sw_D: Start
247.149: DIMM 0 RttWr: 1
247.149: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.149: mct_SendMrsCmd: Start
247.149: mct_SendMrsCmd: Done
247.149: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
247.149: mct_SendMrsCmd: Start
247.149: mct_SendMrsCmd: Done
247.149: DIMM 0 RttNom: 3
247.149: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.149: mct_SendMrsCmd: Start
247.149: mct_SendMrsCmd: Done
247.150: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001978
247.150: mct_SendMrsCmd: Start
247.150: mct_SendMrsCmd: Done
247.150: DIMM 0 RttWr: 1
247.150: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.150: mct_SendMrsCmd: Start
247.150: mct_SendMrsCmd: Done
247.150: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
247.150: mct_SendMrsCmd: Start
247.150: mct_SendMrsCmd: Done
247.150: DIMM 0 RttNom: 3
247.150: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.150: mct_SendMrsCmd: Start
247.150: mct_SendMrsCmd: Done
247.150: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201978
247.150: mct_SendMrsCmd: Start
247.150: mct_SendMrsCmd: Done
247.150: DIMM 1 RttWr: 1
247.150: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.150: mct_SendMrsCmd: Start
247.150: mct_SendMrsCmd: Done
247.150: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
247.150: mct_SendMrsCmd: Start
247.150: mct_SendMrsCmd: Done
247.150: DIMM 1 RttNom: 3
247.150: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.150: mct_SendMrsCmd: Start
247.150: mct_SendMrsCmd: Done
247.150: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401978
247.150: mct_SendMrsCmd: Start
247.150: mct_SendMrsCmd: Done
247.150: DIMM 1 RttWr: 1
247.150: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.150: mct_SendMrsCmd: Start
247.150: mct_SendMrsCmd: Done
247.150: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
247.150: mct_SendMrsCmd: Start
247.150: mct_SendMrsCmd: Done
247.150: DIMM 1 RttNom: 3
247.150: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.150: mct_SendMrsCmd: Start
247.150: mct_SendMrsCmd: Done
247.150: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601978
247.150: mct_SendMrsCmd: Start
247.150: mct_SendMrsCmd: Done
247.150: mct_DramInit_Sw_D: Done
247.150: AgesaHwWlPhase1: training nibble 0
247.150: DIMM 0 RttNom: 3
247.150: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.150: DIMM 0 RttWr: 1
247.150: DIMM 0 RttWr: 1
247.150: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.150: DIMM 0 RttWr: 1
247.150: DIMM 0 RttNom: 3
247.150: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.150: DIMM 0 RttNom: 3
247.150: DIMM 0 RttWr: 1
247.150: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.150: DIMM 0 RttWr: 1
247.150: DIMM 1 RttNom: 3
247.150: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.150: DIMM 0 RttNom: 3
247.150: DIMM 1 RttWr: 1
247.150: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.150: DIMM 0 RttWr: 1
247.150: DIMM 1 RttNom: 3
247.150: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.151: DIMM 0 RttNom: 3
247.151: DIMM 1 RttWr: 1
247.151: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.151: DIMM 0 RttWr: 1
247.151: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.151: <09>Lane 00 scaled delay: 0057
247.151: <09>Lane 00 new seed: 0057
247.151: <09>Lane 01 scaled delay: 0055
247.151: <09>Lane 01 new seed: 0055
247.151: <09>Lane 02 scaled delay: 0053
247.151: <09>Lane 02 new seed: 0053
247.151: <09>Lane 03 scaled delay: 0051
247.151: <09>Lane 03 new seed: 0051
247.151: <09>Lane 04 scaled delay: 004a
247.151: <09>Lane 04 new seed: 004a
247.151: <09>Lane 05 scaled delay: 004d
247.151: <09>Lane 05 new seed: 004d
247.151: <09>Lane 06 scaled delay: 004e
247.151: <09>Lane 06 new seed: 004e
247.151: <09>Lane 07 scaled delay: 004f
247.151: <09>Lane 07 new seed: 004f
247.151: <09>Lane 08 scaled delay: 004b
247.151: <09>Lane 08 new seed: 004b
247.151: <09>Lane 00 nibble 0 raw readback: 005c
247.151: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005c
247.151: <09>Lane 00 nibble 0 adjusted value (post nibble): 005c
247.151: <09>Lane 01 nibble 0 raw readback: 0058
247.151: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0058
247.151: <09>Lane 01 nibble 0 adjusted value (post nibble): 0058
247.151: <09>Lane 02 nibble 0 raw readback: 0053
247.151: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0053
247.151: <09>Lane 02 nibble 0 adjusted value (post nibble): 0053
247.151: <09>Lane 03 nibble 0 raw readback: 004f
247.151: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004f
247.151: <09>Lane 03 nibble 0 adjusted value (post nibble): 004f
247.151: <09>Lane 04 nibble 0 raw readback: 0041
247.151: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0041
247.151: <09>Lane 04 nibble 0 adjusted value (post nibble): 0041
247.151: <09>Lane 05 nibble 0 raw readback: 0046
247.151: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0046
247.151: <09>Lane 05 nibble 0 adjusted value (post nibble): 0046
247.151: <09>Lane 06 nibble 0 raw readback: 004b
247.151: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004b
247.151: <09>Lane 06 nibble 0 adjusted value (post nibble): 004b
247.151: <09>Lane 07 nibble 0 raw readback: 004d
247.151: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004d
247.151: <09>Lane 07 nibble 0 adjusted value (post nibble): 004d
247.151: <09>Lane 08 nibble 0 raw readback: 0044
247.151: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0044
247.151: <09>Lane 08 nibble 0 adjusted value (post nibble): 0044
247.151: AgesaHwWlPhase1: training nibble 1
247.151: DIMM 0 RttNom: 3
247.151: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.151: DIMM 0 RttWr: 1
247.151: DIMM 0 RttWr: 1
247.151: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.151: DIMM 0 RttWr: 1
247.151: DIMM 0 RttNom: 3
247.151: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.151: DIMM 0 RttNom: 3
247.151: DIMM 0 RttWr: 1
247.151: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.151: DIMM 0 RttWr: 1
247.152: DIMM 1 RttNom: 3
247.152: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.152: DIMM 0 RttNom: 3
247.152: DIMM 1 RttWr: 1
247.152: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.152: DIMM 0 RttWr: 1
247.152: DIMM 1 RttNom: 3
247.152: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.152: DIMM 0 RttNom: 3
247.152: DIMM 1 RttWr: 1
247.152: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.152: DIMM 0 RttWr: 1
247.152: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.152: <09>Lane 00 new seed: 0057
247.152: <09>Lane 01 new seed: 0055
247.152: <09>Lane 02 new seed: 0053
247.152: <09>Lane 03 new seed: 0051
247.152: <09>Lane 04 new seed: 004a
247.152: <09>Lane 05 new seed: 004d
247.152: <09>Lane 06 new seed: 004e
247.152: <09>Lane 07 new seed: 004f
247.152: <09>Lane 08 new seed: 004b
247.152: <09>Lane 00 nibble 1 raw readback: 005d
247.152: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005d
247.152: <09>Lane 00 nibble 1 adjusted value (post nibble): 005a
247.152: <09>Lane 01 nibble 1 raw readback: 0058
247.152: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0058
247.152: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
247.152: <09>Lane 02 nibble 1 raw readback: 0054
247.152: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0054
247.152: <09>Lane 02 nibble 1 adjusted value (post nibble): 0053
247.152: <09>Lane 03 nibble 1 raw readback: 0051
247.152: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0051
247.152: <09>Lane 03 nibble 1 adjusted value (post nibble): 0051
247.152: <09>Lane 04 nibble 1 raw readback: 0041
247.152: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0041
247.152: <09>Lane 04 nibble 1 adjusted value (post nibble): 0045
247.152: <09>Lane 05 nibble 1 raw readback: 0047
247.152: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0047
247.152: <09>Lane 05 nibble 1 adjusted value (post nibble): 004a
247.152: <09>Lane 06 nibble 1 raw readback: 004b
247.152: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004b
247.152: <09>Lane 06 nibble 1 adjusted value (post nibble): 004c
247.152: <09>Lane 07 nibble 1 raw readback: 004d
247.152: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004d
247.152: <09>Lane 07 nibble 1 adjusted value (post nibble): 004e
247.152: <09>Lane 08 nibble 1 raw readback: 0045
247.152: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0045
247.152: <09>Lane 08 nibble 1 adjusted value (post nibble): 0048
247.152: <09>original critical gross delay: 0
247.152: <09>new critical gross delay: 0
247.152: DIMM 0 RttNom: 3
247.152: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.152: DIMM 0 RttNom: 3
247.152: DIMM 0 RttWr: 1
247.152: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.152: DIMM 0 RttWr: 1
247.152: DIMM 0 RttNom: 3
247.152: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.152: DIMM 0 RttNom: 3
247.152: DIMM 0 RttWr: 1
247.152: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.153: DIMM 0 RttWr: 1
247.153: DIMM 1 RttNom: 3
247.153: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.153: DIMM 0 RttNom: 3
247.153: DIMM 1 RttWr: 1
247.153: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.153: DIMM 0 RttWr: 1
247.153: DIMM 1 RttNom: 3
247.153: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.153: DIMM 0 RttNom: 3
247.153: DIMM 1 RttWr: 1
247.153: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.153: DIMM 0 RttWr: 1
247.153: AgesaHwWlPhase1: training nibble 0
247.153: DIMM 1 RttNom: 3
247.153: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.153: DIMM 1 RttWr: 1
247.153: DIMM 1 RttWr: 1
247.153: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.153: DIMM 1 RttWr: 1
247.153: DIMM 1 RttNom: 3
247.153: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.153: DIMM 1 RttNom: 3
247.153: DIMM 1 RttWr: 1
247.153: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.153: DIMM 1 RttWr: 1
247.153: DIMM 0 RttNom: 3
247.153: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.153: DIMM 1 RttNom: 3
247.153: DIMM 0 RttWr: 1
247.153: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.153: DIMM 1 RttWr: 1
247.153: DIMM 0 RttNom: 3
247.153: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.153: DIMM 1 RttNom: 3
247.153: DIMM 0 RttWr: 1
247.153: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.153: DIMM 1 RttWr: 1
247.153: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.153: <09>Lane 00 scaled delay: 0051
247.153: <09>Lane 00 new seed: 0051
247.153: <09>Lane 01 scaled delay: 004e
247.153: <09>Lane 01 new seed: 004e
247.153: <09>Lane 02 scaled delay: 004d
247.153: <09>Lane 02 new seed: 004d
247.153: <09>Lane 03 scaled delay: 004b
247.153: <09>Lane 03 new seed: 004b
247.153: <09>Lane 04 scaled delay: 0043
247.153: <09>Lane 04 new seed: 0043
247.153: <09>Lane 05 scaled delay: 0046
247.153: <09>Lane 05 new seed: 0046
247.153: <09>Lane 06 scaled delay: 0047
247.153: <09>Lane 06 new seed: 0047
247.153: <09>Lane 07 scaled delay: 004a
247.153: <09>Lane 07 new seed: 004a
247.153: <09>Lane 08 scaled delay: 0045
247.153: <09>Lane 08 new seed: 0045
247.153: <09>Lane 00 nibble 0 raw readback: 0050
247.153: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0050
247.153: <09>Lane 00 nibble 0 adjusted value (post nibble): 0050
247.153: <09>Lane 01 nibble 0 raw readback: 004c
247.153: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004c
247.153: <09>Lane 01 nibble 0 adjusted value (post nibble): 004c
247.153: <09>Lane 02 nibble 0 raw readback: 0048
247.154: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0048
247.153: <09>Lane 02 nibble 0 adjusted value (post nibble): 0048
247.154: <09>Lane 03 nibble 0 raw readback: 0044
247.154: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
247.154: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
247.154: <09>Lane 04 nibble 0 raw readback: 0036
247.154: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0036
247.154: <09>Lane 04 nibble 0 adjusted value (post nibble): 0036
247.154: <09>Lane 05 nibble 0 raw readback: 003b
247.154: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003b
247.154: <09>Lane 05 nibble 0 adjusted value (post nibble): 003b
247.154: <09>Lane 06 nibble 0 raw readback: 003e
247.154: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003e
247.154: <09>Lane 06 nibble 0 adjusted value (post nibble): 003e
247.154: <09>Lane 07 nibble 0 raw readback: 0042
247.154: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0042
247.154: <09>Lane 07 nibble 0 adjusted value (post nibble): 0042
247.154: <09>Lane 08 nibble 0 raw readback: 0039
247.154: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0039
247.154: <09>Lane 08 nibble 0 adjusted value (post nibble): 0039
247.154: AgesaHwWlPhase1: training nibble 1
247.154: DIMM 1 RttNom: 3
247.154: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.154: DIMM 1 RttWr: 1
247.154: DIMM 1 RttWr: 1
247.154: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.154: DIMM 1 RttWr: 1
247.154: DIMM 1 RttNom: 3
247.154: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.154: DIMM 1 RttNom: 3
247.154: DIMM 1 RttWr: 1
247.154: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.154: DIMM 1 RttWr: 1
247.154: DIMM 0 RttNom: 3
247.154: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.154: DIMM 1 RttNom: 3
247.154: DIMM 0 RttWr: 1
247.154: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.154: DIMM 1 RttWr: 1
247.154: DIMM 0 RttNom: 3
247.154: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.154: DIMM 1 RttNom: 3
247.154: DIMM 0 RttWr: 1
247.154: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.154: DIMM 1 RttWr: 1
247.154: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.154: <09>Lane 00 new seed: 0051
247.154: <09>Lane 01 new seed: 004e
247.154: <09>Lane 02 new seed: 004d
247.154: <09>Lane 03 new seed: 004b
247.154: <09>Lane 04 new seed: 0043
247.154: <09>Lane 05 new seed: 0046
247.154: <09>Lane 06 new seed: 0047
247.154: <09>Lane 07 new seed: 004a
247.154: <09>Lane 08 new seed: 0045
247.154: <09>Lane 00 nibble 1 raw readback: 004f
247.154: <09>Lane 00 nibble 1 adjusted value (pre nibble): 004f
247.154: <09>Lane 00 nibble 1 adjusted value (post nibble): 0050
247.154: <09>Lane 01 nibble 1 raw readback: 004a
247.154: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004a
247.154: <09>Lane 01 nibble 1 adjusted value (post nibble): 004c
247.154: <09>Lane 02 nibble 1 raw readback: 0047
247.154: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0047
247.154: <09>Lane 02 nibble 1 adjusted value (post nibble): 004a
247.154: <09>Lane 03 nibble 1 raw readback: 0045
247.154: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
247.154: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
247.154: <09>Lane 04 nibble 1 raw readback: 0036
247.154: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0036
247.154: <09>Lane 04 nibble 1 adjusted value (post nibble): 003c
247.154: <09>Lane 05 nibble 1 raw readback: 003a
247.154: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003a
247.154: <09>Lane 05 nibble 1 adjusted value (post nibble): 0040
247.154: <09>Lane 06 nibble 1 raw readback: 003e
247.154: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003e
247.155: <09>Lane 06 nibble 1 adjusted value (post nibble): 0042
247.155: <09>Lane 07 nibble 1 raw readback: 0042
247.155: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
247.155: <09>Lane 07 nibble 1 adjusted value (post nibble): 0046
247.155: <09>Lane 08 nibble 1 raw readback: 0039
247.155: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0039
247.155: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
247.155: <09>original critical gross delay: 0
247.155: <09>new critical gross delay: 0
247.155: DIMM 1 RttNom: 3
247.155: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.155: DIMM 1 RttNom: 3
247.155: DIMM 1 RttWr: 1
247.155: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.155: DIMM 1 RttWr: 1
247.155: DIMM 1 RttNom: 3
247.155: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.155: DIMM 1 RttNom: 3
247.155: DIMM 1 RttWr: 1
247.155: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.155: DIMM 1 RttWr: 1
247.155: DIMM 0 RttNom: 3
247.155: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.155: DIMM 1 RttNom: 3
247.155: DIMM 0 RttWr: 1
247.155: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.155: DIMM 1 RttWr: 1
247.155: DIMM 0 RttNom: 3
247.155: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.155: DIMM 1 RttNom: 3
247.155: DIMM 0 RttWr: 1
247.155: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.155: DIMM 1 RttWr: 1
247.155: SetTargetFreq: Start
247.155: SetTargetFreq: Node 2: New frequency code: 000e
247.155: ChangeMemClk: Start
247.155: set_2t_configuration: Start
247.155: set_2t_configuration: Done
247.155: mct_BeforePlatformSpec: Start
247.155: mct_BeforePlatformSpec: Done
247.155: mct_PlatformSpec: Start
247.156: Programmed DCT 0 timing/termination pattern 00383a38 30222222
247.156: mct_PlatformSpec: Done
247.156: set_2t_configuration: Start
247.156: set_2t_configuration: Done
247.156: mct_BeforePlatformSpec: Start
247.156: mct_BeforePlatformSpec: Done
247.156: mct_PlatformSpec: Start
247.156: Programmed DCT 1 timing/termination pattern 00383a38 30222222
247.156: mct_PlatformSpec: Done
247.156: ChangeMemClk: Done
247.156: phyAssistedMemFnceTraining: Start
247.156: phyAssistedMemFnceTraining: training node 2 DCT 0
247.156: phyAssistedMemFnceTraining: done training node 2 DCT 0
247.156: phyAssistedMemFnceTraining: training node 2 DCT 1
247.156: phyAssistedMemFnceTraining: done training node 2 DCT 1
247.156: phyAssistedMemFnceTraining: Done
247.156: InitPhyCompensation: DCT 0: Start
247.156: Waiting for predriver calibration to be applied...done!
247.156: InitPhyCompensation: DCT 0: Done
247.156: phyAssistedMemFnceTraining: Start
247.156: phyAssistedMemFnceTraining: training node 2 DCT 0
247.156: phyAssistedMemFnceTraining: done training node 2 DCT 0
247.156: phyAssistedMemFnceTraining: training node 2 DCT 1
247.156: phyAssistedMemFnceTraining: done training node 2 DCT 1
247.157: phyAssistedMemFnceTraining: Done
247.156: InitPhyCompensation: DCT 1: Start
247.157: Waiting for predriver calibration to be applied...done!
247.157: InitPhyCompensation: DCT 1: Done
247.157: Preparing to send DCT 0 DIMM 0 RC10: 02 (F2xA8: 02000300)
247.157: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.157: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
247.157: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.157: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
247.157: Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 02000c00)
247.157: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.157: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
247.157: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.157: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
247.157: Preparing to send DCT 1 DIMM 0 RC10: 02 (F2xA8: 02000300)
247.157: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.157: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
247.157: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.157: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
247.157: Preparing to send DCT 1 DIMM 1 RC10: 02 (F2xA8: 02000c00)
247.157: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.157: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
247.157: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.157: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
247.157: SetTargetFreq: Done
247.157: SPD2ndTiming: Start
247.158: SPD2ndTiming: Done
247.158: mct_BeforeDramInit_Prod_D: Start
247.158: mct_ProgramODT_D: Start
247.158: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
247.158: mct_ProgramODT_D: Done
247.158: mct_BeforeDramInit_Prod_D: Done
247.158: mct_DramInit_Sw_D: Start
247.158: DIMM 0 RttWr: 2
247.158: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.158: mct_SendMrsCmd: Start
247.158: mct_SendMrsCmd: Done
247.158: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
247.158: mct_SendMrsCmd: Start
247.158: mct_SendMrsCmd: Done
247.158: DIMM 0 RttNom: 5
247.158: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.158: mct_SendMrsCmd: Start
247.158: mct_SendMrsCmd: Done
247.158: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001b78
247.158: mct_SendMrsCmd: Start
247.158: mct_SendMrsCmd: Done
247.158: DIMM 0 RttWr: 2
247.158: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.158: mct_SendMrsCmd: Start
247.158: mct_SendMrsCmd: Done
247.158: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
247.158: mct_SendMrsCmd: Start
247.158: mct_SendMrsCmd: Done
247.158: DIMM 0 RttNom: 5
247.158: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.158: mct_SendMrsCmd: Start
247.158: mct_SendMrsCmd: Done
247.158: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201b78
247.158: mct_SendMrsCmd: Start
247.158: mct_SendMrsCmd: Done
247.158: DIMM 1 RttWr: 2
247.158: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.158: mct_SendMrsCmd: Start
247.158: mct_SendMrsCmd: Done
247.158: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
247.158: mct_SendMrsCmd: Start
247.158: mct_SendMrsCmd: Done
247.158: DIMM 1 RttNom: 5
247.158: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.158: mct_SendMrsCmd: Start
247.158: mct_SendMrsCmd: Done
247.158: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b78
247.158: mct_SendMrsCmd: Start
247.158: mct_SendMrsCmd: Done
247.158: DIMM 1 RttWr: 2
247.158: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.158: mct_SendMrsCmd: Start
247.158: mct_SendMrsCmd: Done
247.158: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
247.158: mct_SendMrsCmd: Start
247.158: mct_SendMrsCmd: Done
247.158: DIMM 1 RttNom: 5
247.158: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.158: mct_SendMrsCmd: Start
247.158: mct_SendMrsCmd: Done
247.158: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b78
247.158: mct_SendMrsCmd: Start
247.158: mct_SendMrsCmd: Done
247.158: mct_DramInit_Sw_D: Done
247.159: AgesaHwWlPhase1: training nibble 0
247.159: DIMM 0 RttNom: 5
247.159: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.159: DIMM 0 RttWr: 2
247.159: DIMM 0 RttWr: 2
247.159: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.159: DIMM 0 RttWr: 2
247.159: DIMM 0 RttNom: 5
247.159: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.159: DIMM 0 RttNom: 5
247.159: DIMM 0 RttWr: 2
247.159: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.159: DIMM 0 RttWr: 2
247.159: DIMM 1 RttNom: 5
247.159: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.159: DIMM 0 RttNom: 5
247.159: DIMM 1 RttWr: 2
247.159: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.159: DIMM 0 RttWr: 2
247.159: DIMM 1 RttNom: 5
247.159: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.159: DIMM 0 RttNom: 5
247.159: DIMM 1 RttWr: 2
247.159: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.159: DIMM 0 RttWr: 2
247.159: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.159: <09>Lane 00 scaled delay: 0069
247.159: <09>Lane 00 new seed: 0069
247.159: <09>Lane 01 scaled delay: 0064
247.159: <09>Lane 01 new seed: 0064
247.159: <09>Lane 02 scaled delay: 0061
247.159: <09>Lane 02 new seed: 0061
247.159: <09>Lane 03 scaled delay: 005e
247.159: <09>Lane 03 new seed: 005e
247.159: <09>Lane 04 scaled delay: 0050
247.159: <09>Lane 04 new seed: 0050
247.159: <09>Lane 05 scaled delay: 0054
247.159: <09>Lane 05 new seed: 0054
247.159: <09>Lane 06 scaled delay: 0059
247.160: <09>Lane 06 new seed: 0059
247.159: <09>Lane 07 scaled delay: 005a
247.160: <09>Lane 07 new seed: 005a
247.160: <09>Lane 08 scaled delay: 0052
247.160: <09>Lane 08 new seed: 0052
247.160: <09>Lane 00 nibble 0 raw readback: 002f
247.160: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006f
247.160: <09>Lane 00 nibble 0 adjusted value (post nibble): 006f
247.160: <09>Lane 01 nibble 0 raw readback: 0024
247.160: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0064
247.160: <09>Lane 01 nibble 0 adjusted value (post nibble): 0064
247.160: <09>Lane 02 nibble 0 raw readback: 0021
247.160: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0061
247.160: <09>Lane 02 nibble 0 adjusted value (post nibble): 0061
247.160: <09>Lane 03 nibble 0 raw readback: 005c
247.160: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005c
247.160: <09>Lane 03 nibble 0 adjusted value (post nibble): 005c
247.160: <09>Lane 04 nibble 0 raw readback: 004b
247.160: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004b
247.160: <09>Lane 04 nibble 0 adjusted value (post nibble): 004b
247.160: <09>Lane 05 nibble 0 raw readback: 0054
247.160: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0054
247.160: <09>Lane 05 nibble 0 adjusted value (post nibble): 0054
247.160: <09>Lane 06 nibble 0 raw readback: 0058
247.160: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0058
247.160: <09>Lane 06 nibble 0 adjusted value (post nibble): 0058
247.160: <09>Lane 07 nibble 0 raw readback: 005c
247.160: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005c
247.160: <09>Lane 07 nibble 0 adjusted value (post nibble): 005c
247.160: <09>Lane 08 nibble 0 raw readback: 004e
247.160: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004e
247.160: <09>Lane 08 nibble 0 adjusted value (post nibble): 004e
247.160: AgesaHwWlPhase1: training nibble 1
247.160: DIMM 0 RttNom: 5
247.160: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.160: DIMM 0 RttWr: 2
247.160: DIMM 0 RttWr: 2
247.160: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.160: DIMM 0 RttWr: 2
247.160: DIMM 0 RttNom: 5
247.160: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.160: DIMM 0 RttNom: 5
247.160: DIMM 0 RttWr: 2
247.160: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.160: DIMM 0 RttWr: 2
247.160: DIMM 1 RttNom: 5
247.160: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.160: DIMM 0 RttNom: 5
247.160: DIMM 1 RttWr: 2
247.160: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.160: DIMM 0 RttWr: 2
247.160: DIMM 1 RttNom: 5
247.160: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.160: DIMM 0 RttNom: 5
247.160: DIMM 1 RttWr: 2
247.160: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.160: DIMM 0 RttWr: 2
247.160: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.160: <09>Lane 00 new seed: 0069
247.160: <09>Lane 01 new seed: 0064
247.160: <09>Lane 02 new seed: 0061
247.160: <09>Lane 03 new seed: 005e
247.160: <09>Lane 04 new seed: 0050
247.161: <09>Lane 05 new seed: 0054
247.161: <09>Lane 06 new seed: 0059
247.161: <09>Lane 07 new seed: 005a
247.161: <09>Lane 08 new seed: 0052
247.161: <09>Lane 00 nibble 1 raw readback: 002f
247.161: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006f
247.161: <09>Lane 00 nibble 1 adjusted value (post nibble): 006c
247.161: <09>Lane 01 nibble 1 raw readback: 0026
247.161: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0066
247.161: <09>Lane 01 nibble 1 adjusted value (post nibble): 0065
247.161: <09>Lane 02 nibble 1 raw readback: 0022
247.161: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0062
247.161: <09>Lane 02 nibble 1 adjusted value (post nibble): 0061
247.161: <09>Lane 03 nibble 1 raw readback: 005d
247.161: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005d
247.161: <09>Lane 03 nibble 1 adjusted value (post nibble): 005d
247.161: <09>Lane 04 nibble 1 raw readback: 004a
247.161: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004a
247.161: <09>Lane 04 nibble 1 adjusted value (post nibble): 004d
247.161: <09>Lane 05 nibble 1 raw readback: 0052
247.161: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0052
247.161: <09>Lane 05 nibble 1 adjusted value (post nibble): 0053
247.161: <09>Lane 06 nibble 1 raw readback: 0059
247.161: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0059
247.161: <09>Lane 06 nibble 1 adjusted value (post nibble): 0059
247.161: <09>Lane 07 nibble 1 raw readback: 005c
247.161: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005c
247.161: <09>Lane 07 nibble 1 adjusted value (post nibble): 005b
247.161: <09>Lane 08 nibble 1 raw readback: 004d
247.161: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004d
247.161: <09>Lane 08 nibble 1 adjusted value (post nibble): 004f
247.161: <09>original critical gross delay: 0
247.161: <09>new critical gross delay: 0
247.161: DIMM 0 RttNom: 5
247.161: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.161: DIMM 0 RttNom: 5
247.161: DIMM 0 RttWr: 2
247.161: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.161: DIMM 0 RttWr: 2
247.161: DIMM 0 RttNom: 5
247.161: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.161: DIMM 0 RttNom: 5
247.161: DIMM 0 RttWr: 2
247.161: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.161: DIMM 0 RttWr: 2
247.161: DIMM 1 RttNom: 5
247.161: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.161: DIMM 0 RttNom: 5
247.161: DIMM 1 RttWr: 2
247.161: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.161: DIMM 0 RttWr: 2
247.161: DIMM 1 RttNom: 5
247.161: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.161: DIMM 0 RttNom: 5
247.161: DIMM 1 RttWr: 2
247.161: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.161: DIMM 0 RttWr: 2
247.161: AgesaHwWlPhase1: training nibble 0
247.161: DIMM 1 RttNom: 5
247.161: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.162: DIMM 1 RttWr: 2
247.161: DIMM 1 RttWr: 2
247.161: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.162: DIMM 1 RttWr: 2
247.162: DIMM 1 RttNom: 5
247.162: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.162: DIMM 1 RttNom: 5
247.162: DIMM 1 RttWr: 2
247.162: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.162: DIMM 1 RttWr: 2
247.162: DIMM 0 RttNom: 5
247.162: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.162: DIMM 1 RttNom: 5
247.162: DIMM 0 RttWr: 2
247.162: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.162: DIMM 1 RttWr: 2
247.162: DIMM 0 RttNom: 5
247.162: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.162: DIMM 1 RttNom: 5
247.162: DIMM 0 RttWr: 2
247.162: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.162: DIMM 1 RttWr: 2
247.162: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.162: <09>Lane 00 scaled delay: 005d
247.162: <09>Lane 00 new seed: 005d
247.162: <09>Lane 01 scaled delay: 0057
247.162: <09>Lane 01 new seed: 0057
247.162: <09>Lane 02 scaled delay: 0057
247.162: <09>Lane 02 new seed: 0057
247.162: <09>Lane 03 scaled delay: 0053
247.162: <09>Lane 03 new seed: 0053
247.162: <09>Lane 04 scaled delay: 0045
247.162: <09>Lane 04 new seed: 0045
247.162: <09>Lane 05 scaled delay: 0049
247.162: <09>Lane 05 new seed: 0049
247.162: <09>Lane 06 scaled delay: 004d
247.162: <09>Lane 06 new seed: 004d
247.162: <09>Lane 07 scaled delay: 0050
247.162: <09>Lane 07 new seed: 0050
247.162: <09>Lane 08 scaled delay: 0048
247.162: <09>Lane 08 new seed: 0048
247.162: <09>Lane 00 nibble 0 raw readback: 0060
247.162: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0060
247.162: <09>Lane 00 nibble 0 adjusted value (post nibble): 0060
247.162: <09>Lane 01 nibble 0 raw readback: 0055
247.162: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0055
247.162: <09>Lane 01 nibble 0 adjusted value (post nibble): 0055
247.162: <09>Lane 02 nibble 0 raw readback: 0053
247.162: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0053
247.162: <09>Lane 02 nibble 0 adjusted value (post nibble): 0053
247.162: <09>Lane 03 nibble 0 raw readback: 004c
247.162: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004c
247.162: <09>Lane 03 nibble 0 adjusted value (post nibble): 004c
247.162: <09>Lane 04 nibble 0 raw readback: 003a
247.162: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
247.162: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
247.162: <09>Lane 05 nibble 0 raw readback: 0044
247.162: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0044
247.162: <09>Lane 05 nibble 0 adjusted value (post nibble): 0044
247.162: <09>Lane 06 nibble 0 raw readback: 0049
247.162: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0049
247.162: <09>Lane 06 nibble 0 adjusted value (post nibble): 0049
247.162: <09>Lane 07 nibble 0 raw readback: 004d
247.162: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004d
247.162: <09>Lane 07 nibble 0 adjusted value (post nibble): 004d
247.162: <09>Lane 08 nibble 0 raw readback: 003f
247.162: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003f
247.162: <09>Lane 08 nibble 0 adjusted value (post nibble): 003f
247.162: AgesaHwWlPhase1: training nibble 1
247.162: DIMM 1 RttNom: 5
247.162: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.162: DIMM 1 RttWr: 2
247.162: DIMM 1 RttWr: 2
247.163: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.163: DIMM 1 RttWr: 2
247.163: DIMM 1 RttNom: 5
247.163: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.163: DIMM 1 RttNom: 5
247.163: DIMM 1 RttWr: 2
247.163: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.163: DIMM 1 RttWr: 2
247.163: DIMM 0 RttNom: 5
247.163: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.163: DIMM 1 RttNom: 5
247.163: DIMM 0 RttWr: 2
247.163: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.163: DIMM 1 RttWr: 2
247.163: DIMM 0 RttNom: 5
247.163: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.163: DIMM 1 RttNom: 5
247.163: DIMM 0 RttWr: 2
247.163: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.163: DIMM 1 RttWr: 2
247.163: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.163: <09>Lane 00 new seed: 005d
247.163: <09>Lane 01 new seed: 0057
247.163: <09>Lane 02 new seed: 0057
247.163: <09>Lane 03 new seed: 0053
247.163: <09>Lane 04 new seed: 0045
247.163: <09>Lane 05 new seed: 0049
247.163: <09>Lane 06 new seed: 004d
247.163: <09>Lane 07 new seed: 0050
247.163: <09>Lane 08 new seed: 0048
247.163: <09>Lane 00 nibble 1 raw readback: 005f
247.163: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005f
247.163: <09>Lane 00 nibble 1 adjusted value (post nibble): 005e
247.163: <09>Lane 01 nibble 1 raw readback: 0056
247.163: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0056
247.163: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
247.163: <09>Lane 02 nibble 1 raw readback: 0055
247.163: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0055
247.163: <09>Lane 02 nibble 1 adjusted value (post nibble): 0056
247.163: <09>Lane 03 nibble 1 raw readback: 004f
247.163: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004f
247.163: <09>Lane 03 nibble 1 adjusted value (post nibble): 0051
247.163: <09>Lane 04 nibble 1 raw readback: 003d
247.163: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003d
247.163: <09>Lane 04 nibble 1 adjusted value (post nibble): 0041
247.163: <09>Lane 05 nibble 1 raw readback: 0044
247.163: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0044
247.163: <09>Lane 05 nibble 1 adjusted value (post nibble): 0046
247.163: <09>Lane 06 nibble 1 raw readback: 0049
247.163: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0049
247.163: <09>Lane 06 nibble 1 adjusted value (post nibble): 004b
247.163: <09>Lane 07 nibble 1 raw readback: 004e
247.163: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004e
247.163: <09>Lane 07 nibble 1 adjusted value (post nibble): 004f
247.163: <09>Lane 08 nibble 1 raw readback: 003f
247.163: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003f
247.163: <09>Lane 08 nibble 1 adjusted value (post nibble): 0043
247.163: <09>original critical gross delay: 0
247.163: <09>new critical gross delay: 0
247.163: DIMM 1 RttNom: 5
247.163: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.163: DIMM 1 RttNom: 5
247.163: DIMM 1 RttWr: 2
247.163: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.163: DIMM 1 RttWr: 2
247.163: DIMM 1 RttNom: 5
247.164: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.164: DIMM 1 RttNom: 5
247.164: DIMM 1 RttWr: 2
247.164: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.164: DIMM 1 RttWr: 2
247.164: DIMM 0 RttNom: 5
247.164: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.164: DIMM 1 RttNom: 5
247.164: DIMM 0 RttWr: 2
247.164: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.164: DIMM 1 RttWr: 2
247.164: DIMM 0 RttNom: 5
247.164: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.164: DIMM 1 RttNom: 5
247.164: DIMM 0 RttWr: 2
247.164: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.164: DIMM 1 RttWr: 2
247.164: SPD2ndTiming: Start
247.164: SPD2ndTiming: Done
247.164: mct_BeforeDramInit_Prod_D: Start
247.164: mct_ProgramODT_D: Start
247.164: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
247.164: mct_ProgramODT_D: Done
247.164: mct_BeforeDramInit_Prod_D: Done
247.164: mct_DramInit_Sw_D: Start
247.164: DIMM 0 RttWr: 2
247.164: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.164: mct_SendMrsCmd: Start
247.164: mct_SendMrsCmd: Done
247.164: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
247.164: mct_SendMrsCmd: Start
247.164: mct_SendMrsCmd: Done
247.165: DIMM 0 RttNom: 5
247.165: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.164: mct_SendMrsCmd: Start
247.165: mct_SendMrsCmd: Done
247.165: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001b78
247.165: mct_SendMrsCmd: Start
247.165: mct_SendMrsCmd: Done
247.165: DIMM 0 RttWr: 2
247.165: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.165: mct_SendMrsCmd: Start
247.165: mct_SendMrsCmd: Done
247.165: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
247.165: mct_SendMrsCmd: Start
247.165: mct_SendMrsCmd: Done
247.165: DIMM 0 RttNom: 5
247.165: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.165: mct_SendMrsCmd: Start
247.165: mct_SendMrsCmd: Done
247.165: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201b78
247.165: mct_SendMrsCmd: Start
247.165: mct_SendMrsCmd: Done
247.165: DIMM 1 RttWr: 2
247.165: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.165: mct_SendMrsCmd: Start
247.165: mct_SendMrsCmd: Done
247.165: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
247.165: mct_SendMrsCmd: Start
247.165: mct_SendMrsCmd: Done
247.165: DIMM 1 RttNom: 5
247.165: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.165: mct_SendMrsCmd: Start
247.165: mct_SendMrsCmd: Done
247.165: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401b78
247.165: mct_SendMrsCmd: Start
247.165: mct_SendMrsCmd: Done
247.165: DIMM 1 RttWr: 2
247.165: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.165: mct_SendMrsCmd: Start
247.165: mct_SendMrsCmd: Done
247.165: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
247.165: mct_SendMrsCmd: Start
247.165: mct_SendMrsCmd: Done
247.165: DIMM 1 RttNom: 5
247.165: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.165: mct_SendMrsCmd: Start
247.165: mct_SendMrsCmd: Done
247.165: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601b78
247.165: mct_SendMrsCmd: Start
247.165: mct_SendMrsCmd: Done
247.165: mct_DramInit_Sw_D: Done
247.165: AgesaHwWlPhase1: training nibble 0
247.165: DIMM 0 RttNom: 5
247.165: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.165: DIMM 0 RttWr: 2
247.165: DIMM 0 RttWr: 2
247.165: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.165: DIMM 0 RttWr: 2
247.165: DIMM 0 RttNom: 5
247.165: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.165: DIMM 0 RttNom: 5
247.165: DIMM 0 RttWr: 2
247.165: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.165: DIMM 0 RttWr: 2
247.165: DIMM 1 RttNom: 5
247.165: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.165: DIMM 0 RttNom: 5
247.165: DIMM 1 RttWr: 2
247.165: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.165: DIMM 0 RttWr: 2
247.165: DIMM 1 RttNom: 5
247.166: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.166: DIMM 0 RttNom: 5
247.166: DIMM 1 RttWr: 2
247.166: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.166: DIMM 0 RttWr: 2
247.166: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.166: <09>Lane 00 scaled delay: 0068
247.166: <09>Lane 00 new seed: 0068
247.166: <09>Lane 01 scaled delay: 0063
247.166: <09>Lane 01 new seed: 0063
247.166: <09>Lane 02 scaled delay: 005f
247.166: <09>Lane 02 new seed: 005f
247.166: <09>Lane 03 scaled delay: 005d
247.166: <09>Lane 03 new seed: 005d
247.166: <09>Lane 04 scaled delay: 004e
247.166: <09>Lane 04 new seed: 004e
247.166: <09>Lane 05 scaled delay: 0054
247.166: <09>Lane 05 new seed: 0054
247.166: <09>Lane 06 scaled delay: 0057
247.166: <09>Lane 06 new seed: 0057
247.166: <09>Lane 07 scaled delay: 0059
247.166: <09>Lane 07 new seed: 0059
247.166: <09>Lane 08 scaled delay: 0052
247.166: <09>Lane 08 new seed: 0052
247.166: <09>Lane 00 nibble 0 raw readback: 002c
247.166: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006c
247.166: <09>Lane 00 nibble 0 adjusted value (post nibble): 006c
247.166: <09>Lane 01 nibble 0 raw readback: 0027
247.166: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0067
247.166: <09>Lane 01 nibble 0 adjusted value (post nibble): 0067
247.166: <09>Lane 02 nibble 0 raw readback: 0060
247.166: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0060
247.166: <09>Lane 02 nibble 0 adjusted value (post nibble): 0060
247.166: <09>Lane 03 nibble 0 raw readback: 005c
247.166: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005c
247.166: <09>Lane 03 nibble 0 adjusted value (post nibble): 005c
247.166: <09>Lane 04 nibble 0 raw readback: 0049
247.166: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0049
247.166: <09>Lane 04 nibble 0 adjusted value (post nibble): 0049
247.166: <09>Lane 05 nibble 0 raw readback: 0051
247.166: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0051
247.166: <09>Lane 05 nibble 0 adjusted value (post nibble): 0051
247.166: <09>Lane 06 nibble 0 raw readback: 0057
247.166: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0057
247.166: <09>Lane 06 nibble 0 adjusted value (post nibble): 0057
247.166: <09>Lane 07 nibble 0 raw readback: 005b
247.166: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005b
247.166: <09>Lane 07 nibble 0 adjusted value (post nibble): 005b
247.166: <09>Lane 08 nibble 0 raw readback: 004d
247.166: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004d
247.166: <09>Lane 08 nibble 0 adjusted value (post nibble): 004d
247.166: AgesaHwWlPhase1: training nibble 1
247.166: DIMM 0 RttNom: 5
247.166: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.166: DIMM 0 RttWr: 2
247.166: DIMM 0 RttWr: 2
247.166: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.166: DIMM 0 RttWr: 2
247.166: DIMM 0 RttNom: 5
247.167: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.167: DIMM 0 RttNom: 5
247.167: DIMM 0 RttWr: 2
247.167: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.167: DIMM 0 RttWr: 2
247.167: DIMM 1 RttNom: 5
247.167: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.167: DIMM 0 RttNom: 5
247.167: DIMM 1 RttWr: 2
247.167: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.167: DIMM 0 RttWr: 2
247.167: DIMM 1 RttNom: 5
247.167: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.167: DIMM 0 RttNom: 5
247.167: DIMM 1 RttWr: 2
247.167: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.167: DIMM 0 RttWr: 2
247.167: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.167: <09>Lane 00 new seed: 0068
247.167: <09>Lane 01 new seed: 0063
247.167: <09>Lane 02 new seed: 005f
247.167: <09>Lane 03 new seed: 005d
247.167: <09>Lane 04 new seed: 004e
247.167: <09>Lane 05 new seed: 0054
247.167: <09>Lane 06 new seed: 0057
247.167: <09>Lane 07 new seed: 0059
247.167: <09>Lane 08 new seed: 0052
247.167: <09>Lane 00 nibble 1 raw readback: 002d
247.167: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006d
247.167: <09>Lane 00 nibble 1 adjusted value (post nibble): 006a
247.167: <09>Lane 01 nibble 1 raw readback: 0027
247.167: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0067
247.167: <09>Lane 01 nibble 1 adjusted value (post nibble): 0065
247.167: <09>Lane 02 nibble 1 raw readback: 0062
247.167: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0062
247.167: <09>Lane 02 nibble 1 adjusted value (post nibble): 0060
247.167: <09>Lane 03 nibble 1 raw readback: 005d
247.167: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005d
247.167: <09>Lane 03 nibble 1 adjusted value (post nibble): 005d
247.167: <09>Lane 04 nibble 1 raw readback: 004a
247.167: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004a
247.167: <09>Lane 04 nibble 1 adjusted value (post nibble): 004c
247.167: <09>Lane 05 nibble 1 raw readback: 0052
247.167: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0052
247.167: <09>Lane 05 nibble 1 adjusted value (post nibble): 0053
247.167: <09>Lane 06 nibble 1 raw readback: 0057
247.167: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0057
247.167: <09>Lane 06 nibble 1 adjusted value (post nibble): 0057
247.167: <09>Lane 07 nibble 1 raw readback: 005b
247.167: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005b
247.167: <09>Lane 07 nibble 1 adjusted value (post nibble): 005a
247.167: <09>Lane 08 nibble 1 raw readback: 004e
247.167: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004e
247.167: <09>Lane 08 nibble 1 adjusted value (post nibble): 0050
247.167: <09>original critical gross delay: 0
247.167: <09>new critical gross delay: 0
247.167: DIMM 0 RttNom: 5
247.167: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.167: DIMM 0 RttNom: 5
247.167: DIMM 0 RttWr: 2
247.168: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.168: DIMM 0 RttWr: 2
247.168: DIMM 0 RttNom: 5
247.168: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.168: DIMM 0 RttNom: 5
247.168: DIMM 0 RttWr: 2
247.168: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.168: DIMM 0 RttWr: 2
247.168: DIMM 1 RttNom: 5
247.168: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.168: DIMM 0 RttNom: 5
247.168: DIMM 1 RttWr: 2
247.168: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.168: DIMM 0 RttWr: 2
247.168: DIMM 1 RttNom: 5
247.168: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.168: DIMM 0 RttNom: 5
247.168: DIMM 1 RttWr: 2
247.168: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.168: DIMM 0 RttWr: 2
247.168: AgesaHwWlPhase1: training nibble 0
247.168: DIMM 1 RttNom: 5
247.168: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.168: DIMM 1 RttWr: 2
247.168: DIMM 1 RttWr: 2
247.168: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.168: DIMM 1 RttWr: 2
247.168: DIMM 1 RttNom: 5
247.168: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.168: DIMM 1 RttNom: 5
247.168: DIMM 1 RttWr: 2
247.168: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.168: DIMM 1 RttWr: 2
247.168: DIMM 0 RttNom: 5
247.168: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.168: DIMM 1 RttNom: 5
247.168: DIMM 0 RttWr: 2
247.168: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.168: DIMM 1 RttWr: 2
247.168: DIMM 0 RttNom: 5
247.168: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.168: DIMM 1 RttNom: 5
247.168: DIMM 0 RttWr: 2
247.168: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.168: DIMM 1 RttWr: 2
247.168: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.168: <09>Lane 00 scaled delay: 005c
247.168: <09>Lane 00 new seed: 005c
247.168: <09>Lane 01 scaled delay: 0057
247.168: <09>Lane 01 new seed: 0057
247.168: <09>Lane 02 scaled delay: 0054
247.168: <09>Lane 02 new seed: 0054
247.168: <09>Lane 03 scaled delay: 0052
247.168: <09>Lane 03 new seed: 0052
247.168: <09>Lane 04 scaled delay: 0043
247.168: <09>Lane 04 new seed: 0043
247.168: <09>Lane 05 scaled delay: 0048
247.168: <09>Lane 05 new seed: 0048
247.168: <09>Lane 06 scaled delay: 004a
247.168: <09>Lane 06 new seed: 004a
247.168: <09>Lane 07 scaled delay: 004f
247.168: <09>Lane 07 new seed: 004f
247.168: <09>Lane 08 scaled delay: 0046
247.168: <09>Lane 08 new seed: 0046
247.169: <09>Lane 00 nibble 0 raw readback: 005c
247.169: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005c
247.169: <09>Lane 00 nibble 0 adjusted value (post nibble): 005c
247.169: <09>Lane 01 nibble 0 raw readback: 0056
247.169: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0056
247.169: <09>Lane 01 nibble 0 adjusted value (post nibble): 0056
247.169: <09>Lane 02 nibble 0 raw readback: 0050
247.169: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0050
247.169: <09>Lane 02 nibble 0 adjusted value (post nibble): 0050
247.169: <09>Lane 03 nibble 0 raw readback: 004b
247.169: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004b
247.169: <09>Lane 03 nibble 0 adjusted value (post nibble): 004b
247.169: <09>Lane 04 nibble 0 raw readback: 003a
247.169: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
247.169: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
247.169: <09>Lane 05 nibble 0 raw readback: 0042
247.169: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0042
247.169: <09>Lane 05 nibble 0 adjusted value (post nibble): 0042
247.169: <09>Lane 06 nibble 0 raw readback: 0045
247.169: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0045
247.169: <09>Lane 06 nibble 0 adjusted value (post nibble): 0045
247.169: <09>Lane 07 nibble 0 raw readback: 004b
247.169: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004b
247.169: <09>Lane 07 nibble 0 adjusted value (post nibble): 004b
247.169: <09>Lane 08 nibble 0 raw readback: 003f
247.169: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003f
247.169: <09>Lane 08 nibble 0 adjusted value (post nibble): 003f
247.169: AgesaHwWlPhase1: training nibble 1
247.169: DIMM 1 RttNom: 5
247.169: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.169: DIMM 1 RttWr: 2
247.169: DIMM 1 RttWr: 2
247.169: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.169: DIMM 1 RttWr: 2
247.169: DIMM 1 RttNom: 5
247.169: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.169: DIMM 1 RttNom: 5
247.169: DIMM 1 RttWr: 2
247.169: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.169: DIMM 1 RttWr: 2
247.169: DIMM 0 RttNom: 5
247.169: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.169: DIMM 1 RttNom: 5
247.169: DIMM 0 RttWr: 2
247.169: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.169: DIMM 1 RttWr: 2
247.169: DIMM 0 RttNom: 5
247.169: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.169: DIMM 1 RttNom: 5
247.169: DIMM 0 RttWr: 2
247.169: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.169: DIMM 1 RttWr: 2
247.169: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.169: <09>Lane 00 new seed: 005c
247.169: <09>Lane 01 new seed: 0057
247.169: <09>Lane 02 new seed: 0054
247.169: <09>Lane 03 new seed: 0052
247.169: <09>Lane 04 new seed: 0043
247.169: <09>Lane 05 new seed: 0048
247.169: <09>Lane 06 new seed: 004a
247.169: <09>Lane 07 new seed: 004f
247.169: <09>Lane 08 new seed: 0046
247.169: <09>Lane 00 nibble 1 raw readback: 005b
247.169: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005b
247.169: <09>Lane 00 nibble 1 adjusted value (post nibble): 005b
247.169: <09>Lane 01 nibble 1 raw readback: 0055
247.169: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0055
247.169: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
247.169: <09>Lane 02 nibble 1 raw readback: 0051
247.169: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0051
247.169: <09>Lane 02 nibble 1 adjusted value (post nibble): 0052
247.169: <09>Lane 03 nibble 1 raw readback: 004d
247.169: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004d
247.169: <09>Lane 03 nibble 1 adjusted value (post nibble): 004f
247.169: <09>Lane 04 nibble 1 raw readback: 003b
247.169: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003b
247.170: <09>Lane 04 nibble 1 adjusted value (post nibble): 003f
247.170: <09>Lane 05 nibble 1 raw readback: 0042
247.170: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0042
247.170: <09>Lane 05 nibble 1 adjusted value (post nibble): 0045
247.170: <09>Lane 06 nibble 1 raw readback: 0046
247.170: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0046
247.170: <09>Lane 06 nibble 1 adjusted value (post nibble): 0048
247.170: <09>Lane 07 nibble 1 raw readback: 004b
247.170: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004b
247.170: <09>Lane 07 nibble 1 adjusted value (post nibble): 004d
247.170: <09>Lane 08 nibble 1 raw readback: 0040
247.170: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0040
247.170: <09>Lane 08 nibble 1 adjusted value (post nibble): 0043
247.170: <09>original critical gross delay: 0
247.170: <09>new critical gross delay: 0
247.170: DIMM 1 RttNom: 5
247.170: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.170: DIMM 1 RttNom: 5
247.170: DIMM 1 RttWr: 2
247.170: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.170: DIMM 1 RttWr: 2
247.170: DIMM 1 RttNom: 5
247.170: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.170: DIMM 1 RttNom: 5
247.170: DIMM 1 RttWr: 2
247.170: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.170: DIMM 1 RttWr: 2
247.170: DIMM 0 RttNom: 5
247.170: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.170: DIMM 1 RttNom: 5
247.170: DIMM 0 RttWr: 2
247.170: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.170: DIMM 1 RttWr: 2
247.170: DIMM 0 RttNom: 5
247.170: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.170: DIMM 1 RttNom: 5
247.170: DIMM 0 RttWr: 2
247.170: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.170: DIMM 1 RttWr: 2
247.170: SetTargetFreq: Start
247.170: SetTargetFreq: Node 2: New frequency code: 0012
247.170: ChangeMemClk: Start
247.170: set_2t_configuration: Start
247.170: set_2t_configuration: Done
247.171: mct_BeforePlatformSpec: Start
247.171: mct_BeforePlatformSpec: Done
247.171: mct_PlatformSpec: Start
247.171: Programmed DCT 0 timing/termination pattern 00353935 30222222
247.171: mct_PlatformSpec: Done
247.171: set_2t_configuration: Start
247.171: set_2t_configuration: Done
247.171: mct_BeforePlatformSpec: Start
247.171: mct_BeforePlatformSpec: Done
247.171: mct_PlatformSpec: Start
247.171: Programmed DCT 1 timing/termination pattern 00353935 30222222
247.171: mct_PlatformSpec: Done
247.171: ChangeMemClk: Done
247.171: phyAssistedMemFnceTraining: Start
247.171: phyAssistedMemFnceTraining: training node 2 DCT 0
247.171: phyAssistedMemFnceTraining: done training node 2 DCT 0
247.171: phyAssistedMemFnceTraining: training node 2 DCT 1
247.171: phyAssistedMemFnceTraining: done training node 2 DCT 1
247.171: phyAssistedMemFnceTraining: Done
247.171: InitPhyCompensation: DCT 0: Start
247.171: Waiting for predriver calibration to be applied...done!
247.171: InitPhyCompensation: DCT 0: Done
247.171: phyAssistedMemFnceTraining: Start
247.171: phyAssistedMemFnceTraining: training node 2 DCT 0
247.171: phyAssistedMemFnceTraining: done training node 2 DCT 0
247.171: phyAssistedMemFnceTraining: training node 2 DCT 1
247.171: phyAssistedMemFnceTraining: done training node 2 DCT 1
247.172: phyAssistedMemFnceTraining: Done
247.172: InitPhyCompensation: DCT 1: Start
247.172: Waiting for predriver calibration to be applied...done!
247.172: InitPhyCompensation: DCT 1: Done
247.172: Preparing to send DCT 0 DIMM 0 RC10: 03 (F2xA8: 02000300)
247.172: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.172: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
247.172: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.172: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
247.172: Preparing to send DCT 0 DIMM 1 RC10: 03 (F2xA8: 02000c00)
247.172: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.172: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
247.172: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.172: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
247.172: Preparing to send DCT 1 DIMM 0 RC10: 03 (F2xA8: 02000300)
247.172: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.172: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
247.172: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.172: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
247.172: Preparing to send DCT 1 DIMM 1 RC10: 03 (F2xA8: 02000c00)
247.172: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.172: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
247.172: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.172: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
247.172: SetTargetFreq: Done
247.172: SPD2ndTiming: Start
247.173: SPD2ndTiming: Done
247.173: mct_BeforeDramInit_Prod_D: Start
247.173: mct_ProgramODT_D: Start
247.173: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
247.173: mct_ProgramODT_D: Done
247.173: mct_BeforeDramInit_Prod_D: Done
247.173: mct_DramInit_Sw_D: Start
247.173: DIMM 0 RttWr: 1
247.173: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.173: mct_SendMrsCmd: Start
247.173: mct_SendMrsCmd: Done
247.173: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
247.173: mct_SendMrsCmd: Start
247.173: mct_SendMrsCmd: Done
247.173: DIMM 0 RttNom: 4
247.173: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.173: mct_SendMrsCmd: Start
247.173: mct_SendMrsCmd: Done
247.173: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001d78
247.173: mct_SendMrsCmd: Start
247.173: mct_SendMrsCmd: Done
247.173: DIMM 0 RttWr: 1
247.173: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.173: mct_SendMrsCmd: Start
247.173: mct_SendMrsCmd: Done
247.173: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
247.173: mct_SendMrsCmd: Start
247.173: mct_SendMrsCmd: Done
247.173: DIMM 0 RttNom: 4
247.173: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.173: mct_SendMrsCmd: Start
247.173: mct_SendMrsCmd: Done
247.173: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201d78
247.173: mct_SendMrsCmd: Start
247.173: mct_SendMrsCmd: Done
247.173: DIMM 1 RttWr: 1
247.173: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.173: mct_SendMrsCmd: Start
247.173: mct_SendMrsCmd: Done
247.173: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
247.173: mct_SendMrsCmd: Start
247.173: mct_SendMrsCmd: Done
247.173: DIMM 1 RttNom: 4
247.173: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.173: mct_SendMrsCmd: Start
247.173: mct_SendMrsCmd: Done
247.173: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401d78
247.173: mct_SendMrsCmd: Start
247.173: mct_SendMrsCmd: Done
247.173: DIMM 1 RttWr: 1
247.173: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.173: mct_SendMrsCmd: Start
247.173: mct_SendMrsCmd: Done
247.173: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
247.173: mct_SendMrsCmd: Start
247.173: mct_SendMrsCmd: Done
247.173: DIMM 1 RttNom: 4
247.173: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.173: mct_SendMrsCmd: Start
247.173: mct_SendMrsCmd: Done
247.173: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601d78
247.173: mct_SendMrsCmd: Start
247.174: mct_SendMrsCmd: Done
247.174: mct_DramInit_Sw_D: Done
247.174: AgesaHwWlPhase1: training nibble 0
247.174: DIMM 0 RttNom: 4
247.174: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.174: DIMM 0 RttWr: 1
247.174: DIMM 0 RttWr: 1
247.174: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.174: DIMM 0 RttWr: 1
247.174: DIMM 0 RttNom: 4
247.174: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.174: DIMM 0 RttNom: 4
247.174: DIMM 0 RttWr: 1
247.174: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.174: DIMM 0 RttWr: 1
247.174: DIMM 1 RttNom: 4
247.174: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.174: DIMM 0 RttNom: 4
247.174: DIMM 1 RttWr: 1
247.174: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.174: DIMM 0 RttWr: 1
247.174: DIMM 1 RttNom: 4
247.174: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.174: DIMM 0 RttNom: 4
247.174: DIMM 1 RttWr: 1
247.174: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.174: DIMM 0 RttWr: 1
247.174: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.174: <09>Lane 00 scaled delay: 007b
247.174: <09>Lane 00 new seed: 007b
247.174: <09>Lane 01 scaled delay: 0072
247.174: <09>Lane 01 new seed: 0072
247.174: <09>Lane 02 scaled delay: 006d
247.174: <09>Lane 02 new seed: 006d
247.174: <09>Lane 03 scaled delay: 0069
247.174: <09>Lane 03 new seed: 0069
247.174: <09>Lane 04 scaled delay: 0055
247.174: <09>Lane 04 new seed: 0055
247.174: <09>Lane 05 scaled delay: 005d
247.174: <09>Lane 05 new seed: 005d
247.174: <09>Lane 06 scaled delay: 0064
247.175: <09>Lane 06 new seed: 0064
247.175: <09>Lane 07 scaled delay: 0066
247.175: <09>Lane 07 new seed: 0066
247.175: <09>Lane 08 scaled delay: 0058
247.175: <09>Lane 08 new seed: 0058
247.175: <09>Lane 00 nibble 0 raw readback: 0041
247.175: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0081
247.175: <09>Lane 00 nibble 0 adjusted value (post nibble): 0081
247.175: <09>Lane 01 nibble 0 raw readback: 0034
247.175: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0074
247.175: <09>Lane 01 nibble 0 adjusted value (post nibble): 0074
247.175: <09>Lane 02 nibble 0 raw readback: 0032
247.175: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0072
247.175: <09>Lane 02 nibble 0 adjusted value (post nibble): 0072
247.175: <09>Lane 03 nibble 0 raw readback: 002c
247.175: <09>Lane 03 nibble 0 adjusted value (pre nibble): 006c
247.175: <09>Lane 03 nibble 0 adjusted value (post nibble): 006c
247.175: <09>Lane 04 nibble 0 raw readback: 0058
247.175: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0058
247.175: <09>Lane 04 nibble 0 adjusted value (post nibble): 0058
247.175: <09>Lane 05 nibble 0 raw readback: 0060
247.175: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0060
247.175: <09>Lane 05 nibble 0 adjusted value (post nibble): 0060
247.175: <09>Lane 06 nibble 0 raw readback: 0025
247.175: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0065
247.175: <09>Lane 06 nibble 0 adjusted value (post nibble): 0065
247.175: <09>Lane 07 nibble 0 raw readback: 002b
247.175: <09>Lane 07 nibble 0 adjusted value (pre nibble): 006b
247.175: <09>Lane 07 nibble 0 adjusted value (post nibble): 006b
247.175: <09>Lane 08 nibble 0 raw readback: 005c
247.175: <09>Lane 08 nibble 0 adjusted value (pre nibble): 005c
247.175: <09>Lane 08 nibble 0 adjusted value (post nibble): 005c
247.175: AgesaHwWlPhase1: training nibble 1
247.175: DIMM 0 RttNom: 4
247.175: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.175: DIMM 0 RttWr: 1
247.175: DIMM 0 RttWr: 1
247.175: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.175: DIMM 0 RttWr: 1
247.175: DIMM 0 RttNom: 4
247.175: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.175: DIMM 0 RttNom: 4
247.175: DIMM 0 RttWr: 1
247.175: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.175: DIMM 0 RttWr: 1
247.175: DIMM 1 RttNom: 4
247.175: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.175: DIMM 0 RttNom: 4
247.175: DIMM 1 RttWr: 1
247.175: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.175: DIMM 0 RttWr: 1
247.175: DIMM 1 RttNom: 4
247.175: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.175: DIMM 0 RttNom: 4
247.175: DIMM 1 RttWr: 1
247.175: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.175: DIMM 0 RttWr: 1
247.175: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.175: <09>Lane 00 new seed: 007b
247.175: <09>Lane 01 new seed: 0072
247.175: <09>Lane 02 new seed: 006d
247.175: <09>Lane 03 new seed: 0069
247.176: <09>Lane 04 new seed: 0055
247.176: <09>Lane 05 new seed: 005d
247.176: <09>Lane 06 new seed: 0064
247.176: <09>Lane 07 new seed: 0066
247.176: <09>Lane 08 new seed: 0058
247.176: <09>Lane 00 nibble 1 raw readback: 0040
247.176: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0080
247.176: <09>Lane 00 nibble 1 adjusted value (post nibble): 007d
247.176: <09>Lane 01 nibble 1 raw readback: 0037
247.176: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0077
247.176: <09>Lane 01 nibble 1 adjusted value (post nibble): 0074
247.176: <09>Lane 02 nibble 1 raw readback: 0032
247.176: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0072
247.176: <09>Lane 02 nibble 1 adjusted value (post nibble): 006f
247.176: <09>Lane 03 nibble 1 raw readback: 002c
247.176: <09>Lane 03 nibble 1 adjusted value (pre nibble): 006c
247.176: <09>Lane 03 nibble 1 adjusted value (post nibble): 006a
247.176: <09>Lane 04 nibble 1 raw readback: 0057
247.176: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0057
247.176: <09>Lane 04 nibble 1 adjusted value (post nibble): 0056
247.176: <09>Lane 05 nibble 1 raw readback: 0060
247.176: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0060
247.176: <09>Lane 05 nibble 1 adjusted value (post nibble): 005e
247.176: <09>Lane 06 nibble 1 raw readback: 0026
247.176: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0066
247.176: <09>Lane 06 nibble 1 adjusted value (post nibble): 0065
247.176: <09>Lane 07 nibble 1 raw readback: 002a
247.176: <09>Lane 07 nibble 1 adjusted value (pre nibble): 006a
247.176: <09>Lane 07 nibble 1 adjusted value (post nibble): 0068
247.176: <09>Lane 08 nibble 1 raw readback: 005a
247.176: <09>Lane 08 nibble 1 adjusted value (pre nibble): 005a
247.176: <09>Lane 08 nibble 1 adjusted value (post nibble): 0059
247.176: <09>original critical gross delay: 0
247.176: <09>new critical gross delay: 0
247.176: DIMM 0 RttNom: 4
247.176: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.176: DIMM 0 RttNom: 4
247.176: DIMM 0 RttWr: 1
247.176: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.176: DIMM 0 RttWr: 1
247.176: DIMM 0 RttNom: 4
247.176: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.176: DIMM 0 RttNom: 4
247.176: DIMM 0 RttWr: 1
247.176: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.176: DIMM 0 RttWr: 1
247.176: DIMM 1 RttNom: 4
247.176: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.176: DIMM 0 RttNom: 4
247.176: DIMM 1 RttWr: 1
247.176: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.176: DIMM 0 RttWr: 1
247.176: DIMM 1 RttNom: 4
247.176: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.176: DIMM 0 RttNom: 4
247.176: DIMM 1 RttWr: 1
247.176: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.176: DIMM 0 RttWr: 1
247.176: AgesaHwWlPhase1: training nibble 0
247.176: DIMM 1 RttNom: 4
247.177: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.176: DIMM 1 RttWr: 1
247.177: DIMM 1 RttWr: 1
247.177: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.177: DIMM 1 RttWr: 1
247.177: DIMM 1 RttNom: 4
247.177: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.177: DIMM 1 RttNom: 4
247.177: DIMM 1 RttWr: 1
247.177: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.177: DIMM 1 RttWr: 1
247.177: DIMM 0 RttNom: 4
247.177: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.177: DIMM 1 RttNom: 4
247.177: DIMM 0 RttWr: 1
247.177: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.177: DIMM 1 RttWr: 1
247.177: DIMM 0 RttNom: 4
247.177: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.177: DIMM 1 RttNom: 4
247.177: DIMM 0 RttWr: 1
247.177: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.177: DIMM 1 RttWr: 1
247.177: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.177: <09>Lane 00 scaled delay: 006a
247.177: <09>Lane 00 new seed: 006a
247.177: <09>Lane 01 scaled delay: 0060
247.177: <09>Lane 01 new seed: 0060
247.177: <09>Lane 02 scaled delay: 0060
247.177: <09>Lane 02 new seed: 0060
247.177: <09>Lane 03 scaled delay: 005a
247.177: <09>Lane 03 new seed: 005a
247.177: <09>Lane 04 scaled delay: 0047
247.177: <09>Lane 04 new seed: 0047
247.177: <09>Lane 05 scaled delay: 004d
247.177: <09>Lane 05 new seed: 004d
247.177: <09>Lane 06 scaled delay: 0053
247.177: <09>Lane 06 new seed: 0053
247.177: <09>Lane 07 scaled delay: 0058
247.177: <09>Lane 07 new seed: 0058
247.177: <09>Lane 08 scaled delay: 0049
247.177: <09>Lane 08 new seed: 0049
247.177: <09>Lane 00 nibble 0 raw readback: 0031
247.177: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0071
247.177: <09>Lane 00 nibble 0 adjusted value (post nibble): 0071
247.177: <09>Lane 01 nibble 0 raw readback: 0024
247.177: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0064
247.177: <09>Lane 01 nibble 0 adjusted value (post nibble): 0064
247.177: <09>Lane 02 nibble 0 raw readback: 0022
247.177: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0062
247.177: <09>Lane 02 nibble 0 adjusted value (post nibble): 0062
247.177: <09>Lane 03 nibble 0 raw readback: 0059
247.177: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0059
247.177: <09>Lane 03 nibble 0 adjusted value (post nibble): 0059
247.177: <09>Lane 04 nibble 0 raw readback: 0045
247.177: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0045
247.177: <09>Lane 04 nibble 0 adjusted value (post nibble): 0045
247.177: <09>Lane 05 nibble 0 raw readback: 004f
247.177: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004f
247.177: <09>Lane 05 nibble 0 adjusted value (post nibble): 004f
247.177: <09>Lane 06 nibble 0 raw readback: 0055
247.177: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0055
247.177: <09>Lane 06 nibble 0 adjusted value (post nibble): 0055
247.177: <09>Lane 07 nibble 0 raw readback: 005a
247.177: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005a
247.177: <09>Lane 07 nibble 0 adjusted value (post nibble): 005a
247.177: <09>Lane 08 nibble 0 raw readback: 004b
247.177: <09>Lane 08 nibble 0 adjusted value (pre nibble): 004b
247.177: <09>Lane 08 nibble 0 adjusted value (post nibble): 004b
247.177: AgesaHwWlPhase1: training nibble 1
247.178: DIMM 1 RttNom: 4
247.177: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.177: DIMM 1 RttWr: 1
247.177: DIMM 1 RttWr: 1
247.178: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.178: DIMM 1 RttWr: 1
247.178: DIMM 1 RttNom: 4
247.178: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.178: DIMM 1 RttNom: 4
247.178: DIMM 1 RttWr: 1
247.178: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.178: DIMM 1 RttWr: 1
247.178: DIMM 0 RttNom: 4
247.178: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.178: DIMM 1 RttNom: 4
247.178: DIMM 0 RttWr: 1
247.178: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.178: DIMM 1 RttWr: 1
247.178: DIMM 0 RttNom: 4
247.178: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.178: DIMM 1 RttNom: 4
247.178: DIMM 0 RttWr: 1
247.178: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.178: DIMM 1 RttWr: 1
247.178: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.178: <09>Lane 00 new seed: 006a
247.178: <09>Lane 01 new seed: 0060
247.178: <09>Lane 02 new seed: 0060
247.178: <09>Lane 03 new seed: 005a
247.178: <09>Lane 04 new seed: 0047
247.178: <09>Lane 05 new seed: 004d
247.178: <09>Lane 06 new seed: 0053
247.178: <09>Lane 07 new seed: 0058
247.178: <09>Lane 08 new seed: 0049
247.178: <09>Lane 00 nibble 1 raw readback: 0030
247.178: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0070
247.178: <09>Lane 00 nibble 1 adjusted value (post nibble): 006d
247.178: <09>Lane 01 nibble 1 raw readback: 0025
247.178: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0065
247.178: <09>Lane 01 nibble 1 adjusted value (post nibble): 0062
247.178: <09>Lane 02 nibble 1 raw readback: 0025
247.178: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0065
247.178: <09>Lane 02 nibble 1 adjusted value (post nibble): 0062
247.178: <09>Lane 03 nibble 1 raw readback: 005d
247.178: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005d
247.178: <09>Lane 03 nibble 1 adjusted value (post nibble): 005b
247.178: <09>Lane 04 nibble 1 raw readback: 0048
247.178: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0048
247.178: <09>Lane 04 nibble 1 adjusted value (post nibble): 0047
247.178: <09>Lane 05 nibble 1 raw readback: 0050
247.178: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0050
247.178: <09>Lane 05 nibble 1 adjusted value (post nibble): 004e
247.178: <09>Lane 06 nibble 1 raw readback: 0056
247.178: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0056
247.178: <09>Lane 06 nibble 1 adjusted value (post nibble): 0054
247.178: <09>Lane 07 nibble 1 raw readback: 005b
247.178: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005b
247.178: <09>Lane 07 nibble 1 adjusted value (post nibble): 0059
247.178: <09>Lane 08 nibble 1 raw readback: 004c
247.178: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004c
247.178: <09>Lane 08 nibble 1 adjusted value (post nibble): 004a
247.178: <09>original critical gross delay: 0
247.178: <09>new critical gross delay: 0
247.179: DIMM 1 RttNom: 4
247.179: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.178: DIMM 1 RttNom: 4
247.178: DIMM 1 RttWr: 1
247.178: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.178: DIMM 1 RttWr: 1
247.179: DIMM 1 RttNom: 4
247.179: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.179: DIMM 1 RttNom: 4
247.179: DIMM 1 RttWr: 1
247.179: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.179: DIMM 1 RttWr: 1
247.179: DIMM 0 RttNom: 4
247.179: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.179: DIMM 1 RttNom: 4
247.179: DIMM 0 RttWr: 1
247.179: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.179: DIMM 1 RttWr: 1
247.179: DIMM 0 RttNom: 4
247.179: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.179: DIMM 1 RttNom: 4
247.179: DIMM 0 RttWr: 1
247.179: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.179: DIMM 1 RttWr: 1
247.179: SPD2ndTiming: Start
247.179: SPD2ndTiming: Done
247.179: mct_BeforeDramInit_Prod_D: Start
247.179: mct_ProgramODT_D: Start
247.179: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
247.179: mct_ProgramODT_D: Done
247.179: mct_BeforeDramInit_Prod_D: Done
247.179: mct_DramInit_Sw_D: Start
247.179: DIMM 0 RttWr: 1
247.179: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.179: mct_SendMrsCmd: Start
247.179: mct_SendMrsCmd: Done
247.179: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
247.179: mct_SendMrsCmd: Start
247.179: mct_SendMrsCmd: Done
247.179: DIMM 0 RttNom: 4
247.179: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.180: mct_SendMrsCmd: Start
247.180: mct_SendMrsCmd: Done
247.180: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001d78
247.180: mct_SendMrsCmd: Start
247.180: mct_SendMrsCmd: Done
247.180: DIMM 0 RttWr: 1
247.180: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.180: mct_SendMrsCmd: Start
247.180: mct_SendMrsCmd: Done
247.180: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
247.180: mct_SendMrsCmd: Start
247.180: mct_SendMrsCmd: Done
247.180: DIMM 0 RttNom: 4
247.180: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.180: mct_SendMrsCmd: Start
247.180: mct_SendMrsCmd: Done
247.180: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201d78
247.180: mct_SendMrsCmd: Start
247.180: mct_SendMrsCmd: Done
247.180: DIMM 1 RttWr: 1
247.180: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.180: mct_SendMrsCmd: Start
247.180: mct_SendMrsCmd: Done
247.180: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
247.180: mct_SendMrsCmd: Start
247.180: mct_SendMrsCmd: Done
247.180: DIMM 1 RttNom: 4
247.180: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.180: mct_SendMrsCmd: Start
247.180: mct_SendMrsCmd: Done
247.180: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401d78
247.180: mct_SendMrsCmd: Start
247.180: mct_SendMrsCmd: Done
247.180: DIMM 1 RttWr: 1
247.180: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.180: mct_SendMrsCmd: Start
247.180: mct_SendMrsCmd: Done
247.180: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
247.180: mct_SendMrsCmd: Start
247.180: mct_SendMrsCmd: Done
247.180: DIMM 1 RttNom: 4
247.180: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.180: mct_SendMrsCmd: Start
247.180: mct_SendMrsCmd: Done
247.180: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601d78
247.180: mct_SendMrsCmd: Start
247.180: mct_SendMrsCmd: Done
247.180: mct_DramInit_Sw_D: Done
247.180: AgesaHwWlPhase1: training nibble 0
247.180: DIMM 0 RttNom: 4
247.180: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.180: DIMM 0 RttWr: 1
247.180: DIMM 0 RttWr: 1
247.180: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.180: DIMM 0 RttWr: 1
247.180: DIMM 0 RttNom: 4
247.180: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.180: DIMM 0 RttNom: 4
247.180: DIMM 0 RttWr: 1
247.180: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.180: DIMM 0 RttWr: 1
247.180: DIMM 1 RttNom: 4
247.180: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.180: DIMM 0 RttNom: 4
247.180: DIMM 1 RttWr: 1
247.181: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.180: DIMM 0 RttWr: 1
247.181: DIMM 1 RttNom: 4
247.181: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.180: DIMM 0 RttNom: 4
247.181: DIMM 1 RttWr: 1
247.181: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.181: DIMM 0 RttWr: 1
247.181: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.181: <09>Lane 00 scaled delay: 0078
247.181: <09>Lane 00 new seed: 0078
247.181: <09>Lane 01 scaled delay: 0072
247.181: <09>Lane 01 new seed: 0072
247.181: <09>Lane 02 scaled delay: 006c
247.181: <09>Lane 02 new seed: 006c
247.181: <09>Lane 03 scaled delay: 0069
247.181: <09>Lane 03 new seed: 0069
247.181: <09>Lane 04 scaled delay: 0054
247.181: <09>Lane 04 new seed: 0054
247.181: <09>Lane 05 scaled delay: 005d
247.181: <09>Lane 05 new seed: 005d
247.181: <09>Lane 06 scaled delay: 0061
247.181: <09>Lane 06 new seed: 0061
247.181: <09>Lane 07 scaled delay: 0065
247.181: <09>Lane 07 new seed: 0065
247.181: <09>Lane 08 scaled delay: 0059
247.181: <09>Lane 08 new seed: 0059
247.181: <09>Lane 00 nibble 0 raw readback: 003e
247.181: <09>Lane 00 nibble 0 adjusted value (pre nibble): 007e
247.181: <09>Lane 00 nibble 0 adjusted value (post nibble): 007e
247.181: <09>Lane 01 nibble 0 raw readback: 0038
247.181: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0078
247.181: <09>Lane 01 nibble 0 adjusted value (post nibble): 0078
247.181: <09>Lane 02 nibble 0 raw readback: 002f
247.181: <09>Lane 02 nibble 0 adjusted value (pre nibble): 006f
247.181: <09>Lane 02 nibble 0 adjusted value (post nibble): 006f
247.181: <09>Lane 03 nibble 0 raw readback: 002a
247.181: <09>Lane 03 nibble 0 adjusted value (pre nibble): 006a
247.181: <09>Lane 03 nibble 0 adjusted value (post nibble): 006a
247.181: <09>Lane 04 nibble 0 raw readback: 0056
247.181: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0056
247.181: <09>Lane 04 nibble 0 adjusted value (post nibble): 0056
247.181: <09>Lane 05 nibble 0 raw readback: 005e
247.181: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005e
247.181: <09>Lane 05 nibble 0 adjusted value (post nibble): 005e
247.181: <09>Lane 06 nibble 0 raw readback: 0024
247.181: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0064
247.181: <09>Lane 06 nibble 0 adjusted value (post nibble): 0064
247.181: <09>Lane 07 nibble 0 raw readback: 0027
247.181: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0067
247.181: <09>Lane 07 nibble 0 adjusted value (post nibble): 0067
247.181: <09>Lane 08 nibble 0 raw readback: 005a
247.181: <09>Lane 08 nibble 0 adjusted value (pre nibble): 005a
247.181: <09>Lane 08 nibble 0 adjusted value (post nibble): 005a
247.181: AgesaHwWlPhase1: training nibble 1
247.181: DIMM 0 RttNom: 4
247.181: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.181: DIMM 0 RttWr: 1
247.181: DIMM 0 RttWr: 1
247.181: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.181: DIMM 0 RttWr: 1
247.181: DIMM 0 RttNom: 4
247.182: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.181: DIMM 0 RttNom: 4
247.181: DIMM 0 RttWr: 1
247.181: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.182: DIMM 0 RttWr: 1
247.182: DIMM 1 RttNom: 4
247.182: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.182: DIMM 0 RttNom: 4
247.182: DIMM 1 RttWr: 1
247.182: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.182: DIMM 0 RttWr: 1
247.182: DIMM 1 RttNom: 4
247.182: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.182: DIMM 0 RttNom: 4
247.182: DIMM 1 RttWr: 1
247.182: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.182: DIMM 0 RttWr: 1
247.182: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.182: <09>Lane 00 new seed: 0078
247.182: <09>Lane 01 new seed: 0072
247.182: <09>Lane 02 new seed: 006c
247.182: <09>Lane 03 new seed: 0069
247.182: <09>Lane 04 new seed: 0054
247.182: <09>Lane 05 new seed: 005d
247.182: <09>Lane 06 new seed: 0061
247.182: <09>Lane 07 new seed: 0065
247.182: <09>Lane 08 new seed: 0059
247.182: <09>Lane 00 nibble 1 raw readback: 003e
247.182: <09>Lane 00 nibble 1 adjusted value (pre nibble): 007e
247.182: <09>Lane 00 nibble 1 adjusted value (post nibble): 007b
247.182: <09>Lane 01 nibble 1 raw readback: 0037
247.182: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0077
247.182: <09>Lane 01 nibble 1 adjusted value (post nibble): 0074
247.182: <09>Lane 02 nibble 1 raw readback: 0030
247.182: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0070
247.182: <09>Lane 02 nibble 1 adjusted value (post nibble): 006e
247.182: <09>Lane 03 nibble 1 raw readback: 002b
247.182: <09>Lane 03 nibble 1 adjusted value (pre nibble): 006b
247.182: <09>Lane 03 nibble 1 adjusted value (post nibble): 006a
247.182: <09>Lane 04 nibble 1 raw readback: 0055
247.182: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0055
247.182: <09>Lane 04 nibble 1 adjusted value (post nibble): 0054
247.182: <09>Lane 05 nibble 1 raw readback: 005e
247.182: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005e
247.182: <09>Lane 05 nibble 1 adjusted value (post nibble): 005d
247.182: <09>Lane 06 nibble 1 raw readback: 0024
247.182: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0064
247.182: <09>Lane 06 nibble 1 adjusted value (post nibble): 0062
247.182: <09>Lane 07 nibble 1 raw readback: 0026
247.182: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0066
247.182: <09>Lane 07 nibble 1 adjusted value (post nibble): 0065
247.182: <09>Lane 08 nibble 1 raw readback: 0059
247.182: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0059
247.182: <09>Lane 08 nibble 1 adjusted value (post nibble): 0059
247.182: <09>original critical gross delay: 0
247.182: <09>new critical gross delay: 0
247.182: DIMM 0 RttNom: 4
247.182: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.182: DIMM 0 RttNom: 4
247.182: DIMM 0 RttWr: 1
247.182: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.182: DIMM 0 RttWr: 1
247.182: DIMM 0 RttNom: 4
247.183: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.183: DIMM 0 RttNom: 4
247.183: DIMM 0 RttWr: 1
247.183: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.183: DIMM 0 RttWr: 1
247.183: DIMM 1 RttNom: 4
247.183: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.183: DIMM 0 RttNom: 4
247.183: DIMM 1 RttWr: 1
247.183: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.183: DIMM 0 RttWr: 1
247.183: DIMM 1 RttNom: 4
247.183: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.183: DIMM 0 RttNom: 4
247.183: DIMM 1 RttWr: 1
247.183: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.183: DIMM 0 RttWr: 1
247.183: AgesaHwWlPhase1: training nibble 0
247.183: DIMM 1 RttNom: 4
247.183: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.183: DIMM 1 RttWr: 1
247.183: DIMM 1 RttWr: 1
247.183: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.183: DIMM 1 RttWr: 1
247.183: DIMM 1 RttNom: 4
247.183: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.183: DIMM 1 RttNom: 4
247.183: DIMM 1 RttWr: 1
247.183: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.183: DIMM 1 RttWr: 1
247.183: DIMM 0 RttNom: 4
247.183: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.183: DIMM 1 RttNom: 4
247.183: DIMM 0 RttWr: 1
247.183: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.183: DIMM 1 RttWr: 1
247.183: DIMM 0 RttNom: 4
247.183: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.183: DIMM 1 RttNom: 4
247.183: DIMM 0 RttWr: 1
247.183: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.183: DIMM 1 RttWr: 1
247.183: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.183: <09>Lane 00 scaled delay: 0066
247.183: <09>Lane 00 new seed: 0066
247.183: <09>Lane 01 scaled delay: 0060
247.183: <09>Lane 01 new seed: 0060
247.183: <09>Lane 02 scaled delay: 005b
247.183: <09>Lane 02 new seed: 005b
247.183: <09>Lane 03 scaled delay: 0058
247.183: <09>Lane 03 new seed: 0058
247.183: <09>Lane 04 scaled delay: 0045
247.183: <09>Lane 04 new seed: 0045
247.183: <09>Lane 05 scaled delay: 004c
247.183: <09>Lane 05 new seed: 004c
247.183: <09>Lane 06 scaled delay: 004f
247.183: <09>Lane 06 new seed: 004f
247.183: <09>Lane 07 scaled delay: 0055
247.183: <09>Lane 07 new seed: 0055
247.183: <09>Lane 08 scaled delay: 0049
247.183: <09>Lane 08 new seed: 0049
247.183: <09>Lane 00 nibble 0 raw readback: 002d
247.183: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006d
247.184: <09>Lane 00 nibble 0 adjusted value (post nibble): 006d
247.183: <09>Lane 01 nibble 0 raw readback: 0025
247.183: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0065
247.183: <09>Lane 01 nibble 0 adjusted value (post nibble): 0065
247.184: <09>Lane 02 nibble 0 raw readback: 005e
247.184: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005e
247.184: <09>Lane 02 nibble 0 adjusted value (post nibble): 005e
247.184: <09>Lane 03 nibble 0 raw readback: 0058
247.184: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0058
247.184: <09>Lane 03 nibble 0 adjusted value (post nibble): 0058
247.184: <09>Lane 04 nibble 0 raw readback: 0043
247.184: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0043
247.184: <09>Lane 04 nibble 0 adjusted value (post nibble): 0043
247.184: <09>Lane 05 nibble 0 raw readback: 004d
247.184: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004d
247.184: <09>Lane 05 nibble 0 adjusted value (post nibble): 004d
247.184: <09>Lane 06 nibble 0 raw readback: 0051
247.184: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0051
247.184: <09>Lane 06 nibble 0 adjusted value (post nibble): 0051
247.184: <09>Lane 07 nibble 0 raw readback: 0057
247.184: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0057
247.184: <09>Lane 07 nibble 0 adjusted value (post nibble): 0057
247.184: <09>Lane 08 nibble 0 raw readback: 0049
247.184: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0049
247.184: <09>Lane 08 nibble 0 adjusted value (post nibble): 0049
247.184: AgesaHwWlPhase1: training nibble 1
247.184: DIMM 1 RttNom: 4
247.184: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.184: DIMM 1 RttWr: 1
247.184: DIMM 1 RttWr: 1
247.184: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.184: DIMM 1 RttWr: 1
247.184: DIMM 1 RttNom: 4
247.184: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.184: DIMM 1 RttNom: 4
247.184: DIMM 1 RttWr: 1
247.184: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.184: DIMM 1 RttWr: 1
247.184: DIMM 0 RttNom: 4
247.184: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.184: DIMM 1 RttNom: 4
247.184: DIMM 0 RttWr: 1
247.184: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.184: DIMM 1 RttWr: 1
247.184: DIMM 0 RttNom: 4
247.184: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.184: DIMM 1 RttNom: 4
247.184: DIMM 0 RttWr: 1
247.184: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.184: DIMM 1 RttWr: 1
247.184: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.184: <09>Lane 00 new seed: 0066
247.184: <09>Lane 01 new seed: 0060
247.184: <09>Lane 02 new seed: 005b
247.184: <09>Lane 03 new seed: 0058
247.184: <09>Lane 04 new seed: 0045
247.184: <09>Lane 05 new seed: 004c
247.184: <09>Lane 06 new seed: 004f
247.184: <09>Lane 07 new seed: 0055
247.184: <09>Lane 08 new seed: 0049
247.184: <09>Lane 00 nibble 1 raw readback: 002c
247.184: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006c
247.184: <09>Lane 00 nibble 1 adjusted value (post nibble): 0069
247.184: <09>Lane 01 nibble 1 raw readback: 0026
247.184: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0066
247.184: <09>Lane 01 nibble 1 adjusted value (post nibble): 0063
247.184: <09>Lane 02 nibble 1 raw readback: 005e
247.184: <09>Lane 02 nibble 1 adjusted value (pre nibble): 005e
247.184: <09>Lane 02 nibble 1 adjusted value (post nibble): 005c
247.184: <09>Lane 03 nibble 1 raw readback: 005a
247.184: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005a
247.184: <09>Lane 03 nibble 1 adjusted value (post nibble): 0059
247.184: <09>Lane 04 nibble 1 raw readback: 0046
247.184: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0046
247.184: <09>Lane 04 nibble 1 adjusted value (post nibble): 0045
247.184: <09>Lane 05 nibble 1 raw readback: 004d
247.184: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004d
247.184: <09>Lane 05 nibble 1 adjusted value (post nibble): 004c
247.185: <09>Lane 06 nibble 1 raw readback: 0053
247.185: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0053
247.185: <09>Lane 06 nibble 1 adjusted value (post nibble): 0051
247.185: <09>Lane 07 nibble 1 raw readback: 0058
247.185: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0058
247.185: <09>Lane 07 nibble 1 adjusted value (post nibble): 0056
247.185: <09>Lane 08 nibble 1 raw readback: 004a
247.185: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004a
247.185: <09>Lane 08 nibble 1 adjusted value (post nibble): 0049
247.185: <09>original critical gross delay: 0
247.185: <09>new critical gross delay: 0
247.185: DIMM 1 RttNom: 4
247.185: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.185: DIMM 1 RttNom: 4
247.185: DIMM 1 RttWr: 1
247.185: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.185: DIMM 1 RttWr: 1
247.185: DIMM 1 RttNom: 4
247.185: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.185: DIMM 1 RttNom: 4
247.185: DIMM 1 RttWr: 1
247.185: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.185: DIMM 1 RttWr: 1
247.185: DIMM 0 RttNom: 4
247.185: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.185: DIMM 1 RttNom: 4
247.185: DIMM 0 RttWr: 1
247.185: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.185: DIMM 1 RttWr: 1
247.185: DIMM 0 RttNom: 4
247.185: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.185: DIMM 1 RttNom: 4
247.185: DIMM 0 RttWr: 1
247.185: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.185: DIMM 1 RttWr: 1
247.186: activate_spd_rom() for node 03
247.186: enable_spd_node3()
247.186: SetTargetFreq: Start
247.186: SetTargetFreq: Node 3: New frequency code: 0006
247.186: ChangeMemClk: Start
247.186: set_2t_configuration: Start
247.186: set_2t_configuration: Done
247.186: mct_BeforePlatformSpec: Start
247.186: mct_BeforePlatformSpec: Done
247.186: mct_PlatformSpec: Start
247.186: Programmed DCT 0 timing/termination pattern 00000000 20222222
247.186: mct_PlatformSpec: Done
247.186: set_2t_configuration: Start
247.186: set_2t_configuration: Done
247.186: mct_BeforePlatformSpec: Start
247.186: mct_BeforePlatformSpec: Done
247.186: mct_PlatformSpec: Start
247.186: Programmed DCT 1 timing/termination pattern 00000000 20222222
247.186: mct_PlatformSpec: Done
247.186: ChangeMemClk: Done
247.186: phyAssistedMemFnceTraining: Start
247.186: phyAssistedMemFnceTraining: training node 3 DCT 0
247.186: phyAssistedMemFnceTraining: done training node 3 DCT 0
247.186: phyAssistedMemFnceTraining: training node 3 DCT 1
247.186: phyAssistedMemFnceTraining: done training node 3 DCT 1
247.186: phyAssistedMemFnceTraining: Done
247.186: InitPhyCompensation: DCT 0: Start
247.187: Waiting for predriver calibration to be applied...done!
247.187: InitPhyCompensation: DCT 0: Done
247.187: phyAssistedMemFnceTraining: Start
247.187: phyAssistedMemFnceTraining: training node 3 DCT 0
247.187: phyAssistedMemFnceTraining: done training node 3 DCT 0
247.187: phyAssistedMemFnceTraining: training node 3 DCT 1
247.187: phyAssistedMemFnceTraining: done training node 3 DCT 1
247.187: phyAssistedMemFnceTraining: Done
247.187: InitPhyCompensation: DCT 1: Start
247.187: Waiting for predriver calibration to be applied...done!
247.187: InitPhyCompensation: DCT 1: Done
247.187: Preparing to send DCT 0 DIMM 0 RC10: 00 (F2xA8: 02000300)
247.187: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.187: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
247.188: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.187: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
247.187: Preparing to send DCT 0 DIMM 1 RC10: 00 (F2xA8: 02000c00)
247.187: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.187: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
247.187: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.188: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
247.188: Preparing to send DCT 1 DIMM 0 RC10: 00 (F2xA8: 02000300)
247.188: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.188: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
247.188: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.188: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
247.188: Preparing to send DCT 1 DIMM 1 RC10: 00 (F2xA8: 02000c00)
247.188: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.188: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
247.188: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.188: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
247.188: SetTargetFreq: Done
247.188: SPD2ndTiming: Start
247.188: SPD2ndTiming: Done
247.188: mct_BeforeDramInit_Prod_D: Start
247.188: mct_ProgramODT_D: Start
247.188: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
247.188: mct_ProgramODT_D: Done
247.188: mct_BeforeDramInit_Prod_D: Done
247.188: mct_DramInit_Sw_D: Start
247.188: DIMM 0 RttWr: 2
247.188: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.188: mct_SendMrsCmd: Start
247.188: mct_SendMrsCmd: Done
247.188: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
247.188: mct_SendMrsCmd: Start
247.188: mct_SendMrsCmd: Done
247.188: DIMM 0 RttNom: 3
247.188: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.188: mct_SendMrsCmd: Start
247.189: mct_SendMrsCmd: Done
247.188: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001578
247.189: mct_SendMrsCmd: Start
247.188: mct_SendMrsCmd: Done
247.189: DIMM 0 RttWr: 2
247.189: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.189: mct_SendMrsCmd: Start
247.189: mct_SendMrsCmd: Done
247.189: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
247.189: mct_SendMrsCmd: Start
247.189: mct_SendMrsCmd: Done
247.189: DIMM 0 RttNom: 3
247.189: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.189: mct_SendMrsCmd: Start
247.189: mct_SendMrsCmd: Done
247.189: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201578
247.189: mct_SendMrsCmd: Start
247.189: mct_SendMrsCmd: Done
247.189: DIMM 1 RttWr: 2
247.189: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.189: mct_SendMrsCmd: Start
247.189: mct_SendMrsCmd: Done
247.189: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
247.189: mct_SendMrsCmd: Start
247.189: mct_SendMrsCmd: Done
247.189: DIMM 1 RttNom: 3
247.189: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.189: mct_SendMrsCmd: Start
247.189: mct_SendMrsCmd: Done
247.189: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401578
247.189: mct_SendMrsCmd: Start
247.189: mct_SendMrsCmd: Done
247.189: DIMM 1 RttWr: 2
247.189: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.189: mct_SendMrsCmd: Start
247.189: mct_SendMrsCmd: Done
247.189: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
247.189: mct_SendMrsCmd: Start
247.189: mct_SendMrsCmd: Done
247.189: DIMM 1 RttNom: 3
247.189: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.189: mct_SendMrsCmd: Start
247.189: mct_SendMrsCmd: Done
247.189: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601578
247.189: mct_SendMrsCmd: Start
247.189: mct_SendMrsCmd: Done
247.189: mct_DramInit_Sw_D: Done
247.189: AgesaHwWlPhase1: training nibble 0
247.189: DIMM 0 RttNom: 3
247.189: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.189: DIMM 0 RttWr: 2
247.189: DIMM 0 RttWr: 2
247.189: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.189: DIMM 0 RttWr: 2
247.189: DIMM 0 RttNom: 3
247.189: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.189: DIMM 0 RttNom: 3
247.189: DIMM 0 RttWr: 2
247.189: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.189: DIMM 0 RttWr: 2
247.189: DIMM 1 RttNom: 3
247.189: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.189: DIMM 0 RttNom: 3
247.190: DIMM 1 RttWr: 2
247.190: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.190: DIMM 0 RttWr: 2
247.190: DIMM 1 RttNom: 3
247.190: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.190: DIMM 0 RttNom: 3
247.190: DIMM 1 RttWr: 2
247.190: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.190: DIMM 0 RttWr: 2
247.190: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.190: <09>Lane 00 scaled delay: 0047
247.190: <09>Lane 00 new seed: 0047
247.190: <09>Lane 01 scaled delay: 0047
247.190: <09>Lane 01 new seed: 0047
247.190: <09>Lane 02 scaled delay: 0047
247.190: <09>Lane 02 new seed: 0047
247.190: <09>Lane 03 scaled delay: 0047
247.190: <09>Lane 03 new seed: 0047
247.190: <09>Lane 04 scaled delay: 0047
247.190: <09>Lane 04 new seed: 0047
247.190: <09>Lane 05 scaled delay: 0047
247.190: <09>Lane 05 new seed: 0047
247.190: <09>Lane 06 scaled delay: 0047
247.190: <09>Lane 06 new seed: 0047
247.190: <09>Lane 07 scaled delay: 0047
247.190: <09>Lane 07 new seed: 0047
247.190: <09>Lane 08 scaled delay: 0047
247.190: <09>Lane 08 new seed: 0047
247.190: <09>Lane 00 nibble 0 raw readback: 0046
247.190: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0046
247.190: <09>Lane 00 nibble 0 adjusted value (post nibble): 0046
247.190: <09>Lane 01 nibble 0 raw readback: 003f
247.190: <09>Lane 01 nibble 0 adjusted value (pre nibble): 003f
247.190: <09>Lane 01 nibble 0 adjusted value (post nibble): 003f
247.190: <09>Lane 02 nibble 0 raw readback: 003d
247.190: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003d
247.190: <09>Lane 02 nibble 0 adjusted value (post nibble): 003d
247.190: <09>Lane 03 nibble 0 raw readback: 003e
247.190: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003e
247.190: <09>Lane 03 nibble 0 adjusted value (post nibble): 003e
247.190: <09>Lane 04 nibble 0 raw readback: 003b
247.190: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003b
247.190: <09>Lane 04 nibble 0 adjusted value (post nibble): 003b
247.190: <09>Lane 05 nibble 0 raw readback: 003e
247.190: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003e
247.190: <09>Lane 05 nibble 0 adjusted value (post nibble): 003e
247.190: <09>Lane 06 nibble 0 raw readback: 0040
247.190: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0040
247.190: <09>Lane 06 nibble 0 adjusted value (post nibble): 0040
247.191: <09>Lane 07 nibble 0 raw readback: 0043
247.191: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0043
247.191: <09>Lane 07 nibble 0 adjusted value (post nibble): 0043
247.191: <09>Lane 08 nibble 0 raw readback: 0037
247.191: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0037
247.191: <09>Lane 08 nibble 0 adjusted value (post nibble): 0037
247.191: AgesaHwWlPhase1: training nibble 1
247.191: DIMM 0 RttNom: 3
247.191: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.191: DIMM 0 RttWr: 2
247.191: DIMM 0 RttWr: 2
247.191: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.191: DIMM 0 RttWr: 2
247.191: DIMM 0 RttNom: 3
247.191: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.191: DIMM 0 RttNom: 3
247.191: DIMM 0 RttWr: 2
247.191: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.191: DIMM 0 RttWr: 2
247.191: DIMM 1 RttNom: 3
247.191: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.191: DIMM 0 RttNom: 3
247.191: DIMM 1 RttWr: 2
247.191: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.191: DIMM 0 RttWr: 2
247.191: DIMM 1 RttNom: 3
247.191: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.191: DIMM 0 RttNom: 3
247.191: DIMM 1 RttWr: 2
247.191: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.191: DIMM 0 RttWr: 2
247.191: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.191: <09>Lane 00 new seed: 0047
247.191: <09>Lane 01 new seed: 0047
247.191: <09>Lane 02 new seed: 0047
247.191: <09>Lane 03 new seed: 0047
247.191: <09>Lane 04 new seed: 0047
247.191: <09>Lane 05 new seed: 0047
247.191: <09>Lane 06 new seed: 0047
247.191: <09>Lane 07 new seed: 0047
247.191: <09>Lane 08 new seed: 0047
247.191: <09>Lane 00 nibble 1 raw readback: 0047
247.191: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0047
247.191: <09>Lane 00 nibble 1 adjusted value (post nibble): 0047
247.191: <09>Lane 01 nibble 1 raw readback: 0042
247.191: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0042
247.191: <09>Lane 01 nibble 1 adjusted value (post nibble): 0044
247.191: <09>Lane 02 nibble 1 raw readback: 003e
247.191: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003e
247.191: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
247.191: <09>Lane 03 nibble 1 raw readback: 003c
247.191: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003c
247.191: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
247.191: <09>Lane 04 nibble 1 raw readback: 003a
247.191: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003a
247.191: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
247.191: <09>Lane 05 nibble 1 raw readback: 003d
247.191: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003d
247.194: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
247.191: <09>Lane 06 nibble 1 raw readback: 0041
247.191: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0041
247.191: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
247.191: <09>Lane 07 nibble 1 raw readback: 0044
247.191: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0044
247.191: <09>Lane 07 nibble 1 adjusted value (post nibble): 0045
247.191: <09>Lane 08 nibble 1 raw readback: 0038
247.191: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0038
247.191: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
247.192: <09>original critical gross delay: 0
247.192: <09>new critical gross delay: 0
247.192: DIMM 0 RttNom: 3
247.192: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.192: DIMM 0 RttNom: 3
247.192: DIMM 0 RttWr: 2
247.192: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.192: DIMM 0 RttWr: 2
247.192: DIMM 0 RttNom: 3
247.192: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.192: DIMM 0 RttNom: 3
247.192: DIMM 0 RttWr: 2
247.192: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.192: DIMM 0 RttWr: 2
247.192: DIMM 1 RttNom: 3
247.192: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.192: DIMM 0 RttNom: 3
247.192: DIMM 1 RttWr: 2
247.192: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.192: DIMM 0 RttWr: 2
247.192: DIMM 1 RttNom: 3
247.192: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.192: DIMM 0 RttNom: 3
247.192: DIMM 1 RttWr: 2
247.192: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.192: DIMM 0 RttWr: 2
247.192: AgesaHwWlPhase1: training nibble 0
247.192: DIMM 1 RttNom: 3
247.192: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.192: DIMM 1 RttWr: 2
247.192: DIMM 1 RttWr: 2
247.192: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.192: DIMM 1 RttWr: 2
247.192: DIMM 1 RttNom: 3
247.192: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.192: DIMM 1 RttNom: 3
247.192: DIMM 1 RttWr: 2
247.192: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.192: DIMM 1 RttWr: 2
247.192: DIMM 0 RttNom: 3
247.192: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.192: DIMM 1 RttNom: 3
247.192: DIMM 0 RttWr: 2
247.192: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.192: DIMM 1 RttWr: 2
247.192: DIMM 0 RttNom: 3
247.192: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.192: DIMM 1 RttNom: 3
247.192: DIMM 0 RttWr: 2
247.192: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.192: DIMM 1 RttWr: 2
247.192: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.192: <09>Lane 00 scaled delay: 0047
247.192: <09>Lane 00 new seed: 0047
247.192: <09>Lane 01 scaled delay: 0047
247.192: <09>Lane 01 new seed: 0047
247.192: <09>Lane 02 scaled delay: 0047
247.192: <09>Lane 02 new seed: 0047
247.193: <09>Lane 03 scaled delay: 0047
247.193: <09>Lane 03 new seed: 0047
247.193: <09>Lane 04 scaled delay: 0047
247.193: <09>Lane 04 new seed: 0047
247.193: <09>Lane 05 scaled delay: 0047
247.193: <09>Lane 05 new seed: 0047
247.193: <09>Lane 06 scaled delay: 0047
247.193: <09>Lane 06 new seed: 0047
247.193: <09>Lane 07 scaled delay: 0047
247.193: <09>Lane 07 new seed: 0047
247.193: <09>Lane 08 scaled delay: 0047
247.193: <09>Lane 08 new seed: 0047
247.193: <09>Lane 00 nibble 0 raw readback: 0045
247.193: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0045
247.193: <09>Lane 00 nibble 0 adjusted value (post nibble): 0045
247.193: <09>Lane 01 nibble 0 raw readback: 0040
247.193: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0040
247.193: <09>Lane 01 nibble 0 adjusted value (post nibble): 0040
247.193: <09>Lane 02 nibble 0 raw readback: 003d
247.193: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003d
247.193: <09>Lane 02 nibble 0 adjusted value (post nibble): 003d
247.193: <09>Lane 03 nibble 0 raw readback: 003c
247.193: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003c
247.193: <09>Lane 03 nibble 0 adjusted value (post nibble): 003c
247.193: <09>Lane 04 nibble 0 raw readback: 0038
247.193: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0038
247.193: <09>Lane 04 nibble 0 adjusted value (post nibble): 0038
247.193: <09>Lane 05 nibble 0 raw readback: 003c
247.193: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003c
247.193: <09>Lane 05 nibble 0 adjusted value (post nibble): 003c
247.193: <09>Lane 06 nibble 0 raw readback: 003e
247.193: <09>Lane 06 nibble 0 adjusted value (pre nibble): 003e
247.193: <09>Lane 06 nibble 0 adjusted value (post nibble): 003e
247.193: <09>Lane 07 nibble 0 raw readback: 0042
247.193: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0042
247.193: <09>Lane 07 nibble 0 adjusted value (post nibble): 0042
247.193: <09>Lane 08 nibble 0 raw readback: 0037
247.193: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0037
247.193: <09>Lane 08 nibble 0 adjusted value (post nibble): 0037
247.193: AgesaHwWlPhase1: training nibble 1
247.193: DIMM 1 RttNom: 3
247.193: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.193: DIMM 1 RttWr: 2
247.193: DIMM 1 RttWr: 2
247.193: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.193: DIMM 1 RttWr: 2
247.193: DIMM 1 RttNom: 3
247.193: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.193: DIMM 1 RttNom: 3
247.193: DIMM 1 RttWr: 2
247.193: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.193: DIMM 1 RttWr: 2
247.193: DIMM 0 RttNom: 3
247.193: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.193: DIMM 1 RttNom: 3
247.193: DIMM 0 RttWr: 2
247.193: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.193: DIMM 1 RttWr: 2
247.193: DIMM 0 RttNom: 3
247.193: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.193: DIMM 1 RttNom: 3
247.193: DIMM 0 RttWr: 2
247.193: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.193: DIMM 1 RttWr: 2
247.193: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.193: <09>Lane 00 new seed: 0047
247.193: <09>Lane 01 new seed: 0047
247.193: <09>Lane 02 new seed: 0047
247.193: <09>Lane 03 new seed: 0047
247.194: <09>Lane 04 new seed: 0047
247.194: <09>Lane 05 new seed: 0047
247.194: <09>Lane 06 new seed: 0047
247.194: <09>Lane 07 new seed: 0047
247.194: <09>Lane 08 new seed: 0047
247.194: <09>Lane 00 nibble 1 raw readback: 0044
247.194: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0044
247.194: <09>Lane 00 nibble 1 adjusted value (post nibble): 0045
247.194: <09>Lane 01 nibble 1 raw readback: 0040
247.194: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0040
247.194: <09>Lane 01 nibble 1 adjusted value (post nibble): 0043
247.194: <09>Lane 02 nibble 1 raw readback: 003d
247.194: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003d
247.194: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
247.194: <09>Lane 03 nibble 1 raw readback: 003c
247.194: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003c
247.194: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
247.194: <09>Lane 04 nibble 1 raw readback: 0039
247.194: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
247.194: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
247.194: <09>Lane 05 nibble 1 raw readback: 003c
247.194: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003c
247.194: <09>Lane 05 nibble 1 adjusted value (post nibble): 0041
247.194: <09>Lane 06 nibble 1 raw readback: 003d
247.194: <09>Lane 06 nibble 1 adjusted value (pre nibble): 003d
247.194: <09>Lane 06 nibble 1 adjusted value (post nibble): 0042
247.194: <09>Lane 07 nibble 1 raw readback: 0042
247.194: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0042
247.194: <09>Lane 07 nibble 1 adjusted value (post nibble): 0044
247.194: <09>Lane 08 nibble 1 raw readback: 0036
247.194: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0036
247.194: <09>Lane 08 nibble 1 adjusted value (post nibble): 003e
247.194: <09>original critical gross delay: 0
247.194: <09>new critical gross delay: 0
247.194: DIMM 1 RttNom: 3
247.194: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.194: DIMM 1 RttNom: 3
247.194: DIMM 1 RttWr: 2
247.194: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480480
247.194: DIMM 1 RttWr: 2
247.194: DIMM 1 RttNom: 3
247.194: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.194: DIMM 1 RttNom: 3
247.194: DIMM 1 RttWr: 2
247.194: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680480
247.194: DIMM 1 RttWr: 2
247.194: DIMM 0 RttNom: 3
247.194: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.194: DIMM 1 RttNom: 3
247.194: DIMM 0 RttWr: 2
247.194: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080480
247.194: DIMM 1 RttWr: 2
247.194: DIMM 0 RttNom: 3
247.194: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.194: DIMM 1 RttNom: 3
247.194: DIMM 0 RttWr: 2
247.194: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280480
247.194: DIMM 1 RttWr: 2
247.195: SPD2ndTiming: Start
247.195: SPD2ndTiming: Done
247.195: mct_BeforeDramInit_Prod_D: Start
247.195: mct_ProgramODT_D: Start
247.195: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
247.195: mct_ProgramODT_D: Done
247.195: mct_BeforeDramInit_Prod_D: Done
247.195: mct_DramInit_Sw_D: Start
247.195: DIMM 0 RttWr: 2
247.195: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.195: mct_SendMrsCmd: Start
247.195: mct_SendMrsCmd: Done
247.195: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
247.195: mct_SendMrsCmd: Start
247.195: mct_SendMrsCmd: Done
247.195: DIMM 0 RttNom: 3
247.195: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.195: mct_SendMrsCmd: Start
247.195: mct_SendMrsCmd: Done
247.195: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001578
247.195: mct_SendMrsCmd: Start
247.195: mct_SendMrsCmd: Done
247.195: DIMM 0 RttWr: 2
247.195: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.195: mct_SendMrsCmd: Start
247.195: mct_SendMrsCmd: Done
247.195: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
247.195: mct_SendMrsCmd: Start
247.195: mct_SendMrsCmd: Done
247.195: DIMM 0 RttNom: 3
247.195: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.195: mct_SendMrsCmd: Start
247.195: mct_SendMrsCmd: Done
247.195: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201578
247.195: mct_SendMrsCmd: Start
247.195: mct_SendMrsCmd: Done
247.195: DIMM 1 RttWr: 2
247.195: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.195: mct_SendMrsCmd: Start
247.195: mct_SendMrsCmd: Done
247.195: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
247.196: mct_SendMrsCmd: Start
247.196: mct_SendMrsCmd: Done
247.196: DIMM 1 RttNom: 3
247.196: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.196: mct_SendMrsCmd: Start
247.196: mct_SendMrsCmd: Done
247.196: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401578
247.196: mct_SendMrsCmd: Start
247.196: mct_SendMrsCmd: Done
247.196: DIMM 1 RttWr: 2
247.196: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.196: mct_SendMrsCmd: Start
247.196: mct_SendMrsCmd: Done
247.196: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
247.196: mct_SendMrsCmd: Start
247.196: mct_SendMrsCmd: Done
247.196: DIMM 1 RttNom: 3
247.196: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.196: mct_SendMrsCmd: Start
247.196: mct_SendMrsCmd: Done
247.196: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601578
247.196: mct_SendMrsCmd: Start
247.196: mct_SendMrsCmd: Done
247.196: mct_DramInit_Sw_D: Done
247.196: AgesaHwWlPhase1: training nibble 0
247.196: DIMM 0 RttNom: 3
247.196: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.196: DIMM 0 RttWr: 2
247.196: DIMM 0 RttWr: 2
247.196: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.196: DIMM 0 RttWr: 2
247.196: DIMM 0 RttNom: 3
247.196: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.196: DIMM 0 RttNom: 3
247.196: DIMM 0 RttWr: 2
247.196: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.196: DIMM 0 RttWr: 2
247.196: DIMM 1 RttNom: 3
247.196: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.196: DIMM 0 RttNom: 3
247.196: DIMM 1 RttWr: 2
247.196: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.196: DIMM 0 RttWr: 2
247.196: DIMM 1 RttNom: 3
247.196: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.197: DIMM 0 RttNom: 3
247.196: DIMM 1 RttWr: 2
247.196: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.196: DIMM 0 RttWr: 2
247.196: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.196: <09>Lane 00 scaled delay: 0047
247.196: <09>Lane 00 new seed: 0047
247.196: <09>Lane 01 scaled delay: 0047
247.196: <09>Lane 01 new seed: 0047
247.196: <09>Lane 02 scaled delay: 0047
247.196: <09>Lane 02 new seed: 0047
247.196: <09>Lane 03 scaled delay: 0047
247.196: <09>Lane 03 new seed: 0047
247.196: <09>Lane 04 scaled delay: 0047
247.196: <09>Lane 04 new seed: 0047
247.196: <09>Lane 05 scaled delay: 0047
247.197: <09>Lane 05 new seed: 0047
247.196: <09>Lane 06 scaled delay: 0047
247.196: <09>Lane 06 new seed: 0047
247.196: <09>Lane 07 scaled delay: 0047
247.197: <09>Lane 07 new seed: 0047
247.197: <09>Lane 08 scaled delay: 0047
247.197: <09>Lane 08 new seed: 0047
247.197: <09>Lane 00 nibble 0 raw readback: 0047
247.197: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0047
247.197: <09>Lane 00 nibble 0 adjusted value (post nibble): 0047
247.197: <09>Lane 01 nibble 0 raw readback: 0042
247.197: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0042
247.197: <09>Lane 01 nibble 0 adjusted value (post nibble): 0042
247.197: <09>Lane 02 nibble 0 raw readback: 003e
247.197: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003e
247.197: <09>Lane 02 nibble 0 adjusted value (post nibble): 003e
247.197: <09>Lane 03 nibble 0 raw readback: 003b
247.197: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
247.197: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
247.197: <09>Lane 04 nibble 0 raw readback: 003a
247.197: <09>Lane 04 nibble 0 adjusted value (pre nibble): 003a
247.197: <09>Lane 04 nibble 0 adjusted value (post nibble): 003a
247.197: <09>Lane 05 nibble 0 raw readback: 003e
247.197: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003e
247.197: <09>Lane 05 nibble 0 adjusted value (post nibble): 003e
247.197: <09>Lane 06 nibble 0 raw readback: 0041
247.197: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0041
247.197: <09>Lane 06 nibble 0 adjusted value (post nibble): 0041
247.197: <09>Lane 07 nibble 0 raw readback: 0045
247.197: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0045
247.197: <09>Lane 07 nibble 0 adjusted value (post nibble): 0045
247.197: <09>Lane 08 nibble 0 raw readback: 0037
247.197: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0037
247.197: <09>Lane 08 nibble 0 adjusted value (post nibble): 0037
247.197: AgesaHwWlPhase1: training nibble 1
247.197: DIMM 0 RttNom: 3
247.197: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.197: DIMM 0 RttWr: 2
247.197: DIMM 0 RttWr: 2
247.197: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.197: DIMM 0 RttWr: 2
247.197: DIMM 0 RttNom: 3
247.197: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.197: DIMM 0 RttNom: 3
247.197: DIMM 0 RttWr: 2
247.197: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.197: DIMM 0 RttWr: 2
247.197: DIMM 1 RttNom: 3
247.197: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.197: DIMM 0 RttNom: 3
247.197: DIMM 1 RttWr: 2
247.197: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.197: DIMM 0 RttWr: 2
247.197: DIMM 1 RttNom: 3
247.197: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.197: DIMM 0 RttNom: 3
247.197: DIMM 1 RttWr: 2
247.197: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.197: DIMM 0 RttWr: 2
247.197: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.197: <09>Lane 00 new seed: 0047
247.197: <09>Lane 01 new seed: 0047
247.197: <09>Lane 02 new seed: 0047
247.198: <09>Lane 03 new seed: 0047
247.197: <09>Lane 04 new seed: 0047
247.197: <09>Lane 05 new seed: 0047
247.198: <09>Lane 06 new seed: 0047
247.198: <09>Lane 07 new seed: 0047
247.198: <09>Lane 08 new seed: 0047
247.198: <09>Lane 00 nibble 1 raw readback: 0048
247.198: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0048
247.198: <09>Lane 00 nibble 1 adjusted value (post nibble): 0047
247.198: <09>Lane 01 nibble 1 raw readback: 0044
247.198: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0044
247.198: <09>Lane 01 nibble 1 adjusted value (post nibble): 0045
247.198: <09>Lane 02 nibble 1 raw readback: 0040
247.198: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0040
247.198: <09>Lane 02 nibble 1 adjusted value (post nibble): 0043
247.198: <09>Lane 03 nibble 1 raw readback: 003b
247.198: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003b
247.198: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
247.198: <09>Lane 04 nibble 1 raw readback: 003a
247.198: <09>Lane 04 nibble 1 adjusted value (pre nibble): 003a
247.198: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
247.198: <09>Lane 05 nibble 1 raw readback: 003d
247.198: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003d
247.198: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
247.198: <09>Lane 06 nibble 1 raw readback: 0041
247.198: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0041
247.198: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
247.198: <09>Lane 07 nibble 1 raw readback: 0046
247.198: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0046
247.198: <09>Lane 07 nibble 1 adjusted value (post nibble): 0046
247.198: <09>Lane 08 nibble 1 raw readback: 0039
247.198: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0039
247.198: <09>Lane 08 nibble 1 adjusted value (post nibble): 0040
247.198: <09>original critical gross delay: 0
247.198: <09>new critical gross delay: 0
247.198: DIMM 0 RttNom: 3
247.198: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.198: DIMM 0 RttNom: 3
247.198: DIMM 0 RttWr: 2
247.198: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.198: DIMM 0 RttWr: 2
247.198: DIMM 0 RttNom: 3
247.198: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.198: DIMM 0 RttNom: 3
247.198: DIMM 0 RttWr: 2
247.198: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.198: DIMM 0 RttWr: 2
247.198: DIMM 1 RttNom: 3
247.198: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.198: DIMM 0 RttNom: 3
247.198: DIMM 1 RttWr: 2
247.198: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.198: DIMM 0 RttWr: 2
247.198: DIMM 1 RttNom: 3
247.198: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.198: DIMM 0 RttNom: 3
247.198: DIMM 1 RttWr: 2
247.198: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.198: DIMM 0 RttWr: 2
247.198: AgesaHwWlPhase1: training nibble 0
247.198: DIMM 1 RttNom: 3
247.198: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.198: DIMM 1 RttWr: 2
247.198: DIMM 1 RttWr: 2
247.199: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.198: DIMM 1 RttWr: 2
247.199: DIMM 1 RttNom: 3
247.199: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.199: DIMM 1 RttNom: 3
247.199: DIMM 1 RttWr: 2
247.199: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.199: DIMM 1 RttWr: 2
247.199: DIMM 0 RttNom: 3
247.199: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.199: DIMM 1 RttNom: 3
247.199: DIMM 0 RttWr: 2
247.199: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.199: DIMM 1 RttWr: 2
247.199: DIMM 0 RttNom: 3
247.199: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.199: DIMM 1 RttNom: 3
247.199: DIMM 0 RttWr: 2
247.199: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.199: DIMM 1 RttWr: 2
247.199: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.199: <09>Lane 00 scaled delay: 0047
247.199: <09>Lane 00 new seed: 0047
247.199: <09>Lane 01 scaled delay: 0047
247.199: <09>Lane 01 new seed: 0047
247.199: <09>Lane 02 scaled delay: 0047
247.199: <09>Lane 02 new seed: 0047
247.199: <09>Lane 03 scaled delay: 0047
247.199: <09>Lane 03 new seed: 0047
247.199: <09>Lane 04 scaled delay: 0047
247.199: <09>Lane 04 new seed: 0047
247.199: <09>Lane 05 scaled delay: 0047
247.199: <09>Lane 05 new seed: 0047
247.199: <09>Lane 06 scaled delay: 0047
247.199: <09>Lane 06 new seed: 0047
247.199: <09>Lane 07 scaled delay: 0047
247.199: <09>Lane 07 new seed: 0047
247.199: <09>Lane 08 scaled delay: 0047
247.199: <09>Lane 08 new seed: 0047
247.199: <09>Lane 00 nibble 0 raw readback: 0047
247.199: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0047
247.199: <09>Lane 00 nibble 0 adjusted value (post nibble): 0047
247.199: <09>Lane 01 nibble 0 raw readback: 0042
247.199: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0042
247.199: <09>Lane 01 nibble 0 adjusted value (post nibble): 0042
247.199: <09>Lane 02 nibble 0 raw readback: 003d
247.199: <09>Lane 02 nibble 0 adjusted value (pre nibble): 003d
247.199: <09>Lane 02 nibble 0 adjusted value (post nibble): 003d
247.199: <09>Lane 03 nibble 0 raw readback: 003b
247.199: <09>Lane 03 nibble 0 adjusted value (pre nibble): 003b
247.199: <09>Lane 03 nibble 0 adjusted value (post nibble): 003b
247.199: <09>Lane 04 nibble 0 raw readback: 0039
247.199: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0039
247.199: <09>Lane 04 nibble 0 adjusted value (post nibble): 0039
247.199: <09>Lane 05 nibble 0 raw readback: 003e
247.199: <09>Lane 05 nibble 0 adjusted value (pre nibble): 003e
247.199: <09>Lane 05 nibble 0 adjusted value (post nibble): 003e
247.199: <09>Lane 06 nibble 0 raw readback: 0042
247.199: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0042
247.199: <09>Lane 06 nibble 0 adjusted value (post nibble): 0042
247.199: <09>Lane 07 nibble 0 raw readback: 0045
247.199: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0045
247.199: <09>Lane 07 nibble 0 adjusted value (post nibble): 0045
247.199: <09>Lane 08 nibble 0 raw readback: 0039
247.199: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0039
247.199: <09>Lane 08 nibble 0 adjusted value (post nibble): 0039
247.199: AgesaHwWlPhase1: training nibble 1
247.199: DIMM 1 RttNom: 3
247.199: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.199: DIMM 1 RttWr: 2
247.199: DIMM 1 RttWr: 2
247.200: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.199: DIMM 1 RttWr: 2
247.200: DIMM 1 RttNom: 3
247.200: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.200: DIMM 1 RttNom: 3
247.200: DIMM 1 RttWr: 2
247.200: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.200: DIMM 1 RttWr: 2
247.200: DIMM 0 RttNom: 3
247.200: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.200: DIMM 1 RttNom: 3
247.200: DIMM 0 RttWr: 2
247.200: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.200: DIMM 1 RttWr: 2
247.200: DIMM 0 RttNom: 3
247.200: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.200: DIMM 1 RttNom: 3
247.200: DIMM 0 RttWr: 2
247.200: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.200: DIMM 1 RttWr: 2
247.200: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.200: <09>Lane 00 new seed: 0047
247.200: <09>Lane 01 new seed: 0047
247.200: <09>Lane 02 new seed: 0047
247.200: <09>Lane 03 new seed: 0047
247.200: <09>Lane 04 new seed: 0047
247.200: <09>Lane 05 new seed: 0047
247.200: <09>Lane 06 new seed: 0047
247.200: <09>Lane 07 new seed: 0047
247.200: <09>Lane 08 new seed: 0047
247.200: <09>Lane 00 nibble 1 raw readback: 0047
247.200: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0047
247.200: <09>Lane 00 nibble 1 adjusted value (post nibble): 0047
247.200: <09>Lane 01 nibble 1 raw readback: 0043
247.200: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0043
247.200: <09>Lane 01 nibble 1 adjusted value (post nibble): 0045
247.200: <09>Lane 02 nibble 1 raw readback: 003e
247.200: <09>Lane 02 nibble 1 adjusted value (pre nibble): 003e
247.200: <09>Lane 02 nibble 1 adjusted value (post nibble): 0042
247.200: <09>Lane 03 nibble 1 raw readback: 003c
247.200: <09>Lane 03 nibble 1 adjusted value (pre nibble): 003c
247.200: <09>Lane 03 nibble 1 adjusted value (post nibble): 0041
247.200: <09>Lane 04 nibble 1 raw readback: 0039
247.200: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0039
247.200: <09>Lane 04 nibble 1 adjusted value (post nibble): 0040
247.200: <09>Lane 05 nibble 1 raw readback: 003d
247.200: <09>Lane 05 nibble 1 adjusted value (pre nibble): 003d
247.200: <09>Lane 05 nibble 1 adjusted value (post nibble): 0042
247.200: <09>Lane 06 nibble 1 raw readback: 0042
247.200: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0042
247.200: <09>Lane 06 nibble 1 adjusted value (post nibble): 0044
247.200: <09>Lane 07 nibble 1 raw readback: 0045
247.200: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0045
247.200: <09>Lane 07 nibble 1 adjusted value (post nibble): 0046
247.200: <09>Lane 08 nibble 1 raw readback: 0037
247.200: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0037
247.200: <09>Lane 08 nibble 1 adjusted value (post nibble): 003f
247.200: <09>original critical gross delay: 0
247.200: <09>new critical gross delay: 0
247.200: DIMM 1 RttNom: 3
247.200: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.200: DIMM 1 RttNom: 3
247.200: DIMM 1 RttWr: 2
247.200: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480480
247.200: DIMM 1 RttWr: 2
247.200: DIMM 1 RttNom: 3
247.200: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.201: DIMM 1 RttNom: 3
247.201: DIMM 1 RttWr: 2
247.201: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680480
247.201: DIMM 1 RttWr: 2
247.201: DIMM 0 RttNom: 3
247.201: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.201: DIMM 1 RttNom: 3
247.201: DIMM 0 RttWr: 2
247.201: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080480
247.201: DIMM 1 RttWr: 2
247.201: DIMM 0 RttNom: 3
247.201: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.201: DIMM 1 RttNom: 3
247.201: DIMM 0 RttWr: 2
247.201: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280480
247.201: DIMM 1 RttWr: 2
247.201: SetTargetFreq: Start
247.201: SetTargetFreq: Node 3: New frequency code: 000a
247.201: ChangeMemClk: Start
247.201: set_2t_configuration: Start
247.201: set_2t_configuration: Done
247.201: mct_BeforePlatformSpec: Start
247.201: mct_BeforePlatformSpec: Done
247.201: mct_PlatformSpec: Start
247.201: Programmed DCT 0 timing/termination pattern 003a3c3a 30222222
247.201: mct_PlatformSpec: Done
247.201: set_2t_configuration: Start
247.201: set_2t_configuration: Done
247.201: mct_BeforePlatformSpec: Start
247.201: mct_BeforePlatformSpec: Done
247.201: mct_PlatformSpec: Start
247.201: Programmed DCT 1 timing/termination pattern 003a3c3a 30222222
247.201: mct_PlatformSpec: Done
247.201: ChangeMemClk: Done
247.201: phyAssistedMemFnceTraining: Start
247.201: phyAssistedMemFnceTraining: training node 3 DCT 0
247.202: phyAssistedMemFnceTraining: done training node 3 DCT 0
247.202: phyAssistedMemFnceTraining: training node 3 DCT 1
247.202: phyAssistedMemFnceTraining: done training node 3 DCT 1
247.202: phyAssistedMemFnceTraining: Done
247.202: InitPhyCompensation: DCT 0: Start
247.202: Waiting for predriver calibration to be applied...done!
247.202: InitPhyCompensation: DCT 0: Done
247.202: phyAssistedMemFnceTraining: Start
247.202: phyAssistedMemFnceTraining: training node 3 DCT 0
247.202: phyAssistedMemFnceTraining: done training node 3 DCT 0
247.202: phyAssistedMemFnceTraining: training node 3 DCT 1
247.202: phyAssistedMemFnceTraining: done training node 3 DCT 1
247.202: phyAssistedMemFnceTraining: Done
247.202: InitPhyCompensation: DCT 1: Start
247.202: Waiting for predriver calibration to be applied...done!
247.202: InitPhyCompensation: DCT 1: Done
247.202: Preparing to send DCT 0 DIMM 0 RC10: 01 (F2xA8: 02000300)
247.203: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.203: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
247.203: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.203: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
247.203: Preparing to send DCT 0 DIMM 1 RC10: 01 (F2xA8: 02000c00)
247.203: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.203: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
247.203: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.203: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
247.203: Preparing to send DCT 1 DIMM 0 RC10: 01 (F2xA8: 02000300)
247.203: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.203: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
247.203: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.203: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
247.203: Preparing to send DCT 1 DIMM 1 RC10: 01 (F2xA8: 02000c00)
247.203: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.203: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
247.203: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.203: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
247.203: SetTargetFreq: Done
247.203: SPD2ndTiming: Start
247.203: SPD2ndTiming: Done
247.203: mct_BeforeDramInit_Prod_D: Start
247.203: mct_ProgramODT_D: Start
247.203: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
247.203: mct_ProgramODT_D: Done
247.203: mct_BeforeDramInit_Prod_D: Done
247.203: mct_DramInit_Sw_D: Start
247.203: DIMM 0 RttWr: 1
247.203: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.203: mct_SendMrsCmd: Start
247.203: mct_SendMrsCmd: Done
247.203: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
247.203: mct_SendMrsCmd: Start
247.203: mct_SendMrsCmd: Done
247.203: DIMM 0 RttNom: 3
247.203: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.203: mct_SendMrsCmd: Start
247.204: mct_SendMrsCmd: Done
247.204: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001978
247.204: mct_SendMrsCmd: Start
247.204: mct_SendMrsCmd: Done
247.204: DIMM 0 RttWr: 1
247.204: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.204: mct_SendMrsCmd: Start
247.204: mct_SendMrsCmd: Done
247.204: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
247.204: mct_SendMrsCmd: Start
247.204: mct_SendMrsCmd: Done
247.204: DIMM 0 RttNom: 3
247.204: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.204: mct_SendMrsCmd: Start
247.204: mct_SendMrsCmd: Done
247.204: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201978
247.204: mct_SendMrsCmd: Start
247.204: mct_SendMrsCmd: Done
247.204: DIMM 1 RttWr: 1
247.204: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.204: mct_SendMrsCmd: Start
247.204: mct_SendMrsCmd: Done
247.204: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
247.204: mct_SendMrsCmd: Start
247.204: mct_SendMrsCmd: Done
247.204: DIMM 1 RttNom: 3
247.204: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.204: mct_SendMrsCmd: Start
247.204: mct_SendMrsCmd: Done
247.204: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401978
247.204: mct_SendMrsCmd: Start
247.204: mct_SendMrsCmd: Done
247.204: DIMM 1 RttWr: 1
247.204: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.204: mct_SendMrsCmd: Start
247.204: mct_SendMrsCmd: Done
247.204: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
247.204: mct_SendMrsCmd: Start
247.204: mct_SendMrsCmd: Done
247.204: DIMM 1 RttNom: 3
247.204: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.204: mct_SendMrsCmd: Start
247.204: mct_SendMrsCmd: Done
247.204: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601978
247.204: mct_SendMrsCmd: Start
247.204: mct_SendMrsCmd: Done
247.204: mct_DramInit_Sw_D: Done
247.204: AgesaHwWlPhase1: training nibble 0
247.204: DIMM 0 RttNom: 3
247.204: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.204: DIMM 0 RttWr: 1
247.204: DIMM 0 RttWr: 1
247.204: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.204: DIMM 0 RttWr: 1
247.204: DIMM 0 RttNom: 3
247.204: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.204: DIMM 0 RttNom: 3
247.204: DIMM 0 RttWr: 1
247.205: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.204: DIMM 0 RttWr: 1
247.205: DIMM 1 RttNom: 3
247.205: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.205: DIMM 0 RttNom: 3
247.205: DIMM 1 RttWr: 1
247.205: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.205: DIMM 0 RttWr: 1
247.205: DIMM 1 RttNom: 3
247.205: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.205: DIMM 0 RttNom: 3
247.205: DIMM 1 RttWr: 1
247.205: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.205: DIMM 0 RttWr: 1
247.205: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.205: <09>Lane 00 scaled delay: 0053
247.205: <09>Lane 00 new seed: 0053
247.205: <09>Lane 01 scaled delay: 004f
247.205: <09>Lane 01 new seed: 004f
247.205: <09>Lane 02 scaled delay: 004d
247.205: <09>Lane 02 new seed: 004d
247.205: <09>Lane 03 scaled delay: 004b
247.205: <09>Lane 03 new seed: 004b
247.205: <09>Lane 04 scaled delay: 004a
247.205: <09>Lane 04 new seed: 004a
247.205: <09>Lane 05 scaled delay: 004d
247.205: <09>Lane 05 new seed: 004d
247.205: <09>Lane 06 scaled delay: 004f
247.205: <09>Lane 06 new seed: 004f
247.205: <09>Lane 07 scaled delay: 0051
247.205: <09>Lane 07 new seed: 0051
247.205: <09>Lane 08 scaled delay: 0049
247.205: <09>Lane 08 new seed: 0049
247.205: <09>Lane 00 nibble 0 raw readback: 0052
247.205: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0052
247.205: <09>Lane 00 nibble 0 adjusted value (post nibble): 0052
247.205: <09>Lane 01 nibble 0 raw readback: 0049
247.205: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0049
247.205: <09>Lane 01 nibble 0 adjusted value (post nibble): 0049
247.205: <09>Lane 02 nibble 0 raw readback: 0047
247.205: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0047
247.205: <09>Lane 02 nibble 0 adjusted value (post nibble): 0047
247.205: <09>Lane 03 nibble 0 raw readback: 0048
247.205: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0048
247.205: <09>Lane 03 nibble 0 adjusted value (post nibble): 0048
247.205: <09>Lane 04 nibble 0 raw readback: 0045
247.205: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0045
247.205: <09>Lane 04 nibble 0 adjusted value (post nibble): 0045
247.205: <09>Lane 05 nibble 0 raw readback: 004a
247.205: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004a
247.205: <09>Lane 05 nibble 0 adjusted value (post nibble): 004a
247.205: <09>Lane 06 nibble 0 raw readback: 004b
247.205: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004b
247.205: <09>Lane 06 nibble 0 adjusted value (post nibble): 004b
247.205: <09>Lane 07 nibble 0 raw readback: 004f
247.205: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004f
247.205: <09>Lane 07 nibble 0 adjusted value (post nibble): 004f
247.205: <09>Lane 08 nibble 0 raw readback: 003f
247.206: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003f
247.206: <09>Lane 08 nibble 0 adjusted value (post nibble): 003f
247.206: AgesaHwWlPhase1: training nibble 1
247.206: DIMM 0 RttNom: 3
247.206: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.206: DIMM 0 RttWr: 1
247.206: DIMM 0 RttWr: 1
247.206: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.206: DIMM 0 RttWr: 1
247.206: DIMM 0 RttNom: 3
247.206: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.206: DIMM 0 RttNom: 3
247.206: DIMM 0 RttWr: 1
247.206: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.206: DIMM 0 RttWr: 1
247.206: DIMM 1 RttNom: 3
247.206: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.206: DIMM 0 RttNom: 3
247.206: DIMM 1 RttWr: 1
247.206: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.206: DIMM 0 RttWr: 1
247.206: DIMM 1 RttNom: 3
247.206: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.206: DIMM 0 RttNom: 3
247.206: DIMM 1 RttWr: 1
247.206: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.206: DIMM 0 RttWr: 1
247.206: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.206: <09>Lane 00 new seed: 0053
247.206: <09>Lane 01 new seed: 004f
247.206: <09>Lane 02 new seed: 004d
247.206: <09>Lane 03 new seed: 004b
247.206: <09>Lane 04 new seed: 004a
247.206: <09>Lane 05 new seed: 004d
247.206: <09>Lane 06 new seed: 004f
247.206: <09>Lane 07 new seed: 0051
247.206: <09>Lane 08 new seed: 0049
247.206: <09>Lane 00 nibble 1 raw readback: 0054
247.206: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0054
247.206: <09>Lane 00 nibble 1 adjusted value (post nibble): 0053
247.206: <09>Lane 01 nibble 1 raw readback: 004e
247.206: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004e
247.206: <09>Lane 01 nibble 1 adjusted value (post nibble): 004e
247.206: <09>Lane 02 nibble 1 raw readback: 004a
247.206: <09>Lane 02 nibble 1 adjusted value (pre nibble): 004a
247.206: <09>Lane 02 nibble 1 adjusted value (post nibble): 004b
247.206: <09>Lane 03 nibble 1 raw readback: 0045
247.206: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
247.206: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
247.206: <09>Lane 04 nibble 1 raw readback: 0044
247.206: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0044
247.206: <09>Lane 04 nibble 1 adjusted value (post nibble): 0047
247.206: <09>Lane 05 nibble 1 raw readback: 0047
247.206: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0047
247.206: <09>Lane 05 nibble 1 adjusted value (post nibble): 004a
247.206: <09>Lane 06 nibble 1 raw readback: 004d
247.206: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004d
247.206: <09>Lane 06 nibble 1 adjusted value (post nibble): 004e
247.206: <09>Lane 07 nibble 1 raw readback: 0051
247.206: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0051
247.206: <09>Lane 07 nibble 1 adjusted value (post nibble): 0051
247.206: <09>Lane 08 nibble 1 raw readback: 0041
247.206: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0041
247.206: <09>Lane 08 nibble 1 adjusted value (post nibble): 0045
247.206: <09>original critical gross delay: 0
247.206: <09>new critical gross delay: 0
247.207: DIMM 0 RttNom: 3
247.207: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.207: DIMM 0 RttNom: 3
247.207: DIMM 0 RttWr: 1
247.207: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.207: DIMM 0 RttWr: 1
247.207: DIMM 0 RttNom: 3
247.207: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.207: DIMM 0 RttNom: 3
247.207: DIMM 0 RttWr: 1
247.207: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.207: DIMM 0 RttWr: 1
247.207: DIMM 1 RttNom: 3
247.207: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.207: DIMM 0 RttNom: 3
247.207: DIMM 1 RttWr: 1
247.207: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.207: DIMM 0 RttWr: 1
247.207: DIMM 1 RttNom: 3
247.207: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.207: DIMM 0 RttNom: 3
247.207: DIMM 1 RttWr: 1
247.207: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.207: DIMM 0 RttWr: 1
247.207: AgesaHwWlPhase1: training nibble 0
247.207: DIMM 1 RttNom: 3
247.207: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.207: DIMM 1 RttWr: 1
247.207: DIMM 1 RttWr: 1
247.207: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.207: DIMM 1 RttWr: 1
247.207: DIMM 1 RttNom: 3
247.207: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.207: DIMM 1 RttNom: 3
247.207: DIMM 1 RttWr: 1
247.207: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.207: DIMM 1 RttWr: 1
247.207: DIMM 0 RttNom: 3
247.207: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.207: DIMM 1 RttNom: 3
247.207: DIMM 0 RttWr: 1
247.207: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.207: DIMM 1 RttWr: 1
247.207: DIMM 0 RttNom: 3
247.207: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.207: DIMM 1 RttNom: 3
247.207: DIMM 0 RttWr: 1
247.207: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.207: DIMM 1 RttWr: 1
247.207: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.207: <09>Lane 00 scaled delay: 0051
247.207: <09>Lane 00 new seed: 0051
247.207: <09>Lane 01 scaled delay: 004e
247.207: <09>Lane 01 new seed: 004e
247.207: <09>Lane 02 scaled delay: 004d
247.207: <09>Lane 02 new seed: 004d
247.207: <09>Lane 03 scaled delay: 004b
247.207: <09>Lane 03 new seed: 004b
247.207: <09>Lane 04 scaled delay: 004a
247.208: <09>Lane 04 new seed: 004a
247.207: <09>Lane 05 scaled delay: 004b
247.208: <09>Lane 05 new seed: 004b
247.208: <09>Lane 06 scaled delay: 004d
247.208: <09>Lane 06 new seed: 004d
247.208: <09>Lane 07 scaled delay: 004f
247.208: <09>Lane 07 new seed: 004f
247.208: <09>Lane 08 scaled delay: 0047
247.208: <09>Lane 08 new seed: 0047
247.208: <09>Lane 00 nibble 0 raw readback: 0051
247.208: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0051
247.208: <09>Lane 00 nibble 0 adjusted value (post nibble): 0051
247.208: <09>Lane 01 nibble 0 raw readback: 004b
247.208: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004b
247.208: <09>Lane 01 nibble 0 adjusted value (post nibble): 004b
247.208: <09>Lane 02 nibble 0 raw readback: 0046
247.208: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0046
247.208: <09>Lane 02 nibble 0 adjusted value (post nibble): 0046
247.208: <09>Lane 03 nibble 0 raw readback: 0045
247.208: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0045
247.208: <09>Lane 03 nibble 0 adjusted value (post nibble): 0045
247.208: <09>Lane 04 nibble 0 raw readback: 0042
247.208: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0042
247.208: <09>Lane 04 nibble 0 adjusted value (post nibble): 0042
247.208: <09>Lane 05 nibble 0 raw readback: 0046
247.208: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0046
247.208: <09>Lane 05 nibble 0 adjusted value (post nibble): 0046
247.208: <09>Lane 06 nibble 0 raw readback: 0048
247.208: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0048
247.208: <09>Lane 06 nibble 0 adjusted value (post nibble): 0048
247.208: <09>Lane 07 nibble 0 raw readback: 004d
247.208: <09>Lane 07 nibble 0 adjusted value (pre nibble): 004d
247.208: <09>Lane 07 nibble 0 adjusted value (post nibble): 004d
247.208: <09>Lane 08 nibble 0 raw readback: 003e
247.208: <09>Lane 08 nibble 0 adjusted value (pre nibble): 003e
247.208: <09>Lane 08 nibble 0 adjusted value (post nibble): 003e
247.208: AgesaHwWlPhase1: training nibble 1
247.208: DIMM 1 RttNom: 3
247.208: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.208: DIMM 1 RttWr: 1
247.208: DIMM 1 RttWr: 1
247.208: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.208: DIMM 1 RttWr: 1
247.208: DIMM 1 RttNom: 3
247.208: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.208: DIMM 1 RttNom: 3
247.208: DIMM 1 RttWr: 1
247.208: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.208: DIMM 1 RttWr: 1
247.208: DIMM 0 RttNom: 3
247.208: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.208: DIMM 1 RttNom: 3
247.208: DIMM 0 RttWr: 1
247.208: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.208: DIMM 1 RttWr: 1
247.208: DIMM 0 RttNom: 3
247.208: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.208: DIMM 1 RttNom: 3
247.208: DIMM 0 RttWr: 1
247.208: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.208: DIMM 1 RttWr: 1
247.208: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.208: <09>Lane 00 new seed: 0051
247.208: <09>Lane 01 new seed: 004e
247.208: <09>Lane 02 new seed: 004d
247.208: <09>Lane 03 new seed: 004b
247.208: <09>Lane 04 new seed: 004a
247.208: <09>Lane 05 new seed: 004b
247.208: <09>Lane 06 new seed: 004d
247.209: <09>Lane 07 new seed: 004f
247.208: <09>Lane 08 new seed: 0047
247.209: <09>Lane 00 nibble 1 raw readback: 0050
247.209: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0050
247.209: <09>Lane 00 nibble 1 adjusted value (post nibble): 0050
247.209: <09>Lane 01 nibble 1 raw readback: 004a
247.209: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004a
247.209: <09>Lane 01 nibble 1 adjusted value (post nibble): 004c
247.209: <09>Lane 02 nibble 1 raw readback: 0046
247.209: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0046
247.209: <09>Lane 02 nibble 1 adjusted value (post nibble): 0049
247.209: <09>Lane 03 nibble 1 raw readback: 0044
247.209: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0044
247.209: <09>Lane 03 nibble 1 adjusted value (post nibble): 0047
247.209: <09>Lane 04 nibble 1 raw readback: 0040
247.209: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0040
247.209: <09>Lane 04 nibble 1 adjusted value (post nibble): 0045
247.209: <09>Lane 05 nibble 1 raw readback: 0045
247.209: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0045
247.209: <09>Lane 05 nibble 1 adjusted value (post nibble): 0048
247.209: <09>Lane 06 nibble 1 raw readback: 0046
247.209: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0046
247.209: <09>Lane 06 nibble 1 adjusted value (post nibble): 0049
247.209: <09>Lane 07 nibble 1 raw readback: 004c
247.209: <09>Lane 07 nibble 1 adjusted value (pre nibble): 004c
247.209: <09>Lane 07 nibble 1 adjusted value (post nibble): 004d
247.209: <09>Lane 08 nibble 1 raw readback: 003c
247.209: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003c
247.209: <09>Lane 08 nibble 1 adjusted value (post nibble): 0041
247.209: <09>original critical gross delay: 0
247.209: <09>new critical gross delay: 0
247.209: DIMM 1 RttNom: 3
247.209: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440046
247.209: DIMM 1 RttNom: 3
247.209: DIMM 1 RttWr: 1
247.209: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480288
247.209: DIMM 1 RttWr: 1
247.209: DIMM 1 RttNom: 3
247.209: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640046
247.209: DIMM 1 RttNom: 3
247.209: DIMM 1 RttWr: 1
247.209: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680288
247.209: DIMM 1 RttWr: 1
247.209: DIMM 0 RttNom: 3
247.209: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040046
247.209: DIMM 1 RttNom: 3
247.209: DIMM 0 RttWr: 1
247.209: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080288
247.209: DIMM 1 RttWr: 1
247.209: DIMM 0 RttNom: 3
247.209: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240046
247.209: DIMM 1 RttNom: 3
247.209: DIMM 0 RttWr: 1
247.209: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280288
247.209: DIMM 1 RttWr: 1
247.209: SPD2ndTiming: Start
247.210: SPD2ndTiming: Done
247.210: mct_BeforeDramInit_Prod_D: Start
247.210: mct_ProgramODT_D: Start
247.210: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
247.210: mct_ProgramODT_D: Done
247.210: mct_BeforeDramInit_Prod_D: Done
247.210: mct_DramInit_Sw_D: Start
247.210: DIMM 0 RttWr: 1
247.210: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.210: mct_SendMrsCmd: Start
247.210: mct_SendMrsCmd: Done
247.210: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
247.210: mct_SendMrsCmd: Start
247.210: mct_SendMrsCmd: Done
247.210: DIMM 0 RttNom: 3
247.210: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.210: mct_SendMrsCmd: Start
247.210: mct_SendMrsCmd: Done
247.210: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001978
247.210: mct_SendMrsCmd: Start
247.210: mct_SendMrsCmd: Done
247.210: DIMM 0 RttWr: 1
247.210: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.210: mct_SendMrsCmd: Start
247.210: mct_SendMrsCmd: Done
247.210: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
247.210: mct_SendMrsCmd: Start
247.210: mct_SendMrsCmd: Done
247.210: DIMM 0 RttNom: 3
247.210: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.210: mct_SendMrsCmd: Start
247.210: mct_SendMrsCmd: Done
247.210: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201978
247.210: mct_SendMrsCmd: Start
247.210: mct_SendMrsCmd: Done
247.210: DIMM 1 RttWr: 1
247.210: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.210: mct_SendMrsCmd: Start
247.210: mct_SendMrsCmd: Done
247.210: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
247.210: mct_SendMrsCmd: Start
247.210: mct_SendMrsCmd: Done
247.210: DIMM 1 RttNom: 3
247.210: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.210: mct_SendMrsCmd: Start
247.210: mct_SendMrsCmd: Done
247.210: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401978
247.210: mct_SendMrsCmd: Start
247.210: mct_SendMrsCmd: Done
247.210: DIMM 1 RttWr: 1
247.210: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.210: mct_SendMrsCmd: Start
247.210: mct_SendMrsCmd: Done
247.210: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
247.211: mct_SendMrsCmd: Start
247.211: mct_SendMrsCmd: Done
247.211: DIMM 1 RttNom: 3
247.211: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.211: mct_SendMrsCmd: Start
247.211: mct_SendMrsCmd: Done
247.211: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601978
247.211: mct_SendMrsCmd: Start
247.211: mct_SendMrsCmd: Done
247.211: mct_DramInit_Sw_D: Done
247.211: AgesaHwWlPhase1: training nibble 0
247.211: DIMM 0 RttNom: 3
247.211: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.211: DIMM 0 RttWr: 1
247.211: DIMM 0 RttWr: 1
247.211: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.211: DIMM 0 RttWr: 1
247.211: DIMM 0 RttNom: 3
247.211: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.211: DIMM 0 RttNom: 3
247.211: DIMM 0 RttWr: 1
247.211: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.211: DIMM 0 RttWr: 1
247.211: DIMM 1 RttNom: 3
247.211: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.211: DIMM 0 RttNom: 3
247.211: DIMM 1 RttWr: 1
247.211: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.211: DIMM 0 RttWr: 1
247.211: DIMM 1 RttNom: 3
247.211: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.211: DIMM 0 RttNom: 3
247.211: DIMM 1 RttWr: 1
247.211: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.211: DIMM 0 RttWr: 1
247.211: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.211: <09>Lane 00 scaled delay: 0053
247.211: <09>Lane 00 new seed: 0053
247.211: <09>Lane 01 scaled delay: 0051
247.211: <09>Lane 01 new seed: 0051
247.211: <09>Lane 02 scaled delay: 004e
247.211: <09>Lane 02 new seed: 004e
247.211: <09>Lane 03 scaled delay: 004b
247.211: <09>Lane 03 new seed: 004b
247.211: <09>Lane 04 scaled delay: 004a
247.211: <09>Lane 04 new seed: 004a
247.211: <09>Lane 05 scaled delay: 004d
247.211: <09>Lane 05 new seed: 004d
247.211: <09>Lane 06 scaled delay: 004f
247.211: <09>Lane 06 new seed: 004f
247.211: <09>Lane 07 scaled delay: 0052
247.211: <09>Lane 07 new seed: 0052
247.211: <09>Lane 08 scaled delay: 004a
247.211: <09>Lane 08 new seed: 004a
247.211: <09>Lane 00 nibble 0 raw readback: 0055
247.212: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0055
247.212: <09>Lane 00 nibble 0 adjusted value (post nibble): 0055
247.212: <09>Lane 01 nibble 0 raw readback: 004f
247.212: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004f
247.212: <09>Lane 01 nibble 0 adjusted value (post nibble): 004f
247.212: <09>Lane 02 nibble 0 raw readback: 004a
247.212: <09>Lane 02 nibble 0 adjusted value (pre nibble): 004a
247.212: <09>Lane 02 nibble 0 adjusted value (post nibble): 004a
247.212: <09>Lane 03 nibble 0 raw readback: 0046
247.212: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0046
247.212: <09>Lane 03 nibble 0 adjusted value (post nibble): 0046
247.212: <09>Lane 04 nibble 0 raw readback: 0044
247.212: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0044
247.212: <09>Lane 04 nibble 0 adjusted value (post nibble): 0044
247.212: <09>Lane 05 nibble 0 raw readback: 004b
247.212: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004b
247.212: <09>Lane 05 nibble 0 adjusted value (post nibble): 004b
247.212: <09>Lane 06 nibble 0 raw readback: 004e
247.212: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004e
247.212: <09>Lane 06 nibble 0 adjusted value (post nibble): 004e
247.212: <09>Lane 07 nibble 0 raw readback: 0054
247.212: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0054
247.212: <09>Lane 07 nibble 0 adjusted value (post nibble): 0054
247.212: <09>Lane 08 nibble 0 raw readback: 0041
247.212: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0041
247.212: <09>Lane 08 nibble 0 adjusted value (post nibble): 0041
247.212: AgesaHwWlPhase1: training nibble 1
247.212: DIMM 0 RttNom: 3
247.212: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.212: DIMM 0 RttWr: 1
247.212: DIMM 0 RttWr: 1
247.212: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.212: DIMM 0 RttWr: 1
247.212: DIMM 0 RttNom: 3
247.212: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.212: DIMM 0 RttNom: 3
247.212: DIMM 0 RttWr: 1
247.212: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.212: DIMM 0 RttWr: 1
247.212: DIMM 1 RttNom: 3
247.212: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.212: DIMM 0 RttNom: 3
247.212: DIMM 1 RttWr: 1
247.212: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.212: DIMM 0 RttWr: 1
247.212: DIMM 1 RttNom: 3
247.212: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.212: DIMM 0 RttNom: 3
247.212: DIMM 1 RttWr: 1
247.212: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.212: DIMM 0 RttWr: 1
247.212: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.212: <09>Lane 00 new seed: 0053
247.212: <09>Lane 01 new seed: 0051
247.212: <09>Lane 02 new seed: 004e
247.212: <09>Lane 03 new seed: 004b
247.212: <09>Lane 04 new seed: 004a
247.212: <09>Lane 05 new seed: 004d
247.212: <09>Lane 06 new seed: 004f
247.212: <09>Lane 07 new seed: 0052
247.212: <09>Lane 08 new seed: 004a
247.212: <09>Lane 00 nibble 1 raw readback: 0055
247.212: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0055
247.212: <09>Lane 00 nibble 1 adjusted value (post nibble): 0054
247.212: <09>Lane 01 nibble 1 raw readback: 0050
247.212: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0050
247.212: <09>Lane 01 nibble 1 adjusted value (post nibble): 0050
247.212: <09>Lane 02 nibble 1 raw readback: 004b
247.213: <09>Lane 02 nibble 1 adjusted value (pre nibble): 004b
247.213: <09>Lane 02 nibble 1 adjusted value (post nibble): 004c
247.213: <09>Lane 03 nibble 1 raw readback: 0046
247.213: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0046
247.213: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
247.213: <09>Lane 04 nibble 1 raw readback: 0043
247.213: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0043
247.213: <09>Lane 04 nibble 1 adjusted value (post nibble): 0046
247.213: <09>Lane 05 nibble 1 raw readback: 0049
247.213: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0049
247.213: <09>Lane 05 nibble 1 adjusted value (post nibble): 004b
247.213: <09>Lane 06 nibble 1 raw readback: 004e
247.213: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004e
247.213: <09>Lane 06 nibble 1 adjusted value (post nibble): 004e
247.213: <09>Lane 07 nibble 1 raw readback: 0052
247.213: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0052
247.213: <09>Lane 07 nibble 1 adjusted value (post nibble): 0052
247.213: <09>Lane 08 nibble 1 raw readback: 0041
247.213: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0041
247.213: <09>Lane 08 nibble 1 adjusted value (post nibble): 0045
247.213: <09>original critical gross delay: 0
247.213: <09>new critical gross delay: 0
247.213: DIMM 0 RttNom: 3
247.213: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.213: DIMM 0 RttNom: 3
247.213: DIMM 0 RttWr: 1
247.213: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.213: DIMM 0 RttWr: 1
247.213: DIMM 0 RttNom: 3
247.213: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.213: DIMM 0 RttNom: 3
247.213: DIMM 0 RttWr: 1
247.213: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.213: DIMM 0 RttWr: 1
247.213: DIMM 1 RttNom: 3
247.213: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.213: DIMM 0 RttNom: 3
247.213: DIMM 1 RttWr: 1
247.213: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.213: DIMM 0 RttWr: 1
247.213: DIMM 1 RttNom: 3
247.213: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.213: DIMM 0 RttNom: 3
247.213: DIMM 1 RttWr: 1
247.213: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.213: DIMM 0 RttWr: 1
247.213: AgesaHwWlPhase1: training nibble 0
247.213: DIMM 1 RttNom: 3
247.213: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.213: DIMM 1 RttWr: 1
247.213: DIMM 1 RttWr: 1
247.213: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.213: DIMM 1 RttWr: 1
247.213: DIMM 1 RttNom: 3
247.213: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.213: DIMM 1 RttNom: 3
247.213: DIMM 1 RttWr: 1
247.213: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.213: DIMM 1 RttWr: 1
247.213: DIMM 0 RttNom: 3
247.214: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.213: DIMM 1 RttNom: 3
247.214: DIMM 0 RttWr: 1
247.214: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.214: DIMM 1 RttWr: 1
247.214: DIMM 0 RttNom: 3
247.214: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.214: DIMM 1 RttNom: 3
247.214: DIMM 0 RttWr: 1
247.214: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.214: DIMM 1 RttWr: 1
247.214: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.214: <09>Lane 00 scaled delay: 0053
247.214: <09>Lane 00 new seed: 0053
247.214: <09>Lane 01 scaled delay: 0051
247.214: <09>Lane 01 new seed: 0051
247.214: <09>Lane 02 scaled delay: 004d
247.214: <09>Lane 02 new seed: 004d
247.214: <09>Lane 03 scaled delay: 004b
247.214: <09>Lane 03 new seed: 004b
247.214: <09>Lane 04 scaled delay: 004a
247.214: <09>Lane 04 new seed: 004a
247.214: <09>Lane 05 scaled delay: 004d
247.214: <09>Lane 05 new seed: 004d
247.214: <09>Lane 06 scaled delay: 004f
247.214: <09>Lane 06 new seed: 004f
247.214: <09>Lane 07 scaled delay: 0052
247.214: <09>Lane 07 new seed: 0052
247.214: <09>Lane 08 scaled delay: 0049
247.214: <09>Lane 08 new seed: 0049
247.214: <09>Lane 00 nibble 0 raw readback: 0052
247.214: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0052
247.214: <09>Lane 00 nibble 0 adjusted value (post nibble): 0052
247.214: <09>Lane 01 nibble 0 raw readback: 004d
247.214: <09>Lane 01 nibble 0 adjusted value (pre nibble): 004d
247.214: <09>Lane 01 nibble 0 adjusted value (post nibble): 004d
247.214: <09>Lane 02 nibble 0 raw readback: 0047
247.214: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0047
247.214: <09>Lane 02 nibble 0 adjusted value (post nibble): 0047
247.214: <09>Lane 03 nibble 0 raw readback: 0044
247.214: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0044
247.214: <09>Lane 03 nibble 0 adjusted value (post nibble): 0044
247.214: <09>Lane 04 nibble 0 raw readback: 0041
247.214: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0041
247.214: <09>Lane 04 nibble 0 adjusted value (post nibble): 0041
247.214: <09>Lane 05 nibble 0 raw readback: 0049
247.214: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0049
247.214: <09>Lane 05 nibble 0 adjusted value (post nibble): 0049
247.214: <09>Lane 06 nibble 0 raw readback: 004d
247.214: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004d
247.214: <09>Lane 06 nibble 0 adjusted value (post nibble): 004d
247.214: <09>Lane 07 nibble 0 raw readback: 0051
247.214: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0051
247.214: <09>Lane 07 nibble 0 adjusted value (post nibble): 0051
247.214: <09>Lane 08 nibble 0 raw readback: 0040
247.214: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0040
247.214: <09>Lane 08 nibble 0 adjusted value (post nibble): 0040
247.214: AgesaHwWlPhase1: training nibble 1
247.214: DIMM 1 RttNom: 3
247.214: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.214: DIMM 1 RttWr: 1
247.214: DIMM 1 RttWr: 1
247.214: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.214: DIMM 1 RttWr: 1
247.214: DIMM 1 RttNom: 3
247.214: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.214: DIMM 1 RttNom: 3
247.214: DIMM 1 RttWr: 1
247.214: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.214: DIMM 1 RttWr: 1
247.214: DIMM 0 RttNom: 3
247.214: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.214: DIMM 1 RttNom: 3
247.214: DIMM 0 RttWr: 1
247.214: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.214: DIMM 1 RttWr: 1
247.215: DIMM 0 RttNom: 3
247.215: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.215: DIMM 1 RttNom: 3
247.215: DIMM 0 RttWr: 1
247.215: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.215: DIMM 1 RttWr: 1
247.215: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.215: <09>Lane 00 new seed: 0053
247.215: <09>Lane 01 new seed: 0051
247.215: <09>Lane 02 new seed: 004d
247.215: <09>Lane 03 new seed: 004b
247.215: <09>Lane 04 new seed: 004a
247.215: <09>Lane 05 new seed: 004d
247.215: <09>Lane 06 new seed: 004f
247.215: <09>Lane 07 new seed: 0052
247.215: <09>Lane 08 new seed: 0049
247.215: <09>Lane 00 nibble 1 raw readback: 0053
247.215: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0053
247.215: <09>Lane 00 nibble 1 adjusted value (post nibble): 0053
247.215: <09>Lane 01 nibble 1 raw readback: 004f
247.215: <09>Lane 01 nibble 1 adjusted value (pre nibble): 004f
247.215: <09>Lane 01 nibble 1 adjusted value (post nibble): 0050
247.215: <09>Lane 02 nibble 1 raw readback: 0048
247.215: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0048
247.215: <09>Lane 02 nibble 1 adjusted value (post nibble): 004a
247.215: <09>Lane 03 nibble 1 raw readback: 0045
247.215: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0045
247.215: <09>Lane 03 nibble 1 adjusted value (post nibble): 0048
247.215: <09>Lane 04 nibble 1 raw readback: 0041
247.215: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0041
247.215: <09>Lane 04 nibble 1 adjusted value (post nibble): 0045
247.215: <09>Lane 05 nibble 1 raw readback: 0047
247.215: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0047
247.215: <09>Lane 05 nibble 1 adjusted value (post nibble): 004a
247.215: <09>Lane 06 nibble 1 raw readback: 004d
247.215: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004d
247.215: <09>Lane 06 nibble 1 adjusted value (post nibble): 004e
247.215: <09>Lane 07 nibble 1 raw readback: 0051
247.215: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0051
247.215: <09>Lane 07 nibble 1 adjusted value (post nibble): 0051
247.215: <09>Lane 08 nibble 1 raw readback: 003e
247.215: <09>Lane 08 nibble 1 adjusted value (pre nibble): 003e
247.215: <09>Lane 08 nibble 1 adjusted value (post nibble): 0043
247.215: <09>original critical gross delay: 0
247.215: <09>new critical gross delay: 0
247.215: DIMM 1 RttNom: 3
247.215: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440046
247.215: DIMM 1 RttNom: 3
247.215: DIMM 1 RttWr: 1
247.215: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480288
247.215: DIMM 1 RttWr: 1
247.215: DIMM 1 RttNom: 3
247.215: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640046
247.215: DIMM 1 RttNom: 3
247.215: DIMM 1 RttWr: 1
247.215: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680288
247.215: DIMM 1 RttWr: 1
247.215: DIMM 0 RttNom: 3
247.215: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040046
247.216: DIMM 1 RttNom: 3
247.215: DIMM 0 RttWr: 1
247.215: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080288
247.216: DIMM 1 RttWr: 1
247.216: DIMM 0 RttNom: 3
247.216: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240046
247.216: DIMM 1 RttNom: 3
247.216: DIMM 0 RttWr: 1
247.216: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280288
247.216: DIMM 1 RttWr: 1
247.216: SetTargetFreq: Start
247.216: SetTargetFreq: Node 3: New frequency code: 000e
247.216: ChangeMemClk: Start
247.216: set_2t_configuration: Start
247.216: set_2t_configuration: Done
247.216: mct_BeforePlatformSpec: Start
247.216: mct_BeforePlatformSpec: Done
247.216: mct_PlatformSpec: Start
247.216: Programmed DCT 0 timing/termination pattern 00383a38 30222222
247.216: mct_PlatformSpec: Done
247.216: set_2t_configuration: Start
247.216: set_2t_configuration: Done
247.216: mct_BeforePlatformSpec: Start
247.216: mct_BeforePlatformSpec: Done
247.216: mct_PlatformSpec: Start
247.216: Programmed DCT 1 timing/termination pattern 00383a38 30222222
247.216: mct_PlatformSpec: Done
247.216: ChangeMemClk: Done
247.216: phyAssistedMemFnceTraining: Start
247.216: phyAssistedMemFnceTraining: training node 3 DCT 0
247.216: phyAssistedMemFnceTraining: done training node 3 DCT 0
247.216: phyAssistedMemFnceTraining: training node 3 DCT 1
247.217: phyAssistedMemFnceTraining: done training node 3 DCT 1
247.217: phyAssistedMemFnceTraining: Done
247.217: InitPhyCompensation: DCT 0: Start
247.217: Waiting for predriver calibration to be applied...done!
247.217: InitPhyCompensation: DCT 0: Done
247.217: phyAssistedMemFnceTraining: Start
247.217: phyAssistedMemFnceTraining: training node 3 DCT 0
247.217: phyAssistedMemFnceTraining: done training node 3 DCT 0
247.217: phyAssistedMemFnceTraining: training node 3 DCT 1
247.217: phyAssistedMemFnceTraining: done training node 3 DCT 1
247.217: phyAssistedMemFnceTraining: Done
247.217: InitPhyCompensation: DCT 1: Start
247.217: Waiting for predriver calibration to be applied...done!
247.217: InitPhyCompensation: DCT 1: Done
247.217: Preparing to send DCT 0 DIMM 0 RC10: 02 (F2xA8: 02000300)
247.217: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.217: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
247.217: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.217: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
247.217: Preparing to send DCT 0 DIMM 1 RC10: 02 (F2xA8: 02000c00)
247.218: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.218: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
247.217: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.217: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
247.218: Preparing to send DCT 1 DIMM 0 RC10: 02 (F2xA8: 02000300)
247.218: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.218: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
247.218: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.218: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
247.218: Preparing to send DCT 1 DIMM 1 RC10: 02 (F2xA8: 02000c00)
247.218: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.218: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
247.218: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.218: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
247.218: SetTargetFreq: Done
247.218: SPD2ndTiming: Start
247.218: SPD2ndTiming: Done
247.218: mct_BeforeDramInit_Prod_D: Start
247.218: mct_ProgramODT_D: Start
247.218: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
247.218: mct_ProgramODT_D: Done
247.218: mct_BeforeDramInit_Prod_D: Done
247.218: mct_DramInit_Sw_D: Start
247.218: DIMM 0 RttWr: 2
247.218: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.218: mct_SendMrsCmd: Start
247.218: mct_SendMrsCmd: Done
247.218: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
247.218: mct_SendMrsCmd: Start
247.218: mct_SendMrsCmd: Done
247.218: DIMM 0 RttNom: 5
247.218: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.218: mct_SendMrsCmd: Start
247.218: mct_SendMrsCmd: Done
247.218: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001b78
247.218: mct_SendMrsCmd: Start
247.218: mct_SendMrsCmd: Done
247.218: DIMM 0 RttWr: 2
247.218: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.218: mct_SendMrsCmd: Start
247.218: mct_SendMrsCmd: Done
247.218: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
247.218: mct_SendMrsCmd: Start
247.218: mct_SendMrsCmd: Done
247.219: DIMM 0 RttNom: 5
247.219: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.219: mct_SendMrsCmd: Start
247.219: mct_SendMrsCmd: Done
247.219: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201b78
247.219: mct_SendMrsCmd: Start
247.219: mct_SendMrsCmd: Done
247.219: DIMM 1 RttWr: 2
247.219: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.219: mct_SendMrsCmd: Start
247.219: mct_SendMrsCmd: Done
247.219: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
247.219: mct_SendMrsCmd: Start
247.219: mct_SendMrsCmd: Done
247.219: DIMM 1 RttNom: 5
247.219: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.219: mct_SendMrsCmd: Start
247.219: mct_SendMrsCmd: Done
247.219: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401b78
247.219: mct_SendMrsCmd: Start
247.219: mct_SendMrsCmd: Done
247.219: DIMM 1 RttWr: 2
247.219: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.219: mct_SendMrsCmd: Start
247.219: mct_SendMrsCmd: Done
247.219: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
247.219: mct_SendMrsCmd: Start
247.219: mct_SendMrsCmd: Done
247.219: DIMM 1 RttNom: 5
247.219: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.219: mct_SendMrsCmd: Start
247.219: mct_SendMrsCmd: Done
247.219: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601b78
247.219: mct_SendMrsCmd: Start
247.219: mct_SendMrsCmd: Done
247.219: mct_DramInit_Sw_D: Done
247.219: AgesaHwWlPhase1: training nibble 0
247.219: DIMM 0 RttNom: 5
247.219: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.219: DIMM 0 RttWr: 2
247.219: DIMM 0 RttWr: 2
247.219: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.219: DIMM 0 RttWr: 2
247.219: DIMM 0 RttNom: 5
247.219: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.219: DIMM 0 RttNom: 5
247.219: DIMM 0 RttWr: 2
247.219: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.219: DIMM 0 RttWr: 2
247.219: DIMM 1 RttNom: 5
247.219: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.219: DIMM 0 RttNom: 5
247.219: DIMM 1 RttWr: 2
247.219: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.220: DIMM 0 RttWr: 2
247.220: DIMM 1 RttNom: 5
247.220: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.220: DIMM 0 RttNom: 5
247.220: DIMM 1 RttWr: 2
247.220: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.220: DIMM 0 RttWr: 2
247.220: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.220: <09>Lane 00 scaled delay: 005f
247.220: <09>Lane 00 new seed: 005f
247.220: <09>Lane 01 scaled delay: 0059
247.220: <09>Lane 01 new seed: 0059
247.220: <09>Lane 02 scaled delay: 0055
247.220: <09>Lane 02 new seed: 0055
247.220: <09>Lane 03 scaled delay: 0052
247.220: <09>Lane 03 new seed: 0052
247.220: <09>Lane 04 scaled delay: 0050
247.220: <09>Lane 04 new seed: 0050
247.220: <09>Lane 05 scaled delay: 0054
247.220: <09>Lane 05 new seed: 0054
247.220: <09>Lane 06 scaled delay: 0059
247.220: <09>Lane 06 new seed: 0059
247.220: <09>Lane 07 scaled delay: 005d
247.220: <09>Lane 07 new seed: 005d
247.220: <09>Lane 08 scaled delay: 004e
247.220: <09>Lane 08 new seed: 004e
247.220: <09>Lane 00 nibble 0 raw readback: 005e
247.220: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005e
247.220: <09>Lane 00 nibble 0 adjusted value (post nibble): 005e
247.220: <09>Lane 01 nibble 0 raw readback: 0053
247.220: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0053
247.220: <09>Lane 01 nibble 0 adjusted value (post nibble): 0053
247.220: <09>Lane 02 nibble 0 raw readback: 004f
247.220: <09>Lane 02 nibble 0 adjusted value (pre nibble): 004f
247.220: <09>Lane 02 nibble 0 adjusted value (post nibble): 004f
247.220: <09>Lane 03 nibble 0 raw readback: 0051
247.220: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0051
247.220: <09>Lane 03 nibble 0 adjusted value (post nibble): 0051
247.220: <09>Lane 04 nibble 0 raw readback: 004d
247.220: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004d
247.220: <09>Lane 04 nibble 0 adjusted value (post nibble): 004d
247.220: <09>Lane 05 nibble 0 raw readback: 0053
247.220: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0053
247.220: <09>Lane 05 nibble 0 adjusted value (post nibble): 0053
247.220: <09>Lane 06 nibble 0 raw readback: 0055
247.220: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0055
247.220: <09>Lane 06 nibble 0 adjusted value (post nibble): 0055
247.220: <09>Lane 07 nibble 0 raw readback: 0059
247.220: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0059
247.220: <09>Lane 07 nibble 0 adjusted value (post nibble): 0059
247.220: <09>Lane 08 nibble 0 raw readback: 0047
247.220: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0047
247.220: <09>Lane 08 nibble 0 adjusted value (post nibble): 0047
247.220: AgesaHwWlPhase1: training nibble 1
247.220: DIMM 0 RttNom: 5
247.221: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.221: DIMM 0 RttWr: 2
247.221: DIMM 0 RttWr: 2
247.221: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.221: DIMM 0 RttWr: 2
247.221: DIMM 0 RttNom: 5
247.221: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.221: DIMM 0 RttNom: 5
247.221: DIMM 0 RttWr: 2
247.221: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.221: DIMM 0 RttWr: 2
247.221: DIMM 1 RttNom: 5
247.221: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.221: DIMM 0 RttNom: 5
247.221: DIMM 1 RttWr: 2
247.221: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.221: DIMM 0 RttWr: 2
247.221: DIMM 1 RttNom: 5
247.221: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.221: DIMM 0 RttNom: 5
247.221: DIMM 1 RttWr: 2
247.221: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.221: DIMM 0 RttWr: 2
247.221: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.221: <09>Lane 00 new seed: 005f
247.221: <09>Lane 01 new seed: 0059
247.221: <09>Lane 02 new seed: 0055
247.221: <09>Lane 03 new seed: 0052
247.221: <09>Lane 04 new seed: 0050
247.221: <09>Lane 05 new seed: 0054
247.221: <09>Lane 06 new seed: 0059
247.221: <09>Lane 07 new seed: 005d
247.221: <09>Lane 08 new seed: 004e
247.221: <09>Lane 00 nibble 1 raw readback: 0060
247.221: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0060
247.221: <09>Lane 00 nibble 1 adjusted value (post nibble): 005f
247.221: <09>Lane 01 nibble 1 raw readback: 0059
247.221: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0059
247.221: <09>Lane 01 nibble 1 adjusted value (post nibble): 0059
247.221: <09>Lane 02 nibble 1 raw readback: 0053
247.221: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0053
247.221: <09>Lane 02 nibble 1 adjusted value (post nibble): 0054
247.221: <09>Lane 03 nibble 1 raw readback: 004f
247.221: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004f
247.221: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
247.221: <09>Lane 04 nibble 1 raw readback: 004c
247.221: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004c
247.221: <09>Lane 04 nibble 1 adjusted value (post nibble): 004e
247.221: <09>Lane 05 nibble 1 raw readback: 0050
247.221: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0050
247.221: <09>Lane 05 nibble 1 adjusted value (post nibble): 0052
247.221: <09>Lane 06 nibble 1 raw readback: 0056
247.221: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0056
247.221: <09>Lane 06 nibble 1 adjusted value (post nibble): 0057
247.221: <09>Lane 07 nibble 1 raw readback: 005d
247.221: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005d
247.221: <09>Lane 07 nibble 1 adjusted value (post nibble): 005d
247.221: <09>Lane 08 nibble 1 raw readback: 0049
247.221: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0049
247.221: <09>Lane 08 nibble 1 adjusted value (post nibble): 004b
247.221: <09>original critical gross delay: 0
247.221: <09>new critical gross delay: 0
247.222: DIMM 0 RttNom: 5
247.222: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.222: DIMM 0 RttNom: 5
247.222: DIMM 0 RttWr: 2
247.222: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.222: DIMM 0 RttWr: 2
247.222: DIMM 0 RttNom: 5
247.222: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.222: DIMM 0 RttNom: 5
247.222: DIMM 0 RttWr: 2
247.222: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.222: DIMM 0 RttWr: 2
247.222: DIMM 1 RttNom: 5
247.222: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.222: DIMM 0 RttNom: 5
247.222: DIMM 1 RttWr: 2
247.222: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.222: DIMM 0 RttWr: 2
247.222: DIMM 1 RttNom: 5
247.222: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.222: DIMM 0 RttNom: 5
247.222: DIMM 1 RttWr: 2
247.222: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.222: DIMM 0 RttWr: 2
247.222: AgesaHwWlPhase1: training nibble 0
247.222: DIMM 1 RttNom: 5
247.222: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.222: DIMM 1 RttWr: 2
247.222: DIMM 1 RttWr: 2
247.222: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.222: DIMM 1 RttWr: 2
247.222: DIMM 1 RttNom: 5
247.222: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.222: DIMM 1 RttNom: 5
247.222: DIMM 1 RttWr: 2
247.222: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.222: DIMM 1 RttWr: 2
247.222: DIMM 0 RttNom: 5
247.222: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.222: DIMM 1 RttNom: 5
247.222: DIMM 0 RttWr: 2
247.222: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.222: DIMM 1 RttWr: 2
247.222: DIMM 0 RttNom: 5
247.222: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.222: DIMM 1 RttNom: 5
247.222: DIMM 0 RttWr: 2
247.222: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.222: DIMM 1 RttWr: 2
247.222: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.222: <09>Lane 00 scaled delay: 005c
247.222: <09>Lane 00 new seed: 005c
247.222: <09>Lane 01 scaled delay: 0057
247.222: <09>Lane 01 new seed: 0057
247.222: <09>Lane 02 scaled delay: 0053
247.222: <09>Lane 02 new seed: 0053
247.222: <09>Lane 03 scaled delay: 0050
247.222: <09>Lane 03 new seed: 0050
247.222: <09>Lane 04 scaled delay: 004e
247.222: <09>Lane 04 new seed: 004e
247.222: <09>Lane 05 scaled delay: 0052
247.222: <09>Lane 05 new seed: 0052
247.222: <09>Lane 06 scaled delay: 0053
247.222: <09>Lane 06 new seed: 0053
247.223: <09>Lane 07 scaled delay: 0058
247.223: <09>Lane 07 new seed: 0058
247.223: <09>Lane 08 scaled delay: 0049
247.223: <09>Lane 08 new seed: 0049
247.223: <09>Lane 00 nibble 0 raw readback: 005c
247.223: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005c
247.223: <09>Lane 00 nibble 0 adjusted value (post nibble): 005c
247.223: <09>Lane 01 nibble 0 raw readback: 0054
247.223: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0054
247.223: <09>Lane 01 nibble 0 adjusted value (post nibble): 0054
247.223: <09>Lane 02 nibble 0 raw readback: 004e
247.223: <09>Lane 02 nibble 0 adjusted value (pre nibble): 004e
247.223: <09>Lane 02 nibble 0 adjusted value (post nibble): 004e
247.223: <09>Lane 03 nibble 0 raw readback: 004e
247.223: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004e
247.223: <09>Lane 03 nibble 0 adjusted value (post nibble): 004e
247.223: <09>Lane 04 nibble 0 raw readback: 0049
247.223: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0049
247.223: <09>Lane 04 nibble 0 adjusted value (post nibble): 0049
247.223: <09>Lane 05 nibble 0 raw readback: 004f
247.223: <09>Lane 05 nibble 0 adjusted value (pre nibble): 004f
247.223: <09>Lane 05 nibble 0 adjusted value (post nibble): 004f
247.223: <09>Lane 06 nibble 0 raw readback: 004f
247.223: <09>Lane 06 nibble 0 adjusted value (pre nibble): 004f
247.223: <09>Lane 06 nibble 0 adjusted value (post nibble): 004f
247.223: <09>Lane 07 nibble 0 raw readback: 0058
247.223: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0058
247.223: <09>Lane 07 nibble 0 adjusted value (post nibble): 0058
247.223: <09>Lane 08 nibble 0 raw readback: 0045
247.223: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0045
247.223: <09>Lane 08 nibble 0 adjusted value (post nibble): 0045
247.223: AgesaHwWlPhase1: training nibble 1
247.223: DIMM 1 RttNom: 5
247.223: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.223: DIMM 1 RttWr: 2
247.223: DIMM 1 RttWr: 2
247.223: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.223: DIMM 1 RttWr: 2
247.223: DIMM 1 RttNom: 5
247.223: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.223: DIMM 1 RttNom: 5
247.223: DIMM 1 RttWr: 2
247.223: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.223: DIMM 1 RttWr: 2
247.223: DIMM 0 RttNom: 5
247.223: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.223: DIMM 1 RttNom: 5
247.223: DIMM 0 RttWr: 2
247.223: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.223: DIMM 1 RttWr: 2
247.223: DIMM 0 RttNom: 5
247.223: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.223: DIMM 1 RttNom: 5
247.223: DIMM 0 RttWr: 2
247.223: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.223: DIMM 1 RttWr: 2
247.223: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.223: <09>Lane 00 new seed: 005c
247.223: <09>Lane 01 new seed: 0057
247.223: <09>Lane 02 new seed: 0053
247.223: <09>Lane 03 new seed: 0050
247.223: <09>Lane 04 new seed: 004e
247.223: <09>Lane 05 new seed: 0052
247.223: <09>Lane 06 new seed: 0053
247.223: <09>Lane 07 new seed: 0058
247.223: <09>Lane 08 new seed: 0049
247.223: <09>Lane 00 nibble 1 raw readback: 005d
247.223: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005d
247.223: <09>Lane 00 nibble 1 adjusted value (post nibble): 005c
247.223: <09>Lane 01 nibble 1 raw readback: 0055
247.223: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0055
247.223: <09>Lane 01 nibble 1 adjusted value (post nibble): 0056
247.223: <09>Lane 02 nibble 1 raw readback: 0050
247.224: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0050
247.224: <09>Lane 02 nibble 1 adjusted value (post nibble): 0051
247.224: <09>Lane 03 nibble 1 raw readback: 004d
247.224: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004d
247.224: <09>Lane 03 nibble 1 adjusted value (post nibble): 004e
247.224: <09>Lane 04 nibble 1 raw readback: 0048
247.224: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0048
247.224: <09>Lane 04 nibble 1 adjusted value (post nibble): 004b
247.224: <09>Lane 05 nibble 1 raw readback: 004d
247.224: <09>Lane 05 nibble 1 adjusted value (pre nibble): 004d
247.224: <09>Lane 05 nibble 1 adjusted value (post nibble): 004f
247.224: <09>Lane 06 nibble 1 raw readback: 004f
247.224: <09>Lane 06 nibble 1 adjusted value (pre nibble): 004f
247.224: <09>Lane 06 nibble 1 adjusted value (post nibble): 0051
247.224: <09>Lane 07 nibble 1 raw readback: 0057
247.224: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0057
247.224: <09>Lane 07 nibble 1 adjusted value (post nibble): 0057
247.224: <09>Lane 08 nibble 1 raw readback: 0043
247.224: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0043
247.224: <09>Lane 08 nibble 1 adjusted value (post nibble): 0046
247.224: <09>original critical gross delay: 0
247.224: <09>new critical gross delay: 0
247.224: DIMM 1 RttNom: 5
247.224: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440206
247.224: DIMM 1 RttNom: 5
247.224: DIMM 1 RttWr: 2
247.224: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480490
247.224: DIMM 1 RttWr: 2
247.224: DIMM 1 RttNom: 5
247.224: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640206
247.224: DIMM 1 RttNom: 5
247.224: DIMM 1 RttWr: 2
247.224: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680490
247.224: DIMM 1 RttWr: 2
247.224: DIMM 0 RttNom: 5
247.224: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040206
247.224: DIMM 1 RttNom: 5
247.224: DIMM 0 RttWr: 2
247.224: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080490
247.224: DIMM 1 RttWr: 2
247.224: DIMM 0 RttNom: 5
247.224: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240206
247.224: DIMM 1 RttNom: 5
247.224: DIMM 0 RttWr: 2
247.224: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280490
247.224: DIMM 1 RttWr: 2
247.224: SPD2ndTiming: Start
247.225: SPD2ndTiming: Done
247.225: mct_BeforeDramInit_Prod_D: Start
247.225: mct_ProgramODT_D: Start
247.225: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
247.225: mct_ProgramODT_D: Done
247.225: mct_BeforeDramInit_Prod_D: Done
247.225: mct_DramInit_Sw_D: Start
247.225: DIMM 0 RttWr: 2
247.225: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.225: mct_SendMrsCmd: Start
247.225: mct_SendMrsCmd: Done
247.225: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
247.225: mct_SendMrsCmd: Start
247.225: mct_SendMrsCmd: Done
247.225: DIMM 0 RttNom: 5
247.225: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.225: mct_SendMrsCmd: Start
247.225: mct_SendMrsCmd: Done
247.225: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001b78
247.225: mct_SendMrsCmd: Start
247.225: mct_SendMrsCmd: Done
247.225: DIMM 0 RttWr: 2
247.225: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.225: mct_SendMrsCmd: Start
247.225: mct_SendMrsCmd: Done
247.225: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
247.225: mct_SendMrsCmd: Start
247.225: mct_SendMrsCmd: Done
247.225: DIMM 0 RttNom: 5
247.225: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.225: mct_SendMrsCmd: Start
247.225: mct_SendMrsCmd: Done
247.225: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201b78
247.225: mct_SendMrsCmd: Start
247.225: mct_SendMrsCmd: Done
247.225: DIMM 1 RttWr: 2
247.225: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.225: mct_SendMrsCmd: Start
247.225: mct_SendMrsCmd: Done
247.225: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
247.225: mct_SendMrsCmd: Start
247.225: mct_SendMrsCmd: Done
247.225: DIMM 1 RttNom: 5
247.225: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.225: mct_SendMrsCmd: Start
247.225: mct_SendMrsCmd: Done
247.225: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401b78
247.225: mct_SendMrsCmd: Start
247.225: mct_SendMrsCmd: Done
247.225: DIMM 1 RttWr: 2
247.225: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.225: mct_SendMrsCmd: Start
247.225: mct_SendMrsCmd: Done
247.225: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
247.226: mct_SendMrsCmd: Start
247.226: mct_SendMrsCmd: Done
247.226: DIMM 1 RttNom: 5
247.226: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.226: mct_SendMrsCmd: Start
247.226: mct_SendMrsCmd: Done
247.226: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601b78
247.226: mct_SendMrsCmd: Start
247.226: mct_SendMrsCmd: Done
247.226: mct_DramInit_Sw_D: Done
247.226: AgesaHwWlPhase1: training nibble 0
247.226: DIMM 0 RttNom: 5
247.226: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.226: DIMM 0 RttWr: 2
247.226: DIMM 0 RttWr: 2
247.226: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.226: DIMM 0 RttWr: 2
247.226: DIMM 0 RttNom: 5
247.226: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.226: DIMM 0 RttNom: 5
247.226: DIMM 0 RttWr: 2
247.226: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.226: DIMM 0 RttWr: 2
247.226: DIMM 1 RttNom: 5
247.226: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.226: DIMM 0 RttNom: 5
247.226: DIMM 1 RttWr: 2
247.226: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.226: DIMM 0 RttWr: 2
247.226: DIMM 1 RttNom: 5
247.226: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.226: DIMM 0 RttNom: 5
247.226: DIMM 1 RttWr: 2
247.226: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.226: DIMM 0 RttWr: 2
247.226: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.226: <09>Lane 00 scaled delay: 0061
247.226: <09>Lane 00 new seed: 0061
247.226: <09>Lane 01 scaled delay: 005c
247.226: <09>Lane 01 new seed: 005c
247.226: <09>Lane 02 scaled delay: 0057
247.226: <09>Lane 02 new seed: 0057
247.226: <09>Lane 03 scaled delay: 0052
247.226: <09>Lane 03 new seed: 0052
247.226: <09>Lane 04 scaled delay: 004f
247.226: <09>Lane 04 new seed: 004f
247.226: <09>Lane 05 scaled delay: 0055
247.226: <09>Lane 05 new seed: 0055
247.226: <09>Lane 06 scaled delay: 0059
247.226: <09>Lane 06 new seed: 0059
247.226: <09>Lane 07 scaled delay: 005e
247.226: <09>Lane 07 new seed: 005e
247.226: <09>Lane 08 scaled delay: 004e
247.226: <09>Lane 08 new seed: 004e
247.226: <09>Lane 00 nibble 0 raw readback: 0020
247.227: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0060
247.227: <09>Lane 00 nibble 0 adjusted value (post nibble): 0060
247.227: <09>Lane 01 nibble 0 raw readback: 0058
247.227: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0058
247.227: <09>Lane 01 nibble 0 adjusted value (post nibble): 0058
247.227: <09>Lane 02 nibble 0 raw readback: 0054
247.227: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0054
247.227: <09>Lane 02 nibble 0 adjusted value (post nibble): 0054
247.227: <09>Lane 03 nibble 0 raw readback: 004f
247.227: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004f
247.227: <09>Lane 03 nibble 0 adjusted value (post nibble): 004f
247.227: <09>Lane 04 nibble 0 raw readback: 004c
247.227: <09>Lane 04 nibble 0 adjusted value (pre nibble): 004c
247.227: <09>Lane 04 nibble 0 adjusted value (post nibble): 004c
247.227: <09>Lane 05 nibble 0 raw readback: 0054
247.227: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0054
247.227: <09>Lane 05 nibble 0 adjusted value (post nibble): 0054
247.227: <09>Lane 06 nibble 0 raw readback: 0059
247.227: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0059
247.227: <09>Lane 06 nibble 0 adjusted value (post nibble): 0059
247.227: <09>Lane 07 nibble 0 raw readback: 005f
247.227: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005f
247.227: <09>Lane 07 nibble 0 adjusted value (post nibble): 005f
247.227: <09>Lane 08 nibble 0 raw readback: 0049
247.227: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0049
247.227: <09>Lane 08 nibble 0 adjusted value (post nibble): 0049
247.227: AgesaHwWlPhase1: training nibble 1
247.227: DIMM 0 RttNom: 5
247.227: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.227: DIMM 0 RttWr: 2
247.227: DIMM 0 RttWr: 2
247.227: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.227: DIMM 0 RttWr: 2
247.227: DIMM 0 RttNom: 5
247.227: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.227: DIMM 0 RttNom: 5
247.227: DIMM 0 RttWr: 2
247.227: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.227: DIMM 0 RttWr: 2
247.227: DIMM 1 RttNom: 5
247.227: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.227: DIMM 0 RttNom: 5
247.227: DIMM 1 RttWr: 2
247.227: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.227: DIMM 0 RttWr: 2
247.227: DIMM 1 RttNom: 5
247.227: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.227: DIMM 0 RttNom: 5
247.227: DIMM 1 RttWr: 2
247.227: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.227: DIMM 0 RttWr: 2
247.227: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.227: <09>Lane 00 new seed: 0061
247.227: <09>Lane 01 new seed: 005c
247.227: <09>Lane 02 new seed: 0057
247.227: <09>Lane 03 new seed: 0052
247.227: <09>Lane 04 new seed: 004f
247.227: <09>Lane 05 new seed: 0055
247.227: <09>Lane 06 new seed: 0059
247.227: <09>Lane 07 new seed: 005e
247.227: <09>Lane 08 new seed: 004e
247.227: <09>Lane 00 nibble 1 raw readback: 0020
247.227: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0060
247.227: <09>Lane 00 nibble 1 adjusted value (post nibble): 0060
247.227: <09>Lane 01 nibble 1 raw readback: 005c
247.227: <09>Lane 01 nibble 1 adjusted value (pre nibble): 005c
247.228: <09>Lane 01 nibble 1 adjusted value (post nibble): 005c
247.228: <09>Lane 02 nibble 1 raw readback: 0056
247.228: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0056
247.228: <09>Lane 02 nibble 1 adjusted value (post nibble): 0056
247.228: <09>Lane 03 nibble 1 raw readback: 004f
247.228: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004f
247.228: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
247.228: <09>Lane 04 nibble 1 raw readback: 004b
247.228: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004b
247.228: <09>Lane 04 nibble 1 adjusted value (post nibble): 004d
247.228: <09>Lane 05 nibble 1 raw readback: 0052
247.228: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0052
247.228: <09>Lane 05 nibble 1 adjusted value (post nibble): 0053
247.228: <09>Lane 06 nibble 1 raw readback: 0059
247.228: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0059
247.228: <09>Lane 06 nibble 1 adjusted value (post nibble): 0059
247.228: <09>Lane 07 nibble 1 raw readback: 005f
247.228: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005f
247.228: <09>Lane 07 nibble 1 adjusted value (post nibble): 005e
247.228: <09>Lane 08 nibble 1 raw readback: 004a
247.228: <09>Lane 08 nibble 1 adjusted value (pre nibble): 004a
247.228: <09>Lane 08 nibble 1 adjusted value (post nibble): 004c
247.228: <09>original critical gross delay: 0
247.228: <09>new critical gross delay: 0
247.228: DIMM 0 RttNom: 5
247.228: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.228: DIMM 0 RttNom: 5
247.228: DIMM 0 RttWr: 2
247.228: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.228: DIMM 0 RttWr: 2
247.228: DIMM 0 RttNom: 5
247.228: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.228: DIMM 0 RttNom: 5
247.228: DIMM 0 RttWr: 2
247.228: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.228: DIMM 0 RttWr: 2
247.228: DIMM 1 RttNom: 5
247.228: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.228: DIMM 0 RttNom: 5
247.228: DIMM 1 RttWr: 2
247.228: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.228: DIMM 0 RttWr: 2
247.228: DIMM 1 RttNom: 5
247.228: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.228: DIMM 0 RttNom: 5
247.228: DIMM 1 RttWr: 2
247.228: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.228: DIMM 0 RttWr: 2
247.228: AgesaHwWlPhase1: training nibble 0
247.228: DIMM 1 RttNom: 5
247.228: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.228: DIMM 1 RttWr: 2
247.228: DIMM 1 RttWr: 2
247.228: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.228: DIMM 1 RttWr: 2
247.228: DIMM 1 RttNom: 5
247.228: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.228: DIMM 1 RttNom: 5
247.228: DIMM 1 RttWr: 2
247.228: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.228: DIMM 1 RttWr: 2
247.228: DIMM 0 RttNom: 5
247.229: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.229: DIMM 1 RttNom: 5
247.229: DIMM 0 RttWr: 2
247.229: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.229: DIMM 1 RttWr: 2
247.229: DIMM 0 RttNom: 5
247.229: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.229: DIMM 1 RttNom: 5
247.229: DIMM 0 RttWr: 2
247.229: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.229: DIMM 1 RttWr: 2
247.229: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.229: <09>Lane 00 scaled delay: 005f
247.229: <09>Lane 00 new seed: 005f
247.229: <09>Lane 01 scaled delay: 005c
247.229: <09>Lane 01 new seed: 005c
247.229: <09>Lane 02 scaled delay: 0054
247.229: <09>Lane 02 new seed: 0054
247.229: <09>Lane 03 scaled delay: 0052
247.229: <09>Lane 03 new seed: 0052
247.229: <09>Lane 04 scaled delay: 004e
247.229: <09>Lane 04 new seed: 004e
247.229: <09>Lane 05 scaled delay: 0054
247.229: <09>Lane 05 new seed: 0054
247.229: <09>Lane 06 scaled delay: 0059
247.229: <09>Lane 06 new seed: 0059
247.229: <09>Lane 07 scaled delay: 005d
247.229: <09>Lane 07 new seed: 005d
247.229: <09>Lane 08 scaled delay: 004b
247.229: <09>Lane 08 new seed: 004b
247.229: <09>Lane 00 nibble 0 raw readback: 005e
247.229: <09>Lane 00 nibble 0 adjusted value (pre nibble): 005e
247.229: <09>Lane 00 nibble 0 adjusted value (post nibble): 005e
247.229: <09>Lane 01 nibble 0 raw readback: 0058
247.229: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0058
247.229: <09>Lane 01 nibble 0 adjusted value (post nibble): 0058
247.229: <09>Lane 02 nibble 0 raw readback: 0051
247.229: <09>Lane 02 nibble 0 adjusted value (pre nibble): 0051
247.229: <09>Lane 02 nibble 0 adjusted value (post nibble): 0051
247.229: <09>Lane 03 nibble 0 raw readback: 004d
247.229: <09>Lane 03 nibble 0 adjusted value (pre nibble): 004d
247.229: <09>Lane 03 nibble 0 adjusted value (post nibble): 004d
247.229: <09>Lane 04 nibble 0 raw readback: 0049
247.229: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0049
247.229: <09>Lane 04 nibble 0 adjusted value (post nibble): 0049
247.229: <09>Lane 05 nibble 0 raw readback: 0052
247.229: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0052
247.229: <09>Lane 05 nibble 0 adjusted value (post nibble): 0052
247.229: <09>Lane 06 nibble 0 raw readback: 0058
247.229: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0058
247.229: <09>Lane 06 nibble 0 adjusted value (post nibble): 0058
247.229: <09>Lane 07 nibble 0 raw readback: 005d
247.229: <09>Lane 07 nibble 0 adjusted value (pre nibble): 005d
247.229: <09>Lane 07 nibble 0 adjusted value (post nibble): 005d
247.229: <09>Lane 08 nibble 0 raw readback: 0049
247.229: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0049
247.229: <09>Lane 08 nibble 0 adjusted value (post nibble): 0049
247.229: AgesaHwWlPhase1: training nibble 1
247.229: DIMM 1 RttNom: 5
247.229: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.229: DIMM 1 RttWr: 2
247.229: DIMM 1 RttWr: 2
247.229: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.229: DIMM 1 RttWr: 2
247.229: DIMM 1 RttNom: 5
247.229: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.229: DIMM 1 RttNom: 5
247.229: DIMM 1 RttWr: 2
247.229: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.229: DIMM 1 RttWr: 2
247.229: DIMM 0 RttNom: 5
247.229: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.230: DIMM 1 RttNom: 5
247.230: DIMM 0 RttWr: 2
247.230: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.230: DIMM 1 RttWr: 2
247.230: DIMM 0 RttNom: 5
247.230: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.230: DIMM 1 RttNom: 5
247.230: DIMM 0 RttWr: 2
247.230: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.230: DIMM 1 RttWr: 2
247.230: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.230: <09>Lane 00 new seed: 005f
247.230: <09>Lane 01 new seed: 005c
247.230: <09>Lane 02 new seed: 0054
247.230: <09>Lane 03 new seed: 0052
247.230: <09>Lane 04 new seed: 004e
247.230: <09>Lane 05 new seed: 0054
247.230: <09>Lane 06 new seed: 0059
247.230: <09>Lane 07 new seed: 005d
247.230: <09>Lane 08 new seed: 004b
247.230: <09>Lane 00 nibble 1 raw readback: 005f
247.230: <09>Lane 00 nibble 1 adjusted value (pre nibble): 005f
247.230: <09>Lane 00 nibble 1 adjusted value (post nibble): 005f
247.230: <09>Lane 01 nibble 1 raw readback: 005a
247.230: <09>Lane 01 nibble 1 adjusted value (pre nibble): 005a
247.230: <09>Lane 01 nibble 1 adjusted value (post nibble): 005b
247.230: <09>Lane 02 nibble 1 raw readback: 0051
247.230: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0051
247.230: <09>Lane 02 nibble 1 adjusted value (post nibble): 0052
247.230: <09>Lane 03 nibble 1 raw readback: 004f
247.230: <09>Lane 03 nibble 1 adjusted value (pre nibble): 004f
247.230: <09>Lane 03 nibble 1 adjusted value (post nibble): 0050
247.230: <09>Lane 04 nibble 1 raw readback: 004a
247.230: <09>Lane 04 nibble 1 adjusted value (pre nibble): 004a
247.230: <09>Lane 04 nibble 1 adjusted value (post nibble): 004c
247.230: <09>Lane 05 nibble 1 raw readback: 0050
247.230: <09>Lane 05 nibble 1 adjusted value (pre nibble): 0050
247.230: <09>Lane 05 nibble 1 adjusted value (post nibble): 0052
247.230: <09>Lane 06 nibble 1 raw readback: 0058
247.230: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0058
247.230: <09>Lane 06 nibble 1 adjusted value (post nibble): 0058
247.230: <09>Lane 07 nibble 1 raw readback: 005d
247.230: <09>Lane 07 nibble 1 adjusted value (pre nibble): 005d
247.230: <09>Lane 07 nibble 1 adjusted value (post nibble): 005d
247.230: <09>Lane 08 nibble 1 raw readback: 0047
247.230: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0047
247.230: <09>Lane 08 nibble 1 adjusted value (post nibble): 0049
247.230: <09>original critical gross delay: 0
247.230: <09>new critical gross delay: 0
247.230: DIMM 1 RttNom: 5
247.230: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440206
247.230: DIMM 1 RttNom: 5
247.230: DIMM 1 RttWr: 2
247.230: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480490
247.230: DIMM 1 RttWr: 2
247.230: DIMM 1 RttNom: 5
247.230: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640206
247.230: DIMM 1 RttNom: 5
247.230: DIMM 1 RttWr: 2
247.230: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680490
247.230: DIMM 1 RttWr: 2
247.230: DIMM 0 RttNom: 5
247.230: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040206
247.230: DIMM 1 RttNom: 5
247.231: DIMM 0 RttWr: 2
247.231: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080490
247.231: DIMM 1 RttWr: 2
247.231: DIMM 0 RttNom: 5
247.231: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240206
247.231: DIMM 1 RttNom: 5
247.231: DIMM 0 RttWr: 2
247.231: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280490
247.231: DIMM 1 RttWr: 2
247.231: SetTargetFreq: Start
247.231: SetTargetFreq: Node 3: New frequency code: 0012
247.231: ChangeMemClk: Start
247.231: set_2t_configuration: Start
247.231: set_2t_configuration: Done
247.231: mct_BeforePlatformSpec: Start
247.231: mct_BeforePlatformSpec: Done
247.231: mct_PlatformSpec: Start
247.231: Programmed DCT 0 timing/termination pattern 00353935 30222222
247.231: mct_PlatformSpec: Done
247.231: set_2t_configuration: Start
247.231: set_2t_configuration: Done
247.231: mct_BeforePlatformSpec: Start
247.231: mct_BeforePlatformSpec: Done
247.231: mct_PlatformSpec: Start
247.231: Programmed DCT 1 timing/termination pattern 00353935 30222222
247.231: mct_PlatformSpec: Done
247.231: ChangeMemClk: Done
247.231: phyAssistedMemFnceTraining: Start
247.231: phyAssistedMemFnceTraining: training node 3 DCT 0
247.231: phyAssistedMemFnceTraining: done training node 3 DCT 0
247.231: phyAssistedMemFnceTraining: training node 3 DCT 1
247.232: phyAssistedMemFnceTraining: done training node 3 DCT 1
247.232: phyAssistedMemFnceTraining: Done
247.232: InitPhyCompensation: DCT 0: Start
247.232: Waiting for predriver calibration to be applied...done!
247.232: InitPhyCompensation: DCT 0: Done
247.232: phyAssistedMemFnceTraining: Start
247.232: phyAssistedMemFnceTraining: training node 3 DCT 0
247.232: phyAssistedMemFnceTraining: done training node 3 DCT 0
247.232: phyAssistedMemFnceTraining: training node 3 DCT 1
247.232: phyAssistedMemFnceTraining: done training node 3 DCT 1
247.232: phyAssistedMemFnceTraining: Done
247.232: InitPhyCompensation: DCT 1: Start
247.232: Waiting for predriver calibration to be applied...done!
247.232: InitPhyCompensation: DCT 1: Done
247.232: Preparing to send DCT 0 DIMM 0 RC10: 03 (F2xA8: 02000300)
247.232: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.232: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC2: 04
247.232: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.232: mct_ControlRC: Preparing to send DCT 0 DIMM 0 RC8: 00
247.232: Preparing to send DCT 0 DIMM 1 RC10: 03 (F2xA8: 02000c00)
247.232: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.232: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC2: 04
247.232: fam15h_rdimm_rc2_ibt_code: DCT 0 IBT code: 1
247.232: mct_ControlRC: Preparing to send DCT 0 DIMM 1 RC8: 00
247.233: Preparing to send DCT 1 DIMM 0 RC10: 03 (F2xA8: 02000300)
247.233: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.233: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC2: 04
247.233: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.233: mct_ControlRC: Preparing to send DCT 1 DIMM 0 RC8: 00
247.233: Preparing to send DCT 1 DIMM 1 RC10: 03 (F2xA8: 02000c00)
247.233: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.233: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC2: 04
247.233: fam15h_rdimm_rc2_ibt_code: DCT 1 IBT code: 1
247.233: mct_ControlRC: Preparing to send DCT 1 DIMM 1 RC8: 00
247.233: SetTargetFreq: Done
247.233: SPD2ndTiming: Start
247.233: SPD2ndTiming: Done
247.233: mct_BeforeDramInit_Prod_D: Start
247.233: mct_ProgramODT_D: Start
247.233: Programmed DCT 0 ODT pattern 00000000 01010202 00000000 09030603
247.233: mct_ProgramODT_D: Done
247.233: mct_BeforeDramInit_Prod_D: Done
247.233: mct_DramInit_Sw_D: Start
247.233: DIMM 0 RttWr: 1
247.233: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.233: mct_SendMrsCmd: Start
247.233: mct_SendMrsCmd: Done
247.233: Going to send DCT 0 DIMM 0 rank 0 MR3 control word 000c0000
247.233: mct_SendMrsCmd: Start
247.233: mct_SendMrsCmd: Done
247.233: DIMM 0 RttNom: 4
247.233: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.233: mct_SendMrsCmd: Start
247.233: mct_SendMrsCmd: Done
247.233: Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00001d78
247.233: mct_SendMrsCmd: Start
247.233: mct_SendMrsCmd: Done
247.233: DIMM 0 RttWr: 1
247.233: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.233: mct_SendMrsCmd: Start
247.233: mct_SendMrsCmd: Done
247.233: Going to send DCT 0 DIMM 0 rank 1 MR3 control word 002c0000
247.233: mct_SendMrsCmd: Start
247.233: mct_SendMrsCmd: Done
247.234: DIMM 0 RttNom: 4
247.234: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.234: mct_SendMrsCmd: Start
247.234: mct_SendMrsCmd: Done
247.234: Going to send DCT 0 DIMM 0 rank 1 MR0 control word 00201d78
247.234: mct_SendMrsCmd: Start
247.234: mct_SendMrsCmd: Done
247.234: DIMM 1 RttWr: 1
247.234: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.234: mct_SendMrsCmd: Start
247.234: mct_SendMrsCmd: Done
247.234: Going to send DCT 0 DIMM 1 rank 0 MR3 control word 004c0000
247.234: mct_SendMrsCmd: Start
247.234: mct_SendMrsCmd: Done
247.234: DIMM 1 RttNom: 4
247.234: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.234: mct_SendMrsCmd: Start
247.234: mct_SendMrsCmd: Done
247.234: Going to send DCT 0 DIMM 1 rank 0 MR0 control word 00401d78
247.234: mct_SendMrsCmd: Start
247.234: mct_SendMrsCmd: Done
247.234: DIMM 1 RttWr: 1
247.234: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.234: mct_SendMrsCmd: Start
247.234: mct_SendMrsCmd: Done
247.234: Going to send DCT 0 DIMM 1 rank 1 MR3 control word 006c0000
247.234: mct_SendMrsCmd: Start
247.234: mct_SendMrsCmd: Done
247.234: DIMM 1 RttNom: 4
247.234: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.234: mct_SendMrsCmd: Start
247.234: mct_SendMrsCmd: Done
247.234: Going to send DCT 0 DIMM 1 rank 1 MR0 control word 00601d78
247.234: mct_SendMrsCmd: Start
247.234: mct_SendMrsCmd: Done
247.234: mct_DramInit_Sw_D: Done
247.234: AgesaHwWlPhase1: training nibble 0
247.234: DIMM 0 RttNom: 4
247.234: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.234: DIMM 0 RttWr: 1
247.234: DIMM 0 RttWr: 1
247.234: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.234: DIMM 0 RttWr: 1
247.234: DIMM 0 RttNom: 4
247.234: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.234: DIMM 0 RttNom: 4
247.234: DIMM 0 RttWr: 1
247.234: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.234: DIMM 0 RttWr: 1
247.234: DIMM 1 RttNom: 4
247.234: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.234: DIMM 0 RttNom: 4
247.235: DIMM 1 RttWr: 1
247.235: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.235: DIMM 0 RttWr: 1
247.235: DIMM 1 RttNom: 4
247.235: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.235: DIMM 0 RttNom: 4
247.235: DIMM 1 RttWr: 1
247.235: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.235: DIMM 0 RttWr: 1
247.235: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.235: <09>Lane 00 scaled delay: 006b
247.235: <09>Lane 00 new seed: 006b
247.235: <09>Lane 01 scaled delay: 0064
247.235: <09>Lane 01 new seed: 0064
247.235: <09>Lane 02 scaled delay: 005e
247.235: <09>Lane 02 new seed: 005e
247.235: <09>Lane 03 scaled delay: 0059
247.235: <09>Lane 03 new seed: 0059
247.235: <09>Lane 04 scaled delay: 0057
247.235: <09>Lane 04 new seed: 0057
247.235: <09>Lane 05 scaled delay: 005b
247.235: <09>Lane 05 new seed: 005b
247.235: <09>Lane 06 scaled delay: 0061
247.235: <09>Lane 06 new seed: 0061
247.235: <09>Lane 07 scaled delay: 0069
247.235: <09>Lane 07 new seed: 0069
247.235: <09>Lane 08 scaled delay: 0053
247.235: <09>Lane 08 new seed: 0053
247.235: <09>Lane 00 nibble 0 raw readback: 0030
247.235: <09>Lane 00 nibble 0 adjusted value (pre nibble): 0070
247.235: <09>Lane 00 nibble 0 adjusted value (post nibble): 0070
247.235: <09>Lane 01 nibble 0 raw readback: 0023
247.235: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0063
247.235: <09>Lane 01 nibble 0 adjusted value (post nibble): 0063
247.235: <09>Lane 02 nibble 0 raw readback: 005d
247.235: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005d
247.235: <09>Lane 02 nibble 0 adjusted value (post nibble): 005d
247.235: <09>Lane 03 nibble 0 raw readback: 005e
247.235: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005e
247.235: <09>Lane 03 nibble 0 adjusted value (post nibble): 005e
247.235: <09>Lane 04 nibble 0 raw readback: 005a
247.235: <09>Lane 04 nibble 0 adjusted value (pre nibble): 005a
247.235: <09>Lane 04 nibble 0 adjusted value (post nibble): 005a
247.235: <09>Lane 05 nibble 0 raw readback: 0061
247.235: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0061
247.235: <09>Lane 05 nibble 0 adjusted value (post nibble): 0061
247.235: <09>Lane 06 nibble 0 raw readback: 0025
247.235: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0065
247.235: <09>Lane 06 nibble 0 adjusted value (post nibble): 0065
247.235: <09>Lane 07 nibble 0 raw readback: 002a
247.235: <09>Lane 07 nibble 0 adjusted value (pre nibble): 006a
247.235: <09>Lane 07 nibble 0 adjusted value (post nibble): 006a
247.235: <09>Lane 08 nibble 0 raw readback: 0053
247.235: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0053
247.235: <09>Lane 08 nibble 0 adjusted value (post nibble): 0053
247.235: AgesaHwWlPhase1: training nibble 1
247.236: DIMM 0 RttNom: 4
247.236: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.236: DIMM 0 RttWr: 1
247.236: DIMM 0 RttWr: 1
247.236: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.236: DIMM 0 RttWr: 1
247.236: DIMM 0 RttNom: 4
247.236: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.236: DIMM 0 RttNom: 4
247.236: DIMM 0 RttWr: 1
247.236: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.236: DIMM 0 RttWr: 1
247.236: DIMM 1 RttNom: 4
247.236: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.236: DIMM 0 RttNom: 4
247.236: DIMM 1 RttWr: 1
247.236: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.236: DIMM 0 RttWr: 1
247.236: DIMM 1 RttNom: 4
247.236: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.236: DIMM 0 RttNom: 4
247.236: DIMM 1 RttWr: 1
247.236: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.236: DIMM 0 RttWr: 1
247.236: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 0 data
247.236: <09>Lane 00 new seed: 006b
247.236: <09>Lane 01 new seed: 0064
247.236: <09>Lane 02 new seed: 005e
247.236: <09>Lane 03 new seed: 0059
247.236: <09>Lane 04 new seed: 0057
247.236: <09>Lane 05 new seed: 005b
247.236: <09>Lane 06 new seed: 0061
247.236: <09>Lane 07 new seed: 0069
247.236: <09>Lane 08 new seed: 0053
247.236: <09>Lane 00 nibble 1 raw readback: 0033
247.236: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0073
247.236: <09>Lane 00 nibble 1 adjusted value (post nibble): 006f
247.236: <09>Lane 01 nibble 1 raw readback: 002a
247.236: <09>Lane 01 nibble 1 adjusted value (pre nibble): 006a
247.236: <09>Lane 01 nibble 1 adjusted value (post nibble): 0067
247.236: <09>Lane 02 nibble 1 raw readback: 0061
247.236: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0061
247.236: <09>Lane 02 nibble 1 adjusted value (post nibble): 005f
247.236: <09>Lane 03 nibble 1 raw readback: 005c
247.236: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005c
247.236: <09>Lane 03 nibble 1 adjusted value (post nibble): 005a
247.236: <09>Lane 04 nibble 1 raw readback: 0059
247.236: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0059
247.236: <09>Lane 04 nibble 1 adjusted value (post nibble): 0058
247.236: <09>Lane 05 nibble 1 raw readback: 005f
247.236: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005f
247.236: <09>Lane 05 nibble 1 adjusted value (post nibble): 005d
247.236: <09>Lane 06 nibble 1 raw readback: 0026
247.236: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0066
247.236: <09>Lane 06 nibble 1 adjusted value (post nibble): 0063
247.236: <09>Lane 07 nibble 1 raw readback: 002d
247.236: <09>Lane 07 nibble 1 adjusted value (pre nibble): 006d
247.236: <09>Lane 07 nibble 1 adjusted value (post nibble): 006b
247.236: <09>Lane 08 nibble 1 raw readback: 0055
247.236: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0055
247.236: <09>Lane 08 nibble 1 adjusted value (post nibble): 0054
247.236: <09>original critical gross delay: 0
247.236: <09>new critical gross delay: 0
247.237: DIMM 0 RttNom: 4
247.237: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.237: DIMM 0 RttNom: 4
247.237: DIMM 0 RttWr: 1
247.237: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.237: DIMM 0 RttWr: 1
247.237: DIMM 0 RttNom: 4
247.237: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.237: DIMM 0 RttNom: 4
247.237: DIMM 0 RttWr: 1
247.237: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.237: DIMM 0 RttWr: 1
247.237: DIMM 1 RttNom: 4
247.237: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.237: DIMM 0 RttNom: 4
247.237: DIMM 1 RttWr: 1
247.237: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.237: DIMM 0 RttWr: 1
247.237: DIMM 1 RttNom: 4
247.237: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.237: DIMM 0 RttNom: 4
247.237: DIMM 1 RttWr: 1
247.237: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.237: DIMM 0 RttWr: 1
247.237: AgesaHwWlPhase1: training nibble 0
247.237: DIMM 1 RttNom: 4
247.237: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.237: DIMM 1 RttWr: 1
247.237: DIMM 1 RttWr: 1
247.237: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.237: DIMM 1 RttWr: 1
247.237: DIMM 1 RttNom: 4
247.237: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.237: DIMM 1 RttNom: 4
247.237: DIMM 1 RttWr: 1
247.237: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.237: DIMM 1 RttWr: 1
247.237: DIMM 0 RttNom: 4
247.237: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.237: DIMM 1 RttNom: 4
247.237: DIMM 0 RttWr: 1
247.237: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.237: DIMM 1 RttWr: 1
247.237: DIMM 0 RttNom: 4
247.237: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.237: DIMM 1 RttNom: 4
247.237: DIMM 0 RttWr: 1
247.237: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.237: DIMM 1 RttWr: 1
247.237: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.237: <09>Lane 00 scaled delay: 0067
247.237: <09>Lane 00 new seed: 0067
247.237: <09>Lane 01 scaled delay: 0060
247.237: <09>Lane 01 new seed: 0060
247.237: <09>Lane 02 scaled delay: 005a
247.237: <09>Lane 02 new seed: 005a
247.237: <09>Lane 03 scaled delay: 0057
247.237: <09>Lane 03 new seed: 0057
247.237: <09>Lane 04 scaled delay: 0053
247.237: <09>Lane 04 new seed: 0053
247.237: <09>Lane 05 scaled delay: 0058
247.237: <09>Lane 05 new seed: 0058
247.238: <09>Lane 06 scaled delay: 005a
247.238: <09>Lane 06 new seed: 005a
247.238: <09>Lane 07 scaled delay: 0061
247.238: <09>Lane 07 new seed: 0061
247.238: <09>Lane 08 scaled delay: 004d
247.238: <09>Lane 08 new seed: 004d
247.238: <09>Lane 00 nibble 0 raw readback: 002e
247.238: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006e
247.238: <09>Lane 00 nibble 0 adjusted value (post nibble): 006e
247.238: <09>Lane 01 nibble 0 raw readback: 0024
247.238: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0064
247.238: <09>Lane 01 nibble 0 adjusted value (post nibble): 0064
247.238: <09>Lane 02 nibble 0 raw readback: 005d
247.238: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005d
247.238: <09>Lane 02 nibble 0 adjusted value (post nibble): 005d
247.238: <09>Lane 03 nibble 0 raw readback: 005b
247.238: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005b
247.238: <09>Lane 03 nibble 0 adjusted value (post nibble): 005b
247.238: <09>Lane 04 nibble 0 raw readback: 0056
247.238: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0056
247.238: <09>Lane 04 nibble 0 adjusted value (post nibble): 0056
247.238: <09>Lane 05 nibble 0 raw readback: 005d
247.238: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005d
247.238: <09>Lane 05 nibble 0 adjusted value (post nibble): 005d
247.238: <09>Lane 06 nibble 0 raw readback: 005f
247.238: <09>Lane 06 nibble 0 adjusted value (pre nibble): 005f
247.238: <09>Lane 06 nibble 0 adjusted value (post nibble): 005f
247.238: <09>Lane 07 nibble 0 raw readback: 0028
247.238: <09>Lane 07 nibble 0 adjusted value (pre nibble): 0068
247.238: <09>Lane 07 nibble 0 adjusted value (post nibble): 0068
247.238: <09>Lane 08 nibble 0 raw readback: 0051
247.238: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0051
247.238: <09>Lane 08 nibble 0 adjusted value (post nibble): 0051
247.238: AgesaHwWlPhase1: training nibble 1
247.238: DIMM 1 RttNom: 4
247.238: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.238: DIMM 1 RttWr: 1
247.238: DIMM 1 RttWr: 1
247.238: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.238: DIMM 1 RttWr: 1
247.238: DIMM 1 RttNom: 4
247.238: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.238: DIMM 1 RttNom: 4
247.238: DIMM 1 RttWr: 1
247.238: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.238: DIMM 1 RttWr: 1
247.238: DIMM 0 RttNom: 4
247.238: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.238: DIMM 1 RttNom: 4
247.238: DIMM 0 RttWr: 1
247.238: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.238: DIMM 1 RttWr: 1
247.238: DIMM 0 RttNom: 4
247.238: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.238: DIMM 1 RttNom: 4
247.238: DIMM 0 RttWr: 1
247.238: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.238: DIMM 1 RttWr: 1
247.238: Programmed DCT 0 write levelling ODT pattern 00000003 from DIMM 1 data
247.238: <09>Lane 00 new seed: 0067
247.238: <09>Lane 01 new seed: 0060
247.238: <09>Lane 02 new seed: 005a
247.238: <09>Lane 03 new seed: 0057
247.238: <09>Lane 04 new seed: 0053
247.238: <09>Lane 05 new seed: 0058
247.238: <09>Lane 06 new seed: 005a
247.238: <09>Lane 07 new seed: 0061
247.238: <09>Lane 08 new seed: 004d
247.238: <09>Lane 00 nibble 1 raw readback: 002e
247.238: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006e
247.239: <09>Lane 00 nibble 1 adjusted value (post nibble): 006a
247.239: <09>Lane 01 nibble 1 raw readback: 0026
247.239: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0066
247.239: <09>Lane 01 nibble 1 adjusted value (post nibble): 0063
247.239: <09>Lane 02 nibble 1 raw readback: 005e
247.239: <09>Lane 02 nibble 1 adjusted value (pre nibble): 005e
247.239: <09>Lane 02 nibble 1 adjusted value (post nibble): 005c
247.239: <09>Lane 03 nibble 1 raw readback: 005b
247.239: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005b
247.239: <09>Lane 03 nibble 1 adjusted value (post nibble): 0059
247.239: <09>Lane 04 nibble 1 raw readback: 0055
247.239: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0055
247.239: <09>Lane 04 nibble 1 adjusted value (post nibble): 0054
247.239: <09>Lane 05 nibble 1 raw readback: 005c
247.239: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005c
247.239: <09>Lane 05 nibble 1 adjusted value (post nibble): 005a
247.239: <09>Lane 06 nibble 1 raw readback: 005e
247.239: <09>Lane 06 nibble 1 adjusted value (pre nibble): 005e
247.239: <09>Lane 06 nibble 1 adjusted value (post nibble): 005c
247.239: <09>Lane 07 nibble 1 raw readback: 0028
247.239: <09>Lane 07 nibble 1 adjusted value (pre nibble): 0068
247.239: <09>Lane 07 nibble 1 adjusted value (post nibble): 0064
247.239: <09>Lane 08 nibble 1 raw readback: 0050
247.239: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0050
247.239: <09>Lane 08 nibble 1 adjusted value (post nibble): 004e
247.239: <09>original critical gross delay: 0
247.239: <09>new critical gross delay: 0
247.239: DIMM 1 RttNom: 4
247.239: Going to send DCT 0 DIMM 1 rank 0 MR1 control word 00440202
247.239: DIMM 1 RttNom: 4
247.239: DIMM 1 RttWr: 1
247.239: Going to send DCT 0 DIMM 1 rank 0 MR2 control word 00480298
247.239: DIMM 1 RttWr: 1
247.239: DIMM 1 RttNom: 4
247.239: Going to send DCT 0 DIMM 1 rank 1 MR1 control word 00640202
247.239: DIMM 1 RttNom: 4
247.239: DIMM 1 RttWr: 1
247.239: Going to send DCT 0 DIMM 1 rank 1 MR2 control word 00680298
247.239: DIMM 1 RttWr: 1
247.239: DIMM 0 RttNom: 4
247.239: Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00040202
247.239: DIMM 1 RttNom: 4
247.239: DIMM 0 RttWr: 1
247.239: Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00080298
247.239: DIMM 1 RttWr: 1
247.239: DIMM 0 RttNom: 4
247.239: Going to send DCT 0 DIMM 0 rank 1 MR1 control word 00240202
247.239: DIMM 1 RttNom: 4
247.239: DIMM 0 RttWr: 1
247.239: Going to send DCT 0 DIMM 0 rank 1 MR2 control word 00280298
247.239: DIMM 1 RttWr: 1
247.239: SPD2ndTiming: Start
247.240: SPD2ndTiming: Done
247.240: mct_BeforeDramInit_Prod_D: Start
247.240: mct_ProgramODT_D: Start
247.240: Programmed DCT 1 ODT pattern 00000000 01010202 00000000 09030603
247.240: mct_ProgramODT_D: Done
247.240: mct_BeforeDramInit_Prod_D: Done
247.240: mct_DramInit_Sw_D: Start
247.240: DIMM 0 RttWr: 1
247.240: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.240: mct_SendMrsCmd: Start
247.240: mct_SendMrsCmd: Done
247.240: Going to send DCT 1 DIMM 0 rank 0 MR3 control word 000c0000
247.240: mct_SendMrsCmd: Start
247.240: mct_SendMrsCmd: Done
247.240: DIMM 0 RttNom: 4
247.240: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.240: mct_SendMrsCmd: Start
247.240: mct_SendMrsCmd: Done
247.240: Going to send DCT 1 DIMM 0 rank 0 MR0 control word 00001d78
247.240: mct_SendMrsCmd: Start
247.240: mct_SendMrsCmd: Done
247.240: DIMM 0 RttWr: 1
247.240: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.240: mct_SendMrsCmd: Start
247.240: mct_SendMrsCmd: Done
247.240: Going to send DCT 1 DIMM 0 rank 1 MR3 control word 002c0000
247.240: mct_SendMrsCmd: Start
247.240: mct_SendMrsCmd: Done
247.240: DIMM 0 RttNom: 4
247.240: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.240: mct_SendMrsCmd: Start
247.240: mct_SendMrsCmd: Done
247.240: Going to send DCT 1 DIMM 0 rank 1 MR0 control word 00201d78
247.240: mct_SendMrsCmd: Start
247.240: mct_SendMrsCmd: Done
247.240: DIMM 1 RttWr: 1
247.240: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.240: mct_SendMrsCmd: Start
247.240: mct_SendMrsCmd: Done
247.240: Going to send DCT 1 DIMM 1 rank 0 MR3 control word 004c0000
247.240: mct_SendMrsCmd: Start
247.240: mct_SendMrsCmd: Done
247.240: DIMM 1 RttNom: 4
247.240: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.240: mct_SendMrsCmd: Start
247.240: mct_SendMrsCmd: Done
247.240: Going to send DCT 1 DIMM 1 rank 0 MR0 control word 00401d78
247.240: mct_SendMrsCmd: Start
247.240: mct_SendMrsCmd: Done
247.240: DIMM 1 RttWr: 1
247.240: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.240: mct_SendMrsCmd: Start
247.240: mct_SendMrsCmd: Done
247.240: Going to send DCT 1 DIMM 1 rank 1 MR3 control word 006c0000
247.240: mct_SendMrsCmd: Start
247.241: mct_SendMrsCmd: Done
247.241: DIMM 1 RttNom: 4
247.241: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.241: mct_SendMrsCmd: Start
247.241: mct_SendMrsCmd: Done
247.241: Going to send DCT 1 DIMM 1 rank 1 MR0 control word 00601d78
247.241: mct_SendMrsCmd: Start
247.241: mct_SendMrsCmd: Done
247.241: mct_DramInit_Sw_D: Done
247.241: AgesaHwWlPhase1: training nibble 0
247.241: DIMM 0 RttNom: 4
247.241: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.241: DIMM 0 RttWr: 1
247.241: DIMM 0 RttWr: 1
247.241: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.241: DIMM 0 RttWr: 1
247.241: DIMM 0 RttNom: 4
247.241: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.241: DIMM 0 RttNom: 4
247.241: DIMM 0 RttWr: 1
247.241: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.241: DIMM 0 RttWr: 1
247.241: DIMM 1 RttNom: 4
247.241: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.241: DIMM 0 RttNom: 4
247.241: DIMM 1 RttWr: 1
247.241: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.241: DIMM 0 RttWr: 1
247.241: DIMM 1 RttNom: 4
247.241: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.241: DIMM 0 RttNom: 4
247.241: DIMM 1 RttWr: 1
247.241: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.241: DIMM 0 RttWr: 1
247.241: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.241: <09>Lane 00 scaled delay: 006c
247.241: <09>Lane 00 new seed: 006c
247.241: <09>Lane 01 scaled delay: 0067
247.241: <09>Lane 01 new seed: 0067
247.241: <09>Lane 02 scaled delay: 0060
247.241: <09>Lane 02 new seed: 0060
247.241: <09>Lane 03 scaled delay: 0059
247.241: <09>Lane 03 new seed: 0059
247.241: <09>Lane 04 scaled delay: 0055
247.241: <09>Lane 04 new seed: 0055
247.241: <09>Lane 05 scaled delay: 005d
247.241: <09>Lane 05 new seed: 005d
247.241: <09>Lane 06 scaled delay: 0064
247.241: <09>Lane 06 new seed: 0064
247.241: <09>Lane 07 scaled delay: 006a
247.241: <09>Lane 07 new seed: 006a
247.241: <09>Lane 08 scaled delay: 0054
247.241: <09>Lane 08 new seed: 0054
247.242: <09>Lane 00 nibble 0 raw readback: 002f
247.242: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006f
247.242: <09>Lane 00 nibble 0 adjusted value (post nibble): 006f
247.242: <09>Lane 01 nibble 0 raw readback: 0027
247.242: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0067
247.242: <09>Lane 01 nibble 0 adjusted value (post nibble): 0067
247.242: <09>Lane 02 nibble 0 raw readback: 001f
247.242: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005f
247.242: <09>Lane 02 nibble 0 adjusted value (post nibble): 005f
247.242: <09>Lane 03 nibble 0 raw readback: 005a
247.242: <09>Lane 03 nibble 0 adjusted value (pre nibble): 005a
247.242: <09>Lane 03 nibble 0 adjusted value (post nibble): 005a
247.242: <09>Lane 04 nibble 0 raw readback: 0058
247.242: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0058
247.242: <09>Lane 04 nibble 0 adjusted value (post nibble): 0058
247.242: <09>Lane 05 nibble 0 raw readback: 0062
247.242: <09>Lane 05 nibble 0 adjusted value (pre nibble): 0062
247.242: <09>Lane 05 nibble 0 adjusted value (post nibble): 0062
247.242: <09>Lane 06 nibble 0 raw readback: 0026
247.242: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0066
247.242: <09>Lane 06 nibble 0 adjusted value (post nibble): 0066
247.242: <09>Lane 07 nibble 0 raw readback: 002e
247.242: <09>Lane 07 nibble 0 adjusted value (pre nibble): 006e
247.242: <09>Lane 07 nibble 0 adjusted value (post nibble): 006e
247.242: <09>Lane 08 nibble 0 raw readback: 0054
247.242: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0054
247.242: <09>Lane 08 nibble 0 adjusted value (post nibble): 0054
247.242: AgesaHwWlPhase1: training nibble 1
247.242: DIMM 0 RttNom: 4
247.242: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.242: DIMM 0 RttWr: 1
247.242: DIMM 0 RttWr: 1
247.242: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.242: DIMM 0 RttWr: 1
247.242: DIMM 0 RttNom: 4
247.242: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.242: DIMM 0 RttNom: 4
247.242: DIMM 0 RttWr: 1
247.242: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.242: DIMM 0 RttWr: 1
247.242: DIMM 1 RttNom: 4
247.242: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.242: DIMM 0 RttNom: 4
247.242: DIMM 1 RttWr: 1
247.242: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.242: DIMM 0 RttWr: 1
247.242: DIMM 1 RttNom: 4
247.242: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.242: DIMM 0 RttNom: 4
247.242: DIMM 1 RttWr: 1
247.242: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.242: DIMM 0 RttWr: 1
247.242: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 0 data
247.242: <09>Lane 00 new seed: 006c
247.242: <09>Lane 01 new seed: 0067
247.242: <09>Lane 02 new seed: 0060
247.242: <09>Lane 03 new seed: 0059
247.242: <09>Lane 04 new seed: 0055
247.242: <09>Lane 05 new seed: 005d
247.242: <09>Lane 06 new seed: 0064
247.242: <09>Lane 07 new seed: 006a
247.242: <09>Lane 08 new seed: 0054
247.242: <09>Lane 00 nibble 1 raw readback: 0030
247.243: <09>Lane 00 nibble 1 adjusted value (pre nibble): 0070
247.243: <09>Lane 00 nibble 1 adjusted value (post nibble): 006e
247.243: <09>Lane 01 nibble 1 raw readback: 002a
247.243: <09>Lane 01 nibble 1 adjusted value (pre nibble): 006a
247.243: <09>Lane 01 nibble 1 adjusted value (post nibble): 0068
247.243: <09>Lane 02 nibble 1 raw readback: 0021
247.243: <09>Lane 02 nibble 1 adjusted value (pre nibble): 0061
247.243: <09>Lane 02 nibble 1 adjusted value (post nibble): 0060
247.243: <09>Lane 03 nibble 1 raw readback: 005b
247.243: <09>Lane 03 nibble 1 adjusted value (pre nibble): 005b
247.243: <09>Lane 03 nibble 1 adjusted value (post nibble): 005a
247.243: <09>Lane 04 nibble 1 raw readback: 0056
247.243: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0056
247.243: <09>Lane 04 nibble 1 adjusted value (post nibble): 0055
247.243: <09>Lane 05 nibble 1 raw readback: 005f
247.243: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005f
247.243: <09>Lane 05 nibble 1 adjusted value (post nibble): 005e
247.243: <09>Lane 06 nibble 1 raw readback: 0026
247.243: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0066
247.243: <09>Lane 06 nibble 1 adjusted value (post nibble): 0065
247.243: <09>Lane 07 nibble 1 raw readback: 002d
247.243: <09>Lane 07 nibble 1 adjusted value (pre nibble): 006d
247.243: <09>Lane 07 nibble 1 adjusted value (post nibble): 006b
247.243: <09>Lane 08 nibble 1 raw readback: 0055
247.243: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0055
247.243: <09>Lane 08 nibble 1 adjusted value (post nibble): 0054
247.243: <09>original critical gross delay: 0
247.243: <09>new critical gross delay: 0
247.243: DIMM 0 RttNom: 4
247.243: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.243: DIMM 0 RttNom: 4
247.243: DIMM 0 RttWr: 1
247.243: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.243: DIMM 0 RttWr: 1
247.243: DIMM 0 RttNom: 4
247.243: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.243: DIMM 0 RttNom: 4
247.243: DIMM 0 RttWr: 1
247.243: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.243: DIMM 0 RttWr: 1
247.243: DIMM 1 RttNom: 4
247.243: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.243: DIMM 0 RttNom: 4
247.243: DIMM 1 RttWr: 1
247.243: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.243: DIMM 0 RttWr: 1
247.243: DIMM 1 RttNom: 4
247.243: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.243: DIMM 0 RttNom: 4
247.243: DIMM 1 RttWr: 1
247.243: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.243: DIMM 0 RttWr: 1
247.243: AgesaHwWlPhase1: training nibble 0
247.243: DIMM 1 RttNom: 4
247.243: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.243: DIMM 1 RttWr: 1
247.243: DIMM 1 RttWr: 1
247.243: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.243: DIMM 1 RttWr: 1
247.243: DIMM 1 RttNom: 4
247.243: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.243: DIMM 1 RttNom: 4
247.243: DIMM 1 RttWr: 1
247.243: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.244: DIMM 1 RttWr: 1
247.244: DIMM 0 RttNom: 4
247.244: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.244: DIMM 1 RttNom: 4
247.244: DIMM 0 RttWr: 1
247.244: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.244: DIMM 1 RttWr: 1
247.244: DIMM 0 RttNom: 4
247.244: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.244: DIMM 1 RttNom: 4
247.244: DIMM 0 RttWr: 1
247.244: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.244: DIMM 1 RttWr: 1
247.244: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.244: <09>Lane 00 scaled delay: 006b
247.244: <09>Lane 00 new seed: 006b
247.244: <09>Lane 01 scaled delay: 0066
247.244: <09>Lane 01 new seed: 0066
247.244: <09>Lane 02 scaled delay: 005b
247.244: <09>Lane 02 new seed: 005b
247.244: <09>Lane 03 scaled delay: 0059
247.244: <09>Lane 03 new seed: 0059
247.244: <09>Lane 04 scaled delay: 0054
247.244: <09>Lane 04 new seed: 0054
247.244: <09>Lane 05 scaled delay: 005b
247.244: <09>Lane 05 new seed: 005b
247.244: <09>Lane 06 scaled delay: 0063
247.244: <09>Lane 06 new seed: 0063
247.244: <09>Lane 07 scaled delay: 0069
247.244: <09>Lane 07 new seed: 0069
247.244: <09>Lane 08 scaled delay: 0051
247.244: <09>Lane 08 new seed: 0051
247.244: <09>Lane 00 nibble 0 raw readback: 002d
247.244: <09>Lane 00 nibble 0 adjusted value (pre nibble): 006d
247.244: <09>Lane 00 nibble 0 adjusted value (post nibble): 006d
247.244: <09>Lane 01 nibble 0 raw readback: 0025
247.244: <09>Lane 01 nibble 0 adjusted value (pre nibble): 0065
247.244: <09>Lane 01 nibble 0 adjusted value (post nibble): 0065
247.244: <09>Lane 02 nibble 0 raw readback: 005b
247.244: <09>Lane 02 nibble 0 adjusted value (pre nibble): 005b
247.244: <09>Lane 02 nibble 0 adjusted value (post nibble): 005b
247.244: <09>Lane 03 nibble 0 raw readback: 0057
247.244: <09>Lane 03 nibble 0 adjusted value (pre nibble): 0057
247.244: <09>Lane 03 nibble 0 adjusted value (post nibble): 0057
247.244: <09>Lane 04 nibble 0 raw readback: 0053
247.244: <09>Lane 04 nibble 0 adjusted value (pre nibble): 0053
247.244: <09>Lane 04 nibble 0 adjusted value (post nibble): 0053
247.244: <09>Lane 05 nibble 0 raw readback: 005e
247.244: <09>Lane 05 nibble 0 adjusted value (pre nibble): 005e
247.244: <09>Lane 05 nibble 0 adjusted value (post nibble): 005e
247.244: <09>Lane 06 nibble 0 raw readback: 0025
247.244: <09>Lane 06 nibble 0 adjusted value (pre nibble): 0065
247.244: <09>Lane 06 nibble 0 adjusted value (post nibble): 0065
247.244: <09>Lane 07 nibble 0 raw readback: 002b
247.244: <09>Lane 07 nibble 0 adjusted value (pre nibble): 006b
247.244: <09>Lane 07 nibble 0 adjusted value (post nibble): 006b
247.244: <09>Lane 08 nibble 0 raw readback: 0053
247.244: <09>Lane 08 nibble 0 adjusted value (pre nibble): 0053
247.244: <09>Lane 08 nibble 0 adjusted value (post nibble): 0053
247.244: AgesaHwWlPhase1: training nibble 1
247.244: DIMM 1 RttNom: 4
247.244: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.244: DIMM 1 RttWr: 1
247.244: DIMM 1 RttWr: 1
247.244: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.244: DIMM 1 RttWr: 1
247.244: DIMM 1 RttNom: 4
247.244: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.244: DIMM 1 RttNom: 4
247.244: DIMM 1 RttWr: 1
247.245: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.244: DIMM 1 RttWr: 1
247.245: DIMM 0 RttNom: 4
247.245: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.245: DIMM 1 RttNom: 4
247.245: DIMM 0 RttWr: 1
247.245: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.245: DIMM 1 RttWr: 1
247.245: DIMM 0 RttNom: 4
247.245: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.245: DIMM 1 RttNom: 4
247.245: DIMM 0 RttWr: 1
247.245: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.245: DIMM 1 RttWr: 1
247.245: Programmed DCT 1 write levelling ODT pattern 00000003 from DIMM 1 data
247.245: <09>Lane 00 new seed: 006b
247.245: <09>Lane 01 new seed: 0066
247.245: <09>Lane 02 new seed: 005b
247.245: <09>Lane 03 new seed: 0059
247.245: <09>Lane 04 new seed: 0054
247.245: <09>Lane 05 new seed: 005b
247.245: <09>Lane 06 new seed: 0063
247.245: <09>Lane 07 new seed: 0069
247.245: <09>Lane 08 new seed: 0051
247.245: <09>Lane 00 nibble 1 raw readback: 002e
247.245: <09>Lane 00 nibble 1 adjusted value (pre nibble): 006e
247.245: <09>Lane 00 nibble 1 adjusted value (post nibble): 006c
247.245: <09>Lane 01 nibble 1 raw readback: 0028
247.245: <09>Lane 01 nibble 1 adjusted value (pre nibble): 0068
247.245: <09>Lane 01 nibble 1 adjusted value (post nibble): 0067
247.245: <09>Lane 02 nibble 1 raw readback: 005c
247.245: <09>Lane 02 nibble 1 adjusted value (pre nibble): 005c
247.245: <09>Lane 02 nibble 1 adjusted value (post nibble): 005b
247.245: <09>Lane 03 nibble 1 raw readback: 0059
247.245: <09>Lane 03 nibble 1 adjusted value (pre nibble): 0059
247.245: <09>Lane 03 nibble 1 adjusted value (post nibble): 0059
247.245: <09>Lane 04 nibble 1 raw readback: 0054
247.245: <09>Lane 04 nibble 1 adjusted value (pre nibble): 0054
247.245: <09>Lane 04 nibble 1 adjusted value (post nibble): 0054
247.245: <09>Lane 05 nibble 1 raw readback: 005d
247.245: <09>Lane 05 nibble 1 adjusted value (pre nibble): 005d
247.245: <09>Lane 05 nibble 1 adjusted value (post nibble): 005c
247.245: <09>Lane 06 nibble 1 raw readback: 0025
247.245: <09>Lane 06 nibble 1 adjusted value (pre nibble): 0065
247.245: <09>Lane 06 nibble 1 adjusted value (post nibble): 0064
247.245: <09>Lane 07 nibble 1 raw readback: 002b
247.245: <09>Lane 07 nibble 1 adjusted value (pre nibble): 006b
247.245: <09>Lane 07 nibble 1 adjusted value (post nibble): 006a
247.245: <09>Lane 08 nibble 1 raw readback: 0050
247.245: <09>Lane 08 nibble 1 adjusted value (pre nibble): 0050
247.245: <09>Lane 08 nibble 1 adjusted value (post nibble): 0050
247.245: <09>original critical gross delay: 0
247.245: <09>new critical gross delay: 0
247.245: DIMM 1 RttNom: 4
247.245: Going to send DCT 1 DIMM 1 rank 0 MR1 control word 00440202
247.245: DIMM 1 RttNom: 4
247.245: DIMM 1 RttWr: 1
247.245: Going to send DCT 1 DIMM 1 rank 0 MR2 control word 00480298
247.245: DIMM 1 RttWr: 1
247.245: DIMM 1 RttNom: 4
247.245: Going to send DCT 1 DIMM 1 rank 1 MR1 control word 00640202
247.245: DIMM 1 RttNom: 4
247.245: DIMM 1 RttWr: 1
247.245: Going to send DCT 1 DIMM 1 rank 1 MR2 control word 00680298
247.245: DIMM 1 RttWr: 1
247.245: DIMM 0 RttNom: 4
247.245: Going to send DCT 1 DIMM 0 rank 0 MR1 control word 00040202
247.245: DIMM 1 RttNom: 4
247.246: DIMM 0 RttWr: 1
247.246: Going to send DCT 1 DIMM 0 rank 0 MR2 control word 00080298
247.246: DIMM 1 RttWr: 1
247.246: DIMM 0 RttNom: 4
247.246: Going to send DCT 1 DIMM 0 rank 1 MR1 control word 00240202
247.246: DIMM 1 RttNom: 4
247.246: DIMM 0 RttWr: 1
247.246: Going to send DCT 1 DIMM 0 rank 1 MR2 control word 00280298
247.246: DIMM 1 RttWr: 1
247.247: fam15_receiver_enable_training_seed: using seed: 0054
247.247: fam15_receiver_enable_training_seed: using seed: 0054
247.247: fam15_receiver_enable_training_seed: using seed: 0054
247.247: fam15_receiver_enable_training_seed: using seed: 0054
247.247: fam15_receiver_enable_training_seed: using seed: 0054
247.247: fam15_receiver_enable_training_seed: using seed: 0054
247.247: fam15_receiver_enable_training_seed: using seed: 0054
247.247: fam15_receiver_enable_training_seed: using seed: 0054
247.247: fam15_receiver_enable_training_seed: using seed: 004d
247.247: fam15_receiver_enable_training_seed: using seed: 004d
247.247: fam15_receiver_enable_training_seed: using seed: 004d
247.247: fam15_receiver_enable_training_seed: using seed: 004d
247.247: fam15_receiver_enable_training_seed: using seed: 004d
247.247: fam15_receiver_enable_training_seed: using seed: 004d
247.248: fam15_receiver_enable_training_seed: using seed: 004d
247.248: fam15_receiver_enable_training_seed: using seed: 004d
247.248: TrainRcvrEn: Status 2205
247.248: TrainRcvrEn: ErrStatus 0
247.248: TrainRcvrEn: ErrCode 0
247.248: TrainRcvrEn: Done
247.248: 
247.248: fam15_receiver_enable_training_seed: using seed: 0045
247.248: fam15_receiver_enable_training_seed: using seed: 0045
247.248: fam15_receiver_enable_training_seed: using seed: 0045
247.248: fam15_receiver_enable_training_seed: using seed: 0045
247.248: fam15_receiver_enable_training_seed: using seed: 0045
247.248: fam15_receiver_enable_training_seed: using seed: 0045
247.249: fam15_receiver_enable_training_seed: using seed: 0045
247.249: fam15_receiver_enable_training_seed: using seed: 0045
247.249: fam15_receiver_enable_training_seed: using seed: 0040
247.249: fam15_receiver_enable_training_seed: using seed: 0040
247.249: fam15_receiver_enable_training_seed: using seed: 0040
247.249: fam15_receiver_enable_training_seed: using seed: 0040
247.249: fam15_receiver_enable_training_seed: using seed: 0040
247.249: fam15_receiver_enable_training_seed: using seed: 0040
247.249: fam15_receiver_enable_training_seed: using seed: 0040
247.249: fam15_receiver_enable_training_seed: using seed: 0040
247.249: TrainRcvrEn: Status 2005
247.250: TrainRcvrEn: ErrStatus 0
247.250: TrainRcvrEn: ErrCode 0
247.250: TrainRcvrEn: Done
247.250: 
247.250: fam15_receiver_enable_training_seed: using seed: 0054
247.250: fam15_receiver_enable_training_seed: using seed: 0054
247.250: fam15_receiver_enable_training_seed: using seed: 0054
247.250: fam15_receiver_enable_training_seed: using seed: 0054
247.250: fam15_receiver_enable_training_seed: using seed: 0054
247.250: fam15_receiver_enable_training_seed: using seed: 0054
247.250: fam15_receiver_enable_training_seed: using seed: 0054
247.250: fam15_receiver_enable_training_seed: using seed: 0054
247.250: fam15_receiver_enable_training_seed: using seed: 004d
247.250: fam15_receiver_enable_training_seed: using seed: 004d
247.251: fam15_receiver_enable_training_seed: using seed: 004d
247.251: fam15_receiver_enable_training_seed: using seed: 004d
247.251: fam15_receiver_enable_training_seed: using seed: 004d
247.251: fam15_receiver_enable_training_seed: using seed: 004d
247.251: fam15_receiver_enable_training_seed: using seed: 004d
247.251: fam15_receiver_enable_training_seed: using seed: 004d
247.251: TrainRcvrEn: Status 2005
247.251: TrainRcvrEn: ErrStatus 0
247.251: TrainRcvrEn: ErrCode 0
247.251: TrainRcvrEn: Done
247.251: 
247.251: fam15_receiver_enable_training_seed: using seed: 0045
247.251: fam15_receiver_enable_training_seed: using seed: 0045
247.252: fam15_receiver_enable_training_seed: using seed: 0045
247.252: fam15_receiver_enable_training_seed: using seed: 0045
247.252: fam15_receiver_enable_training_seed: using seed: 0045
247.252: fam15_receiver_enable_training_seed: using seed: 0045
247.252: fam15_receiver_enable_training_seed: using seed: 0045
247.252: fam15_receiver_enable_training_seed: using seed: 0045
247.252: fam15_receiver_enable_training_seed: using seed: 0040
247.252: fam15_receiver_enable_training_seed: using seed: 0040
247.252: fam15_receiver_enable_training_seed: using seed: 0040
247.252: fam15_receiver_enable_training_seed: using seed: 0040
247.252: fam15_receiver_enable_training_seed: using seed: 0040
247.253: fam15_receiver_enable_training_seed: using seed: 0040
247.253: fam15_receiver_enable_training_seed: using seed: 0040
247.253: fam15_receiver_enable_training_seed: using seed: 0040
247.253: TrainRcvrEn: Status 2005
247.253: TrainRcvrEn: ErrStatus 0
247.253: TrainRcvrEn: ErrCode 0
247.253: TrainRcvrEn: Done
247.253: 
257.287: TrainDQSReceiverEnCyc: Status 2205
257.286: TrainDQSReceiverEnCyc: TrainErrors 4000
257.287: TrainDQSReceiverEnCyc: ErrStatus 4000
257.287: TrainDQSReceiverEnCyc: ErrCode 0
257.287: TrainDQSReceiverEnCyc: Done
257.287: 
268.920: TrainDQSReceiverEnCyc: Status 2005
268.920: TrainDQSReceiverEnCyc: TrainErrors 4000
268.920: TrainDQSReceiverEnCyc: ErrStatus 4000
268.920: TrainDQSReceiverEnCyc: ErrCode 0
268.920: TrainDQSReceiverEnCyc: Done
268.920: 
282.320: TrainDQSReceiverEnCyc: Status 2005
282.320: TrainDQSReceiverEnCyc: TrainErrors 4000
282.320: TrainDQSReceiverEnCyc: ErrStatus 4000
282.320: TrainDQSReceiverEnCyc: ErrCode 0
282.320: TrainDQSReceiverEnCyc: Done
282.320: 
293.934: TrainDQSReceiverEnCyc: Status 2005
293.934: TrainDQSReceiverEnCyc: TrainErrors 4000
293.934: TrainDQSReceiverEnCyc: ErrStatus 4000
293.934: TrainDQSReceiverEnCyc: ErrCode 0
293.934: TrainDQSReceiverEnCyc: Done
293.934: 
293.935: TrainMaxRdLatency: Status 2205
293.935: TrainMaxRdLatency: ErrStatus 4000
293.935: TrainMaxRdLatency: ErrCode 0
293.935: TrainMaxRdLatency: Done
293.935: 
293.936: TrainMaxRdLatency: Status 2005
293.936: TrainMaxRdLatency: ErrStatus 4000
293.936: TrainMaxRdLatency: ErrCode 0
293.936: TrainMaxRdLatency: Done
293.936: 
293.937: TrainMaxRdLatency: Status 2005
293.937: TrainMaxRdLatency: ErrStatus 4000
293.937: TrainMaxRdLatency: ErrCode 0
293.937: TrainMaxRdLatency: Done
293.937: 
293.937: TrainMaxRdLatency: Status 2005
293.937: TrainMaxRdLatency: ErrStatus 4000
293.937: TrainMaxRdLatency: ErrCode 0
293.937: TrainMaxRdLatency: Done
293.937: 
293.938: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
293.938: CBFS: Locating 'cmos_layout.bin'
293.939: CBFS: Found @ offset 2b0c0 size e88
293.940: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
293.940: CBFS: Locating 'cmos_layout.bin'
293.940: CBFS: Found @ offset 2b0c0 size e88
293.940: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
293.940: CBFS: Locating 'cmos_layout.bin'
293.940: CBFS: Found @ offset 2b0c0 size e88
293.941: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
293.941: CBFS: Locating 'cmos_layout.bin'
293.941: CBFS: Found @ offset 2b0c0 size e88
293.941: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
293.941: CBFS: Locating 'cmos_layout.bin'
293.941: CBFS: Found @ offset 2b0c0 size e88
293.941: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
293.941: CBFS: Locating 'cmos_layout.bin'
293.941: CBFS: Found @ offset 2b0c0 size e88
293.942: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
293.942: CBFS: Locating 'cmos_layout.bin'
293.942: CBFS: Found @ offset 2b0c0 size e88
293.942: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
293.942: CBFS: Locating 'cmos_layout.bin'
293.942: CBFS: Found @ offset 2b0c0 size e88
293.942: mctAutoInitMCT_D: :OtherTiming
293.943: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
293.943: CBFS: Locating 'cmos_layout.bin'
293.943: CBFS: Found @ offset 2b0c0 size e88
293.944: InterleaveNodes_D: Status 2205
293.944: InterleaveNodes_D: ErrStatus 4000
293.944: InterleaveNodes_D: ErrCode 0
293.944: InterleaveNodes_D: Done
293.944: 
293.944: InterleaveChannels_D: Node 0
293.944: InterleaveChannels_D: Status 2205
293.944: InterleaveChannels_D: ErrStatus 4000
293.944: InterleaveChannels_D: ErrCode 0
293.944: InterleaveChannels_D: Node 1
293.944: InterleaveChannels_D: Status 2005
293.944: InterleaveChannels_D: ErrStatus 4000
293.944: InterleaveChannels_D: ErrCode 0
293.944: InterleaveChannels_D: Node 2
293.944: InterleaveChannels_D: Status 2005
293.944: InterleaveChannels_D: ErrStatus 4000
293.944: InterleaveChannels_D: ErrCode 0
293.944: InterleaveChannels_D: Node 3
293.944: InterleaveChannels_D: Status 2005
293.944: InterleaveChannels_D: ErrStatus 4000
293.944: InterleaveChannels_D: ErrCode 0
293.944: InterleaveChannels_D: Node 4
293.944: InterleaveChannels_D: Status 2000
293.944: InterleaveChannels_D: ErrStatus 0
293.944: InterleaveChannels_D: ErrCode 0
293.944: InterleaveChannels_D: Node 5
293.944: InterleaveChannels_D: Status 2000
293.944: InterleaveChannels_D: ErrStatus 0
293.944: InterleaveChannels_D: ErrCode 0
293.944: InterleaveChannels_D: Node 6
293.944: InterleaveChannels_D: Status 2000
293.944: InterleaveChannels_D: ErrStatus 0
293.944: InterleaveChannels_D: ErrCode 0
293.944: InterleaveChannels_D: Node 7
293.944: InterleaveChannels_D: Status 2000
293.944: InterleaveChannels_D: ErrStatus 0
293.944: InterleaveChannels_D: ErrCode 0
293.944: InterleaveChannels_D: Done
293.944: 
293.944: mctAutoInitMCT_D: ECCInit_D
293.945: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
293.945: CBFS: Locating 'cmos_layout.bin'
293.945: CBFS: Found @ offset 2b0c0 size e88
293.945: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
293.945: CBFS: Locating 'cmos_layout.bin'
293.945: CBFS: Found @ offset 2b0c0 size e88
293.946:   ECC enabled on node: 00
293.946: DCTMemClr_Sync_D: Start
293.946: DCTMemClr_Sync_D: Waiting for memory clear to complete................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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294.925: .
294.925: DCTMemClr_Sync_D: Done
294.925:   ECC enabled on node: 01
294.925: DCTMemClr_Sync_D: Start
294.925: DCTMemClr_Sync_D: Waiting for memory clear to complete................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
295.904: .
295.904: DCTMemClr_Sync_D: Done
295.904:   ECC enabled on node: 02
295.904: DCTMemClr_Sync_D: Start
295.904: DCTMemClr_Sync_D: Waiting for memory clear to complete................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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296.883: .
296.883: DCTMemClr_Sync_D: Done
296.883:   ECC enabled on node: 03
296.883: DCTMemClr_Sync_D: Start
296.883: DCTMemClr_Sync_D: Waiting for memory clear to complete................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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297.862: .
297.862: DCTMemClr_Sync_D: Done
297.862: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
297.862: CBFS: Locating 'cmos_layout.bin'
297.862: CBFS: Found @ offset 2b0c0 size e88
297.862: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
297.862: CBFS: Locating 'cmos_layout.bin'
297.862: CBFS: Found @ offset 2b0c0 size e88
297.862: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
297.862: CBFS: Locating 'cmos_layout.bin'
297.862: CBFS: Found @ offset 2b0c0 size e88
297.863: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
297.863: CBFS: Locating 'cmos_layout.bin'
297.863: CBFS: Found @ offset 2b0c0 size e88
297.863: ECCInit: Node 00
297.863: ECCInit: Status 2205
297.863: ECCInit: ErrStatus 4000
297.863: ECCInit: ErrCode 0
297.863: ECCInit: Done
297.863: ECCInit: Node 01
297.863: ECCInit: Status 2005
297.863: ECCInit: ErrStatus 4000
297.863: ECCInit: ErrCode 0
297.863: ECCInit: Done
297.863: ECCInit: Node 02
297.863: ECCInit: Status 2005
297.863: ECCInit: ErrStatus 4000
297.863: ECCInit: ErrCode 0
297.863: ECCInit: Done
297.863: ECCInit: Node 03
297.863: ECCInit: Status 2005
297.863: ECCInit: ErrStatus 4000
297.863: ECCInit: ErrCode 0
297.863: ECCInit: Done
297.863: mctAutoInitMCT_D: CPUMemTyping_D
297.864: <09> CPUMemTyping: Cache32bTOP:c00000
297.864: <09> CPUMemTyping: Bottom32bIO:c00000
297.864: <09> CPUMemTyping: Bottom40bIO:40400000
297.864: mctAutoInitMCT_D: UMAMemTyping_D
297.864: mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15
297.864: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
297.864: CBFS: Locating 'cmos_layout.bin'
297.864: CBFS: Found @ offset 2b0c0 size e88
297.864: set_up_cc6_storage_fam15: Initializing CC6 DRAM storage area for node 0 (interleaved: 0)
297.864: set_up_cc6_storage_fam15:<09>original (node 3) max_range_limit:       403fffffff DRAM limit:       103fffffff
297.865: set_up_cc6_storage_fam15:<09>new max_range_limit:       403effffff
297.865: set_up_cc6_storage_fam15:<09>Target node: 3
297.865: set_up_cc6_storage_fam15:<09>Done
297.865: set_up_cc6_storage_fam15: Initializing CC6 DRAM storage area for node 1 (interleaved: 0)
297.865: set_up_cc6_storage_fam15:<09>original (node 3) max_range_limit:       403fffffff DRAM limit:       203fffffff
297.865: set_up_cc6_storage_fam15:<09>new max_range_limit:       403effffff
297.865: set_up_cc6_storage_fam15:<09>Target node: 3
297.865: set_up_cc6_storage_fam15:<09>Done
297.865: set_up_cc6_storage_fam15: Initializing CC6 DRAM storage area for node 2 (interleaved: 0)
297.865: set_up_cc6_storage_fam15:<09>original (node 3) max_range_limit:       403fffffff DRAM limit:       303fffffff
297.865: set_up_cc6_storage_fam15:<09>new max_range_limit:       403effffff
297.865: set_up_cc6_storage_fam15:<09>Target node: 3
297.865: set_up_cc6_storage_fam15:<09>Done
297.865: set_up_cc6_storage_fam15: Initializing CC6 DRAM storage area for node 3 (interleaved: 0)
297.865: set_up_cc6_storage_fam15:<09>original (node 3) max_range_limit:       403fffffff DRAM limit:       403fffffff
297.865: set_up_cc6_storage_fam15:<09>new max_range_limit:       403effffff
297.865: set_up_cc6_storage_fam15:<09>Target node: 3
297.865: set_up_cc6_storage_fam15:<09>Done
297.865: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
297.865: CBFS: Locating 'cmos_layout.bin'
297.865: CBFS: Found @ offset 2b0c0 size e88
297.866: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
297.866: CBFS: Locating 'cmos_layout.bin'
297.866: CBFS: Found @ offset 2b0c0 size e88
297.866: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
297.866: CBFS: Locating 'cmos_layout.bin'
297.866: CBFS: Found @ offset 2b0c0 size e88
297.866: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
297.866: CBFS: Locating 'cmos_layout.bin'
297.866: CBFS: Found @ offset 2b0c0 size e88
297.866: mctAutoInitMCT_D Done: Global Status: 12
297.866: raminit_amdmct end:
297.867: CBMEM:
297.867: IMD: root @ b7fff000 254 entries.
297.867: IMD: root @ b7ffec00 62 entries.
297.868: amdmct_cbmem_store_info: Storing AMDMCT configuration in CBMEM
297.868: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
297.868: CBFS: Locating 'cmos_layout.bin'
297.868: CBFS: Found @ offset 2b0c0 size e88
297.869: disable_spd()
297.995: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
297.995: CBFS: Locating 'fallback/ramstage'
297.996: CBFS: Found @ offset 3ff00 size 1544c
298.039: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
298.039: CBFS: Locating 'cmos_layout.bin'
298.039: CBFS: Found @ offset 2b0c0 size e88
298.040: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
298.040: CBFS: Locating 'cmos_layout.bin'
298.040: CBFS: Found @ offset 2b0c0 size e88
298.040: 
298.040: 
298.040: coreboot-4.5-1206-g589fc34 Fri Mar 10 10:20:39 UTC 2017 ramstage starting...
298.040: Moving GDT to b7ffe9e0...ok
298.040: Normal boot.
298.040: BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0
298.040: BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1 exit 0
298.040: Enumerating buses...
298.040: Show all devs... Before device enumeration.
298.040: Root Device: enabled 1
298.040: CPU_CLUSTER: 0: enabled 1
298.040: APIC: 00: enabled 1
298.040: DOMAIN: 0000: enabled 1
298.040: PCI: 00:18.0: enabled 1
298.040: PCI: 00:00.0: enabled 1
298.040: PCI: 00:00.1: enabled 1
298.040: PCI: 00:00.2: enabled 1
298.040: PCI: 00:02.0: enabled 1
298.040: PCI: 00:03.0: enabled 0
298.040: PCI: 00:04.0: enabled 1
298.040: PCI: 00:05.0: enabled 0
298.040: PCI: 00:06.0: enabled 0
298.040: PCI: 00:07.0: enabled 0
298.040: PCI: 00:08.0: enabled 0
298.040: PCI: 00:09.0: enabled 1
298.040: PCI: 00:0a.0: enabled 1
298.040: PCI: 00:0b.0: enabled 1
298.040: PCI: 00:0c.0: enabled 1
298.040: PCI: 00:0d.0: enabled 1
298.040: PCI: 00:11.0: enabled 1
298.040: PCI: 00:12.0: enabled 1
298.040: PCI: 00:12.1: enabled 1
298.040: PCI: 00:12.2: enabled 1
298.040: PCI: 00:13.0: enabled 1
298.040: PCI: 00:13.1: enabled 1
298.040: PCI: 00:13.2: enabled 1
298.040: PCI: 00:14.0: enabled 1
298.040: I2C: 00:50: enabled 1
298.040: I2C: 00:51: enabled 1
298.040: I2C: 00:52: enabled 1
298.040: I2C: 00:53: enabled 1
298.040: I2C: 00:54: enabled 1
298.040: I2C: 00:55: enabled 1
298.041: I2C: 00:56: enabled 1
298.041: I2C: 00:57: enabled 1
298.041: I2C: 00:2f: enabled 1
298.041: PCI: 00:14.1: enabled 1
298.041: PCI: 00:14.2: enabled 1
298.041: PCI: 00:14.3: enabled 1
298.041: PNP: 002e.0: enabled 0
298.041: PNP: 002e.1: enabled 0
298.041: PNP: 002e.2: enabled 1
298.041: PNP: 002e.3: enabled 1
298.041: PNP: 002e.5: enabled 1
298.041: PNP: 002e.106: enabled 0
298.041: PNP: 002e.107: enabled 0
298.041: PNP: 002e.207: enabled 0
298.041: PNP: 002e.307: enabled 0
298.041: PNP: 002e.407: enabled 0
298.041: PNP: 002e.8: enabled 0
298.041: PNP: 002e.108: enabled 0
298.041: PNP: 002e.9: enabled 0
298.041: PNP: 002e.109: enabled 0
298.041: PNP: 002e.209: enabled 0
298.041: PNP: 002e.309: enabled 0
298.041: PNP: 002e.a: enabled 1
298.041: PNP: 002e.b: enabled 1
298.041: PNP: 002e.c: enabled 0
298.041: PNP: 002e.d: enabled 0
298.041: PNP: 002e.f: enabled 0
298.041: PNP: 004e.0: enabled 1
298.041: PCI: 00:14.4: enabled 1
298.041: PCI: 00:01.0: enabled 1
298.041: PCI: 00:02.0: enabled 1
298.041: PCI: 00:03.0: enabled 1
298.041: PCI: 00:14.5: enabled 1
298.041: PCI: 00:18.1: enabled 1
298.041: PCI: 00:18.2: enabled 1
298.041: PCI: 00:18.3: enabled 1
298.041: PCI: 00:18.4: enabled 1
298.041: PCI: 00:18.5: enabled 1
298.041: PCI: 00:19.0: enabled 1
298.041: PCI: 00:19.1: enabled 1
298.041: PCI: 00:19.2: enabled 1
298.041: PCI: 00:19.3: enabled 1
298.041: PCI: 00:19.4: enabled 1
298.041: PCI: 00:19.5: enabled 1
298.041: PCI: 00:1a.0: enabled 1
298.041: PCI: 00:1a.1: enabled 1
298.041: PCI: 00:1a.2: enabled 1
298.041: PCI: 00:1a.3: enabled 1
298.041: PCI: 00:1a.4: enabled 1
298.041: PCI: 00:1a.5: enabled 1
298.041: PCI: 00:1b.0: enabled 1
298.041: PCI: 00:1b.1: enabled 1
298.041: PCI: 00:1b.2: enabled 1
298.041: PCI: 00:1b.3: enabled 1
298.041: PCI: 00:1b.4: enabled 1
298.041: PCI: 00:1b.5: enabled 1
298.041: Compare with tree...
298.041: Root Device: enabled 1
298.041:  CPU_CLUSTER: 0: enabled 1
298.041:   APIC: 00: enabled 1
298.041:  DOMAIN: 0000: enabled 1
298.041:   PCI: 00:18.0: enabled 1
298.041:    PCI: 00:00.0: enabled 1
298.041:    PCI: 00:00.1: enabled 1
298.041:    PCI: 00:00.2: enabled 1
298.041:    PCI: 00:02.0: enabled 1
298.041:    PCI: 00:03.0: enabled 0
298.041:    PCI: 00:04.0: enabled 1
298.041:    PCI: 00:05.0: enabled 0
298.041:    PCI: 00:06.0: enabled 0
298.041:    PCI: 00:07.0: enabled 0
298.041:    PCI: 00:08.0: enabled 0
298.042:    PCI: 00:09.0: enabled 1
298.042:    PCI: 00:0a.0: enabled 1
298.042:    PCI: 00:0b.0: enabled 1
298.042:    PCI: 00:0c.0: enabled 1
298.042:    PCI: 00:0d.0: enabled 1
298.042:    PCI: 00:11.0: enabled 1
298.042:    PCI: 00:12.0: enabled 1
298.042:    PCI: 00:12.1: enabled 1
298.042:    PCI: 00:12.2: enabled 1
298.042:    PCI: 00:13.0: enabled 1
298.042:    PCI: 00:13.1: enabled 1
298.042:    PCI: 00:13.2: enabled 1
298.042:    PCI: 00:14.0: enabled 1
298.042:     I2C: 00:50: enabled 1
298.042:     I2C: 00:51: enabled 1
298.042:     I2C: 00:52: enabled 1
298.042:     I2C: 00:53: enabled 1
298.042:     I2C: 00:54: enabled 1
298.042:     I2C: 00:55: enabled 1
298.042:     I2C: 00:56: enabled 1
298.042:     I2C: 00:57: enabled 1
298.042:     I2C: 00:2f: enabled 1
298.042:    PCI: 00:14.1: enabled 1
298.042:    PCI: 00:14.2: enabled 1
298.042:    PCI: 00:14.3: enabled 1
298.042:     PNP: 002e.0: enabled 0
298.042:     PNP: 002e.1: enabled 0
298.042:     PNP: 002e.2: enabled 1
298.042:     PNP: 002e.3: enabled 1
298.042:     PNP: 002e.5: enabled 1
298.042:     PNP: 002e.106: enabled 0
298.042:     PNP: 002e.107: enabled 0
298.042:     PNP: 002e.207: enabled 0
298.042:     PNP: 002e.307: enabled 0
298.042:     PNP: 002e.407: enabled 0
298.042:     PNP: 002e.8: enabled 0
298.042:     PNP: 002e.108: enabled 0
298.042:     PNP: 002e.9: enabled 0
298.042:     PNP: 002e.109: enabled 0
298.042:     PNP: 002e.209: enabled 0
298.042:     PNP: 002e.309: enabled 0
298.042:     PNP: 002e.a: enabled 1
298.042:     PNP: 002e.b: enabled 1
298.042:     PNP: 002e.c: enabled 0
298.042:     PNP: 002e.d: enabled 0
298.042:     PNP: 002e.f: enabled 0
298.042:     PNP: 004e.0: enabled 1
298.042:    PCI: 00:14.4: enabled 1
298.042:     PCI: 00:01.0: enabled 1
298.042:     PCI: 00:02.0: enabled 1
298.042:     PCI: 00:03.0: enabled 1
298.042:    PCI: 00:14.5: enabled 1
298.042:   PCI: 00:18.1: enabled 1
298.042:   PCI: 00:18.2: enabled 1
298.042:   PCI: 00:18.3: enabled 1
298.042:   PCI: 00:18.4: enabled 1
298.042:   PCI: 00:18.5: enabled 1
298.042:   PCI: 00:19.0: enabled 1
298.042:   PCI: 00:19.1: enabled 1
298.042:   PCI: 00:19.2: enabled 1
298.042:   PCI: 00:19.3: enabled 1
298.042:   PCI: 00:19.4: enabled 1
298.042:   PCI: 00:19.5: enabled 1
298.042:   PCI: 00:1a.0: enabled 1
298.042:   PCI: 00:1a.1: enabled 1
298.042:   PCI: 00:1a.2: enabled 1
298.042:   PCI: 00:1a.3: enabled 1
298.042:   PCI: 00:1a.4: enabled 1
298.042:   PCI: 00:1a.5: enabled 1
298.042:   PCI: 00:1b.0: enabled 1
298.042:   PCI: 00:1b.1: enabled 1
298.042:   PCI: 00:1b.2: enabled 1
298.042:   PCI: 00:1b.3: enabled 1
298.042:   PCI: 00:1b.4: enabled 1
298.042:   PCI: 00:1b.5: enabled 1
298.043: Mainboard KGPE-D16 Enable. dev=0x0012cbe0
298.043: mainboard_enable, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000
298.043: mainboard_enable, TOP MEM2: msr2.lo = 0x40000000, msr2.hi = 0x00000040
298.043: Root Device scanning...
298.043: root_dev_scan_bus for Root Device
298.043: setup_bsp_ramtop, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000
298.043: setup_bsp_ramtop, TOP MEM2: msr.lo = 0x40000000, msr.hi = 0x00000040
298.043: CPU_CLUSTER: 0 enabled
298.043: DOMAIN: 0000 enabled
298.043: CPU_CLUSTER: 0 scanning...
298.043: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
298.043: CBFS: Locating 'cmos_layout.bin'
298.043: CBFS: Found @ offset 2b0c0 size e88
298.043: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
298.043: CBFS: Locating 'cmos_layout.bin'
298.043: CBFS: Found @ offset 2b0c0 size e88
298.044:   PCI: 00:18.5 siblings=7
298.044: CPU: APIC: 00 enabled
298.044: CPU: APIC: 01 enabled
298.044: CPU: APIC: 02 enabled
298.044: CPU: APIC: 03 enabled
298.044: CPU: APIC: 04 enabled
298.044: CPU: APIC: 05 enabled
298.044: CPU: APIC: 06 enabled
298.044: CPU: APIC: 07 enabled
298.044:   PCI: 00:19.5 siblings=7
298.044: CPU: APIC: 08 enabled
298.044: CPU: APIC: 09 enabled
298.044: CPU: APIC: 0a enabled
298.044: CPU: APIC: 0b enabled
298.044: CPU: APIC: 0c enabled
298.044: CPU: APIC: 0d enabled
298.044: CPU: APIC: 0e enabled
298.044: CPU: APIC: 0f enabled
298.044:   PCI: 00:1a.5 siblings=7
298.044: CPU: APIC: 20 enabled
298.044: CPU: APIC: 21 enabled
298.044: CPU: APIC: 22 enabled
298.044: CPU: APIC: 23 enabled
298.044: CPU: APIC: 24 enabled
298.044: CPU: APIC: 25 enabled
298.044: CPU: APIC: 26 enabled
298.044: CPU: APIC: 27 enabled
298.044:   PCI: 00:1b.5 siblings=7
298.044: CPU: APIC: 28 enabled
298.044: CPU: APIC: 29 enabled
298.044: CPU: APIC: 2a enabled
298.044: CPU: APIC: 2b enabled
298.044: CPU: APIC: 2c enabled
298.044: CPU: APIC: 2d enabled
298.044: CPU: APIC: 2e enabled
298.044: CPU: APIC: 2f enabled
298.044: scan_bus: scanning of bus CPU_CLUSTER: 0 took 72680 usecs
298.044: DOMAIN: 0000 scanning...
298.044: PCI: pci_scan_bus for bus 00
298.044: PCI: 00:18.0 [1022/1600] bus ops
298.044: PCI: 00:18.0 [1022/1600] enabled
298.044: PCI: 00:18.1 [1022/1601] enabled
298.044: PCI: 00:18.2 [1022/1602] enabled
298.044: PCI: 00:18.3 [1022/1603] ops
298.044: PCI: 00:18.3 [1022/1603] enabled
298.044: PCI: 00:18.4 [1022/1604] ops
298.044: PCI: 00:18.4 [1022/1604] enabled
298.044: PCI: 00:18.5 [1022/1605] ops
298.044: PCI: 00:18.5 [1022/1605] enabled
298.044: PCI: 00:19.0 [1022/1600] bus ops
298.044: PCI: 00:19.0 [1022/1600] enabled
298.044: PCI: 00:19.1 [1022/1601] enabled
298.044: PCI: 00:19.2 [1022/1602] enabled
298.044: PCI: 00:19.3 [1022/1603] ops
298.044: PCI: 00:19.3 [1022/1603] enabled
298.044: PCI: 00:19.4 [1022/1604] ops
298.044: PCI: 00:19.4 [1022/1604] enabled
298.044: PCI: 00:19.5 [1022/1605] ops
298.044: PCI: 00:19.5 [1022/1605] enabled
298.045: PCI: 00:1a.0 [1022/1600] bus ops
298.045: PCI: 00:1a.0 [1022/1600] enabled
298.045: PCI: 00:1a.1 [1022/1601] enabled
298.045: PCI: 00:1a.2 [1022/1602] enabled
298.045: PCI: 00:1a.3 [1022/1603] ops
298.045: PCI: 00:1a.3 [1022/1603] enabled
298.045: PCI: 00:1a.4 [1022/1604] ops
298.045: PCI: 00:1a.4 [1022/1604] enabled
298.045: PCI: 00:1a.5 [1022/1605] ops
298.045: PCI: 00:1a.5 [1022/1605] enabled
298.045: PCI: 00:1b.0 [1022/1600] bus ops
298.045: PCI: 00:1b.0 [1022/1600] enabled
298.045: PCI: 00:1b.1 [1022/1601] enabled
298.045: PCI: 00:1b.2 [1022/1602] enabled
298.045: PCI: 00:1b.3 [1022/1603] ops
298.045: PCI: 00:1b.3 [1022/1603] enabled
298.045: PCI: 00:1b.4 [1022/1604] ops
298.045: PCI: 00:1b.4 [1022/1604] enabled
298.045: PCI: 00:1b.5 [1022/1605] ops
298.045: PCI: 00:1b.5 [1022/1605] enabled
298.045: PCI: 00:18.0 scanning...
298.045: do_hypertransport_scan_chain for bus 00
298.045: sr5650_enable: dev=0012f500, VID_DID=0x5a101002
298.045: Bus-0, Dev-0, Fun-0.
298.045: enable_pcie_bar3
298.048: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ef60, port=0x8
298.048: PciePowerOffGppPorts() port 8
298.048: NB_PCI_REG04 = 2.
298.048: NB_PCI_REG84 = 3000010.
298.048: NB_PCI_REG4C = 52042.
298.048: Sysmem TOM = 0_c0000000
298.048: Sysmem TOM2 = 40_40000000
298.048: PCI: 00:00.0 [1002/5a10] ops
298.048: PCI: 00:00.0 [1002/5a10] enabled
298.048: Capability: type 0x08 @ 0xf0
298.048: flags: 0xa803
298.048: Capability: type 0x08 @ 0xf0
298.048: Capability: type 0x08 @ 0xc4
298.048: flags: 0x0280
298.048: PCI: 00:00.0 count: 0014 static_count: 0015
298.048: PCI: 00:00.0 [1002/5a10] enabled next_unitid: 0015
298.048: PCI: pci_scan_bus for bus 00
298.048: sr5650_enable: dev=0012f500, VID_DID=0x5a101002
298.048: Bus-0, Dev-0, Fun-0.
298.048: enable_pcie_bar3
298.051: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ef60, port=0x8
298.051: PciePowerOffGppPorts() port 8
298.051: NB_PCI_REG04 = 2.
298.051: NB_PCI_REG84 = 3000010.
298.051: NB_PCI_REG4C = 52042.
298.051: Sysmem TOM = 0_c0000000
298.051: Sysmem TOM2 = 40_40000000
298.051: PCI: 00:00.0 [1002/5a10] enabled
298.051: sr5650_enable: dev=0012f460, VID_DID=0xffffffff
298.051: Bus-0, Dev-0, Fun-1.
298.051: PCI: Static device PCI: 00:00.1 not found, disabling it.
298.051: sr5650_enable: dev=0012f3c0, VID_DID=0x5a231002
298.051: Bus-0, Dev-0, Fun-2.
298.051: PCI: 00:00.2 [1002/5a23] ops
298.051: PCI: 00:00.2 [1002/5a23] enabled
298.051: sr5650_enable: dev=0012f320, VID_DID=0xffffffff
298.051: Bus-0, Dev-2,3, Fun-0. enable=1
298.052: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012f320, port=0x2
298.092: PcieLinkTraining port=2:lc current state=2030400
298.093: sr5650_gpp_sb_init: port=0x2 hw_port=0x2 result=0
298.093: PciePowerOffGppPorts() port 2
298.093: Capability: type 0x01 @ 0x50
298.093: Capability: type 0x10 @ 0x58
298.093: Capability: type 0x05 @ 0xa0
298.093: Capability: type 0x0d @ 0xb0
298.093: Capability: type 0x08 @ 0xb8
298.093: Capability: type 0x01 @ 0x50
298.093: Capability: type 0x10 @ 0x58
298.093: Capability: type 0x05 @ 0xa0
298.093: Capability: type 0x0d @ 0xb0
298.093: Capability: type 0x08 @ 0xb8
298.093: Capability: type 0x01 @ 0x50
298.093: Capability: type 0x10 @ 0x58
298.093: Capability: type 0x05 @ 0xa0
298.093: Capability: type 0x0d @ 0xb0
298.093: Capability: type 0x08 @ 0xb8
298.093: Capability: type 0x01 @ 0x50
298.093: Capability: type 0x10 @ 0x58
298.093: PCI: 00:02.0 subordinate bus PCI Express
298.093: PCI: 00:02.0 [1002/5a16] enabled
298.093: sr5650_enable: dev=0012f280, VID_DID=0xffffffff
298.093: Bus-0, Dev-2,3, Fun-0. enable=0
298.093: sr5650_enable: dev=0012f1e0, VID_DID=0xffffffff
298.093: enable_pcie_bar3
298.093: Bus-0, Dev-4,5,6,7, Fun-0. enable=1
298.093: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012f1e0, port=0x4
298.133: PcieLinkTraining port=4:lc current state=2030400
298.134: sr5650_gpp_sb_init: port=0x4 hw_port=0x4 result=0
298.134: PciePowerOffGppPorts() port 4
298.134: Capability: type 0x01 @ 0x50
298.134: Capability: type 0x10 @ 0x58
298.134: Capability: type 0x05 @ 0xa0
298.134: Capability: type 0x0d @ 0xb0
298.134: Capability: type 0x08 @ 0xb8
298.134: Capability: type 0x01 @ 0x50
298.134: Capability: type 0x10 @ 0x58
298.134: Capability: type 0x05 @ 0xa0
298.134: Capability: type 0x0d @ 0xb0
298.134: Capability: type 0x08 @ 0xb8
298.134: Capability: type 0x01 @ 0x50
298.135: Capability: type 0x10 @ 0x58
298.135: Capability: type 0x05 @ 0xa0
298.135: Capability: type 0x0d @ 0xb0
298.135: Capability: type 0x08 @ 0xb8
298.135: Capability: type 0x01 @ 0x50
298.135: Capability: type 0x10 @ 0x58
298.135: PCI: 00:04.0 subordinate bus PCI Express
298.135: PCI: 00:04.0 [1002/5a18] enabled
298.135: sr5650_enable: dev=0012f140, VID_DID=0xffffffff
298.135: enable_pcie_bar3
298.135: Bus-0, Dev-4,5,6,7, Fun-0. enable=0
298.135: sr5650_enable: dev=0012f0a0, VID_DID=0xffffffff
298.135: enable_pcie_bar3
298.135: Bus-0, Dev-4,5,6,7, Fun-0. enable=0
298.135: sr5650_enable: dev=0012f000, VID_DID=0xffffffff
298.135: enable_pcie_bar3
298.135: Bus-0, Dev-4,5,6,7, Fun-0. enable=0
298.135: sr5650_enable: dev=0012ef60, VID_DID=0xffffffff
298.135: Bus-0, Dev-8, Fun-0. enable=0
298.135: disable_pcie_bar3
298.135: sr5650_enable: dev=0012eec0, VID_DID=0xffffffff
298.135: Bus-0, Dev-9, 10, Fun-0. enable=1
298.135: enable_pcie_bar3
298.135: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012eec0, port=0x9
298.175: PcieLinkTraining port=5:lc current state=a0b0f10
298.175: addr=c0000000,bus=0,devfn=48
298.175: PcieTrainPort reg=0x10000
298.175: sr5650_gpp_sb_init: port=0x9 hw_port=0x5 result=1
298.175: Capability: type 0x01 @ 0x50
298.175: Capability: type 0x10 @ 0x58
298.175: Capability: type 0x05 @ 0xa0
298.175: Capability: type 0x0d @ 0xb0
298.175: Capability: type 0x08 @ 0xb8
298.175: Capability: type 0x01 @ 0x50
298.175: Capability: type 0x10 @ 0x58
298.175: Capability: type 0x05 @ 0xa0
298.175: Capability: type 0x0d @ 0xb0
298.175: Capability: type 0x08 @ 0xb8
298.175: Capability: type 0x01 @ 0x50
298.175: Capability: type 0x10 @ 0x58
298.175: Capability: type 0x05 @ 0xa0
298.175: Capability: type 0x0d @ 0xb0
298.175: Capability: type 0x08 @ 0xb8
298.175: Capability: type 0x01 @ 0x50
298.175: Capability: type 0x10 @ 0x58
298.175: PCI: 00:09.0 subordinate bus PCI Express
298.175: PCI: 00:09.0 [1002/5a1c] enabled
298.175: sr5650_enable: dev=0012ee20, VID_DID=0xffffffff
298.175: Bus-0, Dev-9, 10, Fun-0. enable=1
298.175: enable_pcie_bar3
298.175: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ee20, port=0xa
298.216: PcieLinkTraining port=6:lc current state=a0b0f10
298.216: addr=c0000000,bus=0,devfn=50
298.216: PcieTrainPort reg=0x10000
298.216: sr5650_gpp_sb_init: port=0xa hw_port=0x6 result=1
298.216: Capability: type 0x01 @ 0x50
298.216: Capability: type 0x10 @ 0x58
298.216: Capability: type 0x05 @ 0xa0
298.216: Capability: type 0x0d @ 0xb0
298.216: Capability: type 0x08 @ 0xb8
298.216: Capability: type 0x01 @ 0x50
298.216: Capability: type 0x10 @ 0x58
298.216: Capability: type 0x05 @ 0xa0
298.216: Capability: type 0x0d @ 0xb0
298.216: Capability: type 0x08 @ 0xb8
298.216: Capability: type 0x01 @ 0x50
298.216: Capability: type 0x10 @ 0x58
298.216: Capability: type 0x05 @ 0xa0
298.216: Capability: type 0x0d @ 0xb0
298.216: Capability: type 0x08 @ 0xb8
298.216: Capability: type 0x01 @ 0x50
298.216: Capability: type 0x10 @ 0x58
298.216: PCI: 00:0a.0 subordinate bus PCI Express
298.216: PCI: 00:0a.0 [1002/5a1d] enabled
298.216: sr5650_enable: dev=0012ed80, VID_DID=0xffffffff
298.216: Bus-0, Dev-11,12, Fun-0. enable=1
298.216: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ed80, port=0xb
298.256: PcieLinkTraining port=b:lc current state=2030400
298.257: sr5650_gpp_sb_init: port=0xb hw_port=0xb result=0
298.257: PciePowerOffGppPorts() port 11
298.257: Capability: type 0x01 @ 0x50
298.257: Capability: type 0x10 @ 0x58
298.257: Capability: type 0x05 @ 0xa0
298.257: Capability: type 0x0d @ 0xb0
298.257: Capability: type 0x08 @ 0xb8
298.257: Capability: type 0x01 @ 0x50
298.257: Capability: type 0x10 @ 0x58
298.257: Capability: type 0x05 @ 0xa0
298.257: Capability: type 0x0d @ 0xb0
298.257: Capability: type 0x08 @ 0xb8
298.257: Capability: type 0x01 @ 0x50
298.257: Capability: type 0x10 @ 0x58
298.257: Capability: type 0x05 @ 0xa0
298.257: Capability: type 0x0d @ 0xb0
298.257: Capability: type 0x08 @ 0xb8
298.257: Capability: type 0x01 @ 0x50
298.257: Capability: type 0x10 @ 0x58
298.257: PCI: 00:0b.0 subordinate bus PCI Express
298.257: PCI: 00:0b.0 [1002/5a1f] enabled
298.257: sr5650_enable: dev=0012ece0, VID_DID=0xffffffff
298.257: Bus-0, Dev-11,12, Fun-0. enable=1
298.257: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ece0, port=0xc
298.298: PcieLinkTraining port=c:lc current state=2030400
298.299: sr5650_gpp_sb_init: port=0xc hw_port=0xc result=0
298.299: PciePowerOffGppPorts() port 12
298.299: Capability: type 0x01 @ 0x50
298.299: Capability: type 0x10 @ 0x58
298.299: Capability: type 0x05 @ 0xa0
298.299: Capability: type 0x0d @ 0xb0
298.299: Capability: type 0x08 @ 0xb8
298.299: Capability: type 0x01 @ 0x50
298.299: Capability: type 0x10 @ 0x58
298.299: Capability: type 0x05 @ 0xa0
298.299: Capability: type 0x0d @ 0xb0
298.299: Capability: type 0x08 @ 0xb8
298.299: Capability: type 0x01 @ 0x50
298.299: Capability: type 0x10 @ 0x58
298.299: Capability: type 0x05 @ 0xa0
298.299: Capability: type 0x0d @ 0xb0
298.299: Capability: type 0x08 @ 0xb8
298.299: Capability: type 0x01 @ 0x50
298.299: Capability: type 0x10 @ 0x58
298.299: PCI: 00:0c.0 subordinate bus PCI Express
298.299: PCI: 00:0c.0 [1002/5a20] enabled
298.299: sr5650_enable: dev=0012ec40, VID_DID=0xffffffff
298.299: sr5650_gpp_sb_init: nb_dev=0x0012f500, dev=0x0012ec40, port=0xd
298.339: PcieLinkTraining port=d:lc current state=20212210
298.339: addr=c0000000,bus=0,devfn=68
298.339: PcieTrainPort reg=0x10000
298.339: sr5650_gpp_sb_init: port=0xd hw_port=0xd result=1
299.339: Capability: type 0x01 @ 0x50
299.339: Capability: type 0x10 @ 0x58
299.339: Capability: type 0x05 @ 0xa0
299.339: Capability: type 0x0d @ 0xb0
299.339: Capability: type 0x08 @ 0xb8
299.339: Capability: type 0x01 @ 0x50
299.339: Capability: type 0x10 @ 0x58
299.339: Capability: type 0x05 @ 0xa0
299.339: Capability: type 0x0d @ 0xb0
299.339: Capability: type 0x08 @ 0xb8
299.339: Capability: type 0x01 @ 0x50
299.339: Capability: type 0x10 @ 0x58
299.339: Capability: type 0x05 @ 0xa0
299.339: Capability: type 0x0d @ 0xb0
299.339: Capability: type 0x08 @ 0xb8
299.339: Capability: type 0x01 @ 0x50
299.339: Capability: type 0x10 @ 0x58
299.339: PCI: 00:0d.0 subordinate bus PCI Express
299.339: PCI: 00:0d.0 [1002/5a1e] enabled
299.339: sb7xx_51xx_enable()
299.340: PCI: 00:11.0 [1002/4394] ops
299.340: PCI: 00:11.0 [1002/4394] enabled
299.340: sb7xx_51xx_enable()
299.340: PCI: 00:12.0 [1002/4397] ops
299.340: PCI: 00:12.0 [1002/4397] enabled
299.340: sb7xx_51xx_enable()
299.340: PCI: 00:12.1 [1002/4398] ops
299.340: PCI: 00:12.1 [1002/4398] enabled
299.340: sb7xx_51xx_enable()
299.340: PCI: 00:12.2 [1002/4396] ops
299.340: PCI: 00:12.2 [1002/4396] enabled
299.340: sb7xx_51xx_enable()
299.340: PCI: 00:13.0 [1002/4397] ops
299.340: PCI: 00:13.0 [1002/4397] enabled
299.340: sb7xx_51xx_enable()
299.340: PCI: 00:13.1 [1002/4398] ops
299.340: PCI: 00:13.1 [1002/4398] enabled
299.340: sb7xx_51xx_enable()
299.340: PCI: 00:13.2 [1002/4396] ops
299.340: PCI: 00:13.2 [1002/4396] enabled
299.340: sb7xx_51xx_enable()
299.340: PCI: 00:14.0 [1002/4385] bus ops
299.340: PCI: 00:14.0 [1002/4385] enabled
299.340: sb7xx_51xx_enable()
299.340: PCI: 00:14.1 [1002/439c] ops
299.340: PCI: 00:14.1 [1002/439c] enabled
299.340: sb7xx_51xx_enable()
299.340: PCI: 00:14.2 [1002/4383] ops
299.340: PCI: 00:14.2 [1002/4383] enabled
299.340: sb7xx_51xx_enable()
299.340: PCI: 00:14.3 [1002/439d] bus ops
299.340: PCI: 00:14.3 [1002/439d] enabled
299.340: sb7xx_51xx_enable()
299.340: PCI: 00:14.4 [1002/4384] bus ops
299.340: PCI: 00:14.4 [1002/4384] enabled
299.340: sb7xx_51xx_enable()
299.340: PCI: 00:14.5 [1002/4399] ops
299.340: PCI: 00:14.5 [1002/4399] enabled
299.340: PCI: 00:02.0 scanning...
299.340: do_pci_scan_bridge for PCI: 00:02.0
299.340: PCI: pci_scan_bus for bus 01
299.340: scan_bus: scanning of bus PCI: 00:02.0 took 5919 usecs
299.340: PCI: 00:04.0 scanning...
299.340: do_pci_scan_bridge for PCI: 00:04.0
299.340: PCI: pci_scan_bus for bus 02
299.340: scan_bus: scanning of bus PCI: 00:04.0 took 5920 usecs
299.340: PCI: 00:09.0 scanning...
299.340: do_pci_scan_bridge for PCI: 00:09.0
299.340: PCI: pci_scan_bus for bus 03
299.340: PCI: 03:00.0 [8086/10d3] enabled
299.340: Capability: type 0x01 @ 0xc8
299.340: Capability: type 0x05 @ 0xd0
299.340: Capability: type 0x10 @ 0xe0
299.340: Capability: type 0x01 @ 0x50
299.340: Capability: type 0x10 @ 0x58
299.340: Enabling Common Clock Configuration
299.341: PCIE CLK PM is not supported by endpointASPM: Enabled None
299.341: scan_bus: scanning of bus PCI: 00:09.0 took 23869 usecs
299.341: PCI: 00:0a.0 scanning...
299.341: do_pci_scan_bridge for PCI: 00:0a.0
299.341: PCI: pci_scan_bus for bus 04
299.341: PCI: 04:00.0 [8086/10d3] enabled
299.341: Capability: type 0x01 @ 0xc8
299.341: Capability: type 0x05 @ 0xd0
299.341: Capability: type 0x10 @ 0xe0
299.341: Capability: type 0x01 @ 0x50
299.341: Capability: type 0x10 @ 0x58
299.341: Enabling Common Clock Configuration
299.341: PCIE CLK PM is not supported by endpointASPM: Enabled None
299.341: scan_bus: scanning of bus PCI: 00:0a.0 took 23825 usecs
299.341: PCI: 00:0b.0 scanning...
299.341: do_pci_scan_bridge for PCI: 00:0b.0
299.341: PCI: pci_scan_bus for bus 05
299.341: scan_bus: scanning of bus PCI: 00:0b.0 took 5921 usecs
299.341: PCI: 00:0c.0 scanning...
299.341: do_pci_scan_bridge for PCI: 00:0c.0
299.341: PCI: pci_scan_bus for bus 06
299.341: scan_bus: scanning of bus PCI: 00:0c.0 took 5921 usecs
299.341: PCI: 00:0d.0 scanning...
299.341: do_pci_scan_bridge for PCI: 00:0d.0
299.341: PCI: pci_scan_bus for bus 07
299.341: PCI: 07:00.0 [8086/10fb] enabled
299.341: PCI: 07:00.1 [8086/10fb] enabled
299.341: Capability: type 0x01 @ 0x40
299.341: Capability: type 0x05 @ 0x50
299.341: Capability: type 0x11 @ 0x70
299.341: Capability: type 0x10 @ 0xa0
299.341: Capability: type 0x01 @ 0x50
299.341: Capability: type 0x10 @ 0x58
299.341: Enabling Common Clock Configuration
299.341: PCIE CLK PM is not supported by endpointASPM: Enabled None
299.341: Capability: type 0x01 @ 0x40
299.341: Capability: type 0x05 @ 0x50
299.341: Capability: type 0x11 @ 0x70
299.341: Capability: type 0x10 @ 0xa0
299.341: Capability: type 0x01 @ 0x50
299.341: Capability: type 0x10 @ 0x58
299.341: Enabling Common Clock Configuration
299.341: PCIE CLK PM is not supported by endpointASPM: Enabled None
299.342: scan_bus: scanning of bus PCI: 00:0d.0 took 45514 usecs
299.342: PCI: 00:14.0 scanning...
299.342: scan_generic_bus for PCI: 00:14.0
299.342: bus: PCI: 00:14.0[0]->I2C: 01:50 enabled
299.342: bus: PCI: 00:14.0[0]->I2C: 01:51 enabled
299.342: bus: PCI: 00:14.0[0]->I2C: 01:52 enabled
299.342: bus: PCI: 00:14.0[0]->I2C: 01:53 enabled
299.342: bus: PCI: 00:14.0[0]->I2C: 01:54 enabled
299.342: bus: PCI: 00:14.0[0]->I2C: 01:55 enabled
299.342: bus: PCI: 00:14.0[0]->I2C: 01:56 enabled
299.342: bus: PCI: 00:14.0[0]->I2C: 01:57 enabled
299.342: bus: PCI: 00:14.0[0]->I2C: 01:2f enabled
299.342: scan_generic_bus for PCI: 00:14.0 done
299.342: scan_bus: scanning of bus PCI: 00:14.0 took 30456 usecs
299.342: PCI: 00:14.3 scanning...
299.342: scan_lpc_bus for PCI: 00:14.3
299.342: PNP: 002e.0 disabled
299.342: PNP: 002e.1 disabled
299.342: PNP: 002e.2 enabled
299.342: PNP: 002e.3 enabled
299.342: PNP: 002e.5 enabled
299.342: PNP: 002e.106 disabled
299.342: PNP: 002e.107 disabled
299.342: PNP: 002e.207 disabled
299.342: PNP: 002e.307 disabled
299.342: PNP: 002e.407 disabled
299.342: PNP: 002e.8 disabled
299.342: PNP: 002e.108 disabled
299.342: PNP: 002e.9 disabled
299.342: PNP: 002e.109 disabled
299.342: PNP: 002e.209 disabled
299.342: PNP: 002e.309 disabled
299.342: PNP: 002e.a enabled
299.342: PNP: 002e.b enabled
299.343: PNP: 002e.c disabled
299.343: PNP: 002e.d disabled
299.343: PNP: 002e.f disabled
299.343: PNP: 004e.0 enabled
299.343: scan_lpc_bus for PCI: 00:14.3 done
299.343: scan_bus: scanning of bus PCI: 00:14.3 took 37761 usecs
299.343: PCI: 00:14.4 scanning...
299.343: do_pci_scan_bridge for PCI: 00:14.4
299.343: PCI: pci_scan_bus for bus 08
299.343: sb7xx_51xx_enable()
299.343: PCI: 08:01.0 [1a03/2000] ops
299.343: PCI: 08:01.0 [1a03/2000] enabled
299.343: sb7xx_51xx_enable()
299.343: PCI: 08:02.0 [11c1/5811] enabled
299.343: sb7xx_51xx_enable()
299.343: PCI: Static device PCI: 08:03.0 not found, disabling it.
299.343: scan_bus: scanning of bus PCI: 00:14.4 took 19826 usecs
299.343: scan_bus: scanning of bus PCI: 00:18.0 took 1754962 usecs
299.343: PCI: 00:19.0 scanning...
299.343: scan_bus: scanning of bus PCI: 00:19.0 took 1652 usecs
299.343: PCI: 00:1a.0 scanning...
299.343: scan_bus: scanning of bus PCI: 00:1a.0 took 1652 usecs
299.343: PCI: 00:1b.0 scanning...
299.343: scan_bus: scanning of bus PCI: 00:1b.0 took 1652 usecs
299.343: DOMAIN: 0000 passpw: enabled
299.343: DOMAIN: 0000 passpw: enabled
299.343: DOMAIN: 0000 passpw: enabled
299.343: DOMAIN: 0000 passpw: enabled
299.343: scan_bus: scanning of bus DOMAIN: 0000 took 1868725 usecs
299.343: root_dev_scan_bus for Root Device done
299.343: scan_bus: scanning of bus Root Device took 1966989 usecs
299.343: done
299.343: BS: BS_DEV_ENUMERATE times (us): entry 0 run 2288308 exit 0
299.343: found VGA at PCI: 08:01.0
299.343: Setting up VGA for PCI: 08:01.0
299.343: Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:14.4
299.343: Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
299.343: Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
299.343: Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
299.343: Allocating resources...
299.343: Reading resources...
299.343: Root Device read_resources bus 0 link: 0
299.343: CPU_CLUSTER: 0 read_resources bus 0 link: 0
299.343: CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
299.343: Adding PCIe enhanced config space BAR 0xc0000000-0xd0000000.
299.343: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.343: CBFS: Locating 'cmos_layout.bin'
299.343: CBFS: Found @ offset 2b0c0 size e88
299.344: Reserving CC6 save segment base: 4038000000 size: 08000000
299.344: DOMAIN: 0000 read_resources bus 0 link: 0
299.344: PCI: 00:18.0 read_resources bus 0 link: 2
299.344: PCI: 00:18.0 read_resources bus 0 link: 2 done
299.344: PCI: 00:18.0 read_resources bus 0 link: 3
299.344: PCI: 00:18.0 read_resources bus 0 link: 3 done
299.344: PCI: 00:18.0 read_resources bus 0 link: 0
299.344: PCI: 00:18.0 read_resources bus 0 link: 0 done
299.344: PCI: 00:18.0 read_resources bus 0 link: 1
299.344: sr5690_read_resource: PCI: 00:00.0
299.344: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.344: CBFS: Locating 'cmos_layout.bin'
299.344: CBFS: Found @ offset 2b0c0 size e88
299.345: PCI: 00:02.0 read_resources bus 1 link: 0
299.345: PCI: 00:02.0 read_resources bus 1 link: 0 done
299.345: PCI: 00:04.0 read_resources bus 2 link: 0
299.345: PCI: 00:04.0 read_resources bus 2 link: 0 done
299.345: PCI: 00:09.0 read_resources bus 3 link: 0
299.345: PCI: 00:09.0 read_resources bus 3 link: 0 done
299.345: PCI: 00:0a.0 read_resources bus 4 link: 0
299.345: PCI: 00:0a.0 read_resources bus 4 link: 0 done
299.345: PCI: 00:0b.0 read_resources bus 5 link: 0
299.345: PCI: 00:0b.0 read_resources bus 5 link: 0 done
299.345: PCI: 00:0c.0 read_resources bus 6 link: 0
299.345: PCI: 00:0c.0 read_resources bus 6 link: 0 done
299.345: PCI: 00:0d.0 read_resources bus 7 link: 0
299.345: PCI: 00:0d.0 read_resources bus 7 link: 0 done
299.345: PCI: 00:14.0 read_resources bus 1 link: 0
299.345: I2C: 01:50 missing read_resources
299.345: I2C: 01:51 missing read_resources
299.345: I2C: 01:52 missing read_resources
299.345: I2C: 01:53 missing read_resources
299.345: I2C: 01:54 missing read_resources
299.345: I2C: 01:55 missing read_resources
299.345: I2C: 01:56 missing read_resources
299.345: I2C: 01:57 missing read_resources
299.345: PCI: 00:14.0 read_resources bus 1 link: 0 done
299.346: PCI: 00:14.3 read_resources bus 0 link: 0
299.346: PNP: 004e.0 missing read_resources
299.346: PCI: 00:14.3 read_resources bus 0 link: 0 done
299.346: PCI: 00:14.4 read_resources bus 8 link: 0
299.346: PCI: 00:14.4 read_resources bus 8 link: 0 done
299.346: PCI: 00:18.0 read_resources bus 0 link: 1 done
299.346: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.346: CBFS: Locating 'cmos_layout.bin'
299.346: CBFS: Found @ offset 2b0c0 size e88
299.346: PCI: 00:18.4 read_resources bus 0 link: 0
299.346: PCI: 00:18.4 read_resources bus 0 link: 0 done
299.346: PCI: 00:18.4 read_resources bus 0 link: 1
299.346: PCI: 00:18.4 read_resources bus 0 link: 1 done
299.346: PCI: 00:18.4 read_resources bus 0 link: 2
299.347: PCI: 00:18.4 read_resources bus 0 link: 2 done
299.347: PCI: 00:18.4 read_resources bus 0 link: 3
299.347: PCI: 00:18.4 read_resources bus 0 link: 3 done
299.347: PCI: 00:19.0 read_resources bus 0 link: 3
299.347: PCI: 00:19.0 read_resources bus 0 link: 3 done
299.347: PCI: 00:19.0 read_resources bus 0 link: 2
299.347: PCI: 00:19.0 read_resources bus 0 link: 2 done
299.347: PCI: 00:19.0 read_resources bus 0 link: 0
299.347: PCI: 00:19.0 read_resources bus 0 link: 0 done
299.347: PCI: 00:19.0 read_resources bus 0 link: 1
299.347: PCI: 00:19.0 read_resources bus 0 link: 1 done
299.347: PCI: 00:19.4 read_resources bus 0 link: 0
299.347: PCI: 00:19.4 read_resources bus 0 link: 0 done
299.347: PCI: 00:19.4 read_resources bus 0 link: 1
299.347: PCI: 00:19.4 read_resources bus 0 link: 1 done
299.347: PCI: 00:19.4 read_resources bus 0 link: 2
299.347: PCI: 00:19.4 read_resources bus 0 link: 2 done
299.347: PCI: 00:19.4 read_resources bus 0 link: 3
299.347: PCI: 00:19.4 read_resources bus 0 link: 3 done
299.347: PCI: 00:1a.0 read_resources bus 0 link: 3
299.347: PCI: 00:1a.0 read_resources bus 0 link: 3 done
299.347: PCI: 00:1a.0 read_resources bus 0 link: 2
299.347: PCI: 00:1a.0 read_resources bus 0 link: 2 done
299.347: PCI: 00:1a.0 read_resources bus 0 link: 0
299.347: PCI: 00:1a.0 read_resources bus 0 link: 0 done
299.347: PCI: 00:1a.0 read_resources bus 0 link: 1
299.347: PCI: 00:1a.0 read_resources bus 0 link: 1 done
299.347: PCI: 00:1a.4 read_resources bus 0 link: 0
299.347: PCI: 00:1a.4 read_resources bus 0 link: 0 done
299.347: PCI: 00:1a.4 read_resources bus 0 link: 1
299.347: PCI: 00:1a.4 read_resources bus 0 link: 1 done
299.347: PCI: 00:1a.4 read_resources bus 0 link: 2
299.347: PCI: 00:1a.4 read_resources bus 0 link: 2 done
299.347: PCI: 00:1a.4 read_resources bus 0 link: 3
299.347: PCI: 00:1a.4 read_resources bus 0 link: 3 done
299.347: PCI: 00:1b.0 read_resources bus 0 link: 3
299.347: PCI: 00:1b.0 read_resources bus 0 link: 3 done
299.347: PCI: 00:1b.0 read_resources bus 0 link: 2
299.347: PCI: 00:1b.0 read_resources bus 0 link: 2 done
299.347: PCI: 00:1b.0 read_resources bus 0 link: 0
299.347: PCI: 00:1b.0 read_resources bus 0 link: 0 done
299.347: PCI: 00:1b.0 read_resources bus 0 link: 1
299.347: PCI: 00:1b.0 read_resources bus 0 link: 1 done
299.347: PCI: 00:1b.4 read_resources bus 0 link: 0
299.347: PCI: 00:1b.4 read_resources bus 0 link: 0 done
299.347: PCI: 00:1b.4 read_resources bus 0 link: 1
299.347: PCI: 00:1b.4 read_resources bus 0 link: 1 done
299.347: PCI: 00:1b.4 read_resources bus 0 link: 2
299.347: PCI: 00:1b.4 read_resources bus 0 link: 2 done
299.347: PCI: 00:1b.4 read_resources bus 0 link: 3
299.347: PCI: 00:1b.4 read_resources bus 0 link: 3 done
299.347: DOMAIN: 0000 read_resources bus 0 link: 0 done
299.347: Root Device read_resources bus 0 link: 0 done
299.347: Done reading resources.
299.347: Show resources in subtree (Root Device)...After reading.
299.347:  Root Device child on link 0 CPU_CLUSTER: 0
299.347:   CPU_CLUSTER: 0 child on link 0 APIC: 00
299.347:    APIC: 00
299.347:    APIC: 01
299.347:    APIC: 02
299.347:    APIC: 03
299.347:    APIC: 04
299.347:    APIC: 05
299.347:    APIC: 06
299.348:    APIC: 07
299.348:    APIC: 08
299.348:    APIC: 09
299.348:    APIC: 0a
299.348:    APIC: 0b
299.348:    APIC: 0c
299.348:    APIC: 0d
299.348:    APIC: 0e
299.348:    APIC: 0f
299.348:    APIC: 20
299.348:    APIC: 21
299.348:    APIC: 22
299.348:    APIC: 23
299.348:    APIC: 24
299.348:    APIC: 25
299.348:    APIC: 26
299.348:    APIC: 27
299.348:    APIC: 28
299.348:    APIC: 29
299.348:    APIC: 2a
299.348:    APIC: 2b
299.348:    APIC: 2c
299.348:    APIC: 2d
299.348:    APIC: 2e
299.348:    APIC: 2f
299.348:   DOMAIN: 0000 child on link 0 PCI: 00:18.0
299.348:   DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
299.348:   DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
299.348:   DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
299.348:   DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7
299.348:   DOMAIN: 0000 resource base 4038000000 size 8000000 align 0 gran 0 limit 0 flags f0004200 index 8
299.348:    PCI: 00:18.0
299.348:    PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 110b0
299.348:    PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 110b8
299.348:    PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 110d8
299.348:     PCI: 00:00.0
299.348:     PCI: 00:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 1200 index fc
299.348:     PCI: 00:00.1
299.349:     PCI: 00:00.2
299.349:     PCI: 00:00.2 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 10000200 index 44
299.349:     PCI: 00:02.0
299.349:     PCI: 00:02.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
299.349:     PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
299.349:     PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
299.349:     PCI: 00:03.0
299.349:     PCI: 00:04.0
299.349:     PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
299.349:     PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
299.349:     PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
299.349:     PCI: 00:05.0
299.349:     PCI: 00:06.0
299.349:     PCI: 00:07.0
299.349:     PCI: 00:08.0
299.349:     PCI: 00:09.0 child on link 0 PCI: 03:00.0
299.349:     PCI: 00:09.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
299.349:     PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
299.349:     PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
299.349:      PCI: 03:00.0
299.349:      PCI: 03:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
299.349:      PCI: 03:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
299.349:      PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
299.349:     PCI: 00:0a.0 child on link 0 PCI: 04:00.0
299.349:     PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
299.349:     PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
299.349:     PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
299.349:      PCI: 04:00.0
299.349:      PCI: 04:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
299.349:      PCI: 04:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
299.349:      PCI: 04:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
299.349:     PCI: 00:0b.0
299.349:     PCI: 00:0b.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
299.349:     PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
299.349:     PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
299.349:     PCI: 00:0c.0
299.349:     PCI: 00:0c.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
299.349:     PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
299.349:     PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
299.349:     PCI: 00:0d.0 child on link 0 PCI: 07:00.0
299.349:     PCI: 00:0d.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
299.349:     PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
299.349:     PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
299.349:      PCI: 07:00.0
299.349:      PCI: 07:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffffffffffff flags 1201 index 10
299.349:      PCI: 07:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
299.349:      PCI: 07:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
299.349:      PCI: 07:00.1
299.349:      PCI: 07:00.1 resource base 0 size 80000 align 19 gran 19 limit ffffffffffffffff flags 1201 index 10
299.349:      PCI: 07:00.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
299.349:      PCI: 07:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
299.349:     PCI: 00:11.0
299.349:     PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
299.349:     PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
299.349:     PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
299.349:     PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
299.349:     PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
299.349:     PCI: 00:11.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 24
299.349:     PCI: 00:12.0
299.349:     PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
299.349:     PCI: 00:12.1
299.349:     PCI: 00:12.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
299.349:     PCI: 00:12.2
299.349:     PCI: 00:12.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
299.349:     PCI: 00:13.0
299.349:     PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
299.349:     PCI: 00:13.1
299.349:     PCI: 00:13.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
299.349:     PCI: 00:13.2
299.349:     PCI: 00:13.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
299.350:     PCI: 00:14.0 child on link 0 I2C: 01:50
299.350:     PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
299.350:     PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c
299.350:     PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
299.350:     PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
299.350:     PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58
299.350:      I2C: 01:50
299.350:      I2C: 01:51
299.350:      I2C: 01:52
299.350:      I2C: 01:53
299.350:      I2C: 01:54
299.350:      I2C: 01:55
299.350:      I2C: 01:56
299.350:      I2C: 01:57
299.350:      I2C: 01:2f
299.350:     PCI: 00:14.1
299.350:     PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
299.350:     PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
299.350:     PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
299.350:     PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
299.350:     PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
299.350:     PCI: 00:14.2
299.350:     PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
299.350:     PCI: 00:14.3 child on link 0 PNP: 002e.0
299.350:     PCI: 00:14.3 resource base 0 size 1 align 12 gran 0 limit ffffffff flags 200 index a0
299.350:     PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
299.350:     PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
299.350:     PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
299.350:      PNP: 002e.0
299.350:      PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
299.350:      PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
299.350:      PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
299.350:      PNP: 002e.1
299.350:      PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
299.350:      PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
299.350:      PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
299.350:      PNP: 002e.2
299.350:      PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
299.350:      PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
299.350:      PNP: 002e.3
299.350:      PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
299.350:      PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
299.350:      PNP: 002e.5
299.350:      PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
299.350:      PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
299.350:      PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
299.350:      PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72
299.350:      PNP: 002e.106
299.350:      PNP: 002e.106 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
299.350:      PNP: 002e.107
299.350:      PNP: 002e.207
299.350:      PNP: 002e.307
299.350:      PNP: 002e.407
299.350:      PNP: 002e.8
299.350:      PNP: 002e.108
299.350:      PNP: 002e.9
299.350:      PNP: 002e.109
299.351:      PNP: 002e.209
299.351:      PNP: 002e.309
299.351:      PNP: 002e.a
299.351:      PNP: 002e.b
299.351:      PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags c0000100 index 60
299.351:      PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
299.351:      PNP: 002e.c
299.351:      PNP: 002e.d
299.351:      PNP: 002e.f
299.351:      PNP: 004e.0
299.351:     PCI: 00:14.4 child on link 0 PCI: 08:01.0
299.351:     PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
299.351:     PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
299.351:     PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
299.351:      PCI: 08:01.0
299.351:      PCI: 08:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffff flags 200 index 10
299.351:      PCI: 08:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 14
299.351:      PCI: 08:01.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 18
299.351:      PCI: 08:02.0
299.351:      PCI: 08:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
299.351:      PCI: 08:03.0
299.351:     PCI: 00:14.5
299.351:     PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
299.351:    PCI: 00:18.1
299.351:    PCI: 00:18.2
299.351:    PCI: 00:18.3
299.351:    PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
299.351:    PCI: 00:18.4
299.351:    PCI: 00:18.5
299.351:    PCI: 00:19.0
299.351:    PCI: 00:19.1
299.351:    PCI: 00:19.2
299.351:    PCI: 00:19.3
299.351:    PCI: 00:19.4
299.351:    PCI: 00:19.5
299.351:    PCI: 00:1a.0
299.351:    PCI: 00:1a.1
299.351:    PCI: 00:1a.2
299.351:    PCI: 00:1a.3
299.351:    PCI: 00:1a.4
299.352:    PCI: 00:1a.5
299.352:    PCI: 00:1b.0
299.352:    PCI: 00:1b.1
299.352:    PCI: 00:1b.2
299.352:    PCI: 00:1b.3
299.352:    PCI: 00:1b.4
299.352:    PCI: 00:1b.5
299.352: DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
299.352: PCI: 00:18.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
299.352: PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
299.352: PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
299.352: PCI: 00:04.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
299.352: PCI: 00:04.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
299.352: PCI: 00:09.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
299.352: PCI: 03:00.0 18 *  [0x0 - 0x1f] io
299.352: PCI: 00:09.0 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
299.352: PCI: 00:0a.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
299.352: PCI: 04:00.0 18 *  [0x0 - 0x1f] io
299.352: PCI: 00:0a.0 io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done
299.352: PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
299.352: PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
299.352: PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
299.352: PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
299.352: PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
299.352: PCI: 07:00.0 18 *  [0x0 - 0x1f] io
299.352: PCI: 07:00.1 18 *  [0x20 - 0x3f] io
299.352: PCI: 00:0d.0 io: base: 40 size: 1000 align: 12 gran: 12 limit: ffff done
299.352: PCI: 00:14.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
299.352: PCI: 08:01.0 18 *  [0x0 - 0x7f] io
299.352: PCI: 00:14.4 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done
299.352: PCI: 00:09.0 1c *  [0x0 - 0xfff] io
299.352: PCI: 00:0a.0 1c *  [0x1000 - 0x1fff] io
299.352: PCI: 00:0d.0 1c *  [0x2000 - 0x2fff] io
299.352: PCI: 00:14.4 1c *  [0x3000 - 0x3fff] io
299.352: PCI: 00:11.0 20 *  [0x4000 - 0x400f] io
299.352: PCI: 00:14.1 20 *  [0x4010 - 0x401f] io
299.352: PCI: 00:11.0 10 *  [0x4020 - 0x4027] io
299.352: PCI: 00:11.0 18 *  [0x4028 - 0x402f] io
299.352: PCI: 00:14.1 10 *  [0x4030 - 0x4037] io
299.352: PCI: 00:14.1 18 *  [0x4038 - 0x403f] io
299.352: PCI: 00:11.0 14 *  [0x4040 - 0x4043] io
299.352: PCI: 00:11.0 1c *  [0x4044 - 0x4047] io
299.352: PCI: 00:14.1 14 *  [0x4048 - 0x404b] io
299.352: PCI: 00:14.1 1c *  [0x404c - 0x404f] io
299.352: PCI: 00:18.0 io: base: 4050 size: 5000 align: 12 gran: 12 limit: ffff done
299.352: PCI: 00:18.0 110d8 *  [0x0 - 0x4fff] io
299.352: DOMAIN: 0000 io: base: 5000 size: 5000 align: 12 gran: 0 limit: ffff done
299.352: DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
299.352: PCI: 00:18.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
299.352: PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
299.352: PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
299.352: PCI: 00:04.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
299.352: PCI: 00:04.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
299.352: PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
299.352: PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
299.352: PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
299.352: PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
299.352: PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
299.352: PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
299.352: PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
299.352: PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
299.352: PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
299.352: PCI: 07:00.0 10 *  [0x0 - 0x7ffff] prefmem
299.352: PCI: 07:00.1 10 *  [0x80000 - 0xfffff] prefmem
299.352: PCI: 07:00.0 20 *  [0x100000 - 0x103fff] prefmem
299.352: PCI: 07:00.1 20 *  [0x104000 - 0x107fff] prefmem
299.352: PCI: 00:0d.0 prefmem: base: 108000 size: 200000 align: 20 gran: 20 limit: ffffffffffffffff done
299.353: PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
299.352: PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
299.352: PCI: 00:0d.0 24 *  [0x0 - 0x1fffff] prefmem
299.352: PCI: 00:00.0 fc *  [0x200000 - 0x2000ff] prefmem
299.352: PCI: 00:18.0 prefmem: base: 200100 size: 300000 align: 20 gran: 20 limit: ffffffff done
299.352: PCI: 00:18.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
299.353: PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
299.353: PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
299.353: PCI: 00:04.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
299.353: PCI: 00:04.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
299.353: PCI: 00:09.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
299.353: PCI: 03:00.0 10 *  [0x0 - 0x1ffff] mem
299.353: PCI: 03:00.0 1c *  [0x20000 - 0x23fff] mem
299.353: PCI: 00:09.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
299.353: PCI: 00:0a.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
299.353: PCI: 04:00.0 10 *  [0x0 - 0x1ffff] mem
299.353: PCI: 04:00.0 1c *  [0x20000 - 0x23fff] mem
299.353: PCI: 00:0a.0 mem: base: 24000 size: 100000 align: 20 gran: 20 limit: ffffffff done
299.353: PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
299.353: PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
299.353: PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
299.353: PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
299.353: PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
299.353: PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
299.353: PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
299.353: PCI: 08:01.0 10 *  [0x0 - 0x7fffff] mem
299.353: PCI: 08:01.0 14 *  [0x800000 - 0x81ffff] mem
299.353: PCI: 08:02.0 10 *  [0x820000 - 0x820fff] mem
299.353: PCI: 00:14.4 mem: base: 821000 size: 900000 align: 23 gran: 20 limit: ffffffff done
299.353: PCI: 00:14.4 20 *  [0x0 - 0x8fffff] mem
299.353: PCI: 00:09.0 20 *  [0x900000 - 0x9fffff] mem
299.353: PCI: 00:0a.0 20 *  [0xa00000 - 0xafffff] mem
299.353: PCI: 00:00.2 44 *  [0xb00000 - 0xb03fff] mem
299.353: PCI: 00:14.2 10 *  [0xb04000 - 0xb07fff] mem
299.353: PCI: 00:12.0 10 *  [0xb08000 - 0xb08fff] mem
299.353: PCI: 00:12.1 10 *  [0xb09000 - 0xb09fff] mem
299.353: PCI: 00:13.0 10 *  [0xb0a000 - 0xb0afff] mem
299.353: PCI: 00:13.1 10 *  [0xb0b000 - 0xb0bfff] mem
299.353: PCI: 00:14.5 10 *  [0xb0c000 - 0xb0cfff] mem
299.353: PCI: 00:11.0 24 *  [0xb0d000 - 0xb0d3ff] mem
299.353: PCI: 00:12.2 10 *  [0xb0e000 - 0xb0e0ff] mem
299.353: PCI: 00:13.2 10 *  [0xb0f000 - 0xb0f0ff] mem
299.353: PCI: 00:14.3 a0 *  [0xb10000 - 0xb10000] mem
299.353: PCI: 00:18.0 mem: base: b10001 size: c00000 align: 23 gran: 20 limit: ffffffff done
299.353: PCI: 00:18.3 94 *  [0x0 - 0x3ffffff] mem
299.353: PCI: 00:18.0 110b8 *  [0x4000000 - 0x4bfffff] mem
299.353: PCI: 00:18.0 110b0 *  [0x4c00000 - 0x4efffff] prefmem
299.353: DOMAIN: 0000 mem: base: 4f00000 size: 4f00000 align: 26 gran: 0 limit: ffffffff done
299.353: avoid_fixed_resources: DOMAIN: 0000
299.353: avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
299.353: avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
299.353: constrain_resources: DOMAIN: 0000 c0010058 base c0000000 limit cfffffff mem (fixed)
299.353: constrain_resources: DOMAIN: 0000 07 base 00000000 limit bfffffff mem (fixed)
299.353: constrain_resources: DOMAIN: 0000 08 base 4038000000 limit 403fffffff mem (fixed)
299.353: constrain_resources: PCI: 00:14.0 74 base fec00000 limit fec00fff mem (fixed)
299.353: constrain_resources: PCI: 00:14.0 b4 base fed00000 limit fed003ff mem (fixed)
299.353: constrain_resources: PCI: 00:14.0 90 base 00000b00 limit 00000b0f io (fixed)
299.353: constrain_resources: PCI: 00:14.0 58 base 00000b20 limit 00000b2f io (fixed)
299.353: constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed)
299.353: constrain_resources: PCI: 00:14.3 10000100 base ff800000 limit ffffffff mem (fixed)
299.353: avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff
299.353: avoid_fixed_resources:@DOMAIN: 0000 10000100 base f8000000 limit ffffffff
299.353: Setting resources...
299.353: DOMAIN: 0000 io: base:1000 size:5000 align:12 gran:0 limit:ffff
299.353: PCI: 00:18.0 110d8 *  [0x1000 - 0x5fff] io
299.353: DOMAIN: 0000 io: next_base: 6000 size: 5000 align: 12 gran: 0 done
299.353: PCI: 00:18.0 io: base:1000 size:5000 align:12 gran:12 limit:5fff
299.353: PCI: 00:09.0 1c *  [0x1000 - 0x1fff] io
299.353: PCI: 00:0a.0 1c *  [0x2000 - 0x2fff] io
299.353: PCI: 00:0d.0 1c *  [0x3000 - 0x3fff] io
299.353: PCI: 00:14.4 1c *  [0x4000 - 0x4fff] io
299.353: PCI: 00:11.0 20 *  [0x5000 - 0x500f] io
299.353: PCI: 00:14.1 20 *  [0x5010 - 0x501f] io
299.353: PCI: 00:11.0 10 *  [0x5020 - 0x5027] io
299.353: PCI: 00:11.0 18 *  [0x5028 - 0x502f] io
299.353: PCI: 00:14.1 10 *  [0x5030 - 0x5037] io
299.353: PCI: 00:14.1 18 *  [0x5038 - 0x503f] io
299.353: PCI: 00:11.0 14 *  [0x5040 - 0x5043] io
299.353: PCI: 00:11.0 1c *  [0x5044 - 0x5047] io
299.353: PCI: 00:14.1 14 *  [0x5048 - 0x504b] io
299.353: PCI: 00:14.1 1c *  [0x504c - 0x504f] io
299.353: PCI: 00:18.0 io: next_base: 5050 size: 5000 align: 12 gran: 12 done
299.353: PCI: 00:02.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
299.353: PCI: 00:02.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
299.353: PCI: 00:04.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
299.353: PCI: 00:04.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
299.353: PCI: 00:09.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff
299.353: PCI: 03:00.0 18 *  [0x1000 - 0x101f] io
299.353: PCI: 00:09.0 io: next_base: 1020 size: 1000 align: 12 gran: 12 done
299.353: PCI: 00:0a.0 io: base:2000 size:1000 align:12 gran:12 limit:2fff
299.353: PCI: 04:00.0 18 *  [0x2000 - 0x201f] io
299.353: PCI: 00:0a.0 io: next_base: 2020 size: 1000 align: 12 gran: 12 done
299.353: PCI: 00:0b.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
299.353: PCI: 00:0b.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
299.353: PCI: 00:0c.0 io: base:5fff size:0 align:12 gran:12 limit:5fff
299.353: PCI: 00:0c.0 io: next_base: 5fff size: 0 align: 12 gran: 12 done
299.353: PCI: 00:0d.0 io: base:3000 size:1000 align:12 gran:12 limit:3fff
299.353: PCI: 07:00.0 18 *  [0x3000 - 0x301f] io
299.353: PCI: 07:00.1 18 *  [0x3020 - 0x303f] io
299.353: PCI: 00:0d.0 io: next_base: 3040 size: 1000 align: 12 gran: 12 done
299.353: PCI: 00:14.4 io: base:4000 size:1000 align:12 gran:12 limit:4fff
299.353: PCI: 08:01.0 18 *  [0x4000 - 0x407f] io
299.353: PCI: 00:14.4 io: next_base: 4080 size: 1000 align: 12 gran: 12 done
299.353: DOMAIN: 0000 mem: base:f8000000 size:4f00000 align:26 gran:0 limit:ffffffff
299.353: PCI: 00:18.3 94 *  [0xf8000000 - 0xfbffffff] mem
299.353: PCI: 00:18.0 110b8 *  [0xfc000000 - 0xfcbfffff] mem
299.354: PCI: 00:18.0 110b0 *  [0xfcc00000 - 0xfcefffff] prefmem
299.354: DOMAIN: 0000 mem: next_base: fcf00000 size: 4f00000 align: 26 gran: 0 done
299.353: PCI: 00:18.0 prefmem: base:fcc00000 size:300000 align:20 gran:20 limit:fcefffff
299.354: PCI: 00:0d.0 24 *  [0xfcc00000 - 0xfcdfffff] prefmem
299.354: PCI: 00:00.0 fc *  [0xfce00000 - 0xfce000ff] prefmem
299.354: PCI: 00:18.0 prefmem: next_base: fce00100 size: 300000 align: 20 gran: 20 done
299.354: PCI: 00:02.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
299.354: PCI: 00:02.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
299.354: PCI: 00:04.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
299.354: PCI: 00:04.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
299.354: PCI: 00:09.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
299.354: PCI: 00:09.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
299.354: PCI: 00:0a.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
299.354: PCI: 00:0a.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
299.354: PCI: 00:0b.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
299.354: PCI: 00:0b.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
299.354: PCI: 00:0c.0 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
299.354: PCI: 00:0c.0 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
299.354: PCI: 00:0d.0 prefmem: base:fcc00000 size:200000 align:20 gran:20 limit:fcdfffff
299.354: PCI: 07:00.0 10 *  [0xfcc00000 - 0xfcc7ffff] prefmem
299.354: PCI: 07:00.1 10 *  [0xfcc80000 - 0xfccfffff] prefmem
299.354: PCI: 07:00.0 20 *  [0xfcd00000 - 0xfcd03fff] prefmem
299.354: PCI: 07:00.1 20 *  [0xfcd04000 - 0xfcd07fff] prefmem
299.354: PCI: 00:0d.0 prefmem: next_base: fcd08000 size: 200000 align: 20 gran: 20 done
299.354: PCI: 00:14.4 prefmem: base:fcefffff size:0 align:20 gran:20 limit:fcefffff
299.354: PCI: 00:14.4 prefmem: next_base: fcefffff size: 0 align: 20 gran: 20 done
299.354: PCI: 00:18.0 mem: base:fc000000 size:c00000 align:23 gran:20 limit:fcbfffff
299.354: PCI: 00:14.4 20 *  [0xfc000000 - 0xfc8fffff] mem
299.354: PCI: 00:09.0 20 *  [0xfc900000 - 0xfc9fffff] mem
299.354: PCI: 00:0a.0 20 *  [0xfca00000 - 0xfcafffff] mem
299.354: PCI: 00:00.2 44 *  [0xfcb00000 - 0xfcb03fff] mem
299.354: PCI: 00:14.2 10 *  [0xfcb04000 - 0xfcb07fff] mem
299.354: PCI: 00:12.0 10 *  [0xfcb08000 - 0xfcb08fff] mem
299.354: PCI: 00:12.1 10 *  [0xfcb09000 - 0xfcb09fff] mem
299.354: PCI: 00:13.0 10 *  [0xfcb0a000 - 0xfcb0afff] mem
299.354: PCI: 00:13.1 10 *  [0xfcb0b000 - 0xfcb0bfff] mem
299.354: PCI: 00:14.5 10 *  [0xfcb0c000 - 0xfcb0cfff] mem
299.354: PCI: 00:11.0 24 *  [0xfcb0d000 - 0xfcb0d3ff] mem
299.354: PCI: 00:12.2 10 *  [0xfcb0e000 - 0xfcb0e0ff] mem
299.354: PCI: 00:13.2 10 *  [0xfcb0f000 - 0xfcb0f0ff] mem
299.354: PCI: 00:14.3 a0 *  [0xfcb10000 - 0xfcb10000] mem
299.354: PCI: 00:18.0 mem: next_base: fcb10001 size: c00000 align: 23 gran: 20 done
299.354: PCI: 00:02.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
299.354: PCI: 00:02.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
299.354: PCI: 00:04.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
299.354: PCI: 00:04.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
299.354: PCI: 00:09.0 mem: base:fc900000 size:100000 align:20 gran:20 limit:fc9fffff
299.354: PCI: 03:00.0 10 *  [0xfc900000 - 0xfc91ffff] mem
299.354: PCI: 03:00.0 1c *  [0xfc920000 - 0xfc923fff] mem
299.354: PCI: 00:09.0 mem: next_base: fc924000 size: 100000 align: 20 gran: 20 done
299.354: PCI: 00:0a.0 mem: base:fca00000 size:100000 align:20 gran:20 limit:fcafffff
299.354: PCI: 04:00.0 10 *  [0xfca00000 - 0xfca1ffff] mem
299.354: PCI: 04:00.0 1c *  [0xfca20000 - 0xfca23fff] mem
299.354: PCI: 00:0a.0 mem: next_base: fca24000 size: 100000 align: 20 gran: 20 done
299.354: PCI: 00:0b.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
299.354: PCI: 00:0b.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
299.354: PCI: 00:0c.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
299.354: PCI: 00:0c.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
299.354: PCI: 00:0d.0 mem: base:fcbfffff size:0 align:20 gran:20 limit:fcbfffff
299.354: PCI: 00:0d.0 mem: next_base: fcbfffff size: 0 align: 20 gran: 20 done
299.354: PCI: 00:14.4 mem: base:fc000000 size:900000 align:23 gran:20 limit:fc8fffff
299.354: PCI: 08:01.0 10 *  [0xfc000000 - 0xfc7fffff] mem
299.354: PCI: 08:01.0 14 *  [0xfc800000 - 0xfc81ffff] mem
299.354: PCI: 08:02.0 10 *  [0xfc820000 - 0xfc820fff] mem
299.354: PCI: 00:14.4 mem: next_base: fc821000 size: 900000 align: 23 gran: 20 done
299.354: Root Device assign_resources, bus 0 link: 0
299.354: 0: mmio_basek=00300000, basek=00400000, limitk=04100000
299.354: 1: mmio_basek=00300000, basek=04100000, limitk=08100000
299.354: 2: mmio_basek=00300000, basek=08100000, limitk=0c100000
299.354: 3: mmio_basek=00300000, basek=0c100000, limitk=10100000
299.354: DOMAIN: 0000 assign_resources, bus 0 link: 0
299.354: VGA: PCI: 00:18.0 (aka node 0) link 1 has VGA device
299.354: PCI: 00:18.0 111b8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem <node 0 link 1>
299.354: PCI: 00:18.0 110b0 <- [0x00fcc00000 - 0x00fcefffff] size 0x00300000 gran 0x14 prefmem <node 0 link 1>
299.354: PCI: 00:18.0 110b8 <- [0x00fc000000 - 0x00fcbfffff] size 0x00c00000 gran 0x14 mem <node 0 link 1>
299.354: PCI: 00:18.0 110d8 <- [0x0000001000 - 0x0000005fff] size 0x00005000 gran 0x0c io <node 0 link 1>
299.354: PCI: 00:18.0 assign_resources, bus 0 link: 1
299.354: PCI: 00:00.0 sr5690_set_resources
299.354: sr5690_set_resources: PCI: 00:00.0[0x1c] base = c0000000 limit = cfffffff
299.354: PCI: 00:00.0 c0010058 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x00 mem <mmconfig>
299.354: sr5690_set_resources: PCI: 00:18.1 <- index a8 base c00003 limit cfff90
299.354: PCI: 00:00.0 fc <- [0x00fce00000 - 0x00fce000ff] size 0x00000100 gran 0x08 prefmem
299.354: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.354: CBFS: Locating 'cmos_layout.bin'
299.354: CBFS: Found @ offset 2b0c0 size e88
299.355: PCI: 00:00.2 44 <- [0x00fcb00000 - 0x00fcb03fff] size 0x00004000 gran 0x0e mem
299.355: PCI: 00:02.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 01 io
299.355: PCI: 00:02.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 01 prefmem
299.355: PCI: 00:02.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 01 mem
299.355: PCI: 00:04.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 02 io
299.355: PCI: 00:04.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 02 prefmem
299.355: PCI: 00:04.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 02 mem
299.355: PCI: 00:09.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io
299.355: PCI: 00:09.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 03 prefmem
299.355: PCI: 00:09.0 20 <- [0x00fc900000 - 0x00fc9fffff] size 0x00100000 gran 0x14 bus 03 mem
299.355: PCI: 00:09.0 assign_resources, bus 3 link: 0
299.355: PCI: 03:00.0 10 <- [0x00fc900000 - 0x00fc91ffff] size 0x00020000 gran 0x11 mem
299.355: PCI: 03:00.0 18 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io
299.355: PCI: 03:00.0 1c <- [0x00fc920000 - 0x00fc923fff] size 0x00004000 gran 0x0e mem
299.355: PCI: 00:09.0 assign_resources, bus 3 link: 0
299.355: PCI: 00:0a.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 04 io
299.355: PCI: 00:0a.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 04 prefmem
299.355: PCI: 00:0a.0 20 <- [0x00fca00000 - 0x00fcafffff] size 0x00100000 gran 0x14 bus 04 mem
299.355: PCI: 00:0a.0 assign_resources, bus 4 link: 0
299.355: PCI: 04:00.0 10 <- [0x00fca00000 - 0x00fca1ffff] size 0x00020000 gran 0x11 mem
299.355: PCI: 04:00.0 18 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io
299.355: PCI: 04:00.0 1c <- [0x00fca20000 - 0x00fca23fff] size 0x00004000 gran 0x0e mem
299.355: PCI: 00:0a.0 assign_resources, bus 4 link: 0
299.355: PCI: 00:0b.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 05 io
299.355: PCI: 00:0b.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 05 prefmem
299.355: PCI: 00:0b.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 05 mem
299.355: PCI: 00:0c.0 1c <- [0x0000005fff - 0x0000005ffe] size 0x00000000 gran 0x0c bus 06 io
299.355: PCI: 00:0c.0 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 06 prefmem
299.355: PCI: 00:0c.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 06 mem
299.355: PCI: 00:0d.0 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 07 io
299.355: PCI: 00:0d.0 24 <- [0x00fcc00000 - 0x00fcdfffff] size 0x00200000 gran 0x14 bus 07 prefmem
299.355: PCI: 00:0d.0 20 <- [0x00fcbfffff - 0x00fcbffffe] size 0x00000000 gran 0x14 bus 07 mem
299.355: PCI: 00:0d.0 assign_resources, bus 7 link: 0
299.355: PCI: 07:00.0 10 <- [0x00fcc00000 - 0x00fcc7ffff] size 0x00080000 gran 0x13 prefmem64
299.355: PCI: 07:00.0 18 <- [0x0000003000 - 0x000000301f] size 0x00000020 gran 0x05 io
299.355: PCI: 07:00.0 20 <- [0x00fcd00000 - 0x00fcd03fff] size 0x00004000 gran 0x0e prefmem64
299.355: PCI: 07:00.1 10 <- [0x00fcc80000 - 0x00fccfffff] size 0x00080000 gran 0x13 prefmem64
299.355: PCI: 07:00.1 18 <- [0x0000003020 - 0x000000303f] size 0x00000020 gran 0x05 io
299.355: PCI: 07:00.1 20 <- [0x00fcd04000 - 0x00fcd07fff] size 0x00004000 gran 0x0e prefmem64
299.355: PCI: 00:0d.0 assign_resources, bus 7 link: 0
299.355: PCI: 00:11.0 10 <- [0x0000005020 - 0x0000005027] size 0x00000008 gran 0x03 io
299.355: PCI: 00:11.0 14 <- [0x0000005040 - 0x0000005043] size 0x00000004 gran 0x02 io
299.355: PCI: 00:11.0 18 <- [0x0000005028 - 0x000000502f] size 0x00000008 gran 0x03 io
299.355: PCI: 00:11.0 1c <- [0x0000005044 - 0x0000005047] size 0x00000004 gran 0x02 io
299.355: PCI: 00:11.0 20 <- [0x0000005000 - 0x000000500f] size 0x00000010 gran 0x04 io
299.355: PCI: 00:11.0 24 <- [0x00fcb0d000 - 0x00fcb0d3ff] size 0x00000400 gran 0x0a mem
299.355: PCI: 00:12.0 10 <- [0x00fcb08000 - 0x00fcb08fff] size 0x00001000 gran 0x0c mem
299.355: PCI: 00:12.1 10 <- [0x00fcb09000 - 0x00fcb09fff] size 0x00001000 gran 0x0c mem
299.355: PCI: 00:12.2 10 <- [0x00fcb0e000 - 0x00fcb0e0ff] size 0x00000100 gran 0x08 mem
299.355: PCI: 00:13.0 10 <- [0x00fcb0a000 - 0x00fcb0afff] size 0x00001000 gran 0x0c mem
299.355: PCI: 00:13.1 10 <- [0x00fcb0b000 - 0x00fcb0bfff] size 0x00001000 gran 0x0c mem
299.355: PCI: 00:13.2 10 <- [0x00fcb0f000 - 0x00fcb0f0ff] size 0x00000100 gran 0x08 mem
299.355: PCI: 00:14.0 assign_resources, bus 1 link: 0
299.355: PCI: 00:14.0 assign_resources, bus 1 link: 0
299.355: PCI: 00:14.1 10 <- [0x0000005030 - 0x0000005037] size 0x00000008 gran 0x03 io
299.355: PCI: 00:14.1 14 <- [0x0000005048 - 0x000000504b] size 0x00000004 gran 0x02 io
299.355: PCI: 00:14.1 18 <- [0x0000005038 - 0x000000503f] size 0x00000008 gran 0x03 io
299.355: PCI: 00:14.1 1c <- [0x000000504c - 0x000000504f] size 0x00000004 gran 0x02 io
299.355: PCI: 00:14.1 20 <- [0x0000005010 - 0x000000501f] size 0x00000010 gran 0x04 io
299.355: PCI: 00:14.2 10 <- [0x00fcb04000 - 0x00fcb07fff] size 0x00004000 gran 0x0e mem64
299.355: PCI: 00:14.3 a0 <- [0x00fcb10000 - 0x00fcb10000] size 0x00000001 gran 0x00 mem
299.355: PCI: 00:14.3 assign_resources, bus 0 link: 0
299.355: PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
299.355: PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
299.355: PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
299.355: PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
299.355: PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
299.355: PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
299.356: PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
299.356: PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
299.356: PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io
299.356: ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned
299.356: PCI: 00:14.3 assign_resources, bus 0 link: 0
299.356: PCI: 00:14.4 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 08 io
299.356: PCI: 00:14.4 24 <- [0x00fcefffff - 0x00fceffffe] size 0x00000000 gran 0x14 bus 08 prefmem
299.356: PCI: 00:14.4 20 <- [0x00fc000000 - 0x00fc8fffff] size 0x00900000 gran 0x14 bus 08 mem
299.356: PCI: 00:14.4 assign_resources, bus 8 link: 0
299.356: PCI: 08:01.0 10 <- [0x00fc000000 - 0x00fc7fffff] size 0x00800000 gran 0x17 mem
299.356: PCI: 08:01.0 14 <- [0x00fc800000 - 0x00fc81ffff] size 0x00020000 gran 0x11 mem
299.356: PCI: 08:01.0 18 <- [0x0000004000 - 0x000000407f] size 0x00000080 gran 0x07 io
299.356: PCI: 08:02.0 10 <- [0x00fc820000 - 0x00fc820fff] size 0x00001000 gran 0x0c mem
299.356: PCI: 00:14.4 assign_resources, bus 8 link: 0
299.356: PCI: 00:14.5 10 <- [0x00fcb0c000 - 0x00fcb0cfff] size 0x00001000 gran 0x0c mem
299.356: PCI: 00:18.0 assign_resources, bus 0 link: 1
299.356: PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
299.356: PCI: 00:19.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
299.356: PCI: 00:1a.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
299.356: PCI: 00:1b.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
299.356: DOMAIN: 0000 assign_resources, bus 0 link: 0
299.356: Root Device assign_resources, bus 0 link: 0
299.356: Done setting resources.
299.356: Show resources in subtree (Root Device)...After assigning values.
299.356:  Root Device child on link 0 CPU_CLUSTER: 0
299.356:   CPU_CLUSTER: 0 child on link 0 APIC: 00
299.356:    APIC: 00
299.356:    APIC: 01
299.356:    APIC: 02
299.356:    APIC: 03
299.356:    APIC: 04
299.356:    APIC: 05
299.356:    APIC: 06
299.356:    APIC: 07
299.356:    APIC: 08
299.356:    APIC: 09
299.356:    APIC: 0a
299.356:    APIC: 0b
299.356:    APIC: 0c
299.356:    APIC: 0d
299.356:    APIC: 0e
299.356:    APIC: 0f
299.356:    APIC: 20
299.357:    APIC: 21
299.357:    APIC: 22
299.357:    APIC: 23
299.357:    APIC: 24
299.357:    APIC: 25
299.357:    APIC: 26
299.357:    APIC: 27
299.357:    APIC: 28
299.357:    APIC: 29
299.357:    APIC: 2a
299.357:    APIC: 2b
299.357:    APIC: 2c
299.357:    APIC: 2d
299.357:    APIC: 2e
299.357:    APIC: 2f
299.357:   DOMAIN: 0000 child on link 0 PCI: 00:18.0
299.357:   DOMAIN: 0000 resource base 1000 size 5000 align 12 gran 0 limit ffff flags 40040100 index 10000000
299.357:   DOMAIN: 0000 resource base f8000000 size 4f00000 align 26 gran 0 limit ffffffff flags 40040200 index 10000100
299.357:   DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
299.357:   DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7
299.357:   DOMAIN: 0000 resource base 4038000000 size 8000000 align 0 gran 0 limit 0 flags f0004200 index 8
299.357:   DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
299.357:   DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20
299.357:   DOMAIN: 0000 resource base 100000000 size f40000000 align 0 gran 0 limit 0 flags e0004200 index 30
299.357:   DOMAIN: 0000 resource base 1040000000 size 1000000000 align 0 gran 0 limit 0 flags e0004200 index 41
299.357:   DOMAIN: 0000 resource base 2040000000 size 1000000000 align 0 gran 0 limit 0 flags e0004200 index 52
299.357:   DOMAIN: 0000 resource base 3040000000 size 1000000000 align 0 gran 0 limit 0 flags e0004200 index 63
299.357:    PCI: 00:18.0
299.357:    PCI: 00:18.0 resource base fcc00000 size 300000 align 20 gran 20 limit fcefffff flags 60081200 index 110b0
299.357:    PCI: 00:18.0 resource base fc000000 size c00000 align 23 gran 20 limit fcbfffff flags 60080200 index 110b8
299.357:    PCI: 00:18.0 resource base 1000 size 5000 align 12 gran 12 limit 5fff flags 60080100 index 110d8
299.357:    PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags e0000200 index 111b8
299.357:     PCI: 00:00.0
299.357:     PCI: 00:00.0 resource base fce00000 size 100 align 12 gran 8 limit fce000ff flags 60001200 index fc
299.357:     PCI: 00:00.1
299.357:     PCI: 00:00.2
299.357:     PCI: 00:00.2 resource base fcb00000 size 4000 align 14 gran 14 limit fcb03fff flags 70000200 index 44
299.357:     PCI: 00:02.0
299.357:     PCI: 00:02.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
299.357:     PCI: 00:02.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
299.357:     PCI: 00:02.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
299.357:     PCI: 00:03.0
299.357:     PCI: 00:04.0
299.357:     PCI: 00:04.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
299.357:     PCI: 00:04.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
299.357:     PCI: 00:04.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
299.357:     PCI: 00:05.0
299.357:     PCI: 00:06.0
299.357:     PCI: 00:07.0
299.357:     PCI: 00:08.0
299.357:     PCI: 00:09.0 child on link 0 PCI: 03:00.0
299.358:     PCI: 00:09.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c
299.358:     PCI: 00:09.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
299.358:     PCI: 00:09.0 resource base fc900000 size 100000 align 20 gran 20 limit fc9fffff flags 60080202 index 20
299.358:      PCI: 03:00.0
299.358:      PCI: 03:00.0 resource base fc900000 size 20000 align 17 gran 17 limit fc91ffff flags 60000200 index 10
299.358:      PCI: 03:00.0 resource base 1000 size 20 align 5 gran 5 limit 101f flags 60000100 index 18
299.358:      PCI: 03:00.0 resource base fc920000 size 4000 align 14 gran 14 limit fc923fff flags 60000200 index 1c
299.358:     PCI: 00:0a.0 child on link 0 PCI: 04:00.0
299.358:     PCI: 00:0a.0 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c
299.358:     PCI: 00:0a.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
299.358:     PCI: 00:0a.0 resource base fca00000 size 100000 align 20 gran 20 limit fcafffff flags 60080202 index 20
299.358:      PCI: 04:00.0
299.358:      PCI: 04:00.0 resource base fca00000 size 20000 align 17 gran 17 limit fca1ffff flags 60000200 index 10
299.358:      PCI: 04:00.0 resource base 2000 size 20 align 5 gran 5 limit 201f flags 60000100 index 18
299.358:      PCI: 04:00.0 resource base fca20000 size 4000 align 14 gran 14 limit fca23fff flags 60000200 index 1c
299.358:     PCI: 00:0b.0
299.358:     PCI: 00:0b.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
299.358:     PCI: 00:0b.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
299.358:     PCI: 00:0b.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
299.358:     PCI: 00:0c.0
299.358:     PCI: 00:0c.0 resource base 5fff size 0 align 12 gran 12 limit 5fff flags 60080102 index 1c
299.358:     PCI: 00:0c.0 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
299.358:     PCI: 00:0c.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
299.358:     PCI: 00:0d.0 child on link 0 PCI: 07:00.0
299.358:     PCI: 00:0d.0 resource base 3000 size 1000 align 12 gran 12 limit 3fff flags 60080102 index 1c
299.358:     PCI: 00:0d.0 resource base fcc00000 size 200000 align 20 gran 20 limit fcdfffff flags 60081202 index 24
299.358:     PCI: 00:0d.0 resource base fcbfffff size 0 align 20 gran 20 limit fcbfffff flags 60080202 index 20
299.358:      PCI: 07:00.0
299.358:      PCI: 07:00.0 resource base fcc00000 size 80000 align 19 gran 19 limit fcc7ffff flags 60001201 index 10
299.358:      PCI: 07:00.0 resource base 3000 size 20 align 5 gran 5 limit 301f flags 60000100 index 18
299.358:      PCI: 07:00.0 resource base fcd00000 size 4000 align 14 gran 14 limit fcd03fff flags 60001201 index 20
299.358:      PCI: 07:00.1
299.358:      PCI: 07:00.1 resource base fcc80000 size 80000 align 19 gran 19 limit fccfffff flags 60001201 index 10
299.358:      PCI: 07:00.1 resource base 3020 size 20 align 5 gran 5 limit 303f flags 60000100 index 18
299.358:      PCI: 07:00.1 resource base fcd04000 size 4000 align 14 gran 14 limit fcd07fff flags 60001201 index 20
299.358:     PCI: 00:11.0
299.358:     PCI: 00:11.0 resource base 5020 size 8 align 3 gran 3 limit 5027 flags 60000100 index 10
299.358:     PCI: 00:11.0 resource base 5040 size 4 align 2 gran 2 limit 5043 flags 60000100 index 14
299.358:     PCI: 00:11.0 resource base 5028 size 8 align 3 gran 3 limit 502f flags 60000100 index 18
299.358:     PCI: 00:11.0 resource base 5044 size 4 align 2 gran 2 limit 5047 flags 60000100 index 1c
299.358:     PCI: 00:11.0 resource base 5000 size 10 align 4 gran 4 limit 500f flags 60000100 index 20
299.358:     PCI: 00:11.0 resource base fcb0d000 size 400 align 12 gran 10 limit fcb0d3ff flags 60000200 index 24
299.358:     PCI: 00:12.0
299.358:     PCI: 00:12.0 resource base fcb08000 size 1000 align 12 gran 12 limit fcb08fff flags 60000200 index 10
299.358:     PCI: 00:12.1
299.358:     PCI: 00:12.1 resource base fcb09000 size 1000 align 12 gran 12 limit fcb09fff flags 60000200 index 10
299.358:     PCI: 00:12.2
299.358:     PCI: 00:12.2 resource base fcb0e000 size 100 align 12 gran 8 limit fcb0e0ff flags 60000200 index 10
299.358:     PCI: 00:13.0
299.358:     PCI: 00:13.0 resource base fcb0a000 size 1000 align 12 gran 12 limit fcb0afff flags 60000200 index 10
299.358:     PCI: 00:13.1
299.358:     PCI: 00:13.1 resource base fcb0b000 size 1000 align 12 gran 12 limit fcb0bfff flags 60000200 index 10
299.358:     PCI: 00:13.2
299.358:     PCI: 00:13.2 resource base fcb0f000 size 100 align 12 gran 8 limit fcb0f0ff flags 60000200 index 10
299.358:     PCI: 00:14.0 child on link 0 I2C: 01:50
299.358:     PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
299.358:     PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c
299.358:     PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
299.358:     PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
299.358:     PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58
299.358:      I2C: 01:50
299.358:      I2C: 01:51
299.358:      I2C: 01:52
299.358:      I2C: 01:53
299.358:      I2C: 01:54
299.358:      I2C: 01:55
299.358:      I2C: 01:56
299.358:      I2C: 01:57
299.358:      I2C: 01:2f
299.358:     PCI: 00:14.1
299.359:     PCI: 00:14.1 resource base 5030 size 8 align 3 gran 3 limit 5037 flags 60000100 index 10
299.359:     PCI: 00:14.1 resource base 5048 size 4 align 2 gran 2 limit 504b flags 60000100 index 14
299.359:     PCI: 00:14.1 resource base 5038 size 8 align 3 gran 3 limit 503f flags 60000100 index 18
299.359:     PCI: 00:14.1 resource base 504c size 4 align 2 gran 2 limit 504f flags 60000100 index 1c
299.359:     PCI: 00:14.1 resource base 5010 size 10 align 4 gran 4 limit 501f flags 60000100 index 20
299.359:     PCI: 00:14.2
299.359:     PCI: 00:14.2 resource base fcb04000 size 4000 align 14 gran 14 limit fcb07fff flags 60000201 index 10
299.359:     PCI: 00:14.3 child on link 0 PNP: 002e.0
299.359:     PCI: 00:14.3 resource base fcb10000 size 1 align 12 gran 0 limit fcb10000 flags 60000200 index a0
299.359:     PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
299.359:     PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
299.359:     PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
299.359:      PNP: 002e.0
299.359:      PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
299.359:      PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
299.359:      PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
299.359:      PNP: 002e.1
299.359:      PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
299.359:      PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
299.359:      PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
299.359:      PNP: 002e.2
299.359:      PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
299.359:      PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
299.359:      PNP: 002e.3
299.359:      PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
299.359:      PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
299.359:      PNP: 002e.5
299.359:      PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
299.359:      PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
299.359:      PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
299.359:      PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72
299.359:      PNP: 002e.106
299.359:      PNP: 002e.106 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
299.359:      PNP: 002e.107
299.359:      PNP: 002e.207
299.359:      PNP: 002e.307
299.359:      PNP: 002e.407
299.359:      PNP: 002e.8
299.359:      PNP: 002e.108
299.359:      PNP: 002e.9
299.359:      PNP: 002e.109
299.359:      PNP: 002e.209
299.359:      PNP: 002e.309
299.359:      PNP: 002e.a
299.359:      PNP: 002e.b
299.359:      PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit fff flags e0000100 index 60
299.359:      PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
299.359:      PNP: 002e.c
299.359:      PNP: 002e.d
299.359:      PNP: 002e.f
299.359:      PNP: 004e.0
299.359:     PCI: 00:14.4 child on link 0 PCI: 08:01.0
299.359:     PCI: 00:14.4 resource base 4000 size 1000 align 12 gran 12 limit 4fff flags 60080102 index 1c
299.359:     PCI: 00:14.4 resource base fcefffff size 0 align 20 gran 20 limit fcefffff flags 60081202 index 24
299.359:     PCI: 00:14.4 resource base fc000000 size 900000 align 23 gran 20 limit fc8fffff flags 60080202 index 20
299.359:      PCI: 08:01.0
299.360:      PCI: 08:01.0 resource base fc000000 size 800000 align 23 gran 23 limit fc7fffff flags 60000200 index 10
299.359:      PCI: 08:01.0 resource base fc800000 size 20000 align 17 gran 17 limit fc81ffff flags 60000200 index 14
299.359:      PCI: 08:01.0 resource base 4000 size 80 align 7 gran 7 limit 407f flags 60000100 index 18
299.360:      PCI: 08:01.0 resource base a0000 size 1fc00 align 0 gran 0 limit 0 flags f0000200 index 3
299.360:      PCI: 08:02.0
299.360:      PCI: 08:02.0 resource base fc820000 size 1000 align 12 gran 12 limit fc820fff flags 60000200 index 10
299.360:      PCI: 08:03.0
299.360:     PCI: 00:14.5
299.360:     PCI: 00:14.5 resource base fcb0c000 size 1000 align 12 gran 12 limit fcb0cfff flags 60000200 index 10
299.360:    PCI: 00:18.1
299.360:    PCI: 00:18.2
299.360:    PCI: 00:18.3
299.360:    PCI: 00:18.3 resource base f8000000 size 4000000 align 26 gran 26 limit fbffffff flags 60000200 index 94
299.360:    PCI: 00:18.4
299.360:    PCI: 00:18.5
299.360:    PCI: 00:19.0
299.360:    PCI: 00:19.1
299.360:    PCI: 00:19.2
299.360:    PCI: 00:19.3
299.360:    PCI: 00:19.4
299.360:    PCI: 00:19.5
299.360:    PCI: 00:1a.0
299.360:    PCI: 00:1a.1
299.360:    PCI: 00:1a.2
299.360:    PCI: 00:1a.3
299.360:    PCI: 00:1a.4
299.360:    PCI: 00:1a.5
299.360:    PCI: 00:1b.0
299.360:    PCI: 00:1b.1
299.360:    PCI: 00:1b.2
299.360:    PCI: 00:1b.3
299.360:    PCI: 00:1b.4
299.360:    PCI: 00:1b.5
299.360: Done allocating resources.
299.360: BS: BS_DEV_RESOURCES times (us): entry 0 run 3292465 exit 0
299.360: Enabling resources...
299.360: PCI: 00:18.0 cmd <- 00
299.360: PCI: 00:18.1 subsystem <- 1043/8163
299.360: PCI: 00:18.1 cmd <- 00
299.360: PCI: 00:18.2 subsystem <- 1043/8163
299.360: PCI: 00:18.2 cmd <- 00
299.361: PCI: 00:18.3 cmd <- 00
299.361: PCI: 00:18.4 cmd <- 00
299.361: PCI: 00:18.5 cmd <- 00
299.361: PCI: 00:19.0 cmd <- 00
299.361: PCI: 00:19.1 subsystem <- 1043/8163
299.361: PCI: 00:19.1 cmd <- 00
299.361: PCI: 00:19.2 subsystem <- 1043/8163
299.361: PCI: 00:19.2 cmd <- 00
299.361: PCI: 00:19.3 cmd <- 00
299.361: PCI: 00:19.4 cmd <- 00
299.361: PCI: 00:19.5 cmd <- 00
299.361: PCI: 00:1a.0 cmd <- 00
299.361: PCI: 00:1a.1 subsystem <- 1043/8163
299.361: PCI: 00:1a.1 cmd <- 00
299.361: PCI: 00:1a.2 subsystem <- 1043/8163
299.361: PCI: 00:1a.2 cmd <- 00
299.361: PCI: 00:1a.3 cmd <- 00
299.361: PCI: 00:1a.4 cmd <- 00
299.361: PCI: 00:1a.5 cmd <- 00
299.361: PCI: 00:1b.0 cmd <- 00
299.361: PCI: 00:1b.1 subsystem <- 1043/8163
299.361: PCI: 00:1b.1 cmd <- 00
299.361: PCI: 00:1b.2 subsystem <- 1043/8163
299.361: PCI: 00:1b.2 cmd <- 00
299.361: PCI: 00:1b.3 cmd <- 00
299.361: PCI: 00:1b.4 cmd <- 00
299.361: PCI: 00:1b.5 cmd <- 00
299.361: PCI: 00:00.0 subsystem <- 1043/8163
299.361: PCI: 00:00.0 cmd <- 02
299.361: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.361: CBFS: Locating 'cmos_layout.bin'
299.361: CBFS: Found @ offset 2b0c0 size e88
299.362: Initializing IOMMU
299.362: PCI: 00:02.0 bridge ctrl <- 0003
299.362: PCI: 00:02.0 cmd <- 00
299.362: PCI: 00:04.0 bridge ctrl <- 0003
299.362: PCI: 00:04.0 cmd <- 00
299.362: PCI: 00:09.0 bridge ctrl <- 0003
299.362: PCI: 00:09.0 cmd <- 07
299.362: PCI: 00:0a.0 bridge ctrl <- 0003
299.362: PCI: 00:0a.0 cmd <- 07
299.362: PCI: 00:0b.0 bridge ctrl <- 0003
299.362: PCI: 00:0b.0 cmd <- 00
299.362: PCI: 00:0c.0 bridge ctrl <- 0003
299.362: PCI: 00:0c.0 cmd <- 00
299.362: PCI: 00:0d.0 bridge ctrl <- 0003
299.362: PCI: 00:0d.0 cmd <- 07
299.362: PCI: 00:11.0 subsystem <- 1043/8163
299.362: PCI: 00:11.0 cmd <- 03
299.362: PCI: 00:12.0 subsystem <- 1043/8163
299.362: PCI: 00:12.0 cmd <- 02
299.362: PCI: 00:12.1 subsystem <- 1043/8163
299.362: PCI: 00:12.1 cmd <- 02
299.362: PCI: 00:12.2 subsystem <- 1043/8163
299.362: PCI: 00:12.2 cmd <- 02
299.362: PCI: 00:13.0 subsystem <- 1043/8163
299.362: PCI: 00:13.0 cmd <- 02
299.362: PCI: 00:13.1 subsystem <- 1043/8163
299.362: PCI: 00:13.1 cmd <- 02
299.362: PCI: 00:13.2 subsystem <- 1043/8163
299.362: PCI: 00:13.2 cmd <- 02
299.362: PCI: 00:14.0 subsystem <- 1043/8163
299.362: PCI: 00:14.0 cmd <- 403
299.362: PCI: 00:14.1 subsystem <- 1043/8163
299.362: PCI: 00:14.1 cmd <- 01
299.362: PCI: 00:14.2 subsystem <- 1043/8163
299.362: PCI: 00:14.2 cmd <- 02
299.362: PCI: 00:14.3 subsystem <- 1043/8163
299.362: PCI: 00:14.3 cmd <- 0f
299.362: sb700 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff
299.362: sb700 lpc decode:PNP: 002e.3, base=0x000002f8, end=0x000002ff
299.362: sb700 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060
299.362: sb700 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064
299.362: sb700 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000291
299.362: PCI: 00:14.4 bridge ctrl <- 000b
299.362: PCI: 00:14.4 cmd <- 07
299.362: PCI: 00:14.5 subsystem <- 1043/8163
299.362: PCI: 00:14.5 cmd <- 02
299.362: PCI: 03:00.0 cmd <- 03
299.362: PCI: 04:00.0 cmd <- 03
299.362: PCI: 07:00.0 cmd <- 03
299.362: PCI: 07:00.1 cmd <- 03
299.362: PCI: 08:01.0 cmd <- 03
299.362: PCI: 08:02.0 subsystem <- 1043/8163
299.362: PCI: 08:02.0 cmd <- 02
299.362: done.
299.362: BS: BS_DEV_ENABLE times (us): entry 0 run 178711 exit 0
299.362: Initializing devices...
299.362: Root Device init ...
299.362: Root Device init finished in 1398 usecs
299.362: CPU_CLUSTER: 0 init ...
299.363: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.363: CBFS: Locating 'cmos_layout.bin'
299.363: CBFS: Found @ offset 2b0c0 size e88
299.363: Enabling probe filter
299.368: Enabling ATM mode
299.368: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.368: CBFS: Locating 'cmos_layout.bin'
299.368: CBFS: Found @ offset 2b0c0 size e88
299.369: start_eip=0x00001000, code_size=0x00000031
299.369: CPU1: stack_base 00150000, stack_end 00150ff8
299.369: Asserting INIT.
299.369: Waiting for send to finish...
299.369: +Deasserting INIT.
299.369: Waiting for send to finish...
299.369: +#startup loops: 1.
299.369: Sending STARTUP #1 to 1.
299.369: After apic_write.
299.369: Initializing CPU #1
299.369: Startup point 1.
299.369: Waiting for send to finish...
299.369: +CPU: vendor AMD device 600f12
299.369: After Startup.
299.369: CPU: family 15, model 01, stepping 02
299.369: CPU2: stack_base 0014f000, stack_end 0014fff8
299.370: nodeid = 00, coreid = 01
299.369: Asserting INIT.
299.370: Enabling cache
299.370: Waiting for send to finish...
299.370: +Deasserting INIT.
299.370: Waiting for send to finish...
299.370: +#startup loops: 1.
299.370: Sending STARTUP #1 to 2.
299.370: After apic_write.
299.370: Initializing CPU #2
299.370: Startup point 1.
299.370: Waiting for send to finish...
299.370: +CPU: vendor AMD device 600f12
299.370: After Startup.
299.370: CPU3: stack_base 0014e000, stack_end 0014eff8
299.370: CPU: family 15, model 01, stepping 02
299.370: Asserting INIT.
299.370: Waiting for send to finish...
299.370: +nodeid = 00, coreid = 02
299.370: Deasserting INIT.
299.370: Waiting for send to finish...
299.370: +Enabling cache
299.370: #startup loops: 1.
299.370: Sending STARTUP #1 to 3.
299.370: After apic_write.
299.370: CPU ID 0x80000001: 600f12
299.370: Startup point 1.
299.370: Waiting for send to finish...
299.370: +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
299.370: After Startup.
299.370: CPU4: stack_base 0014d000, stack_end 0014dff8
299.370: Initializing CPU #3
299.370: MTRR: Physical address space:
299.370: Asserting INIT.
299.370: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
299.370: Waiting for send to finish...
299.370: +CPU: vendor AMD device 600f12
299.370: Deasserting INIT.
299.370: 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
299.370: Waiting for send to finish...
299.370: +CPU: family 15, model 01, stepping 02
299.370: 0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6
299.370: #startup loops: 1.
299.370: Sending STARTUP #1 to 4.
299.370: 0x00000000c0000000 - 0x0000000100000000 size 0x40000000 type 0
299.370: After apic_write.
299.370: 0x0000000100000000 - 0x0000004040000000 size 0x3f40000000 type 6
299.370: Startup point 1.
299.370: Waiting for send to finish...
299.371: +nodeid = 00, coreid = 03
299.371: After Startup.
299.371: CPU5: stack_base 0014c000, stack_end 0014cff8
299.371: Enabling cache
299.371: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
299.371: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
299.371: Asserting INIT.
299.371: MTRR: Fixed MSR 0x259 0x0000000000000000
299.371: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
299.371: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
299.371: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
299.371: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
299.371: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
299.371: Waiting for send to finish...
299.371: +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
299.371: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
299.371: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
299.371: Deasserting INIT.
299.371: Waiting for send to finish...
299.371: +Initializing CPU #4
299.371: #startup loops: 1.
299.371: Sending STARTUP #1 to 5.
299.371: MTRR: default type WB/UC MTRR counts: 1/2.
299.371: After apic_write.
299.371: MTRR: WB selected as default type.
299.371: Startup point 1.
299.371: Waiting for send to finish...
299.371: +MTRR: 0 base 0x00000000c0000000 mask 0x0000ffffc0000000 type 0
299.371: After Startup.
299.371: CPU6: stack_base 0014b000, stack_end 0014bff8
299.371: 
299.371: MTRR check
299.371: Fixed MTRRs   : Enabled
299.371: Variable MTRRs: Enabled
299.371: Asserting INIT.
299.371: 
299.371: Waiting for send to finish...
299.371: Setting up local APIC...+ apic_id: 0x02 Deasserting INIT.
299.371: done.
299.371: Waiting for send to finish...
299.371: CPU model: AMD Opteron(tm) Processor 6278
299.371: +siblings = 15, #startup loops: 1.
299.371: Disabling SMM ASeg memory
299.371: Sending STARTUP #1 to 6.
299.371: 
299.371: MTRR check
299.371: Fixed MTRRs   : Enabled
299.371: Variable MTRRs: After apic_write.
299.371: Enabled
299.371: 
299.371: Startup point 1.
299.371: Waiting for send to finish...
299.371: +Setting up local APIC...After Startup.
299.371:  apic_id: 0x03 done.
299.371: CPU7: stack_base 0014a000, stack_end 0014aff8
299.371: CPU model: AMD Opteron(tm) Processor 6278
299.372: CPU #2 initialized
299.372: Asserting INIT.
299.372: siblings = 15, Waiting for send to finish...
299.372: +Disabling SMM ASeg memory
299.372: Deasserting INIT.
299.372: CPU #3 initialized
299.372: Waiting for send to finish...
299.372: +Initializing CPU #5
299.372: #startup loops: 1.
299.372: Sending STARTUP #1 to 7.
299.372: After apic_write.
299.372: CPU: vendor AMD device 600f12
299.372: Startup point 1.
299.372: Waiting for send to finish...
299.372: +CPU: vendor AMD device 600f12
299.372: After Startup.
299.372: CPU8: stack_base 00149000, stack_end 00149ff8
299.372: Initializing CPU #6
299.372: Asserting INIT.
299.372: Waiting for send to finish...
299.372: +CPU: vendor AMD device 600f12
299.372: Deasserting INIT.
299.372: Waiting for send to finish...
299.372: +CPU: family 15, model 01, stepping 02
299.372: #startup loops: 1.
299.372: Sending STARTUP #1 to 8.
299.372: After apic_write.
299.372: nodeid = 00, coreid = 04
299.372: Startup point 1.
299.372: Waiting for send to finish...
299.372: +CPU: family 15, model 01, stepping 02
299.372: After Startup.
299.372: CPU9: stack_base 00148000, stack_end 00148ff8
299.372: nodeid = 00, coreid = 05
299.372: Asserting INIT.
299.372: Waiting for send to finish...
299.372: +Enabling cache
299.372: Deasserting INIT.
299.372: Waiting for send to finish...
299.372: +CPU: family 15, model 01, stepping 02
299.372: #startup loops: 1.
299.372: Sending STARTUP #1 to 9.
299.372: After apic_write.
299.372: Initializing CPU #8
299.372: Startup point 1.
299.372: Waiting for send to finish...
299.372: +Enabling cache
299.372: After Startup.
299.372: CPU ID 0x80000001: 600f12
299.372: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
299.372: CPU10: stack_base 00147000, stack_end 00147ff8
299.372: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
299.373: Asserting INIT.
299.373: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
299.373: MTRR: Fixed MSR 0x259 0x0000000000000000
299.373: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
299.373: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
299.373: Waiting for send to finish...
299.373: +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
299.373: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
299.373: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
299.373: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
299.373: Deasserting INIT.
299.373: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
299.373: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
299.373: Waiting for send to finish...
299.373: +nodeid = 00, coreid = 06
299.373: #startup loops: 1.
299.373: Sending STARTUP #1 to 10.
299.373: 
299.373: MTRR check
299.373: Fixed MTRRs   : Enabled
299.373: Variable MTRRs: Enabled
299.373: 
299.373: After apic_write.
299.373: CPU: vendor AMD device 600f12
299.373: Startup point 1.
299.373: Waiting for send to finish...
299.373: Setting up local APIC...+ apic_id: 0x04 After Startup.
299.373: done.
299.373: CPU11: stack_base 00146000, stack_end 00146ff8
299.373: CPU model: AMD Opteron(tm) Processor 6278
299.373: Asserting INIT.
299.373: siblings = 15, Waiting for send to finish...
299.373: Disabling SMM ASeg memory
299.373: +
299.373: MTRR check
299.373: Fixed MTRRs   : Enabled
299.373: Deasserting INIT.
299.373: Variable MTRRs: Enabled
299.373: 
299.373: Waiting for send to finish...
299.373: +Setting up local APIC...CPU #4 initialized
299.373: #startup loops: 1.
299.373: Sending STARTUP #1 to 11.
299.373:  apic_id: 0x05 done.
299.373: After apic_write.
299.373: CPU model: AMD Opteron(tm) Processor 6278
299.373: Startup point 1.
299.373: Waiting for send to finish...
299.373: +siblings = 15, After Startup.
299.373: Disabling SMM ASeg memory
299.373: CPU12: stack_base 00145000, stack_end 00145ff8
299.373: CPU #5 initialized
299.373: Asserting INIT.
299.373: Waiting for send to finish...
299.374: +Initializing CPU #10
299.374: Deasserting INIT.
299.374: CPU: vendor AMD device 600f12
299.374: Waiting for send to finish...
299.374: +Initializing CPU #7
299.374: #startup loops: 1.
299.374: Sending STARTUP #1 to 12.
299.374: After apic_write.
299.374: Enabling cache
299.374: Startup point 1.
299.374: Waiting for send to finish...
299.374: +Initializing CPU #11
299.374: After Startup.
299.374: CPU13: stack_base 00144000, stack_end 00144ff8
299.374: CPU: vendor AMD device 600f12
299.374: Asserting INIT.
299.374: CPU: family 15, model 01, stepping 02
299.374: Waiting for send to finish...
299.374: +Initializing CPU #12
299.374: Deasserting INIT.
299.374: nodeid = 00, coreid = 07
299.374: Waiting for send to finish...
299.374: +Initializing CPU #9
299.374: CPU: family 15, model 01, stepping 02
299.374: #startup loops: 1.
299.374: Sending STARTUP #1 to 13.
299.374: After apic_write.
299.374: Enabling cache
299.374: Startup point 1.
299.374: CPU ID 0x80000001: 600f12
299.374: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
299.374: Waiting for send to finish...
299.374: +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
299.374: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
299.374: After Startup.
299.374: CPU14: stack_base 00143000, stack_end 00143ff8
299.374: MTRR: Fixed MSR 0x259 0x0000000000000000
299.374: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
299.374: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
299.374: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
299.374: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
299.374: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
299.374: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
299.374: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
299.374: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
299.374: Asserting INIT.
299.374: Waiting for send to finish...
299.374: +nodeid = 01, coreid = 00
299.374: Deasserting INIT.
299.374: 
299.374: MTRR check
299.374: Waiting for send to finish...
299.374: +Fixed MTRRs   : #startup loops: 1.
299.375: Sending STARTUP #1 to 14.
299.375: Enabled
299.375: Variable MTRRs: Enabled
299.375: After apic_write.
299.375: 
299.375: Initializing CPU #13
299.375: Startup point 1.
299.375: Waiting for send to finish...
299.375: +Setting up local APIC...After Startup.
299.375: CPU15: stack_base 00142000, stack_end 00142ff8
299.375:  apic_id: 0x06 done.
299.375: Asserting INIT.
299.375: CPU model: AMD Opteron(tm) Processor 6278
299.375: Waiting for send to finish...
299.375: +siblings = 15, Deasserting INIT.
299.375: Disabling SMM ASeg memory
299.375: Waiting for send to finish...
299.375: CPU #6 initialized
299.375: +
299.375: MTRR check
299.375: #startup loops: 1.
299.375: Sending STARTUP #1 to 15.
299.375: After apic_write.
299.375: Fixed MTRRs   : Enabled
299.375: Variable MTRRs: Startup point 1.
299.375: Enabled
299.375: Waiting for send to finish...
299.375: +
299.375: CPU: family 15, model 01, stepping 02
299.375: After Startup.
299.375: Setting up local APIC...CPU16: stack_base 00141000, stack_end 00141ff8
299.375:  apic_id: 0x07 done.
299.375: Asserting INIT.
299.375: CPU model: AMD Opteron(tm) Processor 6278
299.375: Waiting for send to finish...
299.375: +siblings = 15, Deasserting INIT.
299.375: Disabling SMM ASeg memory
299.375: Waiting for send to finish...
299.375: +CPU #7 initialized
299.375: #startup loops: 1.
299.375: Sending STARTUP #1 to 32.
299.375: After apic_write.
299.375: CPU: vendor AMD device 600f12
299.375: Startup point 1.
299.375: Waiting for send to finish...
299.375: +Initializing CPU #16
299.376: After Startup.
299.375: CPU17: stack_base 00140000, stack_end 00140ff8
299.375: CPU: vendor AMD device 600f12
299.376: Asserting INIT.
299.376: Initializing CPU #14
299.376: Waiting for send to finish...
299.376: +CPU: family 15, model 01, stepping 02
299.376: Deasserting INIT.
299.376: Waiting for send to finish...
299.376: +CPU: vendor AMD device 600f12
299.376: #startup loops: 1.
299.376: Sending STARTUP #1 to 33.
299.376: After apic_write.
299.376: CPU: family 15, model 01, stepping 02
299.376: Startup point 1.
299.376: Waiting for send to finish...
299.376: +Enabling cache
299.376: After Startup.
299.376: CPU18: stack_base 0013f000, stack_end 0013fff8
299.376: nodeid = 01, coreid = 02
299.376: CPU ID 0x80000001: 600f12
299.376: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
299.376: Asserting INIT.
299.376: Waiting for send to finish...
299.376: +Initializing CPU #15
299.376: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
299.376: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
299.376: MTRR: Fixed MSR 0x259 0x0000000000000000
299.376: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
299.376: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
299.376: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
299.376: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
299.376: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
299.376: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
299.376: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
299.376: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
299.376: Deasserting INIT.
299.376: nodeid = 02, coreid = 00
299.376: Waiting for send to finish...
299.376: +CPU: vendor AMD device 600f12
299.376: #startup loops: 1.
299.376: Sending STARTUP #1 to 34.
299.376: After apic_write.
299.376: nodeid = 01, coreid = 01
299.376: Startup point 1.
299.376: Waiting for send to finish...
299.376: +Initializing CPU #18
299.376: 
299.376: MTRR check
299.376: Fixed MTRRs   : Enabled
299.376: Variable MTRRs: Enabled
299.376: 
299.376: After Startup.
299.377: CPU19: stack_base 0013e000, stack_end 0013eff8
299.377: CPU: vendor AMD device 600f12
299.377: Setting up local APIC...Asserting INIT.
299.377: CPU: family 15, model 01, stepping 02
299.377: Waiting for send to finish...
299.377: +Enabling cache
299.377: Deasserting INIT.
299.377: Enabling cache
299.377:  apic_id: 0x08 done.
299.377: Waiting for send to finish...
299.377: +nodeid = 02, coreid = 02
299.377: CPU ID 0x80000001: 600f12
299.377: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
299.377: CPU: family 15, model 01, stepping 02
299.377: CPU ID 0x80000001: 600f12
299.377: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
299.377: #startup loops: 1.
299.377: Sending STARTUP #1 to 35.
299.377: After apic_write.
299.377: CPU: vendor AMD device 600f12
299.377: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
299.377: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
299.377: MTRR: Fixed MSR 0x259 0x0000000000000000
299.377: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
299.377: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
299.377: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
299.377: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
299.377: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
299.377: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
299.377: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
299.377: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
299.377: Startup point 1.
299.377: Waiting for send to finish...
299.377: +Enabling cache
299.377: CPU model: AMD Opteron(tm) Processor 6278
299.377: Initializing CPU #17
299.377: siblings = 15, After Startup.
299.377: CPU20: stack_base 0013d000, stack_end 0013dff8
299.377: Initializing CPU #19
299.377: CPU ID 0x80000001: 600f12
299.377: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
299.377: CPU: vendor AMD device 600f12
299.377: CPU: family 15, model 01, stepping 02
299.377: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
299.377: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
299.377: MTRR: Fixed MSR 0x259 0x0000000000000000
299.377: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
299.377: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
299.377: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
299.377: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
299.377: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
299.377: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
299.378: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
299.378: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
299.378: Asserting INIT.
299.378: CPU: vendor AMD device 600f12
299.378: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
299.378: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
299.378: MTRR: Fixed MSR 0x259 0x0000000000000000
299.378: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
299.378: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
299.378: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
299.378: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
299.378: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
299.378: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
299.378: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
299.378: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
299.378: Waiting for send to finish...
299.378: +Disabling SMM ASeg memory
299.378: 
299.378: MTRR check
299.378: Fixed MTRRs   : Enabled
299.378: Variable MTRRs: Enabled
299.378: 
299.378: Deasserting INIT.
299.378: CPU: family 15, model 01, stepping 02
299.378: 
299.378: MTRR check
299.378: Fixed MTRRs   : Enabled
299.378: Variable MTRRs: Enabled
299.378: 
299.378: Waiting for send to finish...
299.378: +nodeid = 02, coreid = 01
299.378: Setting up local APIC...#startup loops: 1.
299.378: Sending STARTUP #1 to 36.
299.378: After apic_write.
299.378: Enabling cache
299.378: 
299.378: MTRR check
299.378: Fixed MTRRs   : Enabled
299.378: Variable MTRRs: Enabled
299.378: 
299.378: Startup point 1.
299.378: Waiting for send to finish...
299.378: +
299.378: MTRR check
299.378: Fixed MTRRs   : Enabled
299.378: Variable MTRRs: Enabled
299.378: 
299.378: After Startup.
299.378: CPU21: stack_base 0013c000, stack_end 0013cff8
299.378: Setting up local APIC...CPU #8 initialized
299.378: Asserting INIT.
299.378:  apic_id: 0x09 done.
299.378: Waiting for send to finish...
299.378: +Initializing CPU #20
299.379:  apic_id: 0x22 done.
299.379: CPU model: AMD Opteron(tm) Processor 6278
299.379: Deasserting INIT.
299.379: siblings = 15, Waiting for send to finish...
299.379: +Disabling SMM ASeg memory
299.379: #startup loops: 1.
299.379: Sending STARTUP #1 to 37.
299.379: After apic_write.
299.379: CPU #9 initialized
299.379: Startup point 1.
299.379: Waiting for send to finish...
299.379: +Initializing CPU #21
299.379: CPU model: AMD Opteron(tm) Processor 6278
299.379: After Startup.
299.379: CPU22: stack_base 0013b000, stack_end 0013bff8
299.379: nodeid = 01, coreid = 06
299.379: Setting up local APIC...Asserting INIT.
299.379: Enabling cache
299.379:  apic_id: 0x0a done.
299.379: Waiting for send to finish...
299.379: +Setting up local APIC...Deasserting INIT.
299.379:  apic_id: 0x20 done.
299.379: Waiting for send to finish...
299.379: +CPU model: AMD Opteron(tm) Processor 6278
299.379: #startup loops: 1.
299.379: siblings = 15, Sending STARTUP #1 to 38.
299.379: After apic_write.
299.379: Disabling SMM ASeg memory
299.379: Startup point 1.
299.379: Waiting for send to finish...
299.379: +CPU #16 initialized
299.379: After Startup.
299.379: 
299.379: MTRR check
299.379: Fixed MTRRs   : Enabled
299.379: Variable MTRRs: Enabled
299.379: 
299.379: Initializing CPU #22
299.379: siblings = 15, Setting up local APIC...CPU: vendor AMD device 600f12
299.379:  apic_id: 0x21 done.
299.379: CPU23: stack_base 0013a000, stack_end 0013aff8
299.379: CPU model: AMD Opteron(tm) Processor 6278
299.379: Enabling cache
299.379: CPU model: AMD Opteron(tm) Processor 6278
299.379: siblings = 15, Asserting INIT.
299.380: Disabling SMM ASeg memory
299.380: Waiting for send to finish...
299.380: +CPU #17 initialized
299.380: Deasserting INIT.
299.380: CPU: family 15, model 01, stepping 02
299.380: Waiting for send to finish...
299.380: +CPU: vendor AMD device 600f12
299.380: CPU: vendor AMD device 600f12
299.380: siblings = 15, #startup loops: 1.
299.380: Sending STARTUP #1 to 39.
299.380: After apic_write.
299.380: CPU: family 15, model 01, stepping 02
299.380: CPU ID 0x80000001: 600f12
299.380: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
299.380: Startup point 1.
299.380: Waiting for send to finish...
299.380: +CPU: family 15, model 01, stepping 02
299.380: After Startup.
299.380: CPU24: stack_base 00139000, stack_end 00139ff8
299.380: CPU: vendor AMD device 600f12
299.380: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
299.380: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
299.380: MTRR: Fixed MSR 0x259 0x0000000000000000
299.380: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
299.380: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
299.380: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
299.380: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
299.380: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
299.380: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
299.380: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
299.380: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
299.380: Asserting INIT.
299.380: Disabling SMM ASeg memory
299.380: Waiting for send to finish...
299.380: +CPU: family 15, model 01, stepping 02
299.380: Deasserting INIT.
299.380: nodeid = 01, coreid = 03
299.380: 
299.380: MTRR check
299.380: Fixed MTRRs   : Enabled
299.380: Variable MTRRs: Enabled
299.380: 
299.380: Waiting for send to finish...
299.380: +Disabling SMM ASeg memory
299.380: Setting up local APIC...#startup loops: 1.
299.380: Sending STARTUP #1 to 40.
299.380: After apic_write.
299.380: Enabling cache
299.380:  apic_id: 0x0e 
299.380: MTRR check
299.380: Startup point 1.
299.380: Waiting for send to finish...
299.381: +Fixed MTRRs   : After Startup.
299.381: CPU25: stack_base 00138000, stack_end 00138ff8
299.381: CPU #10 initialized
299.381: Enabled
299.381: Variable MTRRs: Enabled
299.381: 
299.381: Asserting INIT.
299.381: CPU #18 initialized
299.381: Setting up local APIC...nodeid = 02, coreid = 03
299.381:  apic_id: 0x0b done.
299.381: Enabling cache
299.381: done.
299.381: Waiting for send to finish...
299.381: +CPU model: AMD Opteron(tm) Processor 6278
299.381: Deasserting INIT.
299.381: siblings = 15, 
299.381: MTRR check
299.381: Fixed MTRRs   : Enabled
299.381: Variable MTRRs: Enabled
299.381: 
299.381: Disabling SMM ASeg memory
299.381: Waiting for send to finish...
299.381: CPU #11 initialized
299.381: Setting up local APIC...+ apic_id: 0x23 done.
299.381: #startup loops: 1.
299.381: Sending STARTUP #1 to 41.
299.381: CPU model: AMD Opteron(tm) Processor 6278
299.381: After apic_write.
299.381: siblings = 15, Startup point 1.
299.381: Waiting for send to finish...
299.381: Disabling SMM ASeg memory
299.381: +CPU #19 initialized
299.381: After Startup.
299.381: CPU26: stack_base 00137000, stack_end 00137ff8
299.381: nodeid = 01, coreid = 07
299.381: CPU model: AMD Opteron(tm) Processor 6278
299.381: Asserting INIT.
299.381: Enabling cache
299.381: Waiting for send to finish...
299.381: siblings = 15, +Disabling SMM ASeg memory
299.381: Deasserting INIT.
299.381: 
299.381: MTRR check
299.381: Fixed MTRRs   : Enabled
299.381: Variable MTRRs: Enabled
299.381: 
299.381: Waiting for send to finish...
299.381: +Setting up local APIC...CPU #14 initialized
299.382: #startup loops: 1.
299.382: Sending STARTUP #1 to 42.
299.382: After apic_write.
299.382:  apic_id: 0x0f done.
299.382: Startup point 1.
299.382: Waiting for send to finish...
299.382: +CPU model: AMD Opteron(tm) Processor 6278
299.382: Initializing CPU #25
299.382: siblings = 15, After Startup.
299.382: CPU27: stack_base 00136000, stack_end 00136ff8
299.382: Disabling SMM ASeg memory
299.382: Asserting INIT.
299.382: CPU #15 initialized
299.382: Waiting for send to finish...
299.382: +Initializing CPU #26
299.382: Deasserting INIT.
299.382: Waiting for send to finish...
299.382: +CPU: family 15, model 01, stepping 02
299.382: #startup loops: 1.
299.382: Sending STARTUP #1 to 43.
299.382: After apic_write.
299.382: CPU: vendor AMD device 600f12
299.382: Startup point 1.
299.382: Waiting for send to finish...
299.382: +nodeid = 02, coreid = 04
299.382: After Startup.
299.382: CPU28: stack_base 00135000, stack_end 00135ff8
299.382: Initializing CPU #24
299.382: Asserting INIT.
299.382: Waiting for send to finish...
299.382: +Enabling cache
299.382: Deasserting INIT.
299.382: Waiting for send to finish...
299.382: +CPU: family 15, model 01, stepping 02
299.382: CPU: vendor AMD device 600f12
299.382: #startup loops: 1.
299.382: Sending STARTUP #1 to 44.
299.382: After apic_write.
299.382: CPU: vendor AMD device 600f12
299.382: CPU ID 0x80000001: 600f12
299.382: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
299.382: Startup point 1.
299.382: Waiting for send to finish...
299.382: +Initializing CPU #28
299.382: After Startup.
299.383: CPU29: stack_base 00134000, stack_end 00134ff8
299.383: CPU: vendor AMD device 600f12
299.383: Asserting INIT.
299.383: Initializing CPU #27
299.383: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
299.383: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
299.383: MTRR: Fixed MSR 0x259 0x0000000000000000
299.383: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
299.383: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
299.383: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
299.383: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
299.383: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
299.383: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
299.383: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
299.383: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
299.383: Waiting for send to finish...
299.383: +nodeid = 03, coreid = 02
299.383: Deasserting INIT.
299.383: CPU: family 15, model 01, stepping 02
299.383: Waiting for send to finish...
299.383: +CPU: family 15, model 01, stepping 02
299.383: #startup loops: 1.
299.383: Sending STARTUP #1 to 45.
299.383: After apic_write.
299.383: Initializing CPU #23
299.383: 
299.383: MTRR check
299.383: Fixed MTRRs   : Enabled
299.383: Variable MTRRs: Enabled
299.383: 
299.383: Startup point 1.
299.383: Waiting for send to finish...
299.383: +nodeid = 02, coreid = 05
299.383: After Startup.
299.383: CPU30: stack_base 00133000, stack_end 00133ff8
299.383: Enabling cache
299.383: Asserting INIT.
299.383: nodeid = 01, coreid = 05
299.383: Setting up local APIC...Waiting for send to finish...
299.383: +Enabling cache
299.383: CPU ID 0x80000001: 600f12
299.383: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
299.383: Deasserting INIT.
299.383: nodeid = 03, coreid = 00
299.383: CPU: vendor AMD device 600f12
299.383: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
299.383: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
299.383: MTRR: Fixed MSR 0x259 0x0000000000000000
299.383: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
299.383: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
299.383: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
299.383: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
299.383: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
299.384: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
299.383: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
299.384: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
299.384: Waiting for send to finish...
299.384: +Enabling cache
299.384: #startup loops: 1.
299.384: Sending STARTUP #1 to 46.
299.384: CPU: family 15, model 01, stepping 02
299.384: After apic_write.
299.384: nodeid = 01, coreid = 04
299.384: Startup point 1.
299.384: Waiting for send to finish...
299.384: +Enabling cache
299.384: CPU ID 0x80000001: 600f12
299.384: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
299.384: After Startup.
299.384: CPU31: stack_base 00132000, stack_end 00132ff8
299.384: CPU ID 0x80000001: 600f12
299.384: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
299.384: Initializing CPU #30
299.384: Asserting INIT.
299.384: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
299.384: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
299.384: MTRR: Fixed MSR 0x259 0x0000000000000000
299.384: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
299.384: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
299.384: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
299.384: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
299.384: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
299.384: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
299.384: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
299.384: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
299.384: Waiting for send to finish...
299.384: +CPU: vendor AMD device 600f12
299.384: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
299.384: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
299.384: MTRR: Fixed MSR 0x259 0x0000000000000000
299.384: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
299.384: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
299.384: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
299.384: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
299.384: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
299.384: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
299.384: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
299.384: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
299.384: 
299.384: MTRR check
299.384: Fixed MTRRs   : Enabled
299.384: Variable MTRRs: Enabled
299.384: 
299.384: Deasserting INIT.
299.384: CPU: vendor AMD device 600f12
299.384: 
299.384: MTRR check
299.384: Fixed MTRRs   : Enabled
299.384: Variable MTRRs: Enabled
299.384: 
299.384: Setting up local APIC...nodeid = 02, coreid = 06
299.385:  apic_id: 0x0c done.
299.385: CPU: family 15, model 01, stepping 02
299.385:  apic_id: 0x24 done.
299.385: CPU model: AMD Opteron(tm) Processor 6278
299.385: Waiting for send to finish...
299.385: +siblings = 15, #startup loops: 1.
299.385: Disabling SMM ASeg memory
299.385: nodeid = 03, coreid = 06
299.385: CPU model: AMD Opteron(tm) Processor 6278
299.385: Enabling cache
299.385: siblings = 15, Sending STARTUP #1 to 47.
299.385: CPU #12 initialized
299.385: 
299.385: MTRR check
299.385: Fixed MTRRs   : Enabled
299.385: Variable MTRRs: Enabled
299.385: 
299.385: CPU ID 0x80000001: 600f12
299.385: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
299.385: After apic_write.
299.385: Setting up local APIC...Enabling cache
299.385: 
299.385: MTRR check
299.385: Fixed MTRRs   : Enabled
299.385: Variable MTRRs: Enabled
299.385: 
299.385: Startup point 1.
299.385: Waiting for send to finish...
299.385: + apic_id: 0x0d done.
299.385: After Startup.
299.385: Initializing CPU #0
299.385: CPU model: AMD Opteron(tm) Processor 6278
299.385: CPU: vendor AMD device 600f12
299.385: CPU: family 15, model 01, stepping 02
299.385: siblings = 15, nodeid = 00, coreid = 00
299.385: Disabling SMM ASeg memory
299.385: Enabling cache
299.385: CPU #13 initialized
299.385: Initializing CPU #31
299.385: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
299.385: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
299.385: MTRR: Fixed MSR 0x259 0x0000000000000000
299.385: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
299.385: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
299.385: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
299.385: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
299.385: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
299.385: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
299.385: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
299.385: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
299.385: CPU ID 0x80000001: 600f12
299.385: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
299.385: Initializing CPU #29
299.386: Setting up local APIC...MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
299.386: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
299.386: MTRR: Fixed MSR 0x259 0x0000000000000000
299.386: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
299.386: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
299.386: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
299.386: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
299.386: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
299.386: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
299.386: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
299.386: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
299.386: CPU: family 15, model 01, stepping 02
299.386: Setting up local APIC...CPU: vendor AMD device 600f12
299.386: CPU: family 15, model 01, stepping 02
299.386: CPU ID 0x80000001: 600f12
299.386: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
299.386: 
299.386: MTRR check
299.386: Fixed MTRRs   : Enabled
299.386: Variable MTRRs: Enabled
299.386: 
299.386: nodeid = 03, coreid = 04
299.386: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
299.386: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
299.386: MTRR: Fixed MSR 0x259 0x0000000000000000
299.386: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
299.386: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
299.386: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
299.386: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
299.386: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
299.386: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
299.386: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
299.386: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
299.386: Setting up local APIC...CPU: vendor AMD device 600f12
299.386:  apic_id: 0x28 done.
299.386:  apic_id: 0x00 done.
299.386: Enabling cache
299.386: 
299.386: MTRR check
299.386: Fixed MTRRs   : Enabled
299.386: Variable MTRRs: Enabled
299.386: 
299.386: CPU model: AMD Opteron(tm) Processor 6278
299.386: Disabling SMM ASeg memory
299.386: siblings = 15, 
299.386: MTRR check
299.386: Fixed MTRRs   : Enabled
299.386: Variable MTRRs: Enabled
299.386: 
299.386: Disabling SMM ASeg memory
299.386: CPU #20 initialized
299.386: CPU #0 initialized
299.386: Waiting for 12 CPUS to stop
299.386: Setting up local APIC...
299.386: MTRR check
299.386: Fixed MTRRs   : Enabled
299.387: Variable MTRRs:  apic_id: 0x25 done.
299.387: Enabled
299.387: 
299.387: CPU model: AMD Opteron(tm) Processor 6278
299.387: Setting up local APIC...siblings = 15,  apic_id: 0x01 done.
299.387: Disabling SMM ASeg memory
299.387: CPU model: AMD Opteron(tm) Processor 6278
299.387: CPU #21 initialized
299.387: siblings = 15, Waiting for 11 CPUS to stop
299.387: Disabling SMM ASeg memory
299.387: CPU: family 15, model 01, stepping 02
299.387: Setting up local APIC...CPU #1 initialized
299.387: nodeid = 03, coreid = 03
299.387: 
299.387: MTRR check
299.387: Fixed MTRRs   : Enabled
299.387: Variable MTRRs: Enabled
299.387: 
299.387: Waiting for 10 CPUS to stop
299.387: CPU: family 15, model 01, stepping 02
299.387: nodeid = 03, coreid = 01
299.387: CPU model: AMD Opteron(tm) Processor 6278
299.387: Enabling cache
299.387: Setting up local APIC...Enabling cache
299.387: CPU: vendor AMD device 600f12
299.387: CPU ID 0x80000001: 600f12
299.387: CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
299.387: siblings = 15, CPU: family 15, model 01, stepping 02
299.387:  apic_id: 0x2a done.
299.387: Disabling SMM ASeg memory
299.387: Enabling cache
299.387: 
299.387: MTRR check
299.387: Fixed MTRRs   : Enabled
299.387: Variable MTRRs: CPU model: AMD Opteron(tm) Processor 6278
299.387: CPU #24 initialized
299.387: siblings = 15, Waiting for 9 CPUS to stop
299.387: Disabling SMM ASeg memory
299.387: Enabled
299.387: 
299.387: 
299.387: MTRR check
299.387: Fixed MTRRs   : Enabled
299.387: Variable MTRRs: Enabled
299.387: 
299.387: Setting up local APIC...nodeid = 03, coreid = 05
299.387:  apic_id: 0x2e done.
299.388: Setting up local APIC...CPU #26 initialized
299.388:  apic_id: 0x2b done.
299.388:  apic_id: 0x29 done.
299.388: Waiting for 8 CPUS to stop
299.388: CPU model: AMD Opteron(tm) Processor 6278
299.388: CPU model: AMD Opteron(tm) Processor 6278
299.388: siblings = 15, siblings = 15, Disabling SMM ASeg memory
299.388: Disabling SMM ASeg memory
299.388: CPU #27 initialized
299.388: CPU #25 initialized
299.388: Waiting for 7 CPUS to stop
299.388: Enabling cache
299.388: Waiting for 6 CPUS to stop
299.388: MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
299.388: MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
299.388: MTRR: Fixed MSR 0x259 0x0000000000000000
299.388: MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
299.388: MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
299.388: MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
299.388: MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
299.388: MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
299.388: MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
299.388: MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
299.388: MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
299.388: nodeid = 03, coreid = 07
299.388: CPU model: AMD Opteron(tm) Processor 6278
299.388: CPU: family 15, model 01, stepping 02
299.388:  apic_id: 0x26 done.
299.388: 
299.388: MTRR check
299.388: Fixed MTRRs   : Enabled
299.388: Variable MTRRs: Enabled
299.388: 
299.388: nodeid = 02, coreid = 07
299.388: siblings = 15, Setting up local APIC...Disabling SMM ASeg memory
299.388: CPU model: AMD Opteron(tm) Processor 6278
299.388:  apic_id: 0x2c done.
299.388: Enabling cache
299.388: siblings = 15, CPU model: AMD Opteron(tm) Processor 6278
299.388: 
299.388: MTRR check
299.388: Fixed MTRRs   : Enabled
299.388: Variable MTRRs: Enabled
299.388: 
299.388: siblings = 15, Enabling cache
299.388: Disabling SMM ASeg memory
299.388: CPU #30 initialized
299.388: 
299.388: MTRR check
299.388: Fixed MTRRs   : Enabled
299.388: Variable MTRRs: Setting up local APIC...CPU #28 initialized
299.389: Waiting for 5 CPUS to stop
299.389: Enabled
299.389: 
299.389:  apic_id: 0x2f done.
299.389: Disabling SMM ASeg memory
299.389: CPU model: AMD Opteron(tm) Processor 6278
299.389: 
299.389: MTRR check
299.389: Fixed MTRRs   : Setting up local APIC...Enabled
299.389: Variable MTRRs: Enabled
299.389: 
299.389: siblings = 15,  apic_id: 0x2d done.
299.389: Disabling SMM ASeg memory
299.389: CPU model: AMD Opteron(tm) Processor 6278
299.389: CPU #22 initialized
299.389: siblings = 15, CPU #31 initialized
299.389: Setting up local APIC...Waiting for 4 CPUS to stop
299.389: Disabling SMM ASeg memory
299.389:  apic_id: 0x27 done.
299.389: CPU #29 initialized
299.389: CPU model: AMD Opteron(tm) Processor 6278
299.389: Waiting for 2 CPUS to stop
299.389: siblings = 15, Waiting for 1 CPUS to stop
299.389: Disabling SMM ASeg memory
299.389: CPU #23 initialized
299.389: All AP CPUs stopped (20840 loops)
299.389: CPU0: stack: 00151000 - 00152000, lowest used address 001519e0, stack used: 1568 bytes
299.389: CPU1: stack: 00150000 - 00151000, lowest used address 00150de8, stack used: 536 bytes
299.389: CPU2: stack: 0014f000 - 00150000, lowest used address 0014fcac, stack used: 852 bytes
299.389: CPU3: stack: 0014e000 - 0014f000, lowest used address 0014ede8, stack used: 536 bytes
299.389: CPU4: stack: 0014d000 - 0014e000, lowest used address 0014dd08, stack used: 760 bytes
299.389: CPU5: stack: 0014c000 - 0014d000, lowest used address 0014cde8, stack used: 536 bytes
299.389: CPU6: stack: 0014b000 - 0014c000, lowest used address 0014bd08, stack used: 760 bytes
299.389: CPU7: stack: 0014a000 - 0014b000, lowest used address 0014ade8, stack used: 536 bytes
299.389: CPU8: stack: 00149000 - 0014a000, lowest used address 00149d08, stack used: 760 bytes
299.389: CPU9: stack: 00148000 - 00149000, lowest used address 00148de8, stack used: 536 bytes
299.389: CPU10: stack: 00147000 - 00148000, lowest used address 00147d08, stack used: 760 bytes
299.389: CPU11: stack: 00146000 - 00147000, lowest used address 00146de8, stack used: 536 bytes
299.389: CPU12: stack: 00145000 - 00146000, lowest used address 00145d08, stack used: 760 bytes
299.390: CPU13: stack: 00144000 - 00145000, lowest used address 00144de8, stack used: 536 bytes
299.390: CPU14: stack: 00143000 - 00144000, lowest used address 00143d08, stack used: 760 bytes
299.390: CPU15: stack: 00142000 - 00143000, lowest used address 00142de8, stack used: 536 bytes
299.390: CPU16: stack: 00141000 - 00142000, lowest used address 00141d08, stack used: 760 bytes
299.390: CPU17: stack: 00140000 - 00141000, lowest used address 00140de8, stack used: 536 bytes
299.390: CPU18: stack: 0013f000 - 00140000, lowest used address 0013fd08, stack used: 760 bytes
299.390: CPU19: stack: 0013e000 - 0013f000, lowest used address 0013ede8, stack used: 536 bytes
299.390: CPU20: stack: 0013d000 - 0013e000, lowest used address 0013dd08, stack used: 760 bytes
299.390: CPU21: stack: 0013c000 - 0013d000, lowest used address 0013cde8, stack used: 536 bytes
299.390: CPU22: stack: 0013b000 - 0013c000, lowest used address 0013bd08, stack used: 760 bytes
299.390: CPU23: stack: 0013a000 - 0013b000, lowest used address 0013ade8, stack used: 536 bytes
299.390: CPU24: stack: 00139000 - 0013a000, lowest used address 00139d08, stack used: 760 bytes
299.390: CPU25: stack: 00138000 - 00139000, lowest used address 00138de8, stack used: 536 bytes
299.390: CPU26: stack: 00137000 - 00138000, lowest used address 00137d08, stack used: 760 bytes
299.390: CPU27: stack: 00136000 - 00137000, lowest used address 00136de8, stack used: 536 bytes
299.390: CPU28: stack: 00135000 - 00136000, lowest used address 00135d08, stack used: 760 bytes
299.390: CPU29: stack: 00134000 - 00135000, lowest used address 00134de8, stack used: 536 bytes
299.390: CPU30: stack: 00133000 - 00134000, lowest used address 00133d08, stack used: 760 bytes
299.390: CPU31: stack: 00132000 - 00133000, lowest used address 00132de8, stack used: 536 bytes
299.390: CPU_CLUSTER: 0 init finished in 2100687 usecs
299.390: PCI: 00:18.0 init ...
299.390: PCI: 00:18.0 init finished in 1461 usecs
299.390: PCI: 00:18.1 init ...
299.390: PCI: 00:18.1 init finished in 1462 usecs
299.390: PCI: 00:18.2 init ...
299.390: PCI: 00:18.2 init finished in 1461 usecs
299.390: PCI: 00:18.3 init ...
299.390: NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.390: CBFS: Locating 'cmos_layout.bin'
299.391: CBFS: Found @ offset 2b0c0 size e88
299.391: done.
299.391: PCI: 00:18.3 init finished in 12592 usecs
299.391: PCI: 00:18.4 init ...
299.391: NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.391: CBFS: Locating 'cmos_layout.bin'
299.391: CBFS: Found @ offset 2b0c0 size e88
299.392: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.392: CBFS: Locating 'cmos_layout.bin'
299.392: CBFS: Found @ offset 2b0c0 size e88
299.392: done.
299.392: PCI: 00:18.4 init finished in 21323 usecs
299.393: PCI: 00:18.5 init ...
299.392: NB: Function 5 Northbridge Control.. done.
299.393: PCI: 00:18.5 init finished in 4260 usecs
299.393: PCI: 00:19.0 init ...
299.393: PCI: 00:19.0 init finished in 1462 usecs
299.393: PCI: 00:19.1 init ...
299.393: PCI: 00:19.1 init finished in 1462 usecs
299.393: PCI: 00:19.2 init ...
299.393: PCI: 00:19.2 init finished in 1462 usecs
299.393: PCI: 00:19.3 init ...
299.393: NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.393: CBFS: Locating 'cmos_layout.bin'
299.393: CBFS: Found @ offset 2b0c0 size e88
299.393: done.
299.393: PCI: 00:19.3 init finished in 12592 usecs
299.393: PCI: 00:19.4 init ...
299.393: NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.393: CBFS: Locating 'cmos_layout.bin'
299.394: CBFS: Found @ offset 2b0c0 size e88
299.394: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.394: CBFS: Locating 'cmos_layout.bin'
299.394: CBFS: Found @ offset 2b0c0 size e88
299.395: done.
299.395: PCI: 00:19.4 init finished in 21323 usecs
299.395: PCI: 00:19.5 init ...
299.395: NB: Function 5 Northbridge Control.. done.
299.395: PCI: 00:19.5 init finished in 4261 usecs
299.395: PCI: 00:1a.0 init ...
299.395: PCI: 00:1a.0 init finished in 1462 usecs
299.395: PCI: 00:1a.1 init ...
299.395: PCI: 00:1a.1 init finished in 1461 usecs
299.395: PCI: 00:1a.2 init ...
299.395: PCI: 00:1a.2 init finished in 1462 usecs
299.395: PCI: 00:1a.3 init ...
299.395: NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.395: CBFS: Locating 'cmos_layout.bin'
299.395: CBFS: Found @ offset 2b0c0 size e88
299.396: done.
299.396: PCI: 00:1a.3 init finished in 12593 usecs
299.396: PCI: 00:1a.4 init ...
299.396: NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.396: CBFS: Locating 'cmos_layout.bin'
299.396: CBFS: Found @ offset 2b0c0 size e88
299.396: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.396: CBFS: Locating 'cmos_layout.bin'
299.396: CBFS: Found @ offset 2b0c0 size e88
299.397: done.
299.397: PCI: 00:1a.4 init finished in 21317 usecs
299.397: PCI: 00:1a.5 init ...
299.397: NB: Function 5 Northbridge Control.. done.
299.397: PCI: 00:1a.5 init finished in 4260 usecs
299.397: PCI: 00:1b.0 init ...
299.397: PCI: 00:1b.0 init finished in 1462 usecs
299.397: PCI: 00:1b.1 init ...
299.397: PCI: 00:1b.1 init finished in 1462 usecs
299.397: PCI: 00:1b.2 init ...
299.397: PCI: 00:1b.2 init finished in 1461 usecs
299.397: PCI: 00:1b.3 init ...
299.397: NB: Function 3 Misc Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.397: CBFS: Locating 'cmos_layout.bin'
299.397: CBFS: Found @ offset 2b0c0 size e88
299.398: done.
299.398: PCI: 00:1b.3 init finished in 12592 usecs
299.398: PCI: 00:1b.4 init ...
299.398: NB: Function 4 Link Control.. CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.398: CBFS: Locating 'cmos_layout.bin'
299.398: CBFS: Found @ offset 2b0c0 size e88
299.399: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.399: CBFS: Locating 'cmos_layout.bin'
299.399: CBFS: Found @ offset 2b0c0 size e88
299.399: done.
299.399: PCI: 00:1b.4 init finished in 21323 usecs
299.399: PCI: 00:1b.5 init ...
299.399: NB: Function 5 Northbridge Control.. done.
299.399: PCI: 00:1b.5 init finished in 4261 usecs
299.399: PCI: 00:00.0 init ...
299.399: pcie_init in sr5650_ht.c
299.399: IOAPIC: Initializing IOAPIC at 0xfce00000
299.399: IOAPIC: Bootstrap Processor Local APIC = 0x00
299.399: IOAPIC: ID = 0x01
299.399: IOAPIC: Dumping registers
299.399:   reg 0x0000: 0x01000000
299.399:   reg 0x0001: 0x001f8021
299.399:   reg 0x0002: 0x00000000
299.399: IOAPIC: 32 interrupts
299.399: IOAPIC: Enabling interrupts on FSB
299.399: IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
299.399: IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
299.399: IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
299.399: IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
299.399: IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x00000018 value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x00000019 value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x0000001a value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x0000001b value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x0000001c value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x0000001d value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x0000001e value 0x00000000 0x00010000
299.400: IOAPIC: reg 0x0000001f value 0x00000000 0x00010000
299.400: PCI: 00:00.0 init finished in 125721 usecs
299.400: PCI: 00:11.0 init ...
299.400: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.400: CBFS: Locating 'cmos_layout.bin'
299.400: CBFS: Found @ offset 2b0c0 size e88
299.400: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.400: CBFS: Locating 'cmos_layout.bin'
299.401: CBFS: Found @ offset 2b0c0 size e88
299.401: rev_id=15
299.401: sata_bar0=5020
299.401: sata_bar1=5040
299.401: sata_bar2=5028
299.401: sata_bar3=5044
299.401: sata_bar4=5000
299.401: sata_bar5=fcb0d000
299.401: ide_bar0=5030
299.401: ide_bar1=5048
299.401: ide_bar2=5038
299.401: ide_bar3=504c
299.401: Maximum SATA port count supported by silicon: 6
299.413: SATA port 0 status = 23
299.413: 0x6=a0, 0x7=80
299.413: drive detection not yet completed, waiting...
299.423: 0x6=0, 0x7=50
299.423: drive no longer selected after 10 ms, retrying init
299.423: drive detection done after 0 ms
299.423: AHCI device 0 is ready after 2 tries
299.423: SATA port 1 status = 23
299.423: drive detection done after 0 ms
299.423: AHCI device 1 is ready after 1 tries
299.424: SATA port 2 status = 0
299.424: No AHCI SATA drive on Slot2
299.423: SATA port 3 status = 23
299.423: drive detection done after 0 ms
299.424: AHCI device 3 is ready after 1 tries
299.424: SATA port 4 status = 0
299.424: No AHCI SATA drive on Slot4
299.424: SATA port 5 status = 0
299.424: No AHCI SATA drive on Slot5
299.424: PCI: 00:11.0 init finished in 85673 usecs
299.424: PCI: 00:12.0 init ...
299.424: PCI: 00:12.0 init finished in 1484 usecs
299.424: PCI: 00:12.1 init ...
299.424: PCI: 00:12.1 init finished in 1483 usecs
299.424: PCI: 00:12.2 init ...
299.424: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.424: CBFS: Locating 'cmos_layout.bin'
299.424: CBFS: Found @ offset 2b0c0 size e88
299.425: usb2_bar0=0xfcb0e000
299.425: rpr 6.23, final dword=849e03c8
299.425: PCI: 00:12.2 init finished in 13779 usecs
299.425: PCI: 00:13.0 init ...
299.425: PCI: 00:13.0 init finished in 1484 usecs
299.425: PCI: 00:13.1 init ...
299.425: PCI: 00:13.1 init finished in 1485 usecs
299.425: PCI: 00:13.2 init ...
299.425: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.425: CBFS: Locating 'cmos_layout.bin'
299.425: CBFS: Found @ offset 2b0c0 size e88
299.426: usb2_bar0=0xfcb0f000
299.426: rpr 6.23, final dword=849e03c8
299.426: PCI: 00:13.2 init finished in 13779 usecs
299.426: PCI: 00:14.0 init ...
299.426: sm_init().
299.426: IOAPIC: Initializing IOAPIC at 0xfec00000
299.426: IOAPIC: Bootstrap Processor Local APIC = 0x00
299.426: IOAPIC: Dumping registers
299.426:   reg 0x0000: 0x00000000
299.426:   reg 0x0001: 0x00178021
299.426:   reg 0x0002: 0x00000000
299.426: IOAPIC: 24 interrupts
299.426: IOAPIC: Enabling interrupts on FSB
299.426: IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
299.426: IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
299.426: IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
299.426: IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
299.426: IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
299.426: IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
299.426: IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
299.426: IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
299.426: IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
299.426: IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
299.426: IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
299.426: IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
299.426: IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
299.426: IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
299.426: IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
299.426: IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
299.426: IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
299.426: IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
299.426: IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
299.426: IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
299.426: IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
299.426: IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
299.426: IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
299.426: IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
299.426: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.426: CBFS: Locating 'cmos_layout.bin'
299.426: CBFS: Found @ offset 2b0c0 size e88
299.427: WARNING: No CMOS option 'enable_legacy_usb'.
299.427: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.427: CBFS: Locating 'cmos_layout.bin'
299.427: CBFS: Found @ offset 2b0c0 size e88
299.427: set power "on" after power fail
299.427: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.427: CBFS: Locating 'cmos_layout.bin'
299.427: CBFS: Found @ offset 2b0c0 size e88
299.428: ++++++++++no set NMI+++++
299.428: RTC Init
299.428: sm_init() end
299.428: PCI: 00:14.0 init finished in 132049 usecs
299.428: PCI: 00:14.1 init ...
299.428: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.428: CBFS: Locating 'cmos_layout.bin'
299.428: CBFS: Found @ offset 2b0c0 size e88
299.429: PCI: 00:14.1 init finished in 10195 usecs
299.429: PCI: 00:14.2 init ...
299.429: base = 0xfcb04000
299.433: No codec!
299.433: PCI: 00:14.2 init finished in 6297 usecs
299.433: PCI: 00:14.3 init ...
299.433: lpc_init
299.433: PCI: 00:14.3 init finished in 2128 usecs
299.433: PCI: 00:14.4 init ...
299.433: PCI: 00:14.4 init finished in 1480 usecs
299.433: PCI: 00:14.5 init ...
299.433: PCI: 00:14.5 init finished in 1484 usecs
299.433: PCI: 03:00.0 init ...
299.433: PCI: 03:00.0 init finished in 1461 usecs
299.433: PCI: 04:00.0 init ...
299.433: PCI: 04:00.0 init finished in 1462 usecs
299.433: PCI: 07:00.0 init ...
299.433: PCI: 07:00.0 init finished in 1462 usecs
299.433: PCI: 07:00.1 init ...
299.433: PCI: 07:00.1 init finished in 1462 usecs
299.433: smbus: PCI: 00:14.0[0]->I2C: 01:2f init ...
299.433: Set SMBUS controller to channel 1
299.438: Found 64 pin W83795G Nuvoton H/W Monitor
299.721: W83795G/ADG work in Thermal Cruise Mode
299.721: Fan<09>CTFS(celsius)<09>TTTI(celsius)
299.724:  1<09>80<09>80
299.730:  2<09>80<09>80
299.735:  3<09>80<09>80
299.741:  4<09>80<09>80
299.746:  5<09>80<09>80
299.752:  6<09>80<09>80
299.757: DTS1 current value: 1a
299.760: DTS2 current value: 17
299.763: DTS3 current value: 0
299.766: DTS4 current value: 0
299.769: DTS5 current value: 0
299.771: DTS6 current value: 0
299.774: DTS7 current value: 0
299.777: DTS8 current value: 0
299.782: Set SMBUS controller to channel 0
299.782: I2C: 01:2f init finished in 283828 usecs
299.782: PNP: 002e.2 init ...
299.782: PNP: 002e.2 init finished in 1399 usecs
299.782: PNP: 002e.3 init ...
299.782: PNP: 002e.3 init finished in 1399 usecs
299.782: PNP: 002e.5 init ...
299.782: PNP: 002e.5 init finished in 1415 usecs
299.782: PNP: 002e.a init ...
299.782: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.782: CBFS: Locating 'cmos_layout.bin'
299.782: CBFS: Found @ offset 2b0c0 size e88
299.783: set power on after power fail
299.783: PNP: 002e.a init finished in 12038 usecs
299.783: PNP: 002e.b init ...
299.783: PNP: 002e.b init finished in 1399 usecs
299.783: PCI: 08:01.0 init ...
299.783: ASpeed AST2050: initializing video device
299.783: ast_detect_chip: AST 1100 detected
299.783: ast_detect_chip: VGA not enabled on entry, requesting chip POST
299.783: ast_detect_chip: Analog VGA only
299.783: ast_driver_load: dram 800000000 0 16 00800000
299.804: ASpeed VGA text mode initialized
299.804: PCI: 08:01.0 init finished in 33444 usecs
299.804: PCI: 08:02.0 init ...
299.804: PCI: 08:02.0 init finished in 1462 usecs
299.804: Devices initialized
299.804: Show all devs... After init.
299.804: Root Device: enabled 1
299.804: CPU_CLUSTER: 0: enabled 1
299.804: APIC: 00: enabled 1
299.804: DOMAIN: 0000: enabled 1
299.804: PCI: 00:18.0: enabled 1
299.804: PCI: 00:00.0: enabled 1
299.804: PCI: 00:00.1: enabled 0
299.805: PCI: 00:00.2: enabled 1
299.804: PCI: 00:02.0: enabled 1
299.805: PCI: 00:03.0: enabled 0
299.805: PCI: 00:04.0: enabled 1
299.805: PCI: 00:05.0: enabled 0
299.805: PCI: 00:06.0: enabled 0
299.805: PCI: 00:07.0: enabled 0
299.805: PCI: 00:08.0: enabled 0
299.805: PCI: 00:09.0: enabled 1
299.805: PCI: 00:0a.0: enabled 1
299.805: PCI: 00:0b.0: enabled 1
299.805: PCI: 00:0c.0: enabled 1
299.805: PCI: 00:0d.0: enabled 1
299.805: PCI: 00:11.0: enabled 1
299.805: PCI: 00:12.0: enabled 1
299.805: PCI: 00:12.1: enabled 1
299.805: PCI: 00:12.2: enabled 1
299.805: PCI: 00:13.0: enabled 1
299.805: PCI: 00:13.1: enabled 1
299.805: PCI: 00:13.2: enabled 1
299.805: PCI: 00:14.0: enabled 1
299.805: I2C: 01:50: enabled 1
299.805: I2C: 01:51: enabled 1
299.805: I2C: 01:52: enabled 1
299.805: I2C: 01:53: enabled 1
299.805: I2C: 01:54: enabled 1
299.805: I2C: 01:55: enabled 1
299.805: I2C: 01:56: enabled 1
299.805: I2C: 01:57: enabled 1
299.805: I2C: 01:2f: enabled 1
299.805: PCI: 00:14.1: enabled 1
299.805: PCI: 00:14.2: enabled 1
299.805: PCI: 00:14.3: enabled 1
299.805: PNP: 002e.0: enabled 0
299.805: PNP: 002e.1: enabled 0
299.805: PNP: 002e.2: enabled 1
299.805: PNP: 002e.3: enabled 1
299.805: PNP: 002e.5: enabled 1
299.805: PNP: 002e.106: enabled 0
299.805: PNP: 002e.107: enabled 0
299.805: PNP: 002e.207: enabled 0
299.805: PNP: 002e.307: enabled 0
299.805: PNP: 002e.407: enabled 0
299.805: PNP: 002e.8: enabled 0
299.805: PNP: 002e.108: enabled 0
299.805: PNP: 002e.9: enabled 0
299.805: PNP: 002e.109: enabled 0
299.805: PNP: 002e.209: enabled 0
299.805: PNP: 002e.309: enabled 0
299.805: PNP: 002e.a: enabled 1
299.805: PNP: 002e.b: enabled 1
299.805: PNP: 002e.c: enabled 0
299.805: PNP: 002e.d: enabled 0
299.805: PNP: 002e.f: enabled 0
299.805: PNP: 004e.0: enabled 1
299.805: PCI: 00:14.4: enabled 1
299.805: PCI: 08:01.0: enabled 1
299.805: PCI: 08:02.0: enabled 1
299.805: PCI: 08:03.0: enabled 0
299.805: PCI: 00:14.5: enabled 1
299.805: PCI: 00:18.1: enabled 1
299.805: PCI: 00:18.2: enabled 1
299.805: PCI: 00:18.3: enabled 1
299.805: PCI: 00:18.4: enabled 1
299.805: PCI: 00:18.5: enabled 1
299.805: PCI: 00:19.0: enabled 1
299.805: PCI: 00:19.1: enabled 1
299.805: PCI: 00:19.2: enabled 1
299.805: PCI: 00:19.3: enabled 1
299.805: PCI: 00:19.4: enabled 1
299.805: PCI: 00:19.5: enabled 1
299.805: PCI: 00:1a.0: enabled 1
299.805: PCI: 00:1a.1: enabled 1
299.805: PCI: 00:1a.2: enabled 1
299.806: PCI: 00:1a.3: enabled 1
299.806: PCI: 00:1a.4: enabled 1
299.806: PCI: 00:1a.5: enabled 1
299.806: PCI: 00:1b.0: enabled 1
299.806: PCI: 00:1b.1: enabled 1
299.806: PCI: 00:1b.2: enabled 1
299.806: PCI: 00:1b.3: enabled 1
299.806: PCI: 00:1b.4: enabled 1
299.806: PCI: 00:1b.5: enabled 1
299.806: APIC: 01: enabled 1
299.806: APIC: 02: enabled 1
299.806: APIC: 03: enabled 1
299.806: APIC: 04: enabled 1
299.806: APIC: 05: enabled 1
299.806: APIC: 06: enabled 1
299.806: APIC: 07: enabled 1
299.806: APIC: 08: enabled 1
299.806: APIC: 09: enabled 1
299.806: APIC: 0a: enabled 1
299.806: APIC: 0b: enabled 1
299.806: APIC: 0c: enabled 1
299.806: APIC: 0d: enabled 1
299.806: APIC: 0e: enabled 1
299.806: APIC: 0f: enabled 1
299.806: APIC: 20: enabled 1
299.806: APIC: 21: enabled 1
299.806: APIC: 22: enabled 1
299.806: APIC: 23: enabled 1
299.806: APIC: 24: enabled 1
299.806: APIC: 25: enabled 1
299.806: APIC: 26: enabled 1
299.806: APIC: 27: enabled 1
299.806: APIC: 28: enabled 1
299.806: APIC: 29: enabled 1
299.806: APIC: 2a: enabled 1
299.806: APIC: 2b: enabled 1
299.806: APIC: 2c: enabled 1
299.806: APIC: 2d: enabled 1
299.806: APIC: 2e: enabled 1
299.806: APIC: 2f: enabled 1
299.806: PCI: 03:00.0: enabled 1
299.806: PCI: 04:00.0: enabled 1
299.806: PCI: 07:00.0: enabled 1
299.806: PCI: 07:00.1: enabled 1
299.806: BS: BS_DEV_INIT times (us): entry 0 run 3346401 exit 0
299.806: Finalize devices...
299.806: Devices finalized
299.806: BS: BS_POST_DEVICE times (us): entry 0 run 2547 exit 0
299.806: BS: BS_OS_RESUME_CHECK times (us): entry 0 run 0 exit 0
299.806: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.806: CBFS: Locating 'cmos_layout.bin'
299.806: CBFS: Found @ offset 2b0c0 size e88
299.807: Writing IRQ routing tables to 0xf0000...done.
299.807: Writing IRQ routing tables to 0xb7cbe000...done.
299.807: PIRQ table: 48 bytes.
299.807: Wrote the mp table end at: 000f0410 - 000f08ac
299.807: Wrote the mp table end at: b7cbd010 - b7cbd4ac
299.807: MP table: 1196 bytes.
299.807: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.807: CBFS: Locating 'fallback/dsdt.aml'
299.807: CBFS: Found @ offset 2bf80 size 2608
299.807: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.807: CBFS: Locating 'fallback/slic'
299.808: CBFS: 'fallback/slic' not found.
299.808: ACPI: Writing ACPI tables at b7c99000.
299.808: ACPI:    * FACS
299.808: ACPI:    * DSDT
299.811: ACPI:    * FADT
299.811: pm_base: 0x0800
299.811: ACPI: added table 1/32, length now 40
299.811: ACPI:     * SSDT
299.811: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.811: CBFS: Locating 'cmos_layout.bin'
299.811: CBFS: Found @ offset 2b0c0 size e88
299.811: processor_brand=AMD Opteron(tm) Processor 6278
299.811: Pstates algorithm ...
299.812: Pstate_freq[0] = 2400MHz<09>Pstate_power[0] = 6150mw
299.812: Pstate_latency[0] = 5us
299.812: Pstate_freq[1] = 2100MHz<09>Pstate_power[1] = 5233mw
299.812: Pstate_latency[1] = 5us
299.812: Pstate_freq[2] = 1900MHz<09>Pstate_power[2] = 4620mw
299.812: Pstate_latency[2] = 5us
299.812: Pstate_freq[3] = 1600MHz<09>Pstate_power[3] = 3990mw
299.812: Pstate_latency[3] = 5us
299.812: Pstate_freq[4] = 1400MHz<09>Pstate_power[4] = 3422mw
299.812: Pstate_latency[4] = 5us
299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.812: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.812: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.812: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.812: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.812: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.813: PSS: 2400MHz power 6150 control 0x0 status 0x0
299.813: PSS: 2100MHz power 5233 control 0x1 status 0x1
299.813: PSS: 1900MHz power 4620 control 0x2 status 0x2
299.813: PSS: 1600MHz power 3990 control 0x3 status 0x3
299.813: PSS: 1400MHz power 3422 control 0x4 status 0x4
299.813: ACPI: added table 2/32, length now 44
299.813: ACPI:    * MCFG
299.813: ACPI: added table 3/32, length now 48
299.813: ACPI:    * TCPA
299.813: TCPA log created at b7c89000
299.813: ACPI: added table 4/32, length now 52
299.814: ACPI:    * MADT
299.814: ACPI: added table 5/32, length now 56
299.814: current = b7c9f410
299.814: ACPI:    * SRAT at b7c9f410
299.814: SRAT: lapic cpu_index=00, node_id=00, apic_id=00
299.814: SRAT: lapic cpu_index=01, node_id=00, apic_id=01
299.814: SRAT: lapic cpu_index=02, node_id=00, apic_id=02
299.814: SRAT: lapic cpu_index=03, node_id=00, apic_id=03
299.814: SRAT: lapic cpu_index=04, node_id=00, apic_id=04
299.814: SRAT: lapic cpu_index=05, node_id=00, apic_id=05
299.814: SRAT: lapic cpu_index=06, node_id=00, apic_id=06
299.814: SRAT: lapic cpu_index=07, node_id=00, apic_id=07
299.814: SRAT: lapic cpu_index=08, node_id=01, apic_id=08
299.814: SRAT: lapic cpu_index=09, node_id=01, apic_id=09
299.814: SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a
299.814: SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b
299.814: SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c
299.814: SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d
299.814: SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e
299.814: SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f
299.814: SRAT: lapic cpu_index=10, node_id=02, apic_id=20
299.814: SRAT: lapic cpu_index=11, node_id=02, apic_id=21
299.814: SRAT: lapic cpu_index=12, node_id=02, apic_id=22
299.814: SRAT: lapic cpu_index=13, node_id=02, apic_id=23
299.814: SRAT: lapic cpu_index=14, node_id=02, apic_id=24
299.814: SRAT: lapic cpu_index=15, node_id=02, apic_id=25
299.814: SRAT: lapic cpu_index=16, node_id=02, apic_id=26
299.814: SRAT: lapic cpu_index=17, node_id=02, apic_id=27
299.814: SRAT: lapic cpu_index=18, node_id=03, apic_id=28
299.814: SRAT: lapic cpu_index=19, node_id=03, apic_id=29
299.814: SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a
299.814: SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b
299.814: SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c
299.814: SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d
299.814: SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e
299.814: SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f
299.814: set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
299.814: set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=100e0000, sizek=00020000
299.814: set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
299.814: set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
299.814: set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=03d00000
299.814: set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=04100000, sizek=04000000
299.814: set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=08100000, sizek=04000000
299.814: set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=0c100000, sizek=04000000
299.814: ACPI: added table 6/32, length now 60
299.814: ACPI:   * SLIT at b7c9f730
299.814: ACPI: added table 7/32, length now 64
299.814: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.814: CBFS: Locating 'cmos_layout.bin'
299.814: CBFS: Found @ offset 2b0c0 size e88
299.815: ACPI:   * IVRS at b7c9f770
299.815: Capability: type 0x01 @ 0xc8
299.815: Capability: type 0x05 @ 0xd0
299.815: Capability: type 0x10 @ 0xe0
299.815: Capability: type 0x01 @ 0xc8
299.815: Capability: type 0x05 @ 0xd0
299.815: Capability: type 0x10 @ 0xe0
299.815: Capability: type 0x01 @ 0x40
299.815: Capability: type 0x05 @ 0x50
299.815: Capability: type 0x11 @ 0x70
299.815: Capability: type 0x10 @ 0xa0
299.815: Capability: type 0x01 @ 0x40
299.815: Capability: type 0x05 @ 0x50
299.815: Capability: type 0x11 @ 0x70
299.815: Capability: type 0x10 @ 0xa0
299.815: Capability: type 0x01 @ 0x40
299.815: Capability: type 0x01 @ 0x44
299.815: ACPI: added table 8/32, length now 68
299.815: ACPI:    * HPET
299.815: ACPI: added table 9/32, length now 72
299.815: ACPI:    * SRAT at b7c9f870
299.815: SRAT: lapic cpu_index=00, node_id=00, apic_id=00
299.815: SRAT: lapic cpu_index=01, node_id=00, apic_id=01
299.815: SRAT: lapic cpu_index=02, node_id=00, apic_id=02
299.815: SRAT: lapic cpu_index=03, node_id=00, apic_id=03
299.815: SRAT: lapic cpu_index=04, node_id=00, apic_id=04
299.815: SRAT: lapic cpu_index=05, node_id=00, apic_id=05
299.815: SRAT: lapic cpu_index=06, node_id=00, apic_id=06
299.815: SRAT: lapic cpu_index=07, node_id=00, apic_id=07
299.815: SRAT: lapic cpu_index=08, node_id=01, apic_id=08
299.815: SRAT: lapic cpu_index=09, node_id=01, apic_id=09
299.815: SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a
299.815: SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b
299.815: SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c
299.815: SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d
299.815: SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e
299.815: SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f
299.815: SRAT: lapic cpu_index=10, node_id=02, apic_id=20
299.815: SRAT: lapic cpu_index=11, node_id=02, apic_id=21
299.815: SRAT: lapic cpu_index=12, node_id=02, apic_id=22
299.815: SRAT: lapic cpu_index=13, node_id=02, apic_id=23
299.815: SRAT: lapic cpu_index=14, node_id=02, apic_id=24
299.815: SRAT: lapic cpu_index=15, node_id=02, apic_id=25
299.815: SRAT: lapic cpu_index=16, node_id=02, apic_id=26
299.815: SRAT: lapic cpu_index=17, node_id=02, apic_id=27
299.815: SRAT: lapic cpu_index=18, node_id=03, apic_id=28
299.815: SRAT: lapic cpu_index=19, node_id=03, apic_id=29
299.815: SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a
299.815: SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b
299.815: SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c
299.815: SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d
299.815: SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e
299.815: SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f
299.815: set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
299.815: set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=100e0000, sizek=00020000
299.815: set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
299.815: set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
299.815: set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=03d00000
299.815: set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=04100000, sizek=04000000
299.815: set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=08100000, sizek=04000000
299.815: set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=0c100000, sizek=04000000
299.815: ACPI: added table 10/32, length now 76
299.815: ACPI:   * SLIT at b7c9fb90
299.815: ACPI: added table 11/32, length now 80
299.815: ACPI:    * SRAT at b7c9fbd0
299.815: SRAT: lapic cpu_index=00, node_id=00, apic_id=00
299.815: SRAT: lapic cpu_index=01, node_id=00, apic_id=01
299.815: SRAT: lapic cpu_index=02, node_id=00, apic_id=02
299.815: SRAT: lapic cpu_index=03, node_id=00, apic_id=03
299.815: SRAT: lapic cpu_index=04, node_id=00, apic_id=04
299.815: SRAT: lapic cpu_index=05, node_id=00, apic_id=05
299.815: SRAT: lapic cpu_index=06, node_id=00, apic_id=06
299.816: SRAT: lapic cpu_index=07, node_id=00, apic_id=07
299.816: SRAT: lapic cpu_index=08, node_id=01, apic_id=08
299.816: SRAT: lapic cpu_index=09, node_id=01, apic_id=09
299.816: SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a
299.816: SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b
299.816: SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c
299.816: SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d
299.816: SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e
299.816: SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f
299.816: SRAT: lapic cpu_index=10, node_id=02, apic_id=20
299.816: SRAT: lapic cpu_index=11, node_id=02, apic_id=21
299.816: SRAT: lapic cpu_index=12, node_id=02, apic_id=22
299.816: SRAT: lapic cpu_index=13, node_id=02, apic_id=23
299.816: SRAT: lapic cpu_index=14, node_id=02, apic_id=24
299.816: SRAT: lapic cpu_index=15, node_id=02, apic_id=25
299.816: SRAT: lapic cpu_index=16, node_id=02, apic_id=26
299.816: SRAT: lapic cpu_index=17, node_id=02, apic_id=27
299.816: SRAT: lapic cpu_index=18, node_id=03, apic_id=28
299.816: SRAT: lapic cpu_index=19, node_id=03, apic_id=29
299.816: SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a
299.816: SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b
299.816: SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c
299.816: SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d
299.816: SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e
299.816: SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f
299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=100e0000, sizek=00020000
299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=03d00000
299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=04100000, sizek=04000000
299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=08100000, sizek=04000000
299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=0c100000, sizek=04000000
299.816: ACPI: added table 12/32, length now 84
299.816: ACPI:   * SLIT at b7c9fef0
299.816: ACPI: added table 13/32, length now 88
299.816: ACPI:    * SRAT at b7c9ff30
299.816: SRAT: lapic cpu_index=00, node_id=00, apic_id=00
299.816: SRAT: lapic cpu_index=01, node_id=00, apic_id=01
299.816: SRAT: lapic cpu_index=02, node_id=00, apic_id=02
299.816: SRAT: lapic cpu_index=03, node_id=00, apic_id=03
299.816: SRAT: lapic cpu_index=04, node_id=00, apic_id=04
299.816: SRAT: lapic cpu_index=05, node_id=00, apic_id=05
299.816: SRAT: lapic cpu_index=06, node_id=00, apic_id=06
299.816: SRAT: lapic cpu_index=07, node_id=00, apic_id=07
299.816: SRAT: lapic cpu_index=08, node_id=01, apic_id=08
299.816: SRAT: lapic cpu_index=09, node_id=01, apic_id=09
299.816: SRAT: lapic cpu_index=0a, node_id=01, apic_id=0a
299.816: SRAT: lapic cpu_index=0b, node_id=01, apic_id=0b
299.816: SRAT: lapic cpu_index=0c, node_id=01, apic_id=0c
299.816: SRAT: lapic cpu_index=0d, node_id=01, apic_id=0d
299.816: SRAT: lapic cpu_index=0e, node_id=01, apic_id=0e
299.816: SRAT: lapic cpu_index=0f, node_id=01, apic_id=0f
299.816: SRAT: lapic cpu_index=10, node_id=02, apic_id=20
299.816: SRAT: lapic cpu_index=11, node_id=02, apic_id=21
299.816: SRAT: lapic cpu_index=12, node_id=02, apic_id=22
299.816: SRAT: lapic cpu_index=13, node_id=02, apic_id=23
299.816: SRAT: lapic cpu_index=14, node_id=02, apic_id=24
299.816: SRAT: lapic cpu_index=15, node_id=02, apic_id=25
299.816: SRAT: lapic cpu_index=16, node_id=02, apic_id=26
299.816: SRAT: lapic cpu_index=17, node_id=02, apic_id=27
299.816: SRAT: lapic cpu_index=18, node_id=03, apic_id=28
299.816: SRAT: lapic cpu_index=19, node_id=03, apic_id=29
299.816: SRAT: lapic cpu_index=1a, node_id=03, apic_id=2a
299.816: SRAT: lapic cpu_index=1b, node_id=03, apic_id=2b
299.816: SRAT: lapic cpu_index=1c, node_id=03, apic_id=2c
299.816: SRAT: lapic cpu_index=1d, node_id=03, apic_id=2d
299.816: SRAT: lapic cpu_index=1e, node_id=03, apic_id=2e
299.816: SRAT: lapic cpu_index=1f, node_id=03, apic_id=2f
299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000
299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0008 startk=100e0000, sizek=00020000
299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=03d00000
299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=04100000, sizek=04000000
299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0052 startk=08100000, sizek=04000000
299.816: set_srat_mem: dev DOMAIN: 0000, res->index=0063 startk=0c100000, sizek=04000000
299.816: ACPI: added table 14/32, length now 92
299.816: ACPI:   * SLIT at b7ca0250
299.816: ACPI: added table 15/32, length now 96
299.816: ACPI: done.
299.816: ACPI tables: 29328 bytes.
299.816: smbios_write_tables: b7c88000
299.816: Root Device (ASUS KGPE-D16)
299.816: CPU_CLUSTER: 0 (AMD Family 10h/15h Root Complex)
299.816: APIC: 00 (unknown)
299.816: DOMAIN: 0000 (AMD Family 10h/15h Root Complex)
299.816: PCI: 00:18.0 (AMD Family 10h/15h Northbridge)
299.816: PCI: 00:00.0 (ATI SR5650)
299.816: PCI: 00:00.1 (ATI SR5650)
299.816: PCI: 00:00.2 (ATI SR5650)
299.816: PCI: 00:02.0 (ATI SR5650)
299.816: PCI: 00:03.0 (ATI SR5650)
299.816: PCI: 00:04.0 (ATI SR5650)
299.816: PCI: 00:05.0 (ATI SR5650)
299.816: PCI: 00:06.0 (ATI SR5650)
299.816: PCI: 00:07.0 (ATI SR5650)
299.817: PCI: 00:08.0 (ATI SR5650)
299.817: PCI: 00:09.0 (ATI SR5650)
299.817: PCI: 00:0a.0 (ATI SR5650)
299.817: PCI: 00:0b.0 (ATI SR5650)
299.817: PCI: 00:0c.0 (ATI SR5650)
299.817: PCI: 00:0d.0 (ATI SR5650)
299.817: PCI: 00:11.0 (ATI SP5100)
299.817: PCI: 00:12.0 (ATI SP5100)
299.817: PCI: 00:12.1 (ATI SP5100)
299.817: PCI: 00:12.2 (ATI SP5100)
299.817: PCI: 00:13.0 (ATI SP5100)
299.817: PCI: 00:13.1 (ATI SP5100)
299.817: PCI: 00:13.2 (ATI SP5100)
299.817: PCI: 00:14.0 (ATI SP5100)
299.817: I2C: 01:50 (unknown)
299.817: I2C: 01:51 (unknown)
299.817: I2C: 01:52 (unknown)
299.817: I2C: 01:53 (unknown)
299.817: I2C: 01:54 (unknown)
299.817: I2C: 01:55 (unknown)
299.817: I2C: 01:56 (unknown)
299.817: I2C: 01:57 (unknown)
299.817: I2C: 01:2f (Nuvoton W83795G/ADG Hardware Monitor)
299.817: PCI: 00:14.1 (ATI SP5100)
299.817: PCI: 00:14.2 (ATI SP5100)
299.817: PCI: 00:14.3 (ATI SP5100)
299.817: PNP: 002e.0 (WINBOND W83667HG-A Super I/O)
299.817: PNP: 002e.1 (WINBOND W83667HG-A Super I/O)
299.817: PNP: 002e.2 (WINBOND W83667HG-A Super I/O)
299.817: PNP: 002e.3 (WINBOND W83667HG-A Super I/O)
299.817: PNP: 002e.5 (WINBOND W83667HG-A Super I/O)
299.817: PNP: 002e.106 (WINBOND W83667HG-A Super I/O)
299.817: PNP: 002e.107 (WINBOND W83667HG-A Super I/O)
299.817: PNP: 002e.207 (WINBOND W83667HG-A Super I/O)
299.817: PNP: 002e.307 (WINBOND W83667HG-A Super I/O)
299.817: PNP: 002e.407 (WINBOND W83667HG-A Super I/O)
299.817: PNP: 002e.8 (WINBOND W83667HG-A Super I/O)
299.817: PNP: 002e.108 (WINBOND W83667HG-A Super I/O)
299.817: PNP: 002e.9 (WINBOND W83667HG-A Super I/O)
299.817: PNP: 002e.109 (WINBOND W83667HG-A Super I/O)
299.817: PNP: 002e.209 (WINBOND W83667HG-A Super I/O)
299.817: PNP: 002e.309 (WINBOND W83667HG-A Super I/O)
299.817: PNP: 002e.a (WINBOND W83667HG-A Super I/O)
299.817: PNP: 002e.b (WINBOND W83667HG-A Super I/O)
299.817: PNP: 002e.c (WINBOND W83667HG-A Super I/O)
299.817: PNP: 002e.d (WINBOND W83667HG-A Super I/O)
299.817: PNP: 002e.f (WINBOND W83667HG-A Super I/O)
299.817: PNP: 004e.0 (unknown)
299.817: PCI: 00:14.4 (ATI SP5100)
299.817: PCI: 08:01.0 (ATI SP5100)
299.817: PCI: 08:02.0 (ATI SP5100)
299.817: PCI: 08:03.0 (ATI SP5100)
299.817: PCI: 00:14.5 (ATI SP5100)
299.817: PCI: 00:18.1 (AMD Family 10h/15h Northbridge)
299.817: PCI: 00:18.2 (AMD Family 10h/15h Northbridge)
299.817: PCI: 00:18.3 (AMD Family 10h/15h Northbridge)
299.817: PCI: 00:18.4 (AMD Family 10h/15h Northbridge)
299.817: PCI: 00:18.5 (AMD Family 10h/15h Northbridge)
299.817: PCI: 00:19.0 (AMD Family 10h/15h Northbridge)
299.817: PCI: 00:19.1 (AMD Family 10h/15h Northbridge)
299.817: PCI: 00:19.2 (AMD Family 10h/15h Northbridge)
299.817: PCI: 00:19.3 (AMD Family 10h/15h Northbridge)
299.817: PCI: 00:19.4 (AMD Family 10h/15h Northbridge)
299.817: PCI: 00:19.5 (AMD Family 10h/15h Northbridge)
299.817: PCI: 00:1a.0 (AMD Family 10h/15h Northbridge)
299.817: PCI: 00:1a.1 (AMD Family 10h/15h Northbridge)
299.817: PCI: 00:1a.2 (AMD Family 10h/15h Northbridge)
299.817: PCI: 00:1a.3 (AMD Family 10h/15h Northbridge)
299.817: PCI: 00:1a.4 (AMD Family 10h/15h Northbridge)
299.817: PCI: 00:1a.5 (AMD Family 10h/15h Northbridge)
299.817: PCI: 00:1b.0 (AMD Family 10h/15h Northbridge)
299.817: PCI: 00:1b.1 (AMD Family 10h/15h Northbridge)
299.817: PCI: 00:1b.2 (AMD Family 10h/15h Northbridge)
299.817: PCI: 00:1b.3 (AMD Family 10h/15h Northbridge)
299.817: PCI: 00:1b.4 (AMD Family 10h/15h Northbridge)
299.817: PCI: 00:1b.5 (AMD Family 10h/15h Northbridge)
299.817: APIC: 01 (unknown)
299.817: APIC: 02 (unknown)
299.817: APIC: 03 (unknown)
299.817: APIC: 04 (unknown)
299.817: APIC: 05 (unknown)
299.817: APIC: 06 (unknown)
299.818: APIC: 07 (unknown)
299.818: APIC: 08 (unknown)
299.818: APIC: 09 (unknown)
299.818: APIC: 0a (unknown)
299.818: APIC: 0b (unknown)
299.818: APIC: 0c (unknown)
299.818: APIC: 0d (unknown)
299.818: APIC: 0e (unknown)
299.818: APIC: 0f (unknown)
299.818: APIC: 20 (unknown)
299.818: APIC: 21 (unknown)
299.818: APIC: 22 (unknown)
299.818: APIC: 23 (unknown)
299.818: APIC: 24 (unknown)
299.818: APIC: 25 (unknown)
299.818: APIC: 26 (unknown)
299.818: APIC: 27 (unknown)
299.818: APIC: 28 (unknown)
299.818: APIC: 29 (unknown)
299.818: APIC: 2a (unknown)
299.818: APIC: 2b (unknown)
299.818: APIC: 2c (unknown)
299.818: APIC: 2d (unknown)
299.818: APIC: 2e (unknown)
299.818: APIC: 2f (unknown)
299.818: PCI: 03:00.0 (unknown)
299.818: PCI: 04:00.0 (unknown)
299.818: PCI: 07:00.0 (unknown)
299.818: PCI: 07:00.1 (unknown)
299.818: SMBIOS tables: 1819 bytes.
299.818: Writing table forward entry at 0x00000500
299.818: Wrote coreboot table at: 00000500, 0x10 bytes, checksum 5812
299.818: Writing coreboot table at 0xb7cbf000
299.818: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.818: CBFS: Locating 'cmos_layout.bin'
299.818: CBFS: Found @ offset 2b0c0 size e88
299.819:  0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
299.819:  1. 0000000000001000-000000000009ffff: RAM
299.819:  2. 00000000000a0000-00000000000bffff: RESERVED
299.819:  3. 00000000000c0000-00000000b7c87fff: RAM
299.819:  4. 00000000b7c88000-00000000b7ffffff: CONFIGURATION TABLES
299.819:  5. 00000000b8000000-00000000bfffffff: RAM
299.819:  6. 00000000c0000000-00000000cfffffff: RESERVED
299.819:  7. 00000000fcb00000-00000000fcb03fff: RESERVED
299.819:  8. 00000000feb00000-00000000feb00fff: RESERVED
299.819:  9. 00000000fec00000-00000000fec00fff: RESERVED
299.819: 10. 00000000fed00000-00000000fed00fff: RESERVED
299.819: 11. 0000000100000000-0000004037ffffff: RAM
299.819: 12. 0000004038000000-000000403fffffff: RESERVED
299.819: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.819: CBFS: Locating 'cmos_layout.bin'
299.820: CBFS: Found @ offset 2b0c0 size e88
299.820: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.820: FMAP: Found "FLASH" version 1.1 at 0.
299.820: FMAP: base = ff000000 size = 1000000 #areas = 3
299.820: Wrote coreboot table at: b7cbf000, 0x1208 bytes, checksum deaf
299.820: coreboot table: 4640 bytes.
299.820: IMD ROOT    0. b7fff000 00001000
299.820: IMD SMALL   1. b7ffe000 00001000
299.820: CAR GLOBALS 2. b7ff3000 0000a6c0
299.820: CONSOLE     3. b7fd3000 00020000
299.820: TIME STAMP  4. b7fd2000 00000400
299.820: AMDMEM INFO 5. b7fc8000 000093fc
299.820: ACPI RESUME 6. b7cc7000 00301000
299.820: COREBOOT    7. b7cbf000 00008000
299.820: IRQ TABLE   8. b7cbe000 00001000
299.821: SMP TABLE   9. b7cbd000 00001000
299.821: ACPI       10. b7c99000 00024000
299.821: TCPA LOG   11. b7c89000 00010000
299.821: SMBIOS     12. b7c88000 00000800
299.821: IMD small region:
299.821:   IMD ROOT    0. b7ffec00 00000400
299.821:   ROMSTAGE    1. b7ffebe0 00000004
299.821:   GDT         2. b7ffe9e0 00000200
299.821: Writing AMD DCT configuration to Flash
299.823: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.823: CBFS: Locating 'cmos_layout.bin'
299.823: CBFS: Found @ offset 2b0c0 size e88
299.824: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.824: CBFS: Locating 'cmos_layout.bin'
299.824: CBFS: Found @ offset 2b0c0 size e88
299.825: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.825: CBFS: Locating 'cmos_layout.bin'
299.825: CBFS: Found @ offset 2b0c0 size e88
299.825: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.825: CBFS: Locating 'cmos_layout.bin'
299.825: CBFS: Found @ offset 2b0c0 size e88
299.826: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.826: CBFS: Locating 'cmos_layout.bin'
299.826: CBFS: Found @ offset 2b0c0 size e88
299.826: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.826: CBFS: Locating 'cmos_layout.bin'
299.826: CBFS: Found @ offset 2b0c0 size e88
299.827: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.827: CBFS: Locating 'cmos_layout.bin'
299.827: CBFS: Found @ offset 2b0c0 size e88
299.827: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.827: CBFS: Locating 'cmos_layout.bin'
299.827: CBFS: Found @ offset 2b0c0 size e88
299.828: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.828: CBFS: Locating 'cmos_layout.bin'
299.828: CBFS: Found @ offset 2b0c0 size e88
299.828: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.828: CBFS: Locating 'cmos_layout.bin'
299.829: CBFS: Found @ offset 2b0c0 size e88
299.829: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
299.829: CBFS: Locating 's3nv'
299.829: CBFS: Found @ offset 2fec0 size 10000
299.829: Manufacturer: ef
299.829: SF: Detected W25Q128 with sector size 0x1000, total 0x1000000
299.831: SF: Successfully erased 32768 bytes @ 0x38000
300.174: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
300.174: CBFS: Locating 'cmos_layout.bin'
300.174: CBFS: Found @ offset 2b0c0 size e88
300.175: BS: BS_WRITE_TABLES times (us): entry 0 run 1989588 exit 0
300.175: CBFS: 'Master Header Locator' located CBFS at [100:ffffc0)
300.175: CBFS: Locating 'fallback/payload'
300.175: CBFS: Found @ offset 95600 size e920
300.175: Loading segment from ROM address 0xff095738
300.175:   code (compression=1)
300.175:   New segment dstaddr 0xe4460 memsize 0x1bba0 srcaddr 0xff095770 filesize 0xe8e8
300.175: Loading segment from ROM address 0xff095754
300.175:   Entry Point 0x000ff06e
300.175: Bounce Buffer at bfdd1000, 2287584 bytes
300.175: Loading Segment: addr: 0x00000000000e4460 memsz: 0x000000000001bba0 filesz: 0x000000000000e8e8
300.175: lb: [0x0000000000100000, 0x00000000002173f0)
300.175: Post relocation: addr: 0x00000000000e4460 memsz: 0x000000000001bba0 filesz: 0x000000000000e8e8
300.176: using LZMA
300.203: [ 0x000e4460, 00100000, 0x00100000) <- ff095770
300.203: dest 000e4460, end 00100000, bouncebuffer bfdd1000
300.203: Loaded segments
300.203: BS: BS_PAYLOAD_LOAD times (us): entry 0 run 68938 exit 0
300.203: Jumping to boot code at 000ff06e(b7cbf000)
300.203: CPU0: stack: 00151000 - 00152000, lowest used address 001519e0, stack used: 1568 bytes
300.204: entry    = 0x000ff06e
300.204: lb_start = 0x00100000
300.204: lb_size  = 0x001173f0
300.204: buffer   = 0xbfdd1000
300.204: SeaBIOS (version rel-1.10.0-25-g1415d46)
300.204: BUILD: gcc: (Ubuntu 6.2.0-5ubuntu12) 6.2.0 20161005 binutils: (GNU Binutils for Ubuntu) 2.27
300.204: Attempting to find coreboot table
300.204: Found coreboot table forwarder.
300.204: Now attempting to find coreboot memory map
300.204: SeaBIOS (version rel-1.10.0-25-g1415d46)
300.204: BUILD: gcc: (Ubuntu 6.2.0-5ubuntu12) 6.2.0 20161005 binutils: (GNU Binutils for Ubuntu) 2.27
300.204: Found coreboot cbmem console @ b7fd3000
300.204: Found mainboard ASUS KGPE-D16
300.204: malloc preinit
300.204: Relocating init from 0x000e5980 to 0xbffb4ca0 (size 45728)
300.204: malloc init
300.204: Found CBFS header at 0xff000138
300.204: Add romfile: cbfs master header (size=32)
300.204: Add romfile: fallback/romstage (size=174404)
300.204: Add romfile: config (size=603)
300.204: Add romfile: revision (size=570)
300.204: Add romfile: cmos.default (size=256)
300.205: Add romfile: cmos_layout.bin (size=3720)
300.205: Add romfile: fallback/dsdt.aml (size=9736)
300.205: Add romfile: bootorder (size=31)
300.205: Add romfile:  (size=6168)
300.205: Add romfile: s3nv (size=65536)
300.205: Add romfile: fallback/ramstage (size=87116)
300.205: Add romfile: pci1106,3230.rom (size=27648)
300.205: Add romfile: img/coreinfo (size=109556)
300.205: Add romfile: img/nvramcui (size=125256)
300.205: Add romfile: fallback/payload (size=59680)
300.205: Add romfile: img/memtest (size=180268)
300.205: Add romfile: microcode_amd.bin (size=12684)
300.205: Add romfile: microcode_amd_fam15h.bin (size=7876)
300.205: Add romfile: vgaroms/seavgabios.bin (size=27648)
300.205: Add romfile:  (size=15873240)
300.205: Add romfile: bootblock (size=3048)
300.205: multiboot: eax=0, ebx=0
300.205: init ivt
300.205: init bda
300.205: Copying romfile 'bootorder' (len 31)
300.205: Copying data 31@0xff02e738 to 31@0xbffb3ae0
300.205: boot order:
300.205: 1: /pci@i0cf8/*@11/drive@3/disk@0
300.205: 2: 
300.205: init bios32
300.205: init PMM
300.205: init PNPBIOS table
300.205: init keyboard
300.205: init mouse
300.205: init pic
300.205: math cp init
300.205: PCI probe
300.205: PCI device 00:00.0 (vd=1002:5a10 c=0600)
300.205: PCI device 00:00.2 (vd=1002:5a23 c=0806)
300.205: PCI device 00:02.0 (vd=1002:5a16 c=0604)
300.205: PCI device 00:04.0 (vd=1002:5a18 c=0604)
300.206: PCI device 00:09.0 (vd=1002:5a1c c=0604)
300.205: PCI device 00:0a.0 (vd=1002:5a1d c=0604)
300.206: PCI device 00:0b.0 (vd=1002:5a1f c=0604)
300.206: PCI device 00:0c.0 (vd=1002:5a20 c=0604)
300.206: PCI device 00:0d.0 (vd=1002:5a1e c=0604)
300.206: PCI device 00:11.0 (vd=1002:4394 c=0106)
300.206: PCI device 00:12.0 (vd=1002:4397 c=0c03)
300.206: PCI device 00:12.1 (vd=1002:4398 c=0c03)
300.206: PCI device 00:12.2 (vd=1002:4396 c=0c03)
300.206: PCI device 00:13.0 (vd=1002:4397 c=0c03)
300.206: PCI device 00:13.1 (vd=1002:4398 c=0c03)
300.206: PCI device 00:13.2 (vd=1002:4396 c=0c03)
300.206: PCI device 00:14.0 (vd=1002:4385 c=0c05)
300.206: PCI device 00:14.1 (vd=1002:439c c=0101)
300.206: PCI device 00:14.2 (vd=1002:4383 c=0403)
300.206: PCI device 00:14.3 (vd=1002:439d c=0601)
300.206: PCI device 00:14.4 (vd=1002:4384 c=0604)
300.206: PCI device 00:14.5 (vd=1002:4399 c=0c03)
300.206: PCI device 00:18.0 (vd=1022:1600 c=0600)
300.206: PCI device 00:18.1 (vd=1022:1601 c=0600)
300.206: PCI device 00:18.2 (vd=1022:1602 c=0600)
300.206: PCI device 00:18.3 (vd=1022:1603 c=0600)
300.206: PCI device 00:18.4 (vd=1022:1604 c=0600)
300.206: PCI device 00:18.5 (vd=1022:1605 c=0600)
300.206: PCI device 00:19.0 (vd=1022:1600 c=0600)
300.206: PCI device 00:19.1 (vd=1022:1601 c=0600)
300.206: PCI device 00:19.2 (vd=1022:1602 c=0600)
300.206: PCI device 00:19.3 (vd=1022:1603 c=0600)
300.206: PCI device 00:19.4 (vd=1022:1604 c=0600)
300.206: PCI device 00:19.5 (vd=1022:1605 c=0600)
300.206: PCI device 00:1a.0 (vd=1022:1600 c=0600)
300.206: PCI device 00:1a.1 (vd=1022:1601 c=0600)
300.206: PCI device 00:1a.2 (vd=1022:1602 c=0600)
300.206: PCI device 00:1a.3 (vd=1022:1603 c=0600)
300.206: PCI device 00:1a.4 (vd=1022:1604 c=0600)
300.206: PCI device 00:1a.5 (vd=1022:1605 c=0600)
300.206: PCI device 00:1b.0 (vd=1022:1600 c=0600)
300.206: PCI device 00:1b.1 (vd=1022:1601 c=0600)
300.206: PCI device 00:1b.2 (vd=1022:1602 c=0600)
300.206: PCI device 00:1b.3 (vd=1022:1603 c=0600)
300.206: PCI device 00:1b.4 (vd=1022:1604 c=0600)
300.206: PCI device 00:1b.5 (vd=1022:1605 c=0600)
300.206: PCI device 03:00.0 (vd=8086:10d3 c=0200)
300.206: PCI device 04:00.0 (vd=8086:10d3 c=0200)
300.206: PCI device 07:00.0 (vd=8086:10fb c=0200)
300.206: PCI device 07:00.1 (vd=8086:10fb c=0200)
300.206: PCI device 08:01.0 (vd=1a03:2000 c=0300)
300.206: PCI device 08:02.0 (vd=11c1:5811 c=0c00)
300.206: Found 52 PCI devices (max PCI bus is 08)
300.206: Relocating coreboot bios tables
300.206: Copying SMBIOS entry point from 0xb7c88000 to 0x000f0c00
300.206: Copying ACPI RSDP from 0xb7c99000 to 0x000f0bd0
300.206: Skipping MPTABLE copy due to large size (1196 bytes)
300.206: Copying PIR from 0xb7cbe000 to 0x000f0ba0
300.208: rsdp=0x000f0bd0
300.208: rsdt=0xb7c99030
300.208: table(50434146)=0xb7c9b890
300.208: pm_tmr_blk=820
300.208: Using pmtimer, ioport 0x820
300.208: init timer
300.208: Scan for VGA option rom
300.208: Attempting to init PCI bdf 08:01.0 (vd 1a03:2000)
300.208: Copying data 27648@0xff0d5288 to 27648@0x000c0000
300.217: Running option rom at c000:0003
300.217: Start SeaVGABIOS (version rel-1.10.0-25-g1415d46)
300.217: VGABUILD: gcc: (Ubuntu 6.2.0-5ubuntu12) 6.2.0 20161005 binutils: (GNU Binutils for Ubuntu) 2.27
300.217: enter vga_post:
300.217:    a=00000000  b=0000ffff  c=00000000  d=0000ffff ds=0000 es=f000 ss=0000
300.217:   si=00000000 di=00008020 bp=00000000 sp=00006dda cs=f000 ip=cfd0  f=0000
300.217: coreboot vga init
300.217: Found coreboot table forwarder.
300.217: Did not find coreboot framebuffer - assuming EGA text
300.217: Attempting to allocate VGA stack via pmm call to f000:d03f
300.217: pmm call arg1=0
300.217: pmm00: length=20 handle=ffffffff flags=9
300.217: VGA stack allocated at ef580
300.217: Hooking hardware timer irq (old=f000fea5 new=c0003ed0)
300.217: Turning on vga text mode console
300.217: set VGA mode 3
300.218: SeaBIOS (version rel-1.10.0-25-g1415d46)
300.218: init usb
300.218: EHCI init on dev 00:12.2 (regs=0xfcb0e020)
300.218: /bffb1000\ Start thread
300.218: EHCI init on dev 00:13.2 (regs=0xfcb0f020)
300.218: /bffb0000\ Start thread
300.218: OHCI init on dev 00:12.0 (regs=0xfcb08000)
300.218: /bffaf000\ Start thread
300.218: OHCI init on dev 00:12.1 (regs=0xfcb09000)
300.218: /bffae000\ Start thread
300.218: OHCI init on dev 00:13.0 (regs=0xfcb0a000)
300.218: /bffad000\ Start thread
300.218: /bffac000\ Start thread
300.219: \bffac000/ End thread
300.219: OHCI init on dev 00:13.1 (regs=0xfcb0b000)
300.219: /bffac000\ Start thread
300.219: /bffab000\ Start thread
300.219: /bffaa000\ Start thread
300.219: OHCI init on dev 00:14.5 (regs=0xfcb0c000)
300.219: /bffa9000\ Start thread
300.219: /bffa8000\ Start thread
300.219: /bffa7000\ Start thread
300.219: init ps2port
300.219: /bffa6000\ Start thread
300.222: /bffa5000\ Start thread
300.222: /bffa3000\ Start thread
300.222: init ahci
300.222: AHCI controller at 00:11.0, iobase 0xfcb0d000, irq 0
300.222: AHCI: cap 0xf322ff85, ports_impl 0x3f
300.222: /bffa2000\ Start thread
300.222: |bffa2000| AHCI/0: probing
300.222: |bffa2000| AHCI/0: link up
300.222: /bffa1000\ Start thread
300.222: /bffa0000\ Start thread
300.222: /bff9f000\ Start thread
300.222: |bff9f000| AHCI/1: probing
300.222: |bff9f000| AHCI/1: link up
300.222: |bffa2000| AHCI/0: ... finished, status 0x51, ERROR 0x4
300.222: /bff9d000\ Start thread
300.222: /bff9c000\ Start thread
300.222: /bff9b000\ Start thread
300.223: /bff9a000\ Start thread
300.223: /bff99000\ Start thread
300.223: /bff98000\ Start thread
300.223: |bff98000| AHCI/2: probing
300.223: |bff9f000| AHCI/1: ... finished, status 0x51, ERROR 0x4
300.223: |bffa2000| Searching bootorder for: /pci@i0cf8/*@11/drive@0/disk@0
300.223: |bffa2000| AHCI/0: supported modes: udma 6, multi-dma 2, pio 4
300.223: |bffa2000| AHCI/0: Set transfer mode to UDMA-6
300.223: /bff97000\ Start thread
300.223: /bff96000\ Start thread
300.223: /bff95000\ Start thread
300.223: /bff94000\ Start thread
300.223: |bff9b000| set_address 0xbffb2730
300.223: /bff93000\ Start thread
300.223: \bff93000/ End thread
300.223: \bff9a000/ End thread
300.223: \bffa1000/ End thread
300.223: \bffa5000/ End thread
300.223: \bffa8000/ End thread
300.223: \bffab000/ End thread
300.223: \bff99000/ End thread
300.223: \bffa0000/ End thread
300.223: \bffa3000/ End thread
300.223: \bffa7000/ End thread
300.223: \bffaa000/ End thread
300.223: /bffaa000\ Start thread
300.223: |bffaa000| AHCI/3: probing
300.223: |bffaa000| AHCI/3: link up
300.223: |bff98000| AHCI/2: link down
300.223: |bff9f000| Searching bootorder for: /pci@i0cf8/*@11/drive@1/disk@0
300.223: |bff9f000| AHCI/1: supported modes: udma 6, multi-dma 2, pio 4
300.223: |bff9f000| AHCI/1: Set transfer mode to UDMA-6
300.223: /bffa8000\ Start thread
300.223: /bffa7000\ Start thread
300.223: /bffa5000\ Start thread
300.223: \bffa5000/ End thread
300.223: \bff96000/ End thread
300.223: \bff9d000/ End thread
300.223: /bffa5000\ Start thread
300.223: \bffa5000/ End thread
300.223: \bff95000/ End thread
300.223: \bff9c000/ End thread
300.223: /bffa5000\ Start thread
300.223: \bffa5000/ End thread
300.223: \bff94000/ End thread
300.223: /bffa5000\ Start thread
300.223: |bffa5000| AHCI/4: probing
300.223: |bffaa000| AHCI/3: ... finished, status 0x51, ERROR 0x4
300.223: \bff98000/ End thread
300.223: |bffa2000| AHCI/0: registering: "AHCI/0: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes)"
300.223: |bffa2000| Registering bootable: AHCI/0: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes) (type:2 prio:103 data:f0b30)
300.223: \bffa2000/ End thread
300.223: /bffa3000\ Start thread
300.223: /bffa2000\ Start thread
300.223: \bffa2000/ End thread
300.223: \bffa7000/ End thread
300.223: \bff97000/ End thread
300.223: /bffa2000\ Start thread
300.223: |bffa2000| AHCI/5: probing
300.224: |bffa5000| AHCI/4: link down
300.224: |bffaa000| Searching bootorder for: /pci@i0cf8/*@11/drive@3/disk@0
300.224: |bffaa000| AHCI/3: supported modes: udma 6, multi-dma 2, pio 4
300.224: |bffaa000| AHCI/3: Set transfer mode to UDMA-6
300.224: |bff9f000| AHCI/1: registering: "AHCI/1: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes)"
300.224: |bff9f000| Registering bootable: AHCI/1: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes) (type:2 prio:103 data:f0ae0)
300.224: \bff9f000/ End thread
300.224: \bffa3000/ End thread
300.224: \bffa8000/ End thread
300.224: \bffad000/ End thread
300.224: \bffae000/ End thread
300.224: |bff9b000| config_usb: 0xbffab9b0
300.224: \bffb0000/ End thread
300.224: \bffb1000/ End thread
300.224: init lpt
300.224: Found 0 lpt ports
300.224: init serial
300.224: Found 2 serial ports
300.224: Searching bootorder for: /rom@img/memtest
300.224: Registering bootable: Payload [memtest] (type:32 prio:9999 data:ff0a4080)
300.224: Searching bootorder for: /rom@img/nvramcui
300.224: Registering bootable: Payload [nvramcui] (type:32 prio:9999 data:ff076d80)
300.224: Searching bootorder for: /rom@img/coreinfo
300.224: Registering bootable: Payload [coreinfo] (type:32 prio:9999 data:ff05c140)
300.224: |bffa2000| AHCI/5: link down
300.224: \bffa5000/ End thread
300.224: \bffac000/ End thread
300.224: |bff9b000| device rev=0110 cls=00 sub=00 proto=00 size=8
300.224: \bffa2000/ End thread
300.224: |bffaa000| AHCI/3: registering: "AHCI/3: Hitachi HUA721010KLA330 ATA-7 Hard-Disk (931 GiBytes)"
300.224: |bffaa000| Registering bootable: AHCI/3: Hitachi HUA721010KLA330 ATA-7 Hard-Disk (931 GiBytes) (type:2 prio:1 data:f0a90)
300.224: \bffaa000/ End thread
300.224: \bffa9000/ End thread
300.226: |bff9b000| usb_hid_setup 0xbffab9b0
300.227: |bff9b000| USB keyboard initialized
300.227: \bff9b000/ End thread
300.228: \bffaf000/ End thread
300.354: |bffa6000| PS2 keyboard initialized
300.354: \bffa6000/ End thread
300.354: All threads complete.
300.354: Scan for option roms
300.354: Attempting to init PCI bdf 00:00.0 (vd 1002:5a10)
300.354: Attempting to init PCI bdf 00:00.2 (vd 1002:5a23)
300.354: Attempting to init PCI bdf 00:02.0 (vd 1002:5a16)
300.354: Attempting to init PCI bdf 00:04.0 (vd 1002:5a18)
300.354: Attempting to init PCI bdf 00:09.0 (vd 1002:5a1c)
300.354: Attempting to init PCI bdf 00:0a.0 (vd 1002:5a1d)
300.354: Attempting to init PCI bdf 00:0b.0 (vd 1002:5a1f)
300.354: Attempting to init PCI bdf 00:0c.0 (vd 1002:5a20)
300.354: Attempting to init PCI bdf 00:0d.0 (vd 1002:5a1e)
300.354: Attempting to init PCI bdf 00:14.0 (vd 1002:4385)
300.354: Attempting to init PCI bdf 00:14.1 (vd 1002:439c)
300.354: Attempting to init PCI bdf 00:14.2 (vd 1002:4383)
300.354: Attempting to init PCI bdf 00:14.3 (vd 1002:439d)
300.354: Attempting to init PCI bdf 00:14.4 (vd 1002:4384)
300.354: Attempting to init PCI bdf 00:18.0 (vd 1022:1600)
300.354: Attempting to init PCI bdf 00:18.1 (vd 1022:1601)
300.354: Attempting to init PCI bdf 00:18.2 (vd 1022:1602)
300.354: Attempting to init PCI bdf 00:18.3 (vd 1022:1603)
300.354: Attempting to init PCI bdf 00:18.4 (vd 1022:1604)
300.354: Attempting to init PCI bdf 00:18.5 (vd 1022:1605)
300.354: Attempting to init PCI bdf 00:19.0 (vd 1022:1600)
300.354: Attempting to init PCI bdf 00:19.1 (vd 1022:1601)
300.354: Attempting to init PCI bdf 00:19.2 (vd 1022:1602)
300.354: Attempting to init PCI bdf 00:19.3 (vd 1022:1603)
300.354: Attempting to init PCI bdf 00:19.4 (vd 1022:1604)
300.354: Attempting to init PCI bdf 00:19.5 (vd 1022:1605)
300.354: Attempting to init PCI bdf 00:1a.0 (vd 1022:1600)
300.354: Attempting to init PCI bdf 00:1a.1 (vd 1022:1601)
300.354: Attempting to init PCI bdf 00:1a.2 (vd 1022:1602)
300.354: Attempting to init PCI bdf 00:1a.3 (vd 1022:1603)
300.354: Attempting to init PCI bdf 00:1a.4 (vd 1022:1604)
300.354: Attempting to init PCI bdf 00:1a.5 (vd 1022:1605)
300.354: Attempting to init PCI bdf 00:1b.0 (vd 1022:1600)
300.354: Attempting to init PCI bdf 00:1b.1 (vd 1022:1601)
300.354: Attempting to init PCI bdf 00:1b.2 (vd 1022:1602)
300.354: Attempting to init PCI bdf 00:1b.3 (vd 1022:1603)
300.354: Attempting to init PCI bdf 00:1b.4 (vd 1022:1604)
300.354: Attempting to init PCI bdf 00:1b.5 (vd 1022:1605)
300.354: Attempting to init PCI bdf 03:00.0 (vd 8086:10d3)
300.354: Attempting to init PCI bdf 04:00.0 (vd 8086:10d3)
300.354: Attempting to init PCI bdf 07:00.0 (vd 8086:10fb)
300.354: Attempting to init PCI bdf 07:00.1 (vd 8086:10fb)
300.354: Attempting to init PCI bdf 08:02.0 (vd 11c1:5811)
300.354: 
300.354: Press ESC for boot menu.
300.354: 
300.354: Checking for bootsplash
301.390: Select boot device:
301.390: 
301.390: 1. AHCI/3: Hitachi HUA721010KLA330 ATA-7 Hard-Disk (931 GiByte
301.390: 2. AHCI/0: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes)
301.390: 3. AHCI/1: HGST HDN724030ALE640 ATA-8 Hard-Disk (2794 GiBytes)
301.390: 4. Payload [memtest]
301.390: 5. Payload [nvramcui]
301.390: 6. Payload [coreinfo]
302.793: 
302.793: Searching bootorder for: HALT
302.793: Mapping hd drive 0x000f0a90 to 0
302.793: drive 0x000f0a90: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1953525168
302.793: Mapping hd drive 0x000f0b30 to 1
302.793: drive 0x000f0b30: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1565565872
302.793: Mapping hd drive 0x000f0ae0 to 2
302.793: drive 0x000f0ae0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1565565872
302.793: finalize PMM
302.793: malloc finalize
302.794: Space available for UMB: c7000-ee800, f0000-f0a90
302.794: Returned 245760 bytes of ZoneHigh
302.794: e820 map has 13 items:
302.794:   0: 0000000000000000 - 000000000009fc00 = 1 RAM
302.794:   1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
302.794:   2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
302.794:   3: 0000000000100000 - 00000000b7c88000 = 1 RAM
302.794:   4: 00000000b7c88000 - 00000000b8000000 = 2 RESERVED
302.794:   5: 00000000b8000000 - 00000000bfffc000 = 1 RAM
302.794:   6: 00000000bfffc000 - 00000000d0000000 = 2 RESERVED
302.794:   7: 00000000fcb00000 - 00000000fcb04000 = 2 RESERVED
302.794:   8: 00000000feb00000 - 00000000feb01000 = 2 RESERVED
302.794:   9: 00000000fec00000 - 00000000fec01000 = 2 RESERVED
302.794:   10: 00000000fed00000 - 00000000fed01000 = 2 RESERVED
302.794:   11: 0000000100000000 - 0000004038000000 = 1 RAM
302.794:   12: 0000004038000000 - 0000004040000000 = 2 RESERVED
302.795: Jump to int19
302.795: enter handle_19:
302.795:   NULL
302.795: Booting from Hard Disk...
302.808: Booting from 0000:7c00
305.206: handle_hwpic1 irq=1