lenovo/x230/4.8-1065-gbb95731dad/2018-08-06T14_16_17Z
diff --git a/lenovo/x230/4.8-1065-gbb95731dad/2018-08-06T14_16_17Z/coreboot_console.txt b/lenovo/x230/4.8-1065-gbb95731dad/2018-08-06T14_16_17Z/coreboot_console.txt
new file mode 100644
index 0000000..ee16730
--- /dev/null
+++ b/lenovo/x230/4.8-1065-gbb95731dad/2018-08-06T14_16_17Z/coreboot_console.txt
@@ -0,0 +1,3325 @@
+link 0 PCI: 01:00.0
+ PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
+ PCI: 00:1c.0 resource base e1400000 size 100000 align 20 gran 20 limit e14fffff flags 60080202 index 20
+ PCI: 01:00.0
+ PCI: 01:00.0 resource base e1400000 size 100 align 12 gran 8 limit e14000ff flags 60000200 index 10
+ PCI: 00:1c.1 child on link 0 PCI: 02:00.0
+ PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
+ PCI: 00:1c.1 resource base e1500000 size 100000 align 20 gran 20 limit e15fffff flags 60080202 index 20
+ PCI: 02:00.0
+ PCI: 02:00.0 resource base e1500000 size 10000 align 16 gran 16 limit e150ffff flags 60000201 index 10
+ PCI: 00:1c.2 child on link 0 NONE
+ PCI: 00:1c.2 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c
+ PCI: 00:1c.2 resource base e0000000 size 800000 align 22 gran 20 limit e07fffff flags 60081202 index 24
+ PCI: 00:1c.2 resource base e0800000 size 800000 align 22 gran 20 limit e0ffffff flags 60080202 index 20
+ NONE
+ NONE resource base e0800000 size 800000 align 22 gran 22 limit e0ffffff flags 40000200 index 10
+ NONE resource base e0000000 size 800000 align 22 gran 22 limit e07fffff flags 40001200 index 14
+ NONE resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 40000100 index 18
+ PCI: 00:1c.3
+ PCI: 00:1c.4
+ PCI: 00:1c.5
+ PCI: 00:1c.6
+ PCI: 00:1c.7
+ PCI: 00:1d.0
+ PCI: 00:1d.0 resource base e1640000 size 400 align 12 gran 10 limit e16403ff flags 60000200 index 10
+ PCI: 00:1e.0
+ PCI: 00:1f.0 child on link 0 PNP: 00ff.1
+ PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
+ PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
+ PNP: 00ff.1
+ PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
+ PNP: 0c31.0
+ PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0
+ PNP: 00ff.2
+ PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
+ PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
+ PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
+ PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
+ PCI: 00:1f.2
+ PCI: 00:1f.2 resource base 3080 size 8 align 3 gran 3 limit 3087 flags 60000100 index 10
+ PCI: 00:1f.2 resource base 3090 size 4 align 2 gran 2 limit 3093 flags 60000100 index 14
+ PCI: 00:1f.2 resource base 3088 size 8 align 3 gran 3 limit 308f flags 60000100 index 18
+ PCI: 00:1f.2 resource base 3094 size 4 align 2 gran 2 limit 3097 flags 60000100 index 1c
+ PCI: 00:1f.2 resource base 3060 size 20 align 5 gran 5 limit 307f flags 60000100 index 20
+ PCI: 00:1f.2 resource base e163e000 size 800 align 12 gran 11 limit e163e7ff flags 60000200 index 24
+ PCI: 00:1f.3 child on link 0 I2C: 01:54
+ PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
+ PCI: 00:1f.3 resource base e1641000 size 100 align 12 gran 8 limit e16410ff flags 60000201 index 10
+ I2C: 01:54
+ I2C: 01:55
+ I2C: 01:56
+ I2C: 01:57
+ I2C: 01:5c
+ I2C: 01:5d
+ I2C: 01:5e
+ I2C: 01:5f
+ PCI: 00:1f.5
+ PCI: 00:1f.6
+ PCI: 00:1f.6 resource base e163d000 size 1000 align 12 gran 12 limit e163dfff flags 60000201 index 10
+Done allocating resources.
+BS: BS_DEV_RESOURCES times (us): entry 0 run 2177 exit 0
+Enabling resources...
+PCI: 00:00.0 subsystem <- 17aa/21fa
+PCI: 00:00.0 cmd <- 06
+PCI: 00:02.0 subsystem <- 17aa/21fa
+PCI: 00:02.0 cmd <- 03
+PCI: 00:04.0 cmd <- 02
+PCI: 00:14.0 subsystem <- 17aa/21fa
+PCI: 00:14.0 cmd <- 102
+PCI: 00:16.0 subsystem <- 17aa/21fa
+PCI: 00:16.0 cmd <- 02
+PCI: 00:19.0 subsystem <- 17aa/21f3
+PCI: 00:19.0 cmd <- 103
+PCI: 00:1a.0 subsystem <- 17aa/21fa
+PCI: 00:1a.0 cmd <- 102
+PCI: 00:1b.0 subsystem <- 17aa/21fa
+PCI: 00:1b.0 cmd <- 102
+PCI: 00:1c.0 bridge ctrl <- 0003
+PCI: 00:1c.0 subsystem <- 17aa/21fa
+PCI: 00:1c.0 cmd <- 106
+PCI: 00:1c.1 bridge ctrl <- 0003
+PCI: 00:1c.1 subsystem <- 17aa/21fa
+PCI: 00:1c.1 cmd <- 106
+PCI: 00:1c.2 bridge ctrl <- 0003
+PCI: 00:1c.2 subsystem <- 17aa/21fa
+PCI: 00:1c.2 cmd <- 107
+PCI: 00:1d.0 subsystem <- 17aa/21fa
+PCI: 00:1d.0 cmd <- 102
+pch_decode_init
+PCI: 00:1f.0 subsystem <- 17aa/21fa
+PCI: 00:1f.0 cmd <- 107
+PCI: 00:1f.2 subsystem <- 17aa/21fa
+PCI: 00:1f.2 cmd <- 03
+PCI: 00:1f.3 subsystem <- 17aa/21fa
+PCI: 00:1f.3 cmd <- 103
+PCI: 00:1f.6 subsystem <- 17aa/21fa
+PCI: 00:1f.6 cmd <- 02
+PCI: 01:00.0 subsystem <- 17aa/21fa
+PCI: 01:00.0 cmd <- 06
+PCI: 02:00.0 cmd <- 02
+done.
+BS: BS_DEV_ENABLE times (us): entry 0 run 122 exit 0
+Found TPM ST33ZP24 by ST Microelectronics
+TPM: Resume
+TPM: command 0x99 returned 0x0
+Initializing devices...
+Root Device init ...
+Root Device init finished in 0 usecs
+CPU_CLUSTER: 0 init ...
+start_eip=0x00001000, code_size=0x00000031
+Setting up SMI for CPU
+Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8
+Processing 13 relocs. Offset value of 0x00038000
+SMM Module: stub loaded at 00038000. Will call bff91b5b(bffc82e0)
+Installing SMM handler to 0xc0000000
+Loading module at c0010000 with entry c001048b. filesize: 0x1b90 memsize: 0x5bb8
+Processing 60 relocs. Offset value of 0xc0010000
+Loading module at c0008000 with entry c0008000. filesize: 0x1a8 memsize: 0x1a8
+Processing 13 relocs. Offset value of 0xc0008000
+SMM Module: placing jmp sequence at c0007c00 rel16 0x03fd
+SMM Module: placing jmp sequence at c0007800 rel16 0x07fd
+SMM Module: placing jmp sequence at c0007400 rel16 0x0bfd
+SMM Module: stub loaded at c0008000. Will call c001048b(00000000)
+Initializing southbridge SMI... ... pmbase = 0x0500
+
+SMI_STS: MCSMI PM1
+PM1_STS: WAK
+PM1_EN: 100
+GPE0_STS: GPIO15 GPIO14 GPIO13 GPIO11 GPIO9 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO1 GPIO0 EL_SCI/BATLOW
+ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI1 GPI0
+TCO_STS:
+ ... raise SMI#
+In relocation handler: cpu 0
+New SMBASE=0xc0000000 IEDBASE=0xc0400000 @ 0003fc00
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Relocation complete.
+Locking SMM.
+Initializing CPU #0
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [820000:bfffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 13480 size 6400
+microcode: sig=0x306a9 pf=0x10 revision=0x20
+CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz.
+CPU: platform id 4
+CPU: cpuid(1) 0x306a9
+CPU: AES supported
+CPU: TXT supported
+CPU: VT supported
+MTRR: Physical address space:
+0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
+0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
+0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6
+0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 0
+0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
+0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
+0x0000000100000000 - 0x000000043d600000 size 0x33d600000 type 6
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+CPU physical address size: 36 bits
+MTRR: default type WB/UC MTRR counts: 3/6.
+MTRR: WB selected as default type.
+MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
+MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
+MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local APIC... apic_id: 0x00 done.
+VMX status: enabled, locked
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 2900
+Turbo is available but hidden
+Turbo has been enabled
+CPU: 0 has 2 cores, 2 threads per core
+CPU: 0 has core 1
+CPU1: stack_base bffae000, stack_end bffaeff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 1.
+After apic_write.
+In relocation handler: cpu 1
+New SMBASE=0xbffffc00 IEDBASE=0xc0400000 @ 0003fc00
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 1.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+Initializing CPU #1
+CPU: 0 has core 2
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [820000:bfffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 13480 size 6400
+microcode: sig=0x306a9 pf=0x10 revision=0x20
+CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz.
+CPU: platform id 4
+CPU: cpuid(1) 0x306a9
+CPU: AES supported
+CPU: TXT supported
+CPU: VT supported
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+CPU physical address size: 36 bits
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local APIC... apic_id: 0x01 done.
+VMX status: enabled, locked
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 2900
+CPU #1 initialized
+CPU2: stack_base bffad000, stack_end bffadff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 2.
+After apic_write.
+In relocation handler: cpu 2
+Startup point 1.
+Waiting for send to finish...
++New SMBASE=0xbffff800 IEDBASE=0xc0400000 @ 0003fc00
+Sending STARTUP #2 to 2.
+After apic_write.
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU: 0 has core 3
+Initializing CPU #2
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [820000:bfffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 13480 size 6400
+microcode: sig=0x306a9 pf=0x10 revision=0x0
+microcode: updated to revision 0x20 date=2018-04-10
+CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz.
+CPU: platform id 4
+CPU: cpuid(1) 0x306a9
+CPU: AES supported
+CPU: TXT supported
+CPU: VT supported
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+CPU physical address size: 36 bits
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local APIC... apic_id: 0x02 done.
+VMX status: enabled, locked
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 2900
+CPU #2 initialized
+CPU3: stack_base bffac000, stack_end bffacff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 3.
+After apic_write.
+In relocation handler: cpu 3
+New SMBASE=0xbffff400 IEDBASE=0xc0400000 @ 0003fc00
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 3.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU #0 initialized
+Waiting for 1 CPUS to stop
+Initializing CPU #3
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [820000:bfffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 13480 size 6400
+microcode: sig=0x306a9 pf=0x10 revision=0x20
+CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz.
+CPU: platform id 4
+CPU: cpuid(1) 0x306a9
+CPU: AES supported
+CPU: TXT supported
+CPU: VT supported
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+CPU physical address size: 36 bits
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local APIC... apic_id: 0x03 done.
+VMX status: enabled, locked
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 2900
+CPU #3 initialized
+All AP CPUs stopped (444 loops)
+CPU0: stack: bffaf000 - bffb0000, lowest used address bffafaac, stack used: 1364 bytes
+CPU1: stack: bffae000 - bffaf000, lowest used address bffaec6c, stack used: 916 bytes
+CPU2: stack: bffad000 - bffae000, lowest used address bffadc6c, stack used: 916 bytes
+CPU3: stack: bffac000 - bffad000, lowest used address bffacc6c, stack used: 916 bytes
+CPU_CLUSTER: 0 init finished in 80412 usecs
+PCI: 00:00.0 init ...
+Disabling PEG12.
+Disabling PEG11.
+Disabling PEG10.
+Disabling PEG60.
+Disabling Device 7.
+Disabling PEG IO clock.
+Set BIOS_RESET_CPL
+CPU TDP: 35 Watts
+PCI: 00:00.0 init finished in 1014 usecs
+PCI: 00:02.0 init ...
+GT Power Management Init
+IVB GT2 25W-35W Power Meter Weights
+GT Power Management Init (post VBIOS)
+PCI: 00:02.0 init finished in 356 usecs
+PCI: 00:04.0 init ...
+PCI: 00:04.0 init finished in 1 usecs
+PCI: 00:14.0 init ...
+XHCI: Setting up controller.. done.
+PCI: 00:14.0 init finished in 7 usecs
+PCI: 00:16.0 init ...
+ME: BIOS path: S3 Wake
+PCI: 00:16.0: Disabling device
+PCI: 00:16.0 init finished in 10 usecs
+PCI: 00:19.0 init ...
+PCI: 00:19.0 init finished in 1 usecs
+PCI: 00:1a.0 init ...
+EHCI: Setting up controller.. done.
+PCI: 00:1a.0 init finished in 12 usecs
+PCI: 00:1b.0 init ...
+Azalia: base = e1638000
+Azalia: codec_mask = 09
+Azalia: Initializing codec #3
+Azalia: codec viddid: 80862806
+Azalia: verb_size: 16
+Azalia: verb loaded.
+Azalia: Initializing codec #0
+Azalia: codec viddid: 10ec0269
+Azalia: verb_size: 76
+Azalia: verb loaded.
+PCI: 00:1b.0 init finished in 5972 usecs
+PCI: 00:1c.0 init ...
+Initializing PCH PCIe bridge.
+PCI: 00:1c.0 init finished in 10 usecs
+PCI: 00:1c.1 init ...
+Initializing PCH PCIe bridge.
+PCI: 00:1c.1 init finished in 10 usecs
+PCI: 00:1c.2 init ...
+Initializing PCH PCIe bridge.
+PCI: 00:1c.2 init finished in 12 usecs
+PCI: 00:1d.0 init ...
+EHCI: Setting up controller.. done.
+PCI: 00:1d.0 init finished in 12 usecs
+PCI: 00:1f.0 init ...
+pch: lpc_init
+PCH: detected QM77, device id: 0x1e55, rev id 0x4
+IOAPIC: Initializing IOAPIC at 0xfec00000
+IOAPIC: Bootstrap Processor Local APIC = 0x00
+IOAPIC: ID = 0x02
+IOAPIC: Dumping registers
+ reg 0x0000: 0x02000000
+ reg 0x0001: 0x00170020
+ reg 0x0002: 0x00170020
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+Set power off after power failure.
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+NMI sources enabled.
+PantherPoint PM init
+rtc_failed = 0x0
+Enabling BIOS updates outside of SMM... pch_spi_init
+PCI: 00:1f.0 init finished in 553 usecs
+PCI: 00:1f.2 init ...
+SATA: Initializing...
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+SATA: Controller in AHCI mode.
+ABAR: e163e000
+PCI: 00:1f.2 init finished in 343 usecs
+PCI: 00:1f.3 init ...
+PCI: 00:1f.3 init finished in 7 usecs
+PCI: 00:1f.6 init ...
+PCI: 00:1f.6 init finished in 1 usecs
+PCI: 01:00.0 init ...
+PCI: 01:00.0 init finished in 15 usecs
+PCI: 02:00.0 init ...
+PCI: 02:00.0 init finished in 1 usecs
+PNP: 00ff.2 init ...
+PNP: 00ff.2 init finished in 1 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:54 init ...
+I2C: 01:54 init finished in 1 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:55 init ...
+I2C: 01:55 init finished in 1 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:56 init ...
+I2C: 01:56 init finished in 1 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:57 init ...
+I2C: 01:57 init finished in 1 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:5c init ...
+Locking EEPROM RFID
+init EEPROM done
+I2C: 01:5c init finished in 25630 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:5d init ...
+I2C: 01:5d init finished in 1 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:5e init ...
+I2C: 01:5e init finished in 1 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:5f init ...
+I2C: 01:5f init finished in 1 usecs
+Devices initialized
+Show all devs... After init.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+DOMAIN: 0000: enabled 1
+APIC: 00: enabled 1
+APIC: acac: enabled 0
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 0
+PCI: 00:02.0: enabled 1
+PCI: 00:14.0: enabled 1
+PCI: 00:16.0: enabled 0
+PCI: 00:16.1: enabled 0
+PCI: 00:16.2: enabled 0
+PCI: 00:16.3: enabled 0
+PCI: 00:19.0: enabled 1
+PCI: 00:1a.0: enabled 1
+PCI: 00:1b.0: enabled 1
+PCI: 00:1c.0: enabled 1
+PCI: 00:1c.1: enabled 1
+PCI: 00:1c.2: enabled 1
+PCI: 00:1c.3: enabled 0
+PCI: 00:1c.4: enabled 0
+PCI: 00:1c.5: enabled 0
+PCI: 00:1c.6: enabled 0
+PCI: 00:1c.7: enabled 0
+PCI: 00:1d.0: enabled 1
+PCI: 00:1e.0: enabled 0
+PCI: 00:1f.0: enabled 1
+PCI: 00:1f.2: enabled 1
+PCI: 00:1f.3: enabled 1
+PCI: 00:1f.5: enabled 0
+PCI: 00:1f.6: enabled 1
+PCI: 01:00.0: enabled 1
+PNP: 00ff.1: enabled 1
+PNP: 0c31.0: enabled 1
+PNP: 00ff.2: enabled 1
+I2C: 01:54: enabled 1
+I2C: 01:55: enabled 1
+I2C: 01:56: enabled 1
+I2C: 01:57: enabled 1
+I2C: 01:5c: enabled 1
+I2C: 01:5d: enabled 1
+I2C: 01:5e: enabled 1
+I2C: 01:5f: enabled 1
+PCI: 00:04.0: enabled 1
+PCI: 02:00.0: enabled 1
+NONE: enabled 1
+APIC: 01: enabled 1
+APIC: 02: enabled 1
+APIC: 03: enabled 1
+BS: BS_DEV_INIT times (us): entry 105005 run 114413 exit 0
+Finalize devices...
+PCI: 00:1f.0 final
+Devices finalized
+BS: BS_POST_DEVICE times (us): entry 0 run 43 exit 0
+Trying to find the wakeup vector...
+Looking on 000f6810 for valid checksum
+Checksum 1 passed
+Checksum 2 passed all OK
+RSDP found at 000f6810
+RSDT found at bff32030 ends at bff32070
+FADT found at bff35b10
+FACS found at bff32240
+OS waking vector is 0009a1d0
+BS: BS_OS_RESUME_CHECK times (us): entry 0 run 10 exit 0
+
+*** Pre-CBMEM romstage console overflowed, log truncated! ***
+aining (1).
+100MHz reference clock support: yes
+Trying CAS 9, tCK 384.
+Found compatible clock, CAS pair.
+Selected DRAM frequency: 666 MHz
+Selected CAS latency : 9T
+PLL busy... done in 70 us
+MCU frequency is set at : 666 MHz
+Done dimm mapping
+Update PCI-E configuration space:
+PCI(0, 0, 0)[a0] = 0
+PCI(0, 0, 0)[a4] = 4
+PCI(0, 0, 0)[bc] = c2a00000
+PCI(0, 0, 0)[a8] = 3d600000
+PCI(0, 0, 0)[ac] = 4
+PCI(0, 0, 0)[b8] = c0000000
+PCI(0, 0, 0)[b0] = c0a00000
+PCI(0, 0, 0)[b4] = c0800000
+Done memory map
+Done io registers
+t123: 1912, 6000, 7620
+ME: FW Partition Table : OK
+ME: Bringup Loader Failure : NO
+ME: Firmware Init Complete : NO
+ME: Manufacturing Mode : YES
+ME: Boot Options Present : NO
+ME: Update In Progress : NO
+ME: Current Working State : Initializing
+ME: Current Operation State : Bring up
+ME: Current Operation Mode : Debug or Disabled by AltDisableBit
+ME: Error Code : No Error
+ME: Progress Phase : BUP Phase
+ME: Power Management Event : Clean Moff->Mx wake
+ME: Progress Phase State : Check to see if straps say ME DISABLED
+ME: Wrong mode : 2
+ME: FWS2: 0x100a0140
+ME: Bist in progress: 0x0
+ME: ICC Status : 0x0
+ME: Invoke MEBx : 0x0
+ME: CPU replaced : 0x0
+ME: MBP ready : 0x0
+ME: MFS failure : 0x1
+ME: Warm reset req : 0x0
+ME: CPU repl valid : 0x1
+ME: (Reserved) : 0x0
+ME: FW update req : 0x0
+ME: (Reserved) : 0x0
+ME: Current state : 0xa
+ME: Current PM event: 0x0
+ME: Progress code : 0x1
+PASSED! Tell ME that DRAM is ready
+ME: ME is reporting as disabled, so not waiting for a response.
+ME: FWS2: 0x100a0140
+ME: Bist in progress: 0x0
+ME: ICC Status : 0x0
+ME: Invoke MEBx : 0x0
+ME: CPU replaced : 0x0
+ME: MBP ready : 0x0
+ME: MFS failure : 0x1
+ME: Warm reset req : 0x0
+ME: CPU repl valid : 0x1
+ME: (Reserved) : 0x0
+ME: FW update req : 0x0
+ME: (Reserved) : 0x0
+ME: Current state : 0xa
+ME: Current PM event: 0x0
+ME: Progress code : 0x1
+ME: Requested BIOS Action: No DID Ack received
+ME: FW Partition Table : OK
+ME: Bringup Loader Failure : NO
+ME: Firmware Init Complete : NO
+ME: Manufacturing Mode : YES
+ME: Boot Options Present : NO
+ME: Update In Progress : NO
+ME: Current Working State : Initializing
+ME: Current Operation State : Bring up
+ME: Current Operation Mode : Debug or Disabled by AltDisableBit
+ME: Error Code : No Error
+ME: Progress Phase : BUP Phase
+ME: Power Management Event : Clean Moff->Mx wake
+ME: Progress Phase State : Check to see if straps say ME DISABLED
+memcfg DDR3 ref clock 133 MHz
+memcfg DDR3 clock 1330 MHz
+memcfg channel assignment: A: 0, B 1, C 2
+memcfg channel[0] config (00620020):
+ ECC inactive
+ enhanced interleave mode on
+ rank interleave on
+ DIMMA 8192 MB width x8 dual rank, selected
+ DIMMB 0 MB width x8 single rank
+memcfg channel[1] config (00620020):
+ ECC inactive
+ enhanced interleave mode on
+ rank interleave on
+ DIMMA 8192 MB width x8 dual rank, selected
+ DIMMB 0 MB width x8 single rank
+CBMEM entry for DIMM info: 0xbfffeaa0
+MTRR Range: Start=ff000000 End=0 (Size 1000000)
+MTRR Range: Start=0 End=1000000 (Size 1000000)
+MTRR Range: Start=bf800000 End=c0000000 (Size 800000)
+MTRR Range: Start=c0000000 End=c0800000 (Size 800000)
+
+
+coreboot-4.8-1053-g4591bb6f7b Mon Aug 6 07:37:48 UTC 2018 postcar starting...
+Jumping to image.
+
+
+coreboot-4.8-1053-g4591bb6f7b Mon Aug 6 07:37:48 UTC 2018 ramstage starting...
+S3 Resume.
+BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0
+BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1 exit 0
+Enumerating buses...
+Show all devs... Before device enumeration.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+DOMAIN: 0000: enabled 1
+APIC: 00: enabled 1
+APIC: acac: enabled 0
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 0
+PCI: 00:02.0: enabled 1
+PCI: 00:14.0: enabled 1
+PCI: 00:16.0: enabled 1
+PCI: 00:16.1: enabled 0
+PCI: 00:16.2: enabled 0
+PCI: 00:16.3: enabled 0
+PCI: 00:19.0: enabled 1
+PCI: 00:1a.0: enabled 1
+PCI: 00:1b.0: enabled 1
+PCI: 00:1c.0: enabled 1
+PCI: 00:1c.1: enabled 1
+PCI: 00:1c.2: enabled 1
+PCI: 00:1c.3: enabled 0
+PCI: 00:1c.4: enabled 0
+PCI: 00:1c.5: enabled 0
+PCI: 00:1c.6: enabled 0
+PCI: 00:1c.7: enabled 0
+PCI: 00:1d.0: enabled 1
+PCI: 00:1e.0: enabled 0
+PCI: 00:1f.0: enabled 1
+PCI: 00:1f.2: enabled 1
+PCI: 00:1f.3: enabled 1
+PCI: 00:1f.5: enabled 0
+PCI: 00:1f.6: enabled 1
+PCI: 00:00.0: enabled 1
+PNP: 00ff.1: enabled 1
+PNP: 0c31.0: enabled 1
+PNP: 00ff.2: enabled 1
+I2C: 00:54: enabled 1
+I2C: 00:55: enabled 1
+I2C: 00:56: enabled 1
+I2C: 00:57: enabled 1
+I2C: 00:5c: enabled 1
+I2C: 00:5d: enabled 1
+I2C: 00:5e: enabled 1
+I2C: 00:5f: enabled 1
+Compare with tree...
+Root Device: enabled 1
+ CPU_CLUSTER: 0: enabled 1
+ APIC: 00: enabled 1
+ APIC: acac: enabled 0
+ DOMAIN: 0000: enabled 1
+ PCI: 00:00.0: enabled 1
+ PCI: 00:01.0: enabled 0
+ PCI: 00:02.0: enabled 1
+ PCI: 00:14.0: enabled 1
+ PCI: 00:16.0: enabled 1
+ PCI: 00:16.1: enabled 0
+ PCI: 00:16.2: enabled 0
+ PCI: 00:16.3: enabled 0
+ PCI: 00:19.0: enabled 1
+ PCI: 00:1a.0: enabled 1
+ PCI: 00:1b.0: enabled 1
+ PCI: 00:1c.0: enabled 1
+ PCI: 00:00.0: enabled 1
+ PCI: 00:1c.1: enabled 1
+ PCI: 00:1c.2: enabled 1
+ PCI: 00:1c.3: enabled 0
+ PCI: 00:1c.4: enabled 0
+ PCI: 00:1c.5: enabled 0
+ PCI: 00:1c.6: enabled 0
+ PCI: 00:1c.7: enabled 0
+ PCI: 00:1d.0: enabled 1
+ PCI: 00:1e.0: enabled 0
+ PCI: 00:1f.0: enabled 1
+ PNP: 00ff.1: enabled 1
+ PNP: 0c31.0: enabled 1
+ PNP: 00ff.2: enabled 1
+ PCI: 00:1f.2: enabled 1
+ PCI: 00:1f.3: enabled 1
+ I2C: 00:54: enabled 1
+ I2C: 00:55: enabled 1
+ I2C: 00:56: enabled 1
+ I2C: 00:57: enabled 1
+ I2C: 00:5c: enabled 1
+ I2C: 00:5d: enabled 1
+ I2C: 00:5e: enabled 1
+ I2C: 00:5f: enabled 1
+ PCI: 00:1f.5: enabled 0
+ PCI: 00:1f.6: enabled 1
+Root Device scanning...
+root_dev_scan_bus for Root Device
+CPU_CLUSTER: 0 enabled
+DOMAIN: 0000 enabled
+DOMAIN: 0000 scanning...
+PCI: pci_scan_bus for bus 00
+PCI: 00:00.0 [8086/0154] ops
+PCI: 00:00.0 [8086/0154] enabled
+PCI: 00:01.0 [8086/0000] bus ops
+PCI: 00:01.0 [8086/0151] disabled
+PCI: 00:02.0 [8086/0000] ops
+PCI: 00:02.0 [8086/0166] enabled
+PCI: 00:04.0 [8086/0153] enabled
+PCI: 00:14.0 [8086/0000] ops
+PCI: 00:14.0 [8086/1e31] enabled
+PCI: 00:16.0 [8086/1e3a] ops
+PCI: 00:16.0 [8086/1e3a] enabled
+PCI: 00:16.1: Disabling device
+PCI: 00:16.2: Disabling device
+PCI: 00:16.3: Disabling device
+PCI: 00:19.0 [8086/1502] enabled
+PCI: 00:1a.0 [8086/0000] ops
+PCI: 00:1a.0 [8086/1e2d] enabled
+PCI: 00:1b.0 [8086/0000] ops
+PCI: 00:1b.0 [8086/1e20] enabled
+PCH: PCIe Root Port coalescing is enabled
+PCI: 00:1c.0 [8086/0000] bus ops
+PCI: 00:1c.0 [8086/1e10] enabled
+PCI: 00:1c.1 [8086/0000] bus ops
+PCI: 00:1c.1 [8086/1e12] enabled
+PCI: 00:1c.2 [8086/0000] bus ops
+PCI: 00:1c.2 [8086/1e14] enabled
+PCI: 00:1c.3: Disabling device
+PCI: 00:1c.3 [8086/0000] bus ops
+PCI: 00:1c.3 [8086/1e16] disabled
+PCI: 00:1c.4: Disabling device
+PCI: 00:1c.4: check set enabled
+PCI: 00:1c.5: Disabling device
+PCI: 00:1c.6: Disabling device
+PCI: 00:1c.7: Disabling device
+PCH: RPFN 0x76543210 -> 0xfedcb210
+PCI: 00:1d.0 [8086/0000] ops
+PCI: 00:1d.0 [8086/1e26] enabled
+PCI: 00:1e.0: Disabling device
+PCI: 00:1e.0 [8086/2448] bus ops
+PCI: 00:1e.0 [8086/2448] disabled
+PCI: 00:1f.0 [8086/0000] bus ops
+PCI: 00:1f.0 [8086/1e55] enabled
+PCI: 00:1f.2 [8086/0000] ops
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+PCI: 00:1f.2 [8086/1e01] enabled
+PCI: 00:1f.3 [8086/0000] bus ops
+PCI: 00:1f.3 [8086/1e22] enabled
+PCI: 00:1f.5: Disabling device
+PCI: 00:1f.5 [8086/1e09] disabled No operations
+PCI: 00:1f.6 [8086/1e24] enabled
+PCI: 00:1c.0 scanning...
+do_pci_scan_bridge for PCI: 00:1c.0
+PCI: pci_scan_bus for bus 01
+PCI: 01:00.0 [1180/0000] ops
+PCI: 01:00.0 [1180/e823] enabled
+Capability: type 0x05 @ 0x50
+Capability: type 0x01 @ 0x78
+Capability: type 0x10 @ 0x80
+Capability: type 0x10 @ 0x40
+Enabling Common Clock Configuration
+ASPM: Enabled L0s and L1
+Capability: type 0x05 @ 0x50
+Capability: type 0x01 @ 0x78
+Capability: type 0x10 @ 0x80
+Failed to enable LTR for dev = PCI: 01:00.0
+scan_bus: scanning of bus PCI: 00:1c.0 took 243 usecs
+PCI: 00:1c.1 scanning...
+do_pci_scan_bridge for PCI: 00:1c.1
+PCI: pci_scan_bus for bus 02
+PCI: 02:00.0 [168c/002b] enabled
+Capability: type 0x01 @ 0x40
+Capability: type 0x05 @ 0x50
+Capability: type 0x10 @ 0x60
+Capability: type 0x10 @ 0x40
+Enabling Common Clock Configuration
+ASPM: Enabled L0s and L1
+Capability: type 0x01 @ 0x40
+Capability: type 0x05 @ 0x50
+Capability: type 0x10 @ 0x60
+Failed to enable LTR for dev = PCI: 02:00.0
+scan_bus: scanning of bus PCI: 00:1c.1 took 210 usecs
+PCI: 00:1c.2 scanning...
+do_pci_scan_bridge for PCI: 00:1c.2
+PCI: pci_scan_bus for bus 03
+scan_bus: scanning of bus PCI: 00:1c.2 took 40 usecs
+PCI: 00:1f.0 scanning...
+scan_lpc_bus for PCI: 00:1f.0
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+PMH7: ID 05 Revision 12
+PNP: 00ff.1 enabled
+PNP: 0c31.0 enabled
+Clearing EC output queue...
+EC output queue has been cleared.
+recv_ec_data: 0x47
+recv_ec_data: 0x32
+recv_ec_data: 0x48
+recv_ec_data: 0x54
+recv_ec_data: 0x33
+recv_ec_data: 0x35
+recv_ec_data: 0x57
+recv_ec_data: 0x57
+recv_ec_data: 0x16
+recv_ec_data: 0x03
+recv_ec_data: 0x40
+recv_ec_data: 0x11
+EC Firmware ID G2HT35WW-3.22, Version 4.01B
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+recv_ec_data: 0x00
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+recv_ec_data: 0x01
+recv_ec_data: 0x80
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+H8: BDC detection not implemented. Assuming BDC installed
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+recv_ec_data: 0x21
+H8: WWAN not installed
+recv_ec_data: 0x31
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+recv_ec_data: 0x00
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+recv_ec_data: 0xa6
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+recv_ec_data: 0xa6
+recv_ec_data: 0x31
+PNP: 00ff.2 enabled
+scan_lpc_bus for PCI: 00:1f.0 done
+scan_bus: scanning of bus PCI: 00:1f.0 took 4640 usecs
+PCI: 00:1f.3 scanning...
+scan_generic_bus for PCI: 00:1f.3
+bus: PCI: 00:1f.3[0]->I2C: 01:54 enabled
+bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled
+bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled
+bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled
+bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled
+bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled
+bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled
+bus: PCI: 00:1f.3[0]->I2C: 01:5f enabled
+scan_generic_bus for PCI: 00:1f.3 done
+scan_bus: scanning of bus PCI: 00:1f.3 took 18 usecs
+scan_bus: scanning of bus DOMAIN: 0000 took 5459 usecs
+root_dev_scan_bus for Root Device done
+scan_bus: scanning of bus Root Device took 5466 usecs
+done
+FMAP: area RW_MRC_CACHE found @ 810000 (65536 bytes)
+MRC: Checking cached data update for 'RW_MRC_CACHE'.
+flash size 0xc00000 bytes
+SF: Detected Opaque HW-sequencing with sector size 0x100, total 0xc00000
+BS: BS_DEV_ENUMERATE times (us): entry 0 run 5558 exit 266
+found VGA at PCI: 00:02.0
+Setting up VGA for PCI: 00:02.0
+Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
+Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
+Allocating resources...
+Reading resources...
+Root Device read_resources bus 0 link: 0
+CPU_CLUSTER: 0 read_resources bus 0 link: 0
+CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
+DOMAIN: 0000 read_resources bus 0 link: 0
+Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
+PCI: 00:1c.0 read_resources bus 1 link: 0
+PCI: 00:1c.0 read_resources bus 1 link: 0 done
+PCI: 00:1c.1 read_resources bus 2 link: 0
+PCI: 00:1c.1 read_resources bus 2 link: 0 done
+PCI: 00:1c.2 read_resources bus 3 link: 0
+PCI: 00:1c.2 read_resources bus 3 link: 0 done
+PCI: 00:1f.0 read_resources bus 0 link: 0
+PNP: 00ff.1 missing read_resources
+PNP: 00ff.2 missing read_resources
+PCI: 00:1f.0 read_resources bus 0 link: 0 done
+PCI: 00:1f.3 read_resources bus 1 link: 0
+PCI: 00:1f.3 read_resources bus 1 link: 0 done
+DOMAIN: 0000 read_resources bus 0 link: 0 done
+Root Device read_resources bus 0 link: 0 done
+Done reading resources.
+Show resources in subtree (Root Device)...After reading.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 00
+ APIC: 00
+ APIC: acac
+ DOMAIN: 0000 child on link 0 PCI: 00:00.0
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
+ PCI: 00:00.0
+ PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60
+ PCI: 00:01.0
+ PCI: 00:02.0
+ PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
+ PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
+ PCI: 00:04.0
+ PCI: 00:04.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:14.0
+ PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:16.0
+ PCI: 00:16.0 resource base 0 size 10 align 12 gran 4 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:16.1
+ PCI: 00:16.2
+ PCI: 00:16.3
+ PCI: 00:19.0
+ PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
+ PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
+ PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
+ PCI: 00:1a.0
+ PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
+ PCI: 00:1b.0
+ PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:1c.0 child on link 0 PCI: 01:00.0
+ PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 01:00.0
+ PCI: 01:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
+ PCI: 00:1c.1 child on link 0 PCI: 02:00.0
+ PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 02:00.0
+ PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:1c.2 child on link 0 NONE
+ PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ NONE
+ NONE resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 200 index 10
+ NONE resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 1200 index 14
+ NONE resource base 0 size 1000 align 12 gran 12 limit ffff flags 100 index 18
+ PCI: 00:1c.3
+ PCI: 00:1c.4
+ PCI: 00:1c.5
+ PCI: 00:1c.6
+ PCI: 00:1c.7
+ PCI: 00:1d.0
+ PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
+ PCI: 00:1e.0
+ PCI: 00:1f.0 child on link 0 PNP: 00ff.1
+ PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
+ PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
+ PNP: 00ff.1
+ PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
+ PNP: 0c31.0
+ PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0
+ PNP: 00ff.2
+ PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
+ PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
+ PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
+ PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
+ PCI: 00:1f.2
+ PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
+ PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
+ PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
+ PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
+ PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
+ PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
+ PCI: 00:1f.3 child on link 0 I2C: 01:54
+ PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
+ PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
+ I2C: 01:54
+ I2C: 01:55
+ I2C: 01:56
+ I2C: 01:57
+ I2C: 01:5c
+ I2C: 01:5d
+ I2C: 01:5e
+ I2C: 01:5f
+ PCI: 00:1f.5
+ PCI: 00:1f.6
+ PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
+DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
+PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
+PCI: 00:1c.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:1c.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
+PCI: 00:1c.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+NONE 18 * [0x0 - 0xfff] io
+PCI: 00:1c.2 io: base: 1000 size: 1000 align: 12 gran: 12 limit: ffff done
+PCI: 00:1c.2 1c * [0x0 - 0xfff] io
+PCI: 00:02.0 20 * [0x1000 - 0x103f] io
+PCI: 00:19.0 18 * [0x1040 - 0x105f] io
+PCI: 00:1f.2 20 * [0x1060 - 0x107f] io
+PCI: 00:1f.2 10 * [0x1080 - 0x1087] io
+PCI: 00:1f.2 18 * [0x1088 - 0x108f] io
+PCI: 00:1f.2 14 * [0x1090 - 0x1093] io
+PCI: 00:1f.2 1c * [0x1094 - 0x1097] io
+DOMAIN: 0000 io: base: 1098 size: 1098 align: 12 gran: 0 limit: ffff done
+DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
+PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 01:00.0 10 * [0x0 - 0xff] mem
+PCI: 00:1c.0 mem: base: 100 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:1c.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:1c.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:1c.1 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 02:00.0 10 * [0x0 - 0xffff] mem
+PCI: 00:1c.1 mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:1c.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+NONE 14 * [0x0 - 0x7fffff] prefmem
+PCI: 00:1c.2 prefmem: base: 800000 size: 800000 align: 22 gran: 20 limit: ffffffff done
+PCI: 00:1c.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+NONE 10 * [0x0 - 0x7fffff] mem
+PCI: 00:1c.2 mem: base: 800000 size: 800000 align: 22 gran: 20 limit: ffffffff done
+PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
+PCI: 00:1c.2 24 * [0x10000000 - 0x107fffff] prefmem
+PCI: 00:1c.2 20 * [0x10800000 - 0x10ffffff] mem
+PCI: 00:02.0 10 * [0x11000000 - 0x113fffff] mem
+PCI: 00:1c.0 20 * [0x11400000 - 0x114fffff] mem
+PCI: 00:1c.1 20 * [0x11500000 - 0x115fffff] mem
+PCI: 00:19.0 10 * [0x11600000 - 0x1161ffff] mem
+PCI: 00:14.0 10 * [0x11620000 - 0x1162ffff] mem
+PCI: 00:04.0 10 * [0x11630000 - 0x11637fff] mem
+PCI: 00:1b.0 10 * [0x11638000 - 0x1163bfff] mem
+PCI: 00:19.0 14 * [0x1163c000 - 0x1163cfff] mem
+PCI: 00:1f.6 10 * [0x1163d000 - 0x1163dfff] mem
+PCI: 00:1f.2 24 * [0x1163e000 - 0x1163e7ff] mem
+PCI: 00:1a.0 10 * [0x1163f000 - 0x1163f3ff] mem
+PCI: 00:1d.0 10 * [0x11640000 - 0x116403ff] mem
+PCI: 00:1f.3 10 * [0x11641000 - 0x116410ff] mem
+PCI: 00:16.0 10 * [0x11642000 - 0x1164200f] mem
+DOMAIN: 0000 mem: base: 11642010 size: 11642010 align: 28 gran: 0 limit: ffffffff done
+avoid_fixed_resources: DOMAIN: 0000
+avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
+avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
+constrain_resources: PCI: 00:00.0 60 base f0000000 limit f3ffffff mem (fixed)
+constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
+constrain_resources: PCI: 00:1f.0 10000200 base 00001600 limit 0000167b io (fixed)
+skipping PNP: 00ff.2@60 fixed resource, size=0!
+skipping PNP: 00ff.2@62 fixed resource, size=0!
+skipping PNP: 00ff.2@64 fixed resource, size=0!
+skipping PNP: 00ff.2@66 fixed resource, size=0!
+avoid_fixed_resources:@DOMAIN: 0000 10000000 base 0000167c limit 0000ffff
+avoid_fixed_resources:@DOMAIN: 0000 10000100 base d0000000 limit efffffff
+Setting resources...
+DOMAIN: 0000 io: base:167c size:1098 align:12 gran:0 limit:ffff
+PCI: 00:1c.2 1c * [0x2000 - 0x2fff] io
+PCI: 00:02.0 20 * [0x3000 - 0x303f] io
+PCI: 00:19.0 18 * [0x3040 - 0x305f] io
+PCI: 00:1f.2 20 * [0x3060 - 0x307f] io
+PCI: 00:1f.2 10 * [0x3080 - 0x3087] io
+PCI: 00:1f.2 18 * [0x3088 - 0x308f] io
+PCI: 00:1f.2 14 * [0x3090 - 0x3093] io
+PCI: 00:1f.2 1c * [0x3094 - 0x3097] io
+DOMAIN: 0000 io: next_base: 3098 size: 1098 align: 12 gran: 0 done
+PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff
+PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done
+PCI: 00:1c.1 io: base:ffff size:0 align:12 gran:12 limit:ffff
+PCI: 00:1c.1 io: next_base: ffff size: 0 align: 12 gran: 12 done
+PCI: 00:1c.2 io: base:2000 size:1000 align:12 gran:12 limit:2fff
+NONE 18 * [0x2000 - 0x2fff] io
+PCI: 00:1c.2 io: next_base: 3000 size: 1000 align: 12 gran: 12 done
+DOMAIN: 0000 mem: base:d0000000 size:11642010 align:28 gran:0 limit:efffffff
+PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem
+PCI: 00:1c.2 24 * [0xe0000000 - 0xe07fffff] prefmem
+PCI: 00:1c.2 20 * [0xe0800000 - 0xe0ffffff] mem
+PCI: 00:02.0 10 * [0xe1000000 - 0xe13fffff] mem
+PCI: 00:1c.0 20 * [0xe1400000 - 0xe14fffff] mem
+PCI: 00:1c.1 20 * [0xe1500000 - 0xe15fffff] mem
+PCI: 00:19.0 10 * [0xe1600000 - 0xe161ffff] mem
+PCI: 00:14.0 10 * [0xe1620000 - 0xe162ffff] mem
+PCI: 00:04.0 10 * [0xe1630000 - 0xe1637fff] mem
+PCI: 00:1b.0 10 * [0xe1638000 - 0xe163bfff] mem
+PCI: 00:19.0 14 * [0xe163c000 - 0xe163cfff] mem
+PCI: 00:1f.6 10 * [0xe163d000 - 0xe163dfff] mem
+PCI: 00:1f.2 24 * [0xe163e000 - 0xe163e7ff] mem
+PCI: 00:1a.0 10 * [0xe163f000 - 0xe163f3ff] mem
+PCI: 00:1d.0 10 * [0xe1640000 - 0xe16403ff] mem
+PCI: 00:1f.3 10 * [0xe1641000 - 0xe16410ff] mem
+PCI: 00:16.0 10 * [0xe1642000 - 0xe164200f] mem
+DOMAIN: 0000 mem: next_base: e1642010 size: 11642010 align: 28 gran: 0 done
+PCI: 00:1c.0 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:1c.0 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1c.0 mem: base:e1400000 size:100000 align:20 gran:20 limit:e14fffff
+PCI: 01:00.0 10 * [0xe1400000 - 0xe14000ff] mem
+PCI: 00:1c.0 mem: next_base: e1400100 size: 100000 align: 20 gran: 20 done
+PCI: 00:1c.1 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:1c.1 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1c.1 mem: base:e1500000 size:100000 align:20 gran:20 limit:e15fffff
+PCI: 02:00.0 10 * [0xe1500000 - 0xe150ffff] mem
+PCI: 00:1c.1 mem: next_base: e1510000 size: 100000 align: 20 gran: 20 done
+PCI: 00:1c.2 prefmem: base:e0000000 size:800000 align:22 gran:20 limit:e07fffff
+NONE 14 * [0xe0000000 - 0xe07fffff] prefmem
+PCI: 00:1c.2 prefmem: next_base: e0800000 size: 800000 align: 22 gran: 20 done
+PCI: 00:1c.2 mem: base:e0800000 size:800000 align:22 gran:20 limit:e0ffffff
+NONE 10 * [0xe0800000 - 0xe0ffffff] mem
+PCI: 00:1c.2 mem: next_base: e1000000 size: 800000 align: 22 gran: 20 done
+Root Device assign_resources, bus 0 link: 0
+TOUUD 0x43d600000 TOLUD 0xc2a00000 TOM 0x400000000
+MEBASE 0x7ffff00000
+IGD decoded, subtracting 32M UMA and 2M GTT
+TSEG base 0xc0000000 size 8M
+Available memory below 4GB: 3072M
+Available memory above 4GB: 13270M
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+PCI: 00:02.0 10 <- [0x00e1000000 - 0x00e13fffff] size 0x00400000 gran 0x16 mem64
+PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64
+PCI: 00:02.0 20 <- [0x0000003000 - 0x000000303f] size 0x00000040 gran 0x06 io
+PCI: 00:04.0 10 <- [0x00e1630000 - 0x00e1637fff] size 0x00008000 gran 0x0f mem64
+PCI: 00:14.0 10 <- [0x00e1620000 - 0x00e162ffff] size 0x00010000 gran 0x10 mem64
+PCI: 00:16.0 10 <- [0x00e1642000 - 0x00e164200f] size 0x00000010 gran 0x04 mem64
+PCI: 00:19.0 10 <- [0x00e1600000 - 0x00e161ffff] size 0x00020000 gran 0x11 mem
+PCI: 00:19.0 14 <- [0x00e163c000 - 0x00e163cfff] size 0x00001000 gran 0x0c mem
+PCI: 00:19.0 18 <- [0x0000003040 - 0x000000305f] size 0x00000020 gran 0x05 io
+PCI: 00:1a.0 10 <- [0x00e163f000 - 0x00e163f3ff] size 0x00000400 gran 0x0a mem
+PCI: 00:1b.0 10 <- [0x00e1638000 - 0x00e163bfff] size 0x00004000 gran 0x0e mem64
+PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
+PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem
+PCI: 00:1c.0 20 <- [0x00e1400000 - 0x00e14fffff] size 0x00100000 gran 0x14 bus 01 mem
+PCI: 00:1c.0 assign_resources, bus 1 link: 0
+PCI: 01:00.0 10 <- [0x00e1400000 - 0x00e14000ff] size 0x00000100 gran 0x08 mem
+PCI: 00:1c.0 assign_resources, bus 1 link: 0
+PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
+PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem
+PCI: 00:1c.1 20 <- [0x00e1500000 - 0x00e15fffff] size 0x00100000 gran 0x14 bus 02 mem
+PCI: 00:1c.1 assign_resources, bus 2 link: 0
+PCI: 02:00.0 10 <- [0x00e1500000 - 0x00e150ffff] size 0x00010000 gran 0x10 mem64
+PCI: 00:1c.1 assign_resources, bus 2 link: 0
+PCI: 00:1c.2 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 03 io
+PCI: 00:1c.2 24 <- [0x00e0000000 - 0x00e07fffff] size 0x00800000 gran 0x14 bus 03 prefmem
+PCI: 00:1c.2 20 <- [0x00e0800000 - 0x00e0ffffff] size 0x00800000 gran 0x14 bus 03 mem
+PCI: 00:1c.2 assign_resources, bus 3 link: 0
+NONE missing set_resources
+PCI: 00:1c.2 assign_resources, bus 3 link: 0
+PCI: 00:1d.0 10 <- [0x00e1640000 - 0x00e16403ff] size 0x00000400 gran 0x0a mem
+PCI: 00:1f.0 assign_resources, bus 0 link: 0
+PNP: 00ff.1 missing set_resources
+PNP: 00ff.2 missing set_resources
+PCI: 00:1f.0 assign_resources, bus 0 link: 0
+PCI: 00:1f.2 10 <- [0x0000003080 - 0x0000003087] size 0x00000008 gran 0x03 io
+PCI: 00:1f.2 14 <- [0x0000003090 - 0x0000003093] size 0x00000004 gran 0x02 io
+PCI: 00:1f.2 18 <- [0x0000003088 - 0x000000308f] size 0x00000008 gran 0x03 io
+PCI: 00:1f.2 1c <- [0x0000003094 - 0x0000003097] size 0x00000004 gran 0x02 io
+PCI: 00:1f.2 20 <- [0x0000003060 - 0x000000307f] size 0x00000020 gran 0x05 io
+PCI: 00:1f.2 24 <- [0x00e163e000 - 0x00e163e7ff] size 0x00000800 gran 0x0b mem
+PCI: 00:1f.3 10 <- [0x00e1641000 - 0x00e16410ff] size 0x00000100 gran 0x08 mem64
+PCI: 00:1f.3 assign_resources, bus 1 link: 0
+PCI: 00:1f.3 assign_resources, bus 1 link: 0
+PCI: 00:1f.6 10 <- [0x00e163d000 - 0x00e163dfff] size 0x00001000 gran 0x0c mem64
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+Root Device assign_resources, bus 0 link: 0
+Done setting resources.
+Show resources in subtree (Root Device)...After assigning values.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 00
+ APIC: 00
+ APIC: acac
+ DOMAIN: 0000 child on link 0 PCI: 00:00.0
+ DOMAIN: 0000 resource base 167c size 1098 align 12 gran 0 limit ffff flags 40040100 index 10000000
+ DOMAIN: 0000 resource base d0000000 size 11642010 align 28 gran 0 limit efffffff flags 40040200 index 10000100
+ DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
+ DOMAIN: 0000 resource base 100000 size bff00000 align 0 gran 0 limit 0 flags e0004200 index 4
+ DOMAIN: 0000 resource base 100000000 size 33d600000 align 0 gran 0 limit 0 flags e0004200 index 5
+ DOMAIN: 0000 resource base c0000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6
+ DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7
+ DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 8
+ DOMAIN: 0000 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
+ DOMAIN: 0000 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
+ PCI: 00:00.0
+ PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60
+ PCI: 00:01.0
+ PCI: 00:02.0
+ PCI: 00:02.0 resource base e1000000 size 400000 align 22 gran 22 limit e13fffff flags 60000201 index 10
+ PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60001201 index 18
+ PCI: 00:02.0 resource base 3000 size 40 align 6 gran 6 limit 303f flags 60000100 index 20
+ PCI: 00:04.0
+ PCI: 00:04.0 resource base e1630000 size 8000 align 15 gran 15 limit e1637fff flags 60000201 index 10
+ PCI: 00:14.0
+ PCI: 00:14.0 resource base e1620000 size 10000 align 16 gran 16 limit e162ffff flags 60000201 index 10
+ PCI: 00:16.0
+ PCI: 00:16.0 resource base e1642000 size 10 align 12 gran 4 limit e164200f flags 60000201 index 10
+ PCI: 00:16.1
+ PCI: 00:16.2
+ PCI: 00:16.3
+ PCI: 00:19.0
+ PCI: 00:19.0 resource base e1600000 size 20000 align 17 gran 17 limit e161ffff flags 60000200 index 10
+ PCI: 00:19.0 resource base e163c000 size 1000 align 12 gran 12 limit e163cfff flags 60000200 index 14
+ PCI: 00:19.0 resource base 3040 size 20 align 5 gran 5 limit 305f flags 60000100 index 18
+ PCI: 00:1a.0
+ PCI: 00:1a.0 resource base e163f000 size 400 align 12 gran 10 limit e163f3ff flags 60000200 index 10
+ PCI: 00:1b.0
+ PCI: 00:1b.0 resource base e1638000 size 4000 align 14 gran 14 limit e163bfff flags 60000201 index 10
+ PCI: 00:1c.0 child on link 0 PCI: 01:00.0
+ PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
+ PCI: 00:1c.0 resource base e1400000 size 100000 align 20 gran 20 limit e14fffff flags 60080202 index 20
+ PCI: 01:00.0
+ PCI: 01:00.0 resource base e1400000 size 100 align 12 gran 8 limit e14000ff flags 60000200 index 10
+ PCI: 00:1c.1 child on link 0 PCI: 02:00.0
+ PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
+ PCI: 00:1c.1 resource base e1500000 size 100000 align 20 gran 20 limit e15fffff flags 60080202 index 20
+ PCI: 02:00.0
+ PCI: 02:00.0 resource base e1500000 size 10000 align 16 gran 16 limit e150ffff flags 60000201 index 10
+ PCI: 00:1c.2 child on link 0 NONE
+ PCI: 00:1c.2 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c
+ PCI: 00:1c.2 resource base e0000000 size 800000 align 22 gran 20 limit e07fffff flags 60081202 index 24
+ PCI: 00:1c.2 resource base e0800000 size 800000 align 22 gran 20 limit e0ffffff flags 60080202 index 20
+ NONE
+ NONE resource base e0800000 size 800000 align 22 gran 22 limit e0ffffff flags 40000200 index 10
+ NONE resource base e0000000 size 800000 align 22 gran 22 limit e07fffff flags 40001200 index 14
+ NONE resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 40000100 index 18
+ PCI: 00:1c.3
+ PCI: 00:1c.4
+ PCI: 00:1c.5
+ PCI: 00:1c.6
+ PCI: 00:1c.7
+ PCI: 00:1d.0
+ PCI: 00:1d.0 resource base e1640000 size 400 align 12 gran 10 limit e16403ff flags 60000200 index 10
+ PCI: 00:1e.0
+ PCI: 00:1f.0 child on link 0 PNP: 00ff.1
+ PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
+ PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
+ PNP: 00ff.1
+ PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
+ PNP: 0c31.0
+ PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0
+ PNP: 00ff.2
+ PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
+ PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
+ PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
+ PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
+ PCI: 00:1f.2
+ PCI: 00:1f.2 resource base 3080 size 8 align 3 gran 3 limit 3087 flags 60000100 index 10
+ PCI: 00:1f.2 resource base 3090 size 4 align 2 gran 2 limit 3093 flags 60000100 index 14
+ PCI: 00:1f.2 resource base 3088 size 8 align 3 gran 3 limit 308f flags 60000100 index 18
+ PCI: 00:1f.2 resource base 3094 size 4 align 2 gran 2 limit 3097 flags 60000100 index 1c
+ PCI: 00:1f.2 resource base 3060 size 20 align 5 gran 5 limit 307f flags 60000100 index 20
+ PCI: 00:1f.2 resource base e163e000 size 800 align 12 gran 11 limit e163e7ff flags 60000200 index 24
+ PCI: 00:1f.3 child on link 0 I2C: 01:54
+ PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
+ PCI: 00:1f.3 resource base e1641000 size 100 align 12 gran 8 limit e16410ff flags 60000201 index 10
+ I2C: 01:54
+ I2C: 01:55
+ I2C: 01:56
+ I2C: 01:57
+ I2C: 01:5c
+ I2C: 01:5d
+ I2C: 01:5e
+ I2C: 01:5f
+ PCI: 00:1f.5
+ PCI: 00:1f.6
+ PCI: 00:1f.6 resource base e163d000 size 1000 align 12 gran 12 limit e163dfff flags 60000201 index 10
+Done allocating resources.
+BS: BS_DEV_RESOURCES times (us): entry 0 run 2177 exit 0
+Enabling resources...
+PCI: 00:00.0 subsystem <- 17aa/21fa
+PCI: 00:00.0 cmd <- 06
+PCI: 00:02.0 subsystem <- 17aa/21fa
+PCI: 00:02.0 cmd <- 03
+PCI: 00:04.0 cmd <- 02
+PCI: 00:14.0 subsystem <- 17aa/21fa
+PCI: 00:14.0 cmd <- 102
+PCI: 00:16.0 subsystem <- 17aa/21fa
+PCI: 00:16.0 cmd <- 02
+PCI: 00:19.0 subsystem <- 17aa/21f3
+PCI: 00:19.0 cmd <- 103
+PCI: 00:1a.0 subsystem <- 17aa/21fa
+PCI: 00:1a.0 cmd <- 102
+PCI: 00:1b.0 subsystem <- 17aa/21fa
+PCI: 00:1b.0 cmd <- 102
+PCI: 00:1c.0 bridge ctrl <- 0003
+PCI: 00:1c.0 subsystem <- 17aa/21fa
+PCI: 00:1c.0 cmd <- 106
+PCI: 00:1c.1 bridge ctrl <- 0003
+PCI: 00:1c.1 subsystem <- 17aa/21fa
+PCI: 00:1c.1 cmd <- 106
+PCI: 00:1c.2 bridge ctrl <- 0003
+PCI: 00:1c.2 subsystem <- 17aa/21fa
+PCI: 00:1c.2 cmd <- 107
+PCI: 00:1d.0 subsystem <- 17aa/21fa
+PCI: 00:1d.0 cmd <- 102
+pch_decode_init
+PCI: 00:1f.0 subsystem <- 17aa/21fa
+PCI: 00:1f.0 cmd <- 107
+PCI: 00:1f.2 subsystem <- 17aa/21fa
+PCI: 00:1f.2 cmd <- 03
+PCI: 00:1f.3 subsystem <- 17aa/21fa
+PCI: 00:1f.3 cmd <- 103
+PCI: 00:1f.6 subsystem <- 17aa/21fa
+PCI: 00:1f.6 cmd <- 02
+PCI: 01:00.0 subsystem <- 17aa/21fa
+PCI: 01:00.0 cmd <- 06
+PCI: 02:00.0 cmd <- 02
+done.
+BS: BS_DEV_ENABLE times (us): entry 0 run 121 exit 0
+Found TPM ST33ZP24 by ST Microelectronics
+TPM: Resume
+TPM: command 0x99 returned 0x0
+Initializing devices...
+Root Device init ...
+Root Device init finished in 0 usecs
+CPU_CLUSTER: 0 init ...
+start_eip=0x00001000, code_size=0x00000031
+Setting up SMI for CPU
+Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8
+Processing 13 relocs. Offset value of 0x00038000
+SMM Module: stub loaded at 00038000. Will call bff91b5b(bffc82e0)
+Installing SMM handler to 0xc0000000
+Loading module at c0010000 with entry c001048b. filesize: 0x1b90 memsize: 0x5bb8
+Processing 60 relocs. Offset value of 0xc0010000
+Loading module at c0008000 with entry c0008000. filesize: 0x1a8 memsize: 0x1a8
+Processing 13 relocs. Offset value of 0xc0008000
+SMM Module: placing jmp sequence at c0007c00 rel16 0x03fd
+SMM Module: placing jmp sequence at c0007800 rel16 0x07fd
+SMM Module: placing jmp sequence at c0007400 rel16 0x0bfd
+SMM Module: stub loaded at c0008000. Will call c001048b(00000000)
+Initializing southbridge SMI... ... pmbase = 0x0500
+
+SMI_STS: MCSMI PM1
+PM1_STS: WAK
+PM1_EN: 100
+GPE0_STS: GPIO15 GPIO14 GPIO13 GPIO11 GPIO9 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO1 GPIO0 EL_SCI/BATLOW
+ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI1 GPI0
+TCO_STS:
+ ... raise SMI#
+In relocation handler: cpu 0
+New SMBASE=0xc0000000 IEDBASE=0xc0400000 @ 0003fc00
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Relocation complete.
+Locking SMM.
+Initializing CPU #0
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [820000:bfffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 13480 size 6400
+microcode: sig=0x306a9 pf=0x10 revision=0x20
+CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz.
+CPU: platform id 4
+CPU: cpuid(1) 0x306a9
+CPU: AES supported
+CPU: TXT supported
+CPU: VT supported
+MTRR: Physical address space:
+0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
+0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
+0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6
+0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 0
+0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
+0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
+0x0000000100000000 - 0x000000043d600000 size 0x33d600000 type 6
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+CPU physical address size: 36 bits
+MTRR: default type WB/UC MTRR counts: 3/6.
+MTRR: WB selected as default type.
+MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
+MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
+MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local APIC... apic_id: 0x00 done.
+VMX status: enabled, locked
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 2900
+Turbo is available but hidden
+Turbo has been enabled
+CPU: 0 has 2 cores, 2 threads per core
+CPU: 0 has core 1
+CPU1: stack_base bffae000, stack_end bffaeff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 1.
+After apic_write.
+In relocation handler: cpu 1
+New SMBASE=0xbffffc00 IEDBASE=0xc0400000 @ 0003fc00
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 1.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+Initializing CPU #1
+CPU: 0 has core 2
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [820000:bfffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 13480 size 6400
+microcode: sig=0x306a9 pf=0x10 revision=0x20
+CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz.
+CPU: platform id 4
+CPU: cpuid(1) 0x306a9
+CPU: AES supported
+CPU: TXT supported
+CPU: VT supported
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+CPU physical address size: 36 bits
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local APIC... apic_id: 0x01 done.
+VMX status: enabled, locked
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 2900
+CPU #1 initialized
+CPU2: stack_base bffad000, stack_end bffadff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 2.
+After apic_write.
+In relocation handler: cpu 2
+Startup point 1.
+Waiting for send to finish...
++New SMBASE=0xbffff800 IEDBASE=0xc0400000 @ 0003fc00
+Sending STARTUP #2 to 2.
+After apic_write.
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU: 0 has core 3
+Initializing CPU #2
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [820000:bfffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 13480 size 6400
+microcode: sig=0x306a9 pf=0x10 revision=0x0
+microcode: updated to revision 0x20 date=2018-04-10
+CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz.
+CPU: platform id 4
+CPU: cpuid(1) 0x306a9
+CPU: AES supported
+CPU: TXT supported
+CPU: VT supported
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+CPU physical address size: 36 bits
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local APIC... apic_id: 0x02 done.
+VMX status: enabled, locked
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 2900
+CPU #2 initialized
+CPU3: stack_base bffac000, stack_end bffacff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 3.
+After apic_write.
+In relocation handler: cpu 3
+New SMBASE=0xbffff400 IEDBASE=0xc0400000 @ 0003fc00
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 3.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU #0 initialized
+Waiting for 1 CPUS to stop
+Initializing CPU #3
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [820000:bfffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 13480 size 6400
+microcode: sig=0x306a9 pf=0x10 revision=0x20
+CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz.
+CPU: platform id 4
+CPU: cpuid(1) 0x306a9
+CPU: AES supported
+CPU: TXT supported
+CPU: VT supported
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+CPU physical address size: 36 bits
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local APIC... apic_id: 0x03 done.
+VMX status: enabled, locked
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 2900
+CPU #3 initialized
+All AP CPUs stopped (444 loops)
+CPU0: stack: bffaf000 - bffb0000, lowest used address bffafaac, stack used: 1364 bytes
+CPU1: stack: bffae000 - bffaf000, lowest used address bffaec6c, stack used: 916 bytes
+CPU2: stack: bffad000 - bffae000, lowest used address bffadc6c, stack used: 916 bytes
+CPU3: stack: bffac000 - bffad000, lowest used address bffacc6c, stack used: 916 bytes
+CPU_CLUSTER: 0 init finished in 80253 usecs
+PCI: 00:00.0 init ...
+Disabling PEG12.
+Disabling PEG11.
+Disabling PEG10.
+Disabling PEG60.
+Disabling Device 7.
+Disabling PEG IO clock.
+Set BIOS_RESET_CPL
+CPU TDP: 35 Watts
+PCI: 00:00.0 init finished in 1013 usecs
+PCI: 00:02.0 init ...
+GT Power Management Init
+IVB GT2 25W-35W Power Meter Weights
+GT Power Management Init (post VBIOS)
+PCI: 00:02.0 init finished in 346 usecs
+PCI: 00:04.0 init ...
+PCI: 00:04.0 init finished in 1 usecs
+PCI: 00:14.0 init ...
+XHCI: Setting up controller.. done.
+PCI: 00:14.0 init finished in 7 usecs
+PCI: 00:16.0 init ...
+ME: BIOS path: S3 Wake
+PCI: 00:16.0: Disabling device
+PCI: 00:16.0 init finished in 10 usecs
+PCI: 00:19.0 init ...
+PCI: 00:19.0 init finished in 1 usecs
+PCI: 00:1a.0 init ...
+EHCI: Setting up controller.. done.
+PCI: 00:1a.0 init finished in 12 usecs
+PCI: 00:1b.0 init ...
+Azalia: base = e1638000
+Azalia: codec_mask = 09
+Azalia: Initializing codec #3
+Azalia: codec viddid: 80862806
+Azalia: verb_size: 16
+Azalia: verb loaded.
+Azalia: Initializing codec #0
+Azalia: codec viddid: 10ec0269
+Azalia: verb_size: 76
+Azalia: verb loaded.
+PCI: 00:1b.0 init finished in 5973 usecs
+PCI: 00:1c.0 init ...
+Initializing PCH PCIe bridge.
+PCI: 00:1c.0 init finished in 10 usecs
+PCI: 00:1c.1 init ...
+Initializing PCH PCIe bridge.
+PCI: 00:1c.1 init finished in 10 usecs
+PCI: 00:1c.2 init ...
+Initializing PCH PCIe bridge.
+PCI: 00:1c.2 init finished in 13 usecs
+PCI: 00:1d.0 init ...
+EHCI: Setting up controller.. done.
+PCI: 00:1d.0 init finished in 12 usecs
+PCI: 00:1f.0 init ...
+pch: lpc_init
+PCH: detected QM77, device id: 0x1e55, rev id 0x4
+IOAPIC: Initializing IOAPIC at 0xfec00000
+IOAPIC: Bootstrap Processor Local APIC = 0x00
+IOAPIC: ID = 0x02
+IOAPIC: Dumping registers
+ reg 0x0000: 0x02000000
+ reg 0x0001: 0x00170020
+ reg 0x0002: 0x00170020
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+Set power off after power failure.
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+NMI sources enabled.
+PantherPoint PM init
+rtc_failed = 0x0
+Enabling BIOS updates outside of SMM... pch_spi_init
+PCI: 00:1f.0 init finished in 553 usecs
+PCI: 00:1f.2 init ...
+SATA: Initializing...
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+SATA: Controller in AHCI mode.
+ABAR: e163e000
+PCI: 00:1f.2 init finished in 341 usecs
+PCI: 00:1f.3 init ...
+PCI: 00:1f.3 init finished in 7 usecs
+PCI: 00:1f.6 init ...
+PCI: 00:1f.6 init finished in 1 usecs
+PCI: 01:00.0 init ...
+PCI: 01:00.0 init finished in 15 usecs
+PCI: 02:00.0 init ...
+PCI: 02:00.0 init finished in 1 usecs
+PNP: 00ff.2 init ...
+PNP: 00ff.2 init finished in 1 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:54 init ...
+I2C: 01:54 init finished in 1 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:55 init ...
+I2C: 01:55 init finished in 1 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:56 init ...
+I2C: 01:56 init finished in 1 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:57 init ...
+I2C: 01:57 init finished in 1 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:5c init ...
+Locking EEPROM RFID
+init EEPROM done
+I2C: 01:5c init finished in 25592 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:5d init ...
+I2C: 01:5d init finished in 1 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:5e init ...
+I2C: 01:5e init finished in 1 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:5f init ...
+I2C: 01:5f init finished in 1 usecs
+Devices initialized
+Show all devs... After init.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+DOMAIN: 0000: enabled 1
+APIC: 00: enabled 1
+APIC: acac: enabled 0
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 0
+PCI: 00:02.0: enabled 1
+PCI: 00:14.0: enabled 1
+PCI: 00:16.0: enabled 0
+PCI: 00:16.1: enabled 0
+PCI: 00:16.2: enabled 0
+PCI: 00:16.3: enabled 0
+PCI: 00:19.0: enabled 1
+PCI: 00:1a.0: enabled 1
+PCI: 00:1b.0: enabled 1
+PCI: 00:1c.0: enabled 1
+PCI: 00:1c.1: enabled 1
+PCI: 00:1c.2: enabled 1
+PCI: 00:1c.3: enabled 0
+PCI: 00:1c.4: enabled 0
+PCI: 00:1c.5: enabled 0
+PCI: 00:1c.6: enabled 0
+PCI: 00:1c.7: enabled 0
+PCI: 00:1d.0: enabled 1
+PCI: 00:1e.0: enabled 0
+PCI: 00:1f.0: enabled 1
+PCI: 00:1f.2: enabled 1
+PCI: 00:1f.3: enabled 1
+PCI: 00:1f.5: enabled 0
+PCI: 00:1f.6: enabled 1
+PCI: 01:00.0: enabled 1
+PNP: 00ff.1: enabled 1
+PNP: 0c31.0: enabled 1
+PNP: 00ff.2: enabled 1
+I2C: 01:54: enabled 1
+I2C: 01:55: enabled 1
+I2C: 01:56: enabled 1
+I2C: 01:57: enabled 1
+I2C: 01:5c: enabled 1
+I2C: 01:5d: enabled 1
+I2C: 01:5e: enabled 1
+I2C: 01:5f: enabled 1
+PCI: 00:04.0: enabled 1
+PCI: 02:00.0: enabled 1
+NONE: enabled 1
+APIC: 01: enabled 1
+APIC: 02: enabled 1
+APIC: 03: enabled 1
+BS: BS_DEV_INIT times (us): entry 108297 run 114204 exit 0
+Finalize devices...
+PCI: 00:1f.0 final
+Devices finalized
+BS: BS_POST_DEVICE times (us): entry 0 run 43 exit 0
+Trying to find the wakeup vector...
+Looking on 000f6810 for valid checksum
+Checksum 1 passed
+Checksum 2 passed all OK
+RSDP found at 000f6810
+RSDT found at bff32030 ends at bff32070
+FADT found at bff35b10
+FACS found at bff32240
+OS waking vector is 0009a1d0
+BS: BS_OS_RESUME_CHECK times (us): entry 0 run 10 exit 0
+
+*** Pre-CBMEM romstage console overflowed, log truncated! ***
+0T
+Selected tRRD : 4T
+Selected tRTP : 5T
+Selected tWTR : 5T
+Selected tRFC : 174T
+Done dimm mapping
+Update PCI-E configuration space:
+PCI(0, 0, 0)[a0] = 0
+PCI(0, 0, 0)[a4] = 4
+PCI(0, 0, 0)[bc] = c2a00000
+PCI(0, 0, 0)[a8] = 3d600000
+PCI(0, 0, 0)[ac] = 4
+PCI(0, 0, 0)[b8] = c0000000
+PCI(0, 0, 0)[b0] = c0a00000
+PCI(0, 0, 0)[b4] = c0800000
+Done memory map
+Done io registers
+Done jedec reset
+Done MRS commands
+t123: 1912, 6000, 7620
+ME: FW Partition Table : OK
+ME: Bringup Loader Failure : NO
+ME: Firmware Init Complete : NO
+ME: Manufacturing Mode : YES
+ME: Boot Options Present : NO
+ME: Update In Progress : NO
+ME: Current Working State : Initializing
+ME: Current Operation State : Bring up
+ME: Current Operation Mode : Debug or Disabled by AltDisableBit
+ME: Error Code : No Error
+ME: Progress Phase : BUP Phase
+ME: Power Management Event : Pseudo-global reset
+ME: Progress Phase State : Check to see if straps say ME DISABLED
+ME: Wrong mode : 2
+ME: FWS2: 0x160a0140
+ME: Bist in progress: 0x0
+ME: ICC Status : 0x0
+ME: Invoke MEBx : 0x0
+ME: CPU replaced : 0x0
+ME: MBP ready : 0x0
+ME: MFS failure : 0x1
+ME: Warm reset req : 0x0
+ME: CPU repl valid : 0x1
+ME: (Reserved) : 0x0
+ME: FW update req : 0x0
+ME: (Reserved) : 0x0
+ME: Current state : 0xa
+ME: Current PM event: 0x6
+ME: Progress code : 0x1
+PASSED! Tell ME that DRAM is ready
+ME: ME is reporting as disabled, so not waiting for a response.
+ME: FWS2: 0x160a0140
+ME: Bist in progress: 0x0
+ME: ICC Status : 0x0
+ME: Invoke MEBx : 0x0
+ME: CPU replaced : 0x0
+ME: MBP ready : 0x0
+ME: MFS failure : 0x1
+ME: Warm reset req : 0x0
+ME: CPU repl valid : 0x1
+ME: (Reserved) : 0x0
+ME: FW update req : 0x0
+ME: (Reserved) : 0x0
+ME: Current state : 0xa
+ME: Current PM event: 0x6
+ME: Progress code : 0x1
+ME: Requested BIOS Action: No DID Ack received
+ME: FW Partition Table : OK
+ME: Bringup Loader Failure : NO
+ME: Firmware Init Complete : NO
+ME: Manufacturing Mode : YES
+ME: Boot Options Present : NO
+ME: Update In Progress : NO
+ME: Current Working State : Initializing
+ME: Current Operation State : Bring up
+ME: Current Operation Mode : Debug or Disabled by AltDisableBit
+ME: Error Code : No Error
+ME: Progress Phase : BUP Phase
+ME: Power Management Event : Pseudo-global reset
+ME: Progress Phase State : Check to see if straps say ME DISABLED
+memcfg DDR3 ref clock 133 MHz
+memcfg DDR3 clock 1330 MHz
+memcfg channel assignment: A: 0, B 1, C 2
+memcfg channel[0] config (00620020):
+ ECC inactive
+ enhanced interleave mode on
+ rank interleave on
+ DIMMA 8192 MB width x8 dual rank, selected
+ DIMMB 0 MB width x8 single rank
+memcfg channel[1] config (00620020):
+ ECC inactive
+ enhanced interleave mode on
+ rank interleave on
+ DIMMA 8192 MB width x8 dual rank, selected
+ DIMMB 0 MB width x8 single rank
+CBMEM:
+IMD: root @ bffff000 254 entries.
+IMD: root @ bfffec00 62 entries.
+External stage cache:
+IMD: root @ c03ff000 254 entries.
+IMD: root @ c03fec00 62 entries.
+CBMEM entry for DIMM info: 0xbfffeaa0
+MTRR Range: Start=ff000000 End=0 (Size 1000000)
+MTRR Range: Start=0 End=1000000 (Size 1000000)
+MTRR Range: Start=bf800000 End=c0000000 (Size 800000)
+MTRR Range: Start=c0000000 End=c0800000 (Size 800000)
+CBFS: 'Master Header Locator' located CBFS at [820000:bfffc0)
+CBFS: Locating 'fallback/postcar'
+CBFS: Found @ offset 45780 size 4110
+Decompressing stage fallback/postcar @ 0xbffcdfc0 (33232 bytes)
+Loading module at bffce000 with entry bffce000. filesize: 0x3ed0 memsize: 0x8190
+Processing 121 relocs. Offset value of 0xbdfce000
+
+
+coreboot-4.8-1053-g4591bb6f7b-dirty Mon Aug 6 07:37:48 UTC 2018 postcar starting...
+CBFS: 'Master Header Locator' located CBFS at [820000:bfffc0)
+CBFS: Locating 'fallback/ramstage'
+CBFS: Found @ offset 19900 size 1aa62
+Decompressing stage fallback/ramstage @ 0xbff6efc0 (382040 bytes)
+Loading module at bff6f000 with entry bff6f000. filesize: 0x38ad0 memsize: 0x5d418
+Processing 5482 relocs. Offset value of 0xbfe6f000
+
+
+coreboot-4.8-1053-g4591bb6f7b-dirty Mon Aug 6 07:37:48 UTC 2018 ramstage starting...
+Normal boot.
+BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0
+BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1 exit 0
+Enumerating buses...
+Show all devs... Before device enumeration.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+DOMAIN: 0000: enabled 1
+APIC: 00: enabled 1
+APIC: acac: enabled 0
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 0
+PCI: 00:02.0: enabled 1
+PCI: 00:14.0: enabled 1
+PCI: 00:16.0: enabled 1
+PCI: 00:16.1: enabled 0
+PCI: 00:16.2: enabled 0
+PCI: 00:16.3: enabled 0
+PCI: 00:19.0: enabled 1
+PCI: 00:1a.0: enabled 1
+PCI: 00:1b.0: enabled 1
+PCI: 00:1c.0: enabled 1
+PCI: 00:1c.1: enabled 1
+PCI: 00:1c.2: enabled 1
+PCI: 00:1c.3: enabled 0
+PCI: 00:1c.4: enabled 0
+PCI: 00:1c.5: enabled 0
+PCI: 00:1c.6: enabled 0
+PCI: 00:1c.7: enabled 0
+PCI: 00:1d.0: enabled 1
+PCI: 00:1e.0: enabled 0
+PCI: 00:1f.0: enabled 1
+PCI: 00:1f.2: enabled 1
+PCI: 00:1f.3: enabled 1
+PCI: 00:1f.5: enabled 0
+PCI: 00:1f.6: enabled 1
+PCI: 00:00.0: enabled 1
+PNP: 00ff.1: enabled 1
+PNP: 0c31.0: enabled 1
+PNP: 00ff.2: enabled 1
+I2C: 00:54: enabled 1
+I2C: 00:55: enabled 1
+I2C: 00:56: enabled 1
+I2C: 00:57: enabled 1
+I2C: 00:5c: enabled 1
+I2C: 00:5d: enabled 1
+I2C: 00:5e: enabled 1
+I2C: 00:5f: enabled 1
+Compare with tree...
+Root Device: enabled 1
+ CPU_CLUSTER: 0: enabled 1
+ APIC: 00: enabled 1
+ APIC: acac: enabled 0
+ DOMAIN: 0000: enabled 1
+ PCI: 00:00.0: enabled 1
+ PCI: 00:01.0: enabled 0
+ PCI: 00:02.0: enabled 1
+ PCI: 00:14.0: enabled 1
+ PCI: 00:16.0: enabled 1
+ PCI: 00:16.1: enabled 0
+ PCI: 00:16.2: enabled 0
+ PCI: 00:16.3: enabled 0
+ PCI: 00:19.0: enabled 1
+ PCI: 00:1a.0: enabled 1
+ PCI: 00:1b.0: enabled 1
+ PCI: 00:1c.0: enabled 1
+ PCI: 00:00.0: enabled 1
+ PCI: 00:1c.1: enabled 1
+ PCI: 00:1c.2: enabled 1
+ PCI: 00:1c.3: enabled 0
+ PCI: 00:1c.4: enabled 0
+ PCI: 00:1c.5: enabled 0
+ PCI: 00:1c.6: enabled 0
+ PCI: 00:1c.7: enabled 0
+ PCI: 00:1d.0: enabled 1
+ PCI: 00:1e.0: enabled 0
+ PCI: 00:1f.0: enabled 1
+ PNP: 00ff.1: enabled 1
+ PNP: 0c31.0: enabled 1
+ PNP: 00ff.2: enabled 1
+ PCI: 00:1f.2: enabled 1
+ PCI: 00:1f.3: enabled 1
+ I2C: 00:54: enabled 1
+ I2C: 00:55: enabled 1
+ I2C: 00:56: enabled 1
+ I2C: 00:57: enabled 1
+ I2C: 00:5c: enabled 1
+ I2C: 00:5d: enabled 1
+ I2C: 00:5e: enabled 1
+ I2C: 00:5f: enabled 1
+ PCI: 00:1f.5: enabled 0
+ PCI: 00:1f.6: enabled 1
+Root Device scanning...
+root_dev_scan_bus for Root Device
+CPU_CLUSTER: 0 enabled
+DOMAIN: 0000 enabled
+DOMAIN: 0000 scanning...
+PCI: pci_scan_bus for bus 00
+PCI: 00:00.0 [8086/0154] ops
+PCI: 00:00.0 [8086/0154] enabled
+PCI: 00:01.0 [8086/0000] bus ops
+PCI: 00:01.0 [8086/0151] disabled
+PCI: 00:02.0 [8086/0000] ops
+PCI: 00:02.0 [8086/0166] enabled
+PCI: 00:04.0 [8086/0153] enabled
+PCI: 00:14.0 [8086/0000] ops
+PCI: 00:14.0 [8086/1e31] enabled
+PCI: 00:16.0 [8086/1e3a] ops
+PCI: 00:16.0 [8086/1e3a] enabled
+PCI: 00:16.1: Disabling device
+PCI: 00:16.2: Disabling device
+PCI: 00:16.3: Disabling device
+PCI: 00:19.0 [8086/1502] enabled
+PCI: 00:1a.0 [8086/0000] ops
+PCI: 00:1a.0 [8086/1e2d] enabled
+PCI: 00:1b.0 [8086/0000] ops
+PCI: 00:1b.0 [8086/1e20] enabled
+PCH: PCIe Root Port coalescing is enabled
+PCI: 00:1c.0 [8086/0000] bus ops
+PCI: 00:1c.0 [8086/1e10] enabled
+PCI: 00:1c.1 [8086/0000] bus ops
+PCI: 00:1c.1 [8086/1e12] enabled
+PCI: 00:1c.2 [8086/0000] bus ops
+PCI: 00:1c.2 [8086/1e14] enabled
+PCI: 00:1c.3: Disabling device
+PCI: 00:1c.3 [8086/0000] bus ops
+PCI: 00:1c.3 [8086/1e16] disabled
+PCI: 00:1c.4: Disabling device
+PCI: 00:1c.4: check set enabled
+PCI: 00:1c.5: Disabling device
+PCI: 00:1c.6: Disabling device
+PCI: 00:1c.7: Disabling device
+PCH: RPFN 0x76543210 -> 0xfedcb210
+PCI: 00:1d.0 [8086/0000] ops
+PCI: 00:1d.0 [8086/1e26] enabled
+PCI: 00:1e.0: Disabling device
+PCI: 00:1e.0 [8086/2448] bus ops
+PCI: 00:1e.0 [8086/2448] disabled
+PCI: 00:1f.0 [8086/0000] bus ops
+PCI: 00:1f.0 [8086/1e55] enabled
+PCI: 00:1f.2 [8086/0000] ops
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+PCI: 00:1f.2 [8086/1e01] enabled
+PCI: 00:1f.3 [8086/0000] bus ops
+PCI: 00:1f.3 [8086/1e22] enabled
+PCI: 00:1f.5: Disabling device
+PCI: 00:1f.5 [8086/1e09] disabled No operations
+PCI: 00:1f.6 [8086/1e24] enabled
+PCI: 00:1c.0 scanning...
+do_pci_scan_bridge for PCI: 00:1c.0
+PCI: pci_scan_bus for bus 01
+PCI: 01:00.0 [1180/0000] ops
+PCI: 01:00.0 [1180/e822] enabled
+Capability: type 0x05 @ 0x50
+Capability: type 0x01 @ 0x78
+Capability: type 0x10 @ 0x80
+Capability: type 0x10 @ 0x40
+Enabling Common Clock Configuration
+ASPM: Enabled L0s and L1
+Capability: type 0x05 @ 0x50
+Capability: type 0x01 @ 0x78
+Capability: type 0x10 @ 0x80
+Failed to enable LTR for dev = PCI: 01:00.0
+scan_bus: scanning of bus PCI: 00:1c.0 took 232 usecs
+PCI: 00:1c.1 scanning...
+do_pci_scan_bridge for PCI: 00:1c.1
+PCI: pci_scan_bus for bus 02
+PCI: 02:00.0 [168c/002b] enabled
+Capability: type 0x01 @ 0x40
+Capability: type 0x05 @ 0x50
+Capability: type 0x10 @ 0x60
+Capability: type 0x10 @ 0x40
+Enabling Common Clock Configuration
+ASPM: Enabled L0s and L1
+Capability: type 0x01 @ 0x40
+Capability: type 0x05 @ 0x50
+Capability: type 0x10 @ 0x60
+Failed to enable LTR for dev = PCI: 02:00.0
+scan_bus: scanning of bus PCI: 00:1c.1 took 210 usecs
+PCI: 00:1c.2 scanning...
+do_pci_scan_bridge for PCI: 00:1c.2
+PCI: pci_scan_bus for bus 03
+scan_bus: scanning of bus PCI: 00:1c.2 took 40 usecs
+PCI: 00:1f.0 scanning...
+scan_lpc_bus for PCI: 00:1f.0
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+PMH7: ID 05 Revision 12
+PNP: 00ff.1 enabled
+PNP: 0c31.0 enabled
+Clearing EC output queue...
+EC output queue has been cleared.
+recv_ec_data: 0x47
+recv_ec_data: 0x32
+recv_ec_data: 0x48
+recv_ec_data: 0x54
+recv_ec_data: 0x33
+recv_ec_data: 0x35
+recv_ec_data: 0x57
+recv_ec_data: 0x57
+recv_ec_data: 0x16
+recv_ec_data: 0x03
+recv_ec_data: 0x40
+recv_ec_data: 0x11
+EC Firmware ID G2HT35WW-3.22, Version 4.01B
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+recv_ec_data: 0x00
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+recv_ec_data: 0x30
+recv_ec_data: 0x90
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+H8: BDC detection not implemented. Assuming BDC installed
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+recv_ec_data: 0x30
+H8: WWAN not installed
+recv_ec_data: 0x30
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+recv_ec_data: 0x00
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+recv_ec_data: 0xa6
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+recv_ec_data: 0xa6
+recv_ec_data: 0x30
+PNP: 00ff.2 enabled
+scan_lpc_bus for PCI: 00:1f.0 done
+scan_bus: scanning of bus PCI: 00:1f.0 took 4659 usecs
+PCI: 00:1f.3 scanning...
+scan_generic_bus for PCI: 00:1f.3
+bus: PCI: 00:1f.3[0]->I2C: 01:54 enabled
+bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled
+bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled
+bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled
+bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled
+bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled
+bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled
+bus: PCI: 00:1f.3[0]->I2C: 01:5f enabled
+scan_generic_bus for PCI: 00:1f.3 done
+scan_bus: scanning of bus PCI: 00:1f.3 took 18 usecs
+scan_bus: scanning of bus DOMAIN: 0000 took 5468 usecs
+root_dev_scan_bus for Root Device done
+scan_bus: scanning of bus Root Device took 5475 usecs
+done
+FMAP: area RW_MRC_CACHE found @ 810000 (65536 bytes)
+MRC: Checking cached data update for 'RW_MRC_CACHE'.
+flash size 0xc00000 bytes
+SF: Detected Opaque HW-sequencing with sector size 0x100, total 0xc00000
+MRC: no data in 'RW_MRC_CACHE'
+MRC: cache data 'RW_MRC_CACHE' needs update.
+SF: Successfully written 2 bytes @ 0x810000
+SF: Successfully written 2 bytes @ 0x810002
+SF: Successfully written 1476 bytes @ 0x810060
+BS: BS_DEV_ENUMERATE times (us): entry 0 run 5567 exit 17121
+found VGA at PCI: 00:02.0
+Setting up VGA for PCI: 00:02.0
+Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
+Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
+Allocating resources...
+Reading resources...
+Root Device read_resources bus 0 link: 0
+CPU_CLUSTER: 0 read_resources bus 0 link: 0
+CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
+DOMAIN: 0000 read_resources bus 0 link: 0
+Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
+PCI: 00:1c.0 read_resources bus 1 link: 0
+PCI: 00:1c.0 read_resources bus 1 link: 0 done
+PCI: 00:1c.1 read_resources bus 2 link: 0
+PCI: 00:1c.1 read_resources bus 2 link: 0 done
+PCI: 00:1c.2 read_resources bus 3 link: 0
+PCI: 00:1c.2 read_resources bus 3 link: 0 done
+PCI: 00:1f.0 read_resources bus 0 link: 0
+PNP: 00ff.1 missing read_resources
+PNP: 00ff.2 missing read_resources
+PCI: 00:1f.0 read_resources bus 0 link: 0 done
+PCI: 00:1f.3 read_resources bus 1 link: 0
+PCI: 00:1f.3 read_resources bus 1 link: 0 done
+DOMAIN: 0000 read_resources bus 0 link: 0 done
+Root Device read_resources bus 0 link: 0 done
+Done reading resources.
+Show resources in subtree (Root Device)...After reading.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 00
+ APIC: 00
+ APIC: acac
+ DOMAIN: 0000 child on link 0 PCI: 00:00.0
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
+ PCI: 00:00.0
+ PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60
+ PCI: 00:01.0
+ PCI: 00:02.0
+ PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
+ PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
+ PCI: 00:04.0
+ PCI: 00:04.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:14.0
+ PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:16.0
+ PCI: 00:16.0 resource base 0 size 10 align 12 gran 4 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:16.1
+ PCI: 00:16.2
+ PCI: 00:16.3
+ PCI: 00:19.0
+ PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
+ PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
+ PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18
+ PCI: 00:1a.0
+ PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
+ PCI: 00:1b.0
+ PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:1c.0 child on link 0 PCI: 01:00.0
+ PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 01:00.0
+ PCI: 01:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
+ PCI: 00:1c.1 child on link 0 PCI: 02:00.0
+ PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 02:00.0
+ PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:1c.2 child on link 0 NONE
+ PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ NONE
+ NONE resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 200 index 10
+ NONE resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 1200 index 14
+ NONE resource base 0 size 1000 align 12 gran 12 limit ffff flags 100 index 18
+ PCI: 00:1c.3
+ PCI: 00:1c.4
+ PCI: 00:1c.5
+ PCI: 00:1c.6
+ PCI: 00:1c.7
+ PCI: 00:1d.0
+ PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
+ PCI: 00:1e.0
+ PCI: 00:1f.0 child on link 0 PNP: 00ff.1
+ PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
+ PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
+ PNP: 00ff.1
+ PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
+ PNP: 0c31.0
+ PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0
+ PNP: 00ff.2
+ PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
+ PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
+ PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
+ PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
+ PCI: 00:1f.2
+ PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
+ PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
+ PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
+ PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
+ PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
+ PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
+ PCI: 00:1f.3 child on link 0 I2C: 01:54
+ PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
+ PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
+ I2C: 01:54
+ I2C: 01:55
+ I2C: 01:56
+ I2C: 01:57
+ I2C: 01:5c
+ I2C: 01:5d
+ I2C: 01:5e
+ I2C: 01:5f
+ PCI: 00:1f.5
+ PCI: 00:1f.6
+ PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
+DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
+PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
+PCI: 00:1c.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:1c.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
+PCI: 00:1c.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+NONE 18 * [0x0 - 0xfff] io
+PCI: 00:1c.2 io: base: 1000 size: 1000 align: 12 gran: 12 limit: ffff done
+PCI: 00:1c.2 1c * [0x0 - 0xfff] io
+PCI: 00:02.0 20 * [0x1000 - 0x103f] io
+PCI: 00:19.0 18 * [0x1040 - 0x105f] io
+PCI: 00:1f.2 20 * [0x1060 - 0x107f] io
+PCI: 00:1f.2 10 * [0x1080 - 0x1087] io
+PCI: 00:1f.2 18 * [0x1088 - 0x108f] io
+PCI: 00:1f.2 14 * [0x1090 - 0x1093] io
+PCI: 00:1f.2 1c * [0x1094 - 0x1097] io
+DOMAIN: 0000 io: base: 1098 size: 1098 align: 12 gran: 0 limit: ffff done
+DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
+PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 01:00.0 10 * [0x0 - 0xff] mem
+PCI: 00:1c.0 mem: base: 100 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:1c.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:1c.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:1c.1 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 02:00.0 10 * [0x0 - 0xffff] mem
+PCI: 00:1c.1 mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:1c.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+NONE 14 * [0x0 - 0x7fffff] prefmem
+PCI: 00:1c.2 prefmem: base: 800000 size: 800000 align: 22 gran: 20 limit: ffffffff done
+PCI: 00:1c.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+NONE 10 * [0x0 - 0x7fffff] mem
+PCI: 00:1c.2 mem: base: 800000 size: 800000 align: 22 gran: 20 limit: ffffffff done
+PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
+PCI: 00:1c.2 24 * [0x10000000 - 0x107fffff] prefmem
+PCI: 00:1c.2 20 * [0x10800000 - 0x10ffffff] mem
+PCI: 00:02.0 10 * [0x11000000 - 0x113fffff] mem
+PCI: 00:1c.0 20 * [0x11400000 - 0x114fffff] mem
+PCI: 00:1c.1 20 * [0x11500000 - 0x115fffff] mem
+PCI: 00:19.0 10 * [0x11600000 - 0x1161ffff] mem
+PCI: 00:14.0 10 * [0x11620000 - 0x1162ffff] mem
+PCI: 00:04.0 10 * [0x11630000 - 0x11637fff] mem
+PCI: 00:1b.0 10 * [0x11638000 - 0x1163bfff] mem
+PCI: 00:19.0 14 * [0x1163c000 - 0x1163cfff] mem
+PCI: 00:1f.6 10 * [0x1163d000 - 0x1163dfff] mem
+PCI: 00:1f.2 24 * [0x1163e000 - 0x1163e7ff] mem
+PCI: 00:1a.0 10 * [0x1163f000 - 0x1163f3ff] mem
+PCI: 00:1d.0 10 * [0x11640000 - 0x116403ff] mem
+PCI: 00:1f.3 10 * [0x11641000 - 0x116410ff] mem
+PCI: 00:16.0 10 * [0x11642000 - 0x1164200f] mem
+DOMAIN: 0000 mem: base: 11642010 size: 11642010 align: 28 gran: 0 limit: ffffffff done
+avoid_fixed_resources: DOMAIN: 0000
+avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
+avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
+constrain_resources: PCI: 00:00.0 60 base f0000000 limit f3ffffff mem (fixed)
+constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
+constrain_resources: PCI: 00:1f.0 10000200 base 00001600 limit 0000167b io (fixed)
+skipping PNP: 00ff.2@60 fixed resource, size=0!
+skipping PNP: 00ff.2@62 fixed resource, size=0!
+skipping PNP: 00ff.2@64 fixed resource, size=0!
+skipping PNP: 00ff.2@66 fixed resource, size=0!
+avoid_fixed_resources:@DOMAIN: 0000 10000000 base 0000167c limit 0000ffff
+avoid_fixed_resources:@DOMAIN: 0000 10000100 base d0000000 limit efffffff
+Setting resources...
+DOMAIN: 0000 io: base:167c size:1098 align:12 gran:0 limit:ffff
+PCI: 00:1c.2 1c * [0x2000 - 0x2fff] io
+PCI: 00:02.0 20 * [0x3000 - 0x303f] io
+PCI: 00:19.0 18 * [0x3040 - 0x305f] io
+PCI: 00:1f.2 20 * [0x3060 - 0x307f] io
+PCI: 00:1f.2 10 * [0x3080 - 0x3087] io
+PCI: 00:1f.2 18 * [0x3088 - 0x308f] io
+PCI: 00:1f.2 14 * [0x3090 - 0x3093] io
+PCI: 00:1f.2 1c * [0x3094 - 0x3097] io
+DOMAIN: 0000 io: next_base: 3098 size: 1098 align: 12 gran: 0 done
+PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff
+PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done
+PCI: 00:1c.1 io: base:ffff size:0 align:12 gran:12 limit:ffff
+PCI: 00:1c.1 io: next_base: ffff size: 0 align: 12 gran: 12 done
+PCI: 00:1c.2 io: base:2000 size:1000 align:12 gran:12 limit:2fff
+NONE 18 * [0x2000 - 0x2fff] io
+PCI: 00:1c.2 io: next_base: 3000 size: 1000 align: 12 gran: 12 done
+DOMAIN: 0000 mem: base:d0000000 size:11642010 align:28 gran:0 limit:efffffff
+PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem
+PCI: 00:1c.2 24 * [0xe0000000 - 0xe07fffff] prefmem
+PCI: 00:1c.2 20 * [0xe0800000 - 0xe0ffffff] mem
+PCI: 00:02.0 10 * [0xe1000000 - 0xe13fffff] mem
+PCI: 00:1c.0 20 * [0xe1400000 - 0xe14fffff] mem
+PCI: 00:1c.1 20 * [0xe1500000 - 0xe15fffff] mem
+PCI: 00:19.0 10 * [0xe1600000 - 0xe161ffff] mem
+PCI: 00:14.0 10 * [0xe1620000 - 0xe162ffff] mem
+PCI: 00:04.0 10 * [0xe1630000 - 0xe1637fff] mem
+PCI: 00:1b.0 10 * [0xe1638000 - 0xe163bfff] mem
+PCI: 00:19.0 14 * [0xe163c000 - 0xe163cfff] mem
+PCI: 00:1f.6 10 * [0xe163d000 - 0xe163dfff] mem
+PCI: 00:1f.2 24 * [0xe163e000 - 0xe163e7ff] mem
+PCI: 00:1a.0 10 * [0xe163f000 - 0xe163f3ff] mem
+PCI: 00:1d.0 10 * [0xe1640000 - 0xe16403ff] mem
+PCI: 00:1f.3 10 * [0xe1641000 - 0xe16410ff] mem
+PCI: 00:16.0 10 * [0xe1642000 - 0xe164200f] mem
+DOMAIN: 0000 mem: next_base: e1642010 size: 11642010 align: 28 gran: 0 done
+PCI: 00:1c.0 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:1c.0 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1c.0 mem: base:e1400000 size:100000 align:20 gran:20 limit:e14fffff
+PCI: 01:00.0 10 * [0xe1400000 - 0xe14000ff] mem
+PCI: 00:1c.0 mem: next_base: e1400100 size: 100000 align: 20 gran: 20 done
+PCI: 00:1c.1 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:1c.1 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1c.1 mem: base:e1500000 size:100000 align:20 gran:20 limit:e15fffff
+PCI: 02:00.0 10 * [0xe1500000 - 0xe150ffff] mem
+PCI: 00:1c.1 mem: next_base: e1510000 size: 100000 align: 20 gran: 20 done
+PCI: 00:1c.2 prefmem: base:e0000000 size:800000 align:22 gran:20 limit:e07fffff
+NONE 14 * [0xe0000000 - 0xe07fffff] prefmem
+PCI: 00:1c.2 prefmem: next_base: e0800000 size: 800000 align: 22 gran: 20 done
+PCI: 00:1c.2 mem: base:e0800000 size:800000 align:22 gran:20 limit:e0ffffff
+NONE 10 * [0xe0800000 - 0xe0ffffff] mem
+PCI: 00:1c.2 mem: next_base: e1000000 size: 800000 align: 22 gran: 20 done
+Root Device assign_resources, bus 0 link: 0
+TOUUD 0x43d600000 TOLUD 0xc2a00000 TOM 0x400000000
+MEBASE 0x7ffff00000
+IGD decoded, subtracting 32M UMA and 2M GTT
+TSEG base 0xc0000000 size 8M
+Available memory below 4GB: 3072M
+Available memory above 4GB: 13270M
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+PCI: 00:02.0 10 <- [0x00e1000000 - 0x00e13fffff] size 0x00400000 gran 0x16 mem64
+PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64
+PCI: 00:02.0 20 <- [0x0000003000 - 0x000000303f] size 0x00000040 gran 0x06 io
+PCI: 00:04.0 10 <- [0x00e1630000 - 0x00e1637fff] size 0x00008000 gran 0x0f mem64
+PCI: 00:14.0 10 <- [0x00e1620000 - 0x00e162ffff] size 0x00010000 gran 0x10 mem64
+PCI: 00:16.0 10 <- [0x00e1642000 - 0x00e164200f] size 0x00000010 gran 0x04 mem64
+PCI: 00:19.0 10 <- [0x00e1600000 - 0x00e161ffff] size 0x00020000 gran 0x11 mem
+PCI: 00:19.0 14 <- [0x00e163c000 - 0x00e163cfff] size 0x00001000 gran 0x0c mem
+PCI: 00:19.0 18 <- [0x0000003040 - 0x000000305f] size 0x00000020 gran 0x05 io
+PCI: 00:1a.0 10 <- [0x00e163f000 - 0x00e163f3ff] size 0x00000400 gran 0x0a mem
+PCI: 00:1b.0 10 <- [0x00e1638000 - 0x00e163bfff] size 0x00004000 gran 0x0e mem64
+PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
+PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem
+PCI: 00:1c.0 20 <- [0x00e1400000 - 0x00e14fffff] size 0x00100000 gran 0x14 bus 01 mem
+PCI: 00:1c.0 assign_resources, bus 1 link: 0
+PCI: 01:00.0 10 <- [0x00e1400000 - 0x00e14000ff] size 0x00000100 gran 0x08 mem
+PCI: 00:1c.0 assign_resources, bus 1 link: 0
+PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
+PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem
+PCI: 00:1c.1 20 <- [0x00e1500000 - 0x00e15fffff] size 0x00100000 gran 0x14 bus 02 mem
+PCI: 00:1c.1 assign_resources, bus 2 link: 0
+PCI: 02:00.0 10 <- [0x00e1500000 - 0x00e150ffff] size 0x00010000 gran 0x10 mem64
+PCI: 00:1c.1 assign_resources, bus 2 link: 0
+PCI: 00:1c.2 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 03 io
+PCI: 00:1c.2 24 <- [0x00e0000000 - 0x00e07fffff] size 0x00800000 gran 0x14 bus 03 prefmem
+PCI: 00:1c.2 20 <- [0x00e0800000 - 0x00e0ffffff] size 0x00800000 gran 0x14 bus 03 mem
+PCI: 00:1c.2 assign_resources, bus 3 link: 0
+NONE missing set_resources
+PCI: 00:1c.2 assign_resources, bus 3 link: 0
+PCI: 00:1d.0 10 <- [0x00e1640000 - 0x00e16403ff] size 0x00000400 gran 0x0a mem
+PCI: 00:1f.0 assign_resources, bus 0 link: 0
+PNP: 00ff.1 missing set_resources
+PNP: 00ff.2 missing set_resources
+PCI: 00:1f.0 assign_resources, bus 0 link: 0
+PCI: 00:1f.2 10 <- [0x0000003080 - 0x0000003087] size 0x00000008 gran 0x03 io
+PCI: 00:1f.2 14 <- [0x0000003090 - 0x0000003093] size 0x00000004 gran 0x02 io
+PCI: 00:1f.2 18 <- [0x0000003088 - 0x000000308f] size 0x00000008 gran 0x03 io
+PCI: 00:1f.2 1c <- [0x0000003094 - 0x0000003097] size 0x00000004 gran 0x02 io
+PCI: 00:1f.2 20 <- [0x0000003060 - 0x000000307f] size 0x00000020 gran 0x05 io
+PCI: 00:1f.2 24 <- [0x00e163e000 - 0x00e163e7ff] size 0x00000800 gran 0x0b mem
+PCI: 00:1f.3 10 <- [0x00e1641000 - 0x00e16410ff] size 0x00000100 gran 0x08 mem64
+PCI: 00:1f.3 assign_resources, bus 1 link: 0
+PCI: 00:1f.3 assign_resources, bus 1 link: 0
+PCI: 00:1f.6 10 <- [0x00e163d000 - 0x00e163dfff] size 0x00001000 gran 0x0c mem64
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+Root Device assign_resources, bus 0 link: 0
+Done setting resources.
+Show resources in subtree (Root Device)...After assigning values.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 00
+ APIC: 00
+ APIC: acac
+ DOMAIN: 0000 child on link 0 PCI: 00:00.0
+ DOMAIN: 0000 resource base 167c size 1098 align 12 gran 0 limit ffff flags 40040100 index 10000000
+ DOMAIN: 0000 resource base d0000000 size 11642010 align 28 gran 0 limit efffffff flags 40040200 index 10000100
+ DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
+ DOMAIN: 0000 resource base 100000 size bff00000 align 0 gran 0 limit 0 flags e0004200 index 4
+ DOMAIN: 0000 resource base 100000000 size 33d600000 align 0 gran 0 limit 0 flags e0004200 index 5
+ DOMAIN: 0000 resource base c0000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6
+ DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7
+ DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 8
+ DOMAIN: 0000 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
+ DOMAIN: 0000 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
+ PCI: 00:00.0
+ PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 60
+ PCI: 00:01.0
+ PCI: 00:02.0
+ PCI: 00:02.0 resource base e1000000 size 400000 align 22 gran 22 limit e13fffff flags 60000201 index 10
+ PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60001201 index 18
+ PCI: 00:02.0 resource base 3000 size 40 align 6 gran 6 limit 303f flags 60000100 index 20
+ PCI: 00:04.0
+ PCI: 00:04.0 resource base e1630000 size 8000 align 15 gran 15 limit e1637fff flags 60000201 index 10
+ PCI: 00:14.0
+ PCI: 00:14.0 resource base e1620000 size 10000 align 16 gran 16 limit e162ffff flags 60000201 index 10
+ PCI: 00:16.0
+ PCI: 00:16.0 resource base e1642000 size 10 align 12 gran 4 limit e164200f flags 60000201 index 10
+ PCI: 00:16.1
+ PCI: 00:16.2
+ PCI: 00:16.3
+ PCI: 00:19.0
+ PCI: 00:19.0 resource base e1600000 size 20000 align 17 gran 17 limit e161ffff flags 60000200 index 10
+ PCI: 00:19.0 resource base e163c000 size 1000 align 12 gran 12 limit e163cfff flags 60000200 index 14
+ PCI: 00:19.0 resource base 3040 size 20 align 5 gran 5 limit 305f flags 60000100 index 18
+ PCI: 00:1a.0
+ PCI: 00:1a.0 resource base e163f000 size 400 align 12 gran 10 limit e163f3ff flags 60000200 index 10
+ PCI: 00:1b.0
+ PCI: 00:1b.0 resource base e1638000 size 4000 align 14 gran 14 limit e163bfff flags 60000201 index 10
+ PCI: 00:1c.0 child on link 0 PCI: 01:00.0
+ PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
+ PCI: 00:1c.0 resource base e1400000 size 100000 align 20 gran 20 limit e14fffff flags 60080202 index 20
+ PCI: 01:00.0
+ PCI: 01:00.0 resource base e1400000 size 100 align 12 gran 8 limit e14000ff flags 60000200 index 10
+ PCI: 00:1c.1 child on link 0 PCI: 02:00.0
+ PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
+ PCI: 00:1c.1 resource base e1500000 size 100000 align 20 gran 20 limit e15fffff flags 60080202 index 20
+ PCI: 02:00.0
+ PCI: 02:00.0 resource base e1500000 size 10000 align 16 gran 16 limit e150ffff flags 60000201 index 10
+ PCI: 00:1c.2 child on link 0 NONE
+ PCI: 00:1c.2 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c
+ PCI: 00:1c.2 resource base e0000000 size 800000 align 22 gran 20 limit e07fffff flags 60081202 index 24
+ PCI: 00:1c.2 resource base e0800000 size 800000 align 22 gran 20 limit e0ffffff flags 60080202 index 20
+ NONE
+ NONE resource base e0800000 size 800000 align 22 gran 22 limit e0ffffff flags 40000200 index 10
+ NONE resource base e0000000 size 800000 align 22 gran 22 limit e07fffff flags 40001200 index 14
+ NONE resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 40000100 index 18
+ PCI: 00:1c.3
+ PCI: 00:1c.4
+ PCI: 00:1c.5
+ PCI: 00:1c.6
+ PCI: 00:1c.7
+ PCI: 00:1d.0
+ PCI: 00:1d.0 resource base e1640000 size 400 align 12 gran 10 limit e16403ff flags 60000200 index 10
+ PCI: 00:1e.0
+ PCI: 00:1f.0 child on link 0 PNP: 00ff.1
+ PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PCI: 00:1f.0 resource base 1600 size 7c align 0 gran 0 limit 0 flags c0040100 index 10000200
+ PCI: 00:1f.0 resource base 15e0 size c align 0 gran 0 limit 0 flags c0040100 index 10000300
+ PNP: 00ff.1
+ PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77
+ PNP: 0c31.0
+ PNP: 0c31.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 0c31.0 resource base fed40000 size 5000 align 0 gran 0 limit 0 flags f0000200 index 0
+ PNP: 00ff.2
+ PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60
+ PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
+ PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64
+ PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66
+ PCI: 00:1f.2
+ PCI: 00:1f.2 resource base 3080 size 8 align 3 gran 3 limit 3087 flags 60000100 index 10
+ PCI: 00:1f.2 resource base 3090 size 4 align 2 gran 2 limit 3093 flags 60000100 index 14
+ PCI: 00:1f.2 resource base 3088 size 8 align 3 gran 3 limit 308f flags 60000100 index 18
+ PCI: 00:1f.2 resource base 3094 size 4 align 2 gran 2 limit 3097 flags 60000100 index 1c
+ PCI: 00:1f.2 resource base 3060 size 20 align 5 gran 5 limit 307f flags 60000100 index 20
+ PCI: 00:1f.2 resource base e163e000 size 800 align 12 gran 11 limit e163e7ff flags 60000200 index 24
+ PCI: 00:1f.3 child on link 0 I2C: 01:54
+ PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
+ PCI: 00:1f.3 resource base e1641000 size 100 align 12 gran 8 limit e16410ff flags 60000201 index 10
+ I2C: 01:54
+ I2C: 01:55
+ I2C: 01:56
+ I2C: 01:57
+ I2C: 01:5c
+ I2C: 01:5d
+ I2C: 01:5e
+ I2C: 01:5f
+ PCI: 00:1f.5
+ PCI: 00:1f.6
+ PCI: 00:1f.6 resource base e163d000 size 1000 align 12 gran 12 limit e163dfff flags 60000201 index 10
+Done allocating resources.
+BS: BS_DEV_RESOURCES times (us): entry 0 run 2172 exit 0
+Enabling resources...
+PCI: 00:00.0 subsystem <- 17aa/21fa
+PCI: 00:00.0 cmd <- 06
+PCI: 00:02.0 subsystem <- 17aa/21fa
+PCI: 00:02.0 cmd <- 03
+PCI: 00:04.0 cmd <- 02
+PCI: 00:14.0 subsystem <- 17aa/21fa
+PCI: 00:14.0 cmd <- 102
+PCI: 00:16.0 subsystem <- 17aa/21fa
+PCI: 00:16.0 cmd <- 02
+PCI: 00:19.0 subsystem <- 17aa/21f3
+PCI: 00:19.0 cmd <- 103
+PCI: 00:1a.0 subsystem <- 17aa/21fa
+PCI: 00:1a.0 cmd <- 102
+PCI: 00:1b.0 subsystem <- 17aa/21fa
+PCI: 00:1b.0 cmd <- 102
+PCI: 00:1c.0 bridge ctrl <- 0003
+PCI: 00:1c.0 subsystem <- 17aa/21fa
+PCI: 00:1c.0 cmd <- 106
+PCI: 00:1c.1 bridge ctrl <- 0003
+PCI: 00:1c.1 subsystem <- 17aa/21fa
+PCI: 00:1c.1 cmd <- 106
+PCI: 00:1c.2 bridge ctrl <- 0003
+PCI: 00:1c.2 subsystem <- 17aa/21fa
+PCI: 00:1c.2 cmd <- 107
+PCI: 00:1d.0 subsystem <- 17aa/21fa
+PCI: 00:1d.0 cmd <- 102
+pch_decode_init
+PCI: 00:1f.0 subsystem <- 17aa/21fa
+PCI: 00:1f.0 cmd <- 107
+PCI: 00:1f.2 subsystem <- 17aa/21fa
+PCI: 00:1f.2 cmd <- 03
+PCI: 00:1f.3 subsystem <- 17aa/21fa
+PCI: 00:1f.3 cmd <- 103
+PCI: 00:1f.6 subsystem <- 17aa/21fa
+PCI: 00:1f.6 cmd <- 02
+PCI: 01:00.0 subsystem <- 17aa/21fa
+PCI: 01:00.0 cmd <- 06
+PCI: 02:00.0 cmd <- 02
+done.
+BS: BS_DEV_ENABLE times (us): entry 0 run 123 exit 0
+Found TPM ST33ZP24 by ST Microelectronics
+TPM: Startup
+TPM: command 0x99 returned 0x0
+TPM: Asserting physical presence
+TPM: command 0x4000000a returned 0x0
+TPM: command 0x65 returned 0x0
+TPM: flags disable=0, deactivated=0, nvlocked=1
+TPM: setup succeeded
+Initializing devices...
+Root Device init ...
+Root Device init finished in 0 usecs
+CPU_CLUSTER: 0 init ...
+start_eip=0x00001000, code_size=0x00000031
+Setting up SMI for CPU
+Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8
+Processing 13 relocs. Offset value of 0x00038000
+SMM Module: stub loaded at 00038000. Will call bff91b5b(bffc82e0)
+Installing SMM handler to 0xc0000000
+Loading module at c0010000 with entry c001048b. filesize: 0x1b90 memsize: 0x5bb8
+Processing 60 relocs. Offset value of 0xc0010000
+Loading module at c0008000 with entry c0008000. filesize: 0x1a8 memsize: 0x1a8
+Processing 13 relocs. Offset value of 0xc0008000
+SMM Module: placing jmp sequence at c0007c00 rel16 0x03fd
+SMM Module: placing jmp sequence at c0007800 rel16 0x07fd
+SMM Module: placing jmp sequence at c0007400 rel16 0x0bfd
+SMM Module: stub loaded at c0008000. Will call c001048b(00000000)
+Initializing southbridge SMI... ... pmbase = 0x0500
+
+SMI_STS: MCSMI
+PM1_STS:
+PM1_EN: 0
+GPE0_STS: GPIO15 GPIO14 GPIO13 GPIO11 GPIO10 GPIO9 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO1 GPIO0
+ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI1 GPI0
+TCO_STS:
+ ... raise SMI#
+In relocation handler: cpu 0
+New SMBASE=0xc0000000 IEDBASE=0xc0400000 @ 0003fc00
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Relocation complete.
+Locking SMM.
+Initializing CPU #0
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [820000:bfffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 13480 size 6400
+microcode: sig=0x306a9 pf=0x10 revision=0x20
+CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz.
+CPU: platform id 4
+CPU: cpuid(1) 0x306a9
+CPU: AES supported
+CPU: TXT supported
+CPU: VT supported
+MTRR: Physical address space:
+0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
+0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
+0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6
+0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 0
+0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
+0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
+0x0000000100000000 - 0x000000043d600000 size 0x33d600000 type 6
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+CPU physical address size: 36 bits
+MTRR: default type WB/UC MTRR counts: 3/6.
+MTRR: WB selected as default type.
+MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
+MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
+MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local APIC... apic_id: 0x00 done.
+VMX is locked, so set_vmx will do nothing
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 2900
+Turbo is available but hidden
+Turbo has been enabled
+CPU: 0 has 2 cores, 2 threads per core
+CPU: 0 has core 1
+CPU1: stack_base bffae000, stack_end bffaeff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 1.
+After apic_write.
+In relocation handler: cpu 1
+New SMBASE=0xbffffc00 IEDBASE=0xc0400000 @ 0003fc00
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 1.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+Initializing CPU #1
+CPU: 0 has core 2
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [820000:bfffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 13480 size 6400
+microcode: sig=0x306a9 pf=0x10 revision=0x20
+CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz.
+CPU: platform id 4
+CPU: cpuid(1) 0x306a9
+CPU: AES supported
+CPU: TXT supported
+CPU: VT supported
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+CPU physical address size: 36 bits
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local APIC... apic_id: 0x01 done.
+VMX is locked, so set_vmx will do nothing
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 2900
+CPU #1 initialized
+CPU2: stack_base bffad000, stack_end bffadff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 2.
+After apic_write.
+In relocation handler: cpu 2
+Startup point 1.
+Waiting for send to finish...
++New SMBASE=0xbffff800 IEDBASE=0xc0400000 @ 0003fc00
+Sending STARTUP #2 to 2.
+After apic_write.
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU: 0 has core 3
+Initializing CPU #2
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [820000:bfffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 13480 size 6400
+microcode: sig=0x306a9 pf=0x10 revision=0x0
+microcode: updated to revision 0x20 date=2018-04-10
+CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz.
+CPU: platform id 4
+CPU: cpuid(1) 0x306a9
+CPU: AES supported
+CPU: TXT supported
+CPU: VT supported
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+CPU physical address size: 36 bits
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local APIC... apic_id: 0x02 done.
+VMX is locked, so set_vmx will do nothing
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 2900
+CPU #2 initialized
+CPU3: stack_base bffac000, stack_end bffacff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 3.
+After apic_write.
+In relocation handler: cpu 3
+New SMBASE=0xbffff400 IEDBASE=0xc0400000 @ 0003fc00
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 3.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU #0 initialized
+Waiting for 1 CPUS to stop
+Initializing CPU #3
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [820000:bfffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 13480 size 6400
+microcode: sig=0x306a9 pf=0x10 revision=0x20
+CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz.
+CPU: platform id 4
+CPU: cpuid(1) 0x306a9
+CPU: AES supported
+CPU: TXT supported
+CPU: VT supported
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+CPU physical address size: 36 bits
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Setting up local APIC... apic_id: 0x03 done.
+VMX is locked, so set_vmx will do nothing
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 2900
+CPU #3 initialized
+All AP CPUs stopped (443 loops)
+CPU0: stack: bffaf000 - bffb0000, lowest used address bffafaac, stack used: 1364 bytes
+CPU1: stack: bffae000 - bffaf000, lowest used address bffaec6c, stack used: 916 bytes
+CPU2: stack: bffad000 - bffae000, lowest used address bffadc6c, stack used: 916 bytes
+CPU3: stack: bffac000 - bffad000, lowest used address bffacc6c, stack used: 916 bytes
+CPU_CLUSTER: 0 init finished in 80457 usecs
+PCI: 00:00.0 init ...
+Disabling PEG12.
+Disabling PEG11.
+Disabling PEG10.
+Disabling PEG60.
+Disabling Device 7.
+Disabling PEG IO clock.
+Set BIOS_RESET_CPL
+CPU TDP: 35 Watts
+PCI: 00:00.0 init finished in 1013 usecs
+PCI: 00:02.0 init ...
+GT Power Management Init
+IVB GT2 25W-35W Power Meter Weights
+CBFS: 'Master Header Locator' located CBFS at [820000:bfffc0)
+CBFS: Locating 'pci8086,0166.rom'
+CBFS: Found @ offset 35700 size 10000
+In CBFS, ROM address for PCI: 00:02.0 = ffc55748
+PCI expansion ROM, signature 0xaa55, INIT size 0x10000, data ptr 0x0040
+PCI ROM image, vendor ID 8086, device ID 0106,
+PCI ROM image, Class Code 030000, Code Type 00
+Copying VGA ROM Image from ffc55748 to 0xc0000, 0x10000 bytes
+pci_cfg_read(): Config read access invalid device! bus: 00 (00), devfn: f8 (10), offs: 02
+Stack unclean, initialization probably NOT COMPLETE!
+VGA Option ROM was run
+GT Power Management Init (post VBIOS)
+PCI: 00:02.0 init finished in 13823 usecs
+PCI: 00:04.0 init ...
+PCI: 00:04.0 init finished in 1 usecs
+PCI: 00:14.0 init ...
+XHCI: Setting up controller.. done.
+PCI: 00:14.0 init finished in 7 usecs
+PCI: 00:16.0 init ...
+ME: FW Partition Table : OK
+ME: Bringup Loader Failure : NO
+ME: Firmware Init Complete : NO
+ME: Manufacturing Mode : YES
+ME: Boot Options Present : NO
+ME: Update In Progress : NO
+ME: Current Working State : Initializing
+ME: Current Operation State : Bring up
+ME: Current Operation Mode : Debug or Disabled by AltDisableBit
+ME: Error Code : No Error
+ME: Progress Phase : BUP Phase
+ME: Power Management Event : Pseudo-global reset
+ME: Progress Phase State : Check to see if straps say ME DISABLED
+intel_me_path: mbp is not ready!
+ME: BIOS path: Error
+PCI: 00:16.0 init finished in 16 usecs
+PCI: 00:19.0 init ...
+PCI: 00:19.0 init finished in 1 usecs
+PCI: 00:1a.0 init ...
+EHCI: Setting up controller.. done.
+PCI: 00:1a.0 init finished in 12 usecs
+PCI: 00:1b.0 init ...
+Azalia: base = e1638000
+Azalia: codec_mask = 09
+Azalia: Initializing codec #3
+Azalia: codec viddid: 80862806
+Azalia: verb_size: 16
+Azalia: verb loaded.
+Azalia: Initializing codec #0
+Azalia: codec viddid: 10ec0269
+Azalia: verb_size: 76
+Azalia: verb loaded.
+PCI: 00:1b.0 init finished in 5972 usecs
+PCI: 00:1c.0 init ...
+Initializing PCH PCIe bridge.
+PCI: 00:1c.0 init finished in 10 usecs
+PCI: 00:1c.1 init ...
+Initializing PCH PCIe bridge.
+PCI: 00:1c.1 init finished in 10 usecs
+PCI: 00:1c.2 init ...
+Initializing PCH PCIe bridge.
+PCI: 00:1c.2 init finished in 13 usecs
+PCI: 00:1d.0 init ...
+EHCI: Setting up controller.. done.
+PCI: 00:1d.0 init finished in 12 usecs
+PCI: 00:1f.0 init ...
+pch: lpc_init
+PCH: detected QM77, device id: 0x1e55, rev id 0x4
+IOAPIC: Initializing IOAPIC at 0xfec00000
+IOAPIC: Bootstrap Processor Local APIC = 0x00
+IOAPIC: ID = 0x02
+IOAPIC: Dumping registers
+ reg 0x0000: 0x02000000
+ reg 0x0001: 0x00170020
+ reg 0x0002: 0x00170020
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+Set power off after power failure.
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+NMI sources enabled.
+PantherPoint PM init
+rtc_failed = 0x0
+RTC Init
+Enabling BIOS updates outside of SMM... Disabling ACPI via APMC:
+done.
+pch_spi_init
+PCI: 00:1f.0 init finished in 887 usecs
+PCI: 00:1f.2 init ...
+SATA: Initializing...
+FMAP: area COREBOOT found @ 820000 (4063232 bytes)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+SATA: Controller in AHCI mode.
+ABAR: e163e000
+PCI: 00:1f.2 init finished in 342 usecs
+PCI: 00:1f.3 init ...
+PCI: 00:1f.3 init finished in 7 usecs
+PCI: 00:1f.6 init ...
+PCI: 00:1f.6 init finished in 1 usecs
+PCI: 01:00.0 init ...
+PCI: 01:00.0 init finished in 15 usecs
+PCI: 02:00.0 init ...
+PCI: 02:00.0 init finished in 0 usecs
+PNP: 00ff.2 init ...
+PNP: 00ff.2 init finished in 0 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:54 init ...
+I2C: 01:54 init finished in 1 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:55 init ...
+I2C: 01:55 init finished in 1 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:56 init ...
+I2C: 01:56 init finished in 1 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:57 init ...
+I2C: 01:57 init finished in 1 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:5c init ...
+Locking EEPROM RFID
+init EEPROM done
+I2C: 01:5c init finished in 25650 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:5d init ...
+I2C: 01:5d init finished in 1 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:5e init ...
+I2C: 01:5e init finished in 1 usecs
+smbus: PCI: 00:1f.3[0]->I2C: 01:5f init ...
+I2C: 01:5f init finished in 1 usecs
+Devices initialized
+Show all devs... After init.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+DOMAIN: 0000: enabled 1
+APIC: 00: enabled 1
+APIC: acac: enabled 0
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 0
+PCI: 00:02.0: enabled 1
+PCI: 00:14.0: enabled 1
+PCI: 00:16.0: enabled 1
+PCI: 00:16.1: enabled 0
+PCI: 00:16.2: enabled 0
+PCI: 00:16.3: enabled 0
+PCI: 00:19.0: enabled 1
+PCI: 00:1a.0: enabled 1
+PCI: 00:1b.0: enabled 1
+PCI: 00:1c.0: enabled 1
+PCI: 00:1c.1: enabled 1
+PCI: 00:1c.2: enabled 1
+PCI: 00:1c.3: enabled 0
+PCI: 00:1c.4: enabled 0
+PCI: 00:1c.5: enabled 0
+PCI: 00:1c.6: enabled 0
+PCI: 00:1c.7: enabled 0
+PCI: 00:1d.0: enabled 1
+PCI: 00:1e.0: enabled 0
+PCI: 00:1f.0: enabled 1
+PCI: 00:1f.2: enabled 1
+PCI: 00:1f.3: enabled 1
+PCI: 00:1f.5: enabled 0
+PCI: 00:1f.6: enabled 1
+PCI: 01:00.0: enabled 1
+PNP: 00ff.1: enabled 1
+PNP: 0c31.0: enabled 1
+PNP: 00ff.2: enabled 1
+I2C: 01:54: enabled 1
+I2C: 01:55: enabled 1
+I2C: 01:56: enabled 1
+I2C: 01:57: enabled 1
+I2C: 01:5c: enabled 1
+I2C: 01:5d: enabled 1
+I2C: 01:5e: enabled 1
+I2C: 01:5f: enabled 1
+PCI: 00:04.0: enabled 1
+PCI: 02:00.0: enabled 1
+NONE: enabled 1
+APIC: 01: enabled 1
+APIC: 02: enabled 1
+APIC: 03: enabled 1
+BS: BS_DEV_INIT times (us): entry 64684 run 128283 exit 0
+Finalize devices...
+PCI: 00:1f.0 final
+Devices finalized
+BS: BS_POST_DEVICE times (us): entry 0 run 59 exit 0
+BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1 exit 0
+CBFS: 'Master Header Locator' located CBFS at [820000:bfffc0)
+CBFS: Locating 'fallback/dsdt.aml'
+CBFS: Found @ offset 49900 size 387c
+CBFS: 'Master Header Locator' located CBFS at [820000:bfffc0)
+CBFS: Locating 'fallback/slic'
+CBFS: 'fallback/slic' not found.
+ACPI: Writing ACPI tables at bff32000.
+ACPI: * FACS
+ACPI: * DSDT
+ACPI: * FADT
+ACPI: added table 1/32, length now 40
+ACPI: * SSDT
+Found 1 CPU(s) with 4 core(s) each.
+PSS: 2901MHz power 35000 control 0x2400 status 0x2400
+PSS: 2900MHz power 35000 control 0x1d00 status 0x1d00
+PSS: 2400MHz power 27295 control 0x1800 status 0x1800
+PSS: 2000MHz power 21703 control 0x1400 status 0x1400
+PSS: 1600MHz power 16527 control 0x1000 status 0x1000
+PSS: 1200MHz power 11795 control 0xc00 status 0xc00
+PSS: 2901MHz power 35000 control 0x2400 status 0x2400
+PSS: 2900MHz power 35000 control 0x1d00 status 0x1d00
+PSS: 2400MHz power 27295 control 0x1800 status 0x1800
+PSS: 2000MHz power 21703 control 0x1400 status 0x1400
+PSS: 1600MHz power 16527 control 0x1000 status 0x1000
+PSS: 1200MHz power 11795 control 0xc00 status 0xc00
+PSS: 2901MHz power 35000 control 0x2400 status 0x2400
+PSS: 2900MHz power 35000 control 0x1d00 status 0x1d00
+PSS: 2400MHz power 27295 control 0x1800 status 0x1800
+PSS: 2000MHz power 21703 control 0x1400 status 0x1400
+PSS: 1600MHz power 16527 control 0x1000 status 0x1000
+PSS: 1200MHz power 11795 control 0xc00 status 0xc00
+PSS: 2901MHz power 35000 control 0x2400 status 0x2400
+PSS: 2900MHz power 35000 control 0x1d00 status 0x1d00
+PSS: 2400MHz power 27295 control 0x1800 status 0x1800
+PSS: 2000MHz power 21703 control 0x1400 status 0x1400
+PSS: 1600MHz power 16527 control 0x1000 status 0x1000
+PSS: 1200MHz power 11795 control 0xc00 status 0xc00
+Generating ACPI PIRQ entries
+ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0
+ACPI_PIRQ_GEN: PCI: 00:04.0: pin=0 pirq=0
+ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=0
+ACPI_PIRQ_GEN: PCI: 00:1a.0: pin=0 pirq=5
+ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=0
+ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=1
+ACPI_PIRQ_GEN: PCI: 00:1c.1: pin=1 pirq=5
+ACPI_PIRQ_GEN: PCI: 00:1c.2: pin=2 pirq=3
+ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=3
+ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=0 pirq=1
+ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=1 pirq=7
+ACPI_PIRQ_GEN: PCI: 00:1f.6: pin=2 pirq=0
+\_SB.PCI0.LPCB.TPM: LPC TPM PNP: 0c31.0
+ACPI: * H8
+H8: BDC detection not implemented. Assuming BDC installed
+H8: WWAN not installed
+ACPI: added table 2/32, length now 44
+ACPI: * MCFG
+ACPI: added table 3/32, length now 48
+ACPI: * TCPA
+TCPA log created at bff21000
+ACPI: added table 4/32, length now 52
+ACPI: * MADT
+ACPI: added table 5/32, length now 56
+current = bff376b0
+ACPI: * DMAR
+ACPI: added table 6/32, length now 60
+current = bff37760
+CBFS: 'Master Header Locator' located CBFS at [820000:bfffc0)
+CBFS: Locating 'vbt.bin'
+CBFS: Found @ offset 34980 size 599
+Found a VBT of 4281 bytes after decompression
+GMA: Found VBT in CBFS
+GMA: Found valid VBT in CBFS
+ACPI: * HPET
+ACPI: added table 7/32, length now 64
+ACPI: done.
+ACPI tables: 30624 bytes.
+smbios_write_tables: bff20000
+recv_ec_data: 0x47
+recv_ec_data: 0x32
+recv_ec_data: 0x48
+recv_ec_data: 0x54
+recv_ec_data: 0x33
+recv_ec_data: 0x35
+recv_ec_data: 0x57
+recv_ec_data: 0x57
+recv_ec_data: 0x16
+recv_ec_data: 0x03
+Create SMBIOS type 17
+SMBIOS tables: 644 bytes.
+Writing table forward entry at 0x00000500
+Wrote coreboot table at: 00000500, 0x10 bytes, checksum dfe8
+Writing coreboot table at 0xbff56000
+CBFS: 'Master Header Locator' located CBFS at [820000:bfffc0)
+CBFS: Locating 'cmos_layout.bin'
+CBFS: Found @ offset 34f80 size 70c
+ 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
+ 1. 0000000000001000-000000000009ffff: RAM
+ 2. 00000000000a0000-00000000000fffff: RESERVED
+ 3. 0000000000100000-00000000bff1ffff: RAM
+ 4. 00000000bff20000-00000000bff6efff: CONFIGURATION TABLES
+ 5. 00000000bff6f000-00000000bffccfff: RAMSTAGE
+ 6. 00000000bffcd000-00000000bfffffff: CONFIGURATION TABLES
+ 7. 00000000c0000000-00000000c29fffff: RESERVED
+ 8. 00000000f0000000-00000000f3ffffff: RESERVED
+ 9. 00000000fed40000-00000000fed44fff: RESERVED
+10. 00000000fed90000-00000000fed91fff: RESERVED
+11. 0000000100000000-000000043d5fffff: RAM
+CBFS: 'Master Header Locator' located CBFS at [820000:bfffc0)
+Wrote coreboot table at: bff56000, 0xa80 bytes, checksum 751f
+coreboot table: 2712 bytes.
+IMD ROOT 0. bffff000 00001000
+IMD SMALL 1. bfffe000 00001000
+CONSOLE 2. bffde000 00020000
+TIME STAMP 3. bffdd000 00000910
+MRC DATA 4. bffdc000 000005c4
+ROMSTG STCK 5. bffd7000 00005000
+AFTER CAR 6. bffcd000 0000a000
+RAMSTAGE 7. bff6e000 0005f000
+SMM BACKUP 8. bff5e000 00010000
+COREBOOT 9. bff56000 00008000
+ACPI 10. bff32000 00024000
+ACPI GNVS 11. bff31000 00001000
+TCPA TCGLOG12. bff21000 00010000
+SMBIOS 13. bff20000 00000800
+IMD small region:
+ IMD ROOT 0. bfffec00 00000400
+ MEM INFO 1. bfffeaa0 00000149
+ ROMSTAGE 2. bfffea80 00000004
+ COREBOOTFWD 3. bfffea40 00000028
+BS: BS_WRITE_TABLES times (us): entry 0 run 26590 exit 0
+CBFS: 'Master Header Locator' located CBFS at [820000:bfffc0)
+CBFS: Locating 'fallback/payload'
+CBFS: Found @ offset 5d2c0 size 1046e
+Loading segment from ROM address 0xffc7d2f8
+ code (compression=1)
+ New segment dstaddr 0xe1140 memsize 0x1eec0 srcaddr 0xffc7d330 filesize 0x10436
+Loading segment from ROM address 0xffc7d314
+ Entry Point 0x000fd254
+Payload being loaded at below 1MiB without region being marked as RAM usable.
+Loading Segment: addr: 0x00000000000e1140 memsz: 0x000000000001eec0 filesz: 0x0000000000010436
+lb: [0x00000000bff6f000, 0x00000000bffcc418)
+Post relocation: addr: 0x00000000000e1140 memsz: 0x000000000001eec0 filesz: 0x0000000000010436
+using LZMA
+[ 0x000e1140, 00100000, 0x00100000) <- ffc7d330
+dest 000e1140, end 00100000, bouncebuffer ffffffff
+Loaded segments
+BS: BS_PAYLOAD_LOAD times (us): entry 0 run 20846 exit 0
+PCH: watchdog disabled
+Jumping to boot code at 000fd254(bff56000)
+CPU0: stack: bffaf000 - bffb0000, lowest used address bffaf85c, stack used: 1956 bytes
+SeaBIOS (version rel-1.11.2-0-gf9626cc)
+BUILD: gcc: (coreboot toolchain v1.52 June 11th, 2018) 8.1.0 binutils: (GNU Binutils) 2.30
+Found coreboot cbmem console @ bffde000
+Found mainboard LENOVO ThinkPad X230
+Relocating init from 0x000e2780 to 0xbfed36c0 (size 51360)
+Found CBFS header at 0xffc20038
+multiboot: eax=bffa6980, ebx=bffa6934
+Found 18 PCI devices (max PCI bus is 03)
+Copying SMBIOS entry point from 0xbff20000 to 0x000f6840
+Copying ACPI RSDP from 0xbff32000 to 0x000f6810
+Using pmtimer, ioport 0x508
+Scan for VGA option rom
+Running option rom at c000:0003
+Turning on vga text mode console
+SeaBIOS (version rel-1.11.2-0-gf9626cc)
+Machine UUID e6ce5b01-52b6-11cb-b410-dccc3572900a
+XHCI init on dev 00:14.0: regs @ 0xe1620000, 8 ports, 32 slots, 32 byte contexts
+XHCI protocol USB 2.00, 4 ports (offset 1), def 3001
+XHCI protocol USB 3.00, 4 ports (offset 5), def 1000
+XHCI extcap 0xc1 @ 0xe1628040
+XHCI extcap 0xc0 @ 0xe1628070
+XHCI extcap 0x1 @ 0xe1628330
+EHCI init on dev 00:1a.0 (regs=0xe163f020)
+EHCI init on dev 00:1d.0 (regs=0xe1640020)
+AHCI controller at 00:1f.2, iobase 0xe163e000, irq 10
+Searching bootorder for: /pci@i0cf8/pci-bridge@1c/*@0
+Found 0 lpt ports
+Found 0 serial ports
+Searching bootorder for: /rom@img/nvramcui
+Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0
+AHCI/0: Set transfer mode to UDMA-6
+AHCI/0: registering: "AHCI/0: Crucial_CT525MX300SSD1 ATA-10 Hard-Disk (489 GiBytes)"
+XHCI no devices found
+Initialized USB HUB (0 ports used)
+Initialized USB HUB (0 ports used)
+PS2 keyboard initialized
+All threads complete.
+Scan for option roms
+
+Press ESC for boot menu.
+
+Searching bootorder for: HALT
+drive 0x000f67a0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1025610768
+Space available for UMB: d0000-ed800, f6060-f67a0
+Returned 188416 bytes of ZoneHigh
+e820 map has 9 items:
+ 0: 0000000000000000 - 000000000009fc00 = 1 RAM
+ 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
+ 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
+ 3: 0000000000100000 - 00000000bff0e000 = 1 RAM
+ 4: 00000000bff0e000 - 00000000c2a00000 = 2 RESERVED
+ 5: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
+ 6: 00000000fed40000 - 00000000fed45000 = 2 RESERVED
+ 7: 00000000fed90000 - 00000000fed92000 = 2 RESERVED
+ 8: 0000000100000000 - 000000043d600000 = 1 RAM
+enter handle_19:
+ NULL
+Booting from Hard Disk...
+Booting from 0000:7c00
+