Add support for "Butterfly" Chromebook 59/2359/3
authorStefan Reinauer <reinauer@chromium.org>
Mon, 11 Feb 2013 19:11:36 +0000 (11:11 -0800)
committerStefan Reinauer <stefan.reinauer@coreboot.org>
Mon, 11 Feb 2013 21:02:32 +0000 (22:02 +0100)
We're happy to announce coreboot support for the "Butterfly"
Chromebook, a.k.a HP Pavilion Chromebook.

More information at:
http://www.google.com/intl/en/chrome/devices/hp-pavilion-chromebook.html

This commit also includes support for the ENE KB3940Q embedded controller
running on Quanta's firmware.

Change-Id: I194f847a94005218ec04eeba091c3257ac459510
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2359
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
39 files changed:
src/ec/Kconfig
src/ec/Makefile.inc
src/ec/quanta/Kconfig [new file with mode: 0644]
src/ec/quanta/Makefile.inc [new file with mode: 0644]
src/ec/quanta/ene_kb3940q/Kconfig [new file with mode: 0644]
src/ec/quanta/ene_kb3940q/Makefile.inc [new file with mode: 0644]
src/ec/quanta/ene_kb3940q/acpi/ac.asl [new file with mode: 0644]
src/ec/quanta/ene_kb3940q/acpi/battery.asl [new file with mode: 0644]
src/ec/quanta/ene_kb3940q/acpi/ec.asl [new file with mode: 0644]
src/ec/quanta/ene_kb3940q/acpi/superio.asl [new file with mode: 0644]
src/ec/quanta/ene_kb3940q/chip.h [new file with mode: 0644]
src/ec/quanta/ene_kb3940q/ec.c [new file with mode: 0644]
src/ec/quanta/ene_kb3940q/ec.h [new file with mode: 0644]
src/mainboard/google/Kconfig
src/mainboard/google/butterfly/Kconfig [new file with mode: 0644]
src/mainboard/google/butterfly/Makefile.inc [new file with mode: 0644]
src/mainboard/google/butterfly/acpi/chromeos.asl [new file with mode: 0644]
src/mainboard/google/butterfly/acpi/ec.asl [new file with mode: 0644]
src/mainboard/google/butterfly/acpi/mainboard.asl [new file with mode: 0644]
src/mainboard/google/butterfly/acpi/platform.asl [new file with mode: 0644]
src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl [new file with mode: 0644]
src/mainboard/google/butterfly/acpi/superio.asl [new file with mode: 0644]
src/mainboard/google/butterfly/acpi/thermal.asl [new file with mode: 0644]
src/mainboard/google/butterfly/acpi/video.asl [new file with mode: 0644]
src/mainboard/google/butterfly/acpi_tables.c [new file with mode: 0644]
src/mainboard/google/butterfly/chromeos.c [new file with mode: 0644]
src/mainboard/google/butterfly/cmos.layout [new file with mode: 0644]
src/mainboard/google/butterfly/devicetree.cb [new file with mode: 0644]
src/mainboard/google/butterfly/dsdt.asl [new file with mode: 0644]
src/mainboard/google/butterfly/ec.c [new file with mode: 0644]
src/mainboard/google/butterfly/ec.h [new file with mode: 0644]
src/mainboard/google/butterfly/fadt.c [new file with mode: 0644]
src/mainboard/google/butterfly/gpio.h [new file with mode: 0644]
src/mainboard/google/butterfly/hda_verb.h [new file with mode: 0644]
src/mainboard/google/butterfly/mainboard.c [new file with mode: 0644]
src/mainboard/google/butterfly/mainboard_smi.c [new file with mode: 0644]
src/mainboard/google/butterfly/onboard.h [new file with mode: 0644]
src/mainboard/google/butterfly/romstage.c [new file with mode: 0644]
src/mainboard/google/butterfly/thermal.h [new file with mode: 0644]

index 0233bd9..7095310 100644 (file)
@@ -2,3 +2,4 @@ source src/ec/acpi/Kconfig
 source src/ec/compal/Kconfig
 source src/ec/lenovo/Kconfig
 source src/ec/smsc/Kconfig
+source src/ec/quanta/Kconfig
index 0ddba79..9bade5f 100644 (file)
@@ -1,2 +1,2 @@
 subdirs-$(CONFIG_EC_ACPI) += acpi
-subdirs-y += compal lenovo smsc
+subdirs-y += compal lenovo smsc quanta
diff --git a/src/ec/quanta/Kconfig b/src/ec/quanta/Kconfig
new file mode 100644 (file)
index 0000000..f29ec00
--- /dev/null
@@ -0,0 +1 @@
+source src/ec/quanta/ene_kb3940q/Kconfig
diff --git a/src/ec/quanta/Makefile.inc b/src/ec/quanta/Makefile.inc
new file mode 100644 (file)
index 0000000..1c39f22
--- /dev/null
@@ -0,0 +1 @@
+subdirs-$(CONFIG_EC_QUANTA_ENE_KB3940Q) += ene_kb3940q
diff --git a/src/ec/quanta/ene_kb3940q/Kconfig b/src/ec/quanta/ene_kb3940q/Kconfig
new file mode 100644 (file)
index 0000000..4258948
--- /dev/null
@@ -0,0 +1,4 @@
+config EC_QUANTA_ENE_KB3940Q
+       bool
+       help
+       Interface to QUANTA ENE KB3940Q Embedded Controller.
diff --git a/src/ec/quanta/ene_kb3940q/Makefile.inc b/src/ec/quanta/ene_kb3940q/Makefile.inc
new file mode 100644 (file)
index 0000000..1ce9a46
--- /dev/null
@@ -0,0 +1,4 @@
+ramstage-y += ec.c
+smm-y += ec.c
+
+smm-y += ../../../lib/delay.c
diff --git a/src/ec/quanta/ene_kb3940q/acpi/ac.asl b/src/ec/quanta/ene_kb3940q/acpi/ac.asl
new file mode 100644 (file)
index 0000000..8c85fc3
--- /dev/null
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Scope (EC0)
+
+Device (AC)
+{
+       Name (_HID, "ACPI0003")
+       Name (_PCL, Package () { \_SB })
+
+       Method (_PSR)
+       {
+               Store(ADPT, Local0)
+               Return(Local0)
+       }
+
+       Method (_STA)
+       {
+               Return (0x0F)
+       }
+}
diff --git a/src/ec/quanta/ene_kb3940q/acpi/battery.asl b/src/ec/quanta/ene_kb3940q/acpi/battery.asl
new file mode 100644 (file)
index 0000000..8fbd9bb
--- /dev/null
@@ -0,0 +1,159 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/*
+ * The mainboard must define strings in the root scope to
+ * report device-specific battery information to the OS.
+ *
+ *  BATV: Vendor
+ */
+
+// Scope (EC0)
+
+Device (BATX)
+{
+       Name (_HID, EISAID ("PNP0C0A"))
+       Name (_UID, 1)
+       Name (_PCL, Package () { \_SB })
+
+       Name (PBIF, Package () {
+               0x00000001,  // 0 Power Unit: mAh
+               0xFFFFFFFF,  // 1 Design Capacity
+               0xFFFFFFFF,  // 2 Last Full Charge Capacity
+               0x00000001,  // 3 Battery Technology: Rechargeable
+               0xFFFFFFFF,  // 4 Design Voltage
+               0x000000FA,  // 5 Design Capacity of Warning
+               0x00000096,  // 6 Design Capacity of Low
+               0x0000000A,  // 7 Capacity Granularity 1
+               0x00000019,  // 8 Capacity Granularity 2
+               "",          // 9 Model Number
+               "",          // 10 Serial Number
+               "",          // 11 Battery Type
+               ""           // 12 OEM Information
+       })
+
+       Name (PBST, Package () {
+               0x00000000,  // Battery State
+               0xFFFFFFFF,  // Battery Present Rate
+               0xFFFFFFFF,  // Battery Remaining Capacity
+               0xFFFFFFFF,  // Battery Present Voltage
+       })
+
+       // Workaround for full battery status, enabled by default
+       Name (BFWK, One)
+
+       // Method to enable full battery workaround
+       Method (BFWE)
+       {
+               Store (One, BFWK)
+       }
+
+       // Method to disable full battery workaround
+       Method (BFWD)
+       {
+               Store (Zero, BFWK)
+       }
+
+       // Device insertion/removal control method that returns a device‚Äôs status.
+       // Power resource object that evaluates to the current on or off state of
+       // the Power Resource.
+       Method (_STA, 0, Serialized)
+       {
+               If (BTIN) {
+                       Return (0x1F)
+               } Else {
+                       Return (0x0F)
+               }
+       }
+
+       Method (_BIF, 0, Serialized)
+       {
+               // Update fields from EC
+               Store (BDC0, Index (PBIF, 1)) // Batt Design Capacity
+               Store (BFC0, Index (PBIF, 2)) // Batt Last Full Charge Capacity
+               Store (BDV0, Index (PBIF, 4)) // Batt Design Voltage
+               Divide(BFC0, 0x64, Local0, Local1)
+               Multiply(Local1, 0x0A, Local0)
+               Store(Local0, Index(PBIF, 5))
+               Multiply(Local1, 0x05, Local0)
+               Store (Local0, Index (PBIF, 6))
+               Store (ToString(BATD), Index (PBIF, 9)) // Model Number
+               Store (ToDecimalString(BSN0), Index (PBIF, 10)) // Serial Number
+               Store (ToString(BCHM), Index (PBIF, 11)) // Battery Type
+               Store (\BATV, Index (PBIF, 12)) // OEM information
+
+               Return (PBIF)
+       }
+
+       Method (_BST, 0, Serialized)
+       {
+               //
+               // 0: BATTERY STATE
+               //
+               // bit 0 = discharging
+               // bit 1 = charging
+               // bit 2 = critical level
+               //
+
+               // Get battery state from EC
+               Store (BST0, Local0)
+               Store (Local0, Index (PBST, 0))
+
+               //
+               // 1: BATTERY PRESENT RATE/CURRENT
+               //
+               Store (BPC0, Local1)
+               If (LAnd (Local1, 0x8000)) {
+                       Xor (Local1, 0xFFFF, Local1)
+                       Increment (Local1)
+               }
+               Store (Local1, Index (PBST, 1))
+
+               //
+               // 2: BATTERY REMAINING CAPACITY
+               //
+               Store (BRC0, Local1)
+
+               If (LAnd (BFWK, LAnd (ADPT, LNot (Local0)))) {
+                       // On AC power and battery is neither charging
+                       // nor discharging.  Linux expects a full battery
+                       // to report same capacity as last full charge.
+                       // https://bugzilla.kernel.org/show_bug.cgi?id=12632
+                       Store (BFC0, Local2)
+
+                       // See if within ~3% of full
+                       ShiftRight (Local2, 5, Local3)
+                       If (LAnd (LGreater (Local1, Subtract (Local2, Local3)),
+                                 LLess (Local1, Add (Local2, Local3))))
+                       {
+                               Store (Local2, Local1)
+                       }
+               }
+               Store (Local1, Index (PBST, 2))
+
+               //
+               // 3: BATTERY PRESENT VOLTAGE
+               //
+               Store (BPV0, Index (PBST, 3))
+
+               Return (PBST)
+       }
+}
diff --git a/src/ec/quanta/ene_kb3940q/acpi/ec.asl b/src/ec/quanta/ene_kb3940q/acpi/ec.asl
new file mode 100644 (file)
index 0000000..4e703fe
--- /dev/null
@@ -0,0 +1,280 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * The mainboard must define a PNOT method to handle power
+ * state notifications and Notify CPU device objects to
+ * re-evaluate their _PPC and _CST tables.
+ */
+
+External (\_PR.CPU0._PPC, IntObj)
+
+Device (EC0)
+{
+       Name (_HID, EISAID ("PNP0C09"))
+       Name (_UID, 1)
+       Name (_GPE, Add(EC_SCI_GPI, 16))        // GPE for Runtime SCI
+
+       OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff)
+       Field (ERAM, ByteAcc, Lock, Preserve)
+       {
+               // EC Name Space Configuration
+
+               Offset(0x40),
+               BDC0, 16,       // Batt Design Capacity                 ; 40h, 41h
+               BDV0, 16,       // Batt Design Voltage                  ; 42h, 43h
+               BFC0, 16,       // Batt Last Full Charge Capacity       ; 44h, 45h
+               BPC0, 16,       // Batt Current                         ; 46h, 47h
+               BRC0, 16,       // Batt Remaining Capacity              ; 48h, 49h
+               BPV0, 16,       // Batt Present Voltage                 ; 4Ah, 4Bh
+               BCG0, 16,       // Batt Charge current                  ; 4Ch, 4Dh
+               BACV, 16,       // Batt Charging Voltage                ; 4Eh, 4Fh
+               BTM0, 16,       // Batt Battery Temp                    ; 50h, 51h
+               BSN0, 16,       // Batt Serial Number                   ; 52h, 53h
+               BPCT, 16,       // Batt Percentage of full charge       ; 54h, 55h
+               BSSB, 16,       // BATT Battery Status SMB              ; 56h, 57h
+               CYC0, 16,       // Batt Cycle Counter                   ; 58h, 59h
+               BMD0, 16,       // Manufacture Date                     ; 5Ah, 5Bh
+                               // Batt Day                             ; BIT[4:0] (Day)
+                               // Batt Month                           ; BIT[9:5] (Month)
+                               // Batt Year                            ; BIT[15:10] (Year)
+
+
+               Offset(0x60),
+               BCHM, 32,       // Battery Chemistry                    ; 60h - 64h
+               BATD, 56,       // Battery Device name                  ; 64h - 6Ah
+
+               Offset(0x70),
+               ADPT, 1,        // AC Adapter Status for OS             ; 70h.0
+               ADPN, 1,        // AC Adapter H/W status                ; 70h.1
+               BTIN, 1,        // Battery Present                      ; 70h.2
+               BTBD, 1,        // Battery Malfunction                  ; 70h.3
+               ACMD, 1,        // ACPI Mode                            ; 70h.4
+                   , 1,        // Reserved                             ; 70h.5
+               SSBS, 1,        // 1=Standard BIOS, 0=Coreboot          ; 70h.6
+               PSTH, 1,        // Passive Thermal Policy               ; 70h.7
+               BST0, 8,        // Battery Status                       ; 71h
+                               // Bit0 : Discharging
+                               // Bit1 : Charging
+                               // Bit2 : Discharging and Critical Low
+                               // Bit3-7 : Reserved
+               LIDF, 1,        // Lid is open                          ; 72h.0
+               GPRC, 1,        // Recovery GPI Status                  ; 72h.1
+                   , 6,        // Reserved                             ; 72h.2-7
+               TPLD, 1,        // TouchPad LED Activation              ; 73h.0
+               TPST, 1,        // Touchpad LED Status                  ; 73h.1
+                   , 6,        // Reserved                             ; 73h.2-7
+
+               Offset(0x78),
+               CTMP, 8,        // Current CPU Temperature              ; 78h
+               SKTB, 8,        // GPU Temperature                      ; 79h
+               LTM1, 8,        // Local Temp 1                         ; 7Ah
+               LTM2, 8,        // Local Temp 2                         ; 7Bh
+               FTCH, 16,       // Fan Tachometer value                 ; 7Ch - 7Dh
+               FDBG, 16,       // Fan Debug - Override Fan Tach value  ; 7Eh - 7Fh
+                   , 1,        // Reserved                             ; 80h.0
+               KBID, 1,        // 0=EN KBD, 1=JP KBD                   ; 80h.1
+                   , 6,        // Reserved                             ; 80h.2-7
+               NPST, 8,        // Number of P-State level              ; 81h
+               MPST, 8,        // Maxumum P-State                      ; 82h
+               KWAK, 1,        // Keyboard WAKE(0=Disable,1=Enable)    ; 83h.0
+               TWAK, 1,        // TouchPad WAKE(0=Disable,1=Enable)    ; 83h.1
+                   , 1,        // Reserved                             ; 83h.2
+               LWAK, 1,        // LAN Wake Enable (0=Disable, 1=Enable); 83h.3
+               RWAK, 1,        // RTC Wake Enable(0=DIsable,1=Enable)  ; 83h.4
+                   , 3,        // Reserved                             ; 83h.5-7
+               KBEV, 1,        // Keyboard Wake Event                  ; 84h.0
+               TPEV, 1,        // TouchPad Wake Event                  ; 84h.1
+               LDEV, 1,        // Lid Wake Event                       ; 84h.2
+                   , 4,        // Reserved                             ; 84h.3-6
+               PBEV, 1,        // Power Button Wake Event              ; 84h.7
+
+               ECCD, 8,        // EC Code State                        ; 85h
+               ROFW, 8,        // RO FW Reason ID                      ; 86h
+
+               Offset(0xBA),
+               FWVR, 48,       // EC Firmware Version                  ; BAh-BFh
+
+               Offset(0xC0),
+               SMPR, 8,        // SMBus protocol register              ; C0h
+               SMST, 8,        // SMBus status register                ; C1h
+               SMAD, 8,        // SMBus address register               ; C2h
+               SMCM, 8,        // SMBus command register               ; C3h
+               SMD0, 0x100,    // SMBus data regs (32)                 ; C4h - E3h
+               BCNT, 8,        // SMBus Block Count                    ; E4h
+       }
+
+       Method (_CRS, 0, NotSerialized)
+       {
+               Name (ECMD, ResourceTemplate()
+               {
+                       IO (Decode16, 0x62, 0x62, 0, 1)
+                       IO (Decode16, 0x66, 0x66, 0, 1)
+               })
+               Return (ECMD)
+       }
+
+       Method(_STA)
+       {
+               Return(0x0F)
+       }
+
+
+       Method (_REG, 2, NotSerialized)
+       {
+               // Initialize AC power state
+               Store (ADPT, \PWRS)
+
+               // Initialize LID switch state
+               Store (LIDF, \LIDS)
+
+               // Force a read of CPU temperature
+               Store (CTMP, Local0)
+
+               // Find and program number of P-States
+               Store (SizeOf (\_PR.CPU0._PSS), MPST)
+               Store ("Programming number of P-states: ", Debug)
+               Store (MPST, Debug)
+
+               // Find and program the current P-State
+               Store(\_PR.CPU0._PPC, NPST)
+               Store ("Programming Current P-state: ", Debug)
+               Store (NPST, Debug)
+       }
+
+/*
+ * EC Query Responses
+ *
+ * Lid Status Change         06h
+ * Wifi Button Event (F12)   07h
+ * TZ Event Update CPU Temp  08h
+ * CPU P-State Down          0Eh
+ * CPU P-State UP            0Fh
+
+ * AC plug in                10h
+ * AC removed                11h
+ * Battery Plugged in        12h
+ * Battery Removed           13h
+ * Battery State Change      14h
+ */
+
+       // Wifi Button Event
+       Method (_Q07)
+       {
+               Store ("Wifi Button Event 0x07", Debug)
+       }
+
+       // Thermal Event
+       Method (_Q08)
+       {
+               Store ("Thermal Event 0x08", Debug)
+               Notify(\_TZ.THRM, 0x80)
+       }
+
+       // Pstate Down
+       Method (_Q0E)
+       {
+               Store ("Pstate Event 0x0E", Debug)
+
+               Store(\_PR.CPU0._PPC, Local0)
+               Subtract(PPCM, 0x01, Local1)
+
+               If(LLess(Local0, Local1)) {
+                       Increment(Local0)
+                       \PPCN ()
+               }
+
+               Store(Local0, NPST)
+       }
+
+       // Pstate Up
+       Method (_Q0F)
+       {
+               Store ("Pstate Event 0x0F", Debug)
+               Store(\_PR.CPU0._PPC, Local0)
+
+               If(Local0) {
+                       Decrement(Local0)
+                       \PPCN ()
+               }
+
+               Store(Local0, NPST)
+       }
+
+       // AC Power Connected
+       Method (_Q10, 0, NotSerialized)
+       {
+               Store ("AC Insertion Event 0x10", Debug)
+               Store (One, \PWRS)
+               Notify (AC, 0x80)
+               Notify (BATX, 0x80)
+               \PNOT ()
+       }
+
+       // AC Power Removed
+       Method (_Q11, 0, NotSerialized)
+       {
+               Store ("AC Detach Event 0x11", Debug)
+               Store (Zero, \PWRS)
+               Notify (AC, 0x80)
+               Notify (BATX, 0x80)
+               \PNOT ()
+       }
+
+       // Battery State Change - Attach Event
+       Method (_Q12, 0, NotSerialized)
+       {
+               Store ("Battery Insertion Event 0x12", Debug)
+
+               Notify (BATX, 0x81)
+               Notify (BATX, 0x80)
+               \PNOT ()
+       }
+
+       // Battery State Change - Detach Event
+       Method (_Q13, 0, NotSerialized)
+       {
+               Store ("Battery Detach Event 0x13", Debug)
+
+               Notify (BATX, 0x81)
+               Notify (BATX, 0x80)
+               \PNOT ()
+       }
+
+
+       // Battery State Change Event
+       Method (_Q14, 0, NotSerialized)
+       {
+               Store ("Battery State Change Event 0x14", Debug)
+
+               Notify (BATX, 0x80)
+       }
+
+       // Lid Switch Event
+       Method (_Q06)
+       {
+               Store ("Lid Switch Event 0x06", Debug)
+               sleep(20)
+               Store (LIDF, \LIDS)
+               Notify (\_SB.LID0, 0x80)
+       }
+
+       #include "ac.asl"
+       #include "battery.asl"
+}
diff --git a/src/ec/quanta/ene_kb3940q/acpi/superio.asl b/src/ec/quanta/ene_kb3940q/acpi/superio.asl
new file mode 100644 (file)
index 0000000..db4b412
--- /dev/null
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Scope is \_SB.PCI0.LPCB
+
+Device (SIO) {
+       Name (_UID, 0)
+       Name (_ADR, 0)
+
+
+#ifdef SIO_EC_ENABLE_PS2K
+       Device (PS2K)           // Keyboard
+       {
+               Name (_UID, 0)
+               Name (_ADR, 0)
+               Name (_HID, EISAID("PNP0303"))
+               Name (_CID, EISAID("PNP030B"))
+
+               Method (_STA, 0, NotSerialized) {
+                       Return (0x0F)
+               }
+
+               Name (_CRS, ResourceTemplate()
+               {
+                       FixedIO (0x60, 0x01)
+                       FixedIO (0x64, 0x01)
+                       IRQNoFlags () {1}
+               })
+
+               Name (_PRS, ResourceTemplate()
+               {
+                       StartDependentFn (0, 0) {
+                               FixedIO (0x60, 0x01)
+                               FixedIO (0x64, 0x01)
+                               IRQNoFlags () {1}
+                       }
+                       EndDependentFn ()
+               })
+       }
+#endif
+}
diff --git a/src/ec/quanta/ene_kb3940q/chip.h b/src/ec/quanta/ene_kb3940q/chip.h
new file mode 100644 (file)
index 0000000..ce95c1c
--- /dev/null
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _EC_QUANTA_ENE_KB3940Q_CHIP_H
+#define _EC_QUANTA_ENE_KB3940Q_CHIP_H
+
+#include <device/device.h>
+#include <pc80/keyboard.h>
+
+struct chip_operations;
+extern struct chip_operations ec_quanta_ene_kb3940q_ops;
+
+struct ec_quanta_ene_kb3940q_config {
+       struct pc_keyboard keyboard;
+};
+
+#endif /* _EC_QUANTA_ENE_KB3940Q_CHIP_H */
diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c
new file mode 100644 (file)
index 0000000..1ef9712
--- /dev/null
@@ -0,0 +1,188 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __PRE_RAM__
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <stdlib.h>
+#include <arch/io.h>
+#include <delay.h>
+#include <elog.h>
+#include "ec.h"
+#include "chip.h"
+
+/* kbc helper functions from drivers/pc80/keyboard.c */
+static int ec_input_buffer_empty(u8 status_port)
+{
+       u32 timeout;
+       for(timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(status_port) & KBD_IBF);
+           timeout--) {
+               mdelay(1);
+       }
+
+       if (!timeout) {
+               printk(BIOS_WARNING, "Unexpected EC/KBD input buffer full\n");
+       }
+       return !!timeout;
+}
+
+
+static int ec_output_buffer_full(u8 status_port)
+{
+       u32 timeout;
+       for(timeout = KBC_TIMEOUT_IN_MS; timeout && ((inb(status_port)
+           & KBD_OBF) == 0); timeout--) {
+               mdelay(1);
+       }
+
+       if (!timeout) {
+               printk(BIOS_INFO, "EC/KBD output buffer result timeout\n");
+       }
+       return !!timeout;
+}
+
+
+
+/* The ENE 60/64 EC registers are the same command/status IB/OB KBC pair.
+ * Check status from 64 port before each command.
+ *
+ *  Ex. Get panel ID command C43/D77
+ *  Check IBF empty. Then Write 0x43(CMD) to 0x64 Port
+ *  Check IBF empty. Then Write 0x77(DATA) to 0x60 Port
+ *  Check OBF set. Then Get Data(0x03:panel ID) from 0x60
+ * Different commands return may or may not respond and may have multiple
+ * bytes. Keep it simple for now
+ */
+
+u8 ec_kbc_read_ob(void)
+{
+       if (!ec_output_buffer_full(KBD_STATUS)) return 0;
+       return inb(KBD_DATA);
+}
+
+void ec_kbc_write_cmd(u8 cmd)
+{
+       if (!ec_input_buffer_empty(KBD_STATUS)) return;
+       outb(cmd, KBD_COMMAND);
+}
+
+void ec_kbc_write_ib(u8 data)
+{
+       if (!ec_input_buffer_empty(KBD_STATUS)) return;
+       outb(data, KBD_DATA);
+}
+
+/* EC Host Control Protocol routines */
+u8 ec_read_ob(void)
+{
+       if (!ec_output_buffer_full(EC_SC)) return 0;
+       return inb(EC_DATA);
+}
+
+void ec_write_cmd(u8 cmd)
+{
+       if (!ec_input_buffer_empty(EC_SC)) return;
+       outb(cmd, EC_COMMAND);
+}
+
+void ec_write_ib(u8 data)
+{
+       if (!ec_input_buffer_empty(EC_SC)) return;
+       outb(data, EC_DATA);
+}
+
+/*
+ * These functions are for accessing the ENE932 device RAM space
+ */
+u8 ec_mem_read(u8 addr)
+{
+       ec_write_cmd(EC_CMD_READ_RAM);
+       ec_write_ib(addr);
+       return ec_read_ob();
+}
+
+void ec_mem_write(u8 addr, u8 data)
+{
+       ec_write_cmd(EC_CMD_WRITE_RAM);
+       ec_write_ib(addr);
+       ec_write_ib(data);
+       return;
+}
+
+#ifndef __SMM__
+static void ene_kb3940q_log_events(void)
+{
+#if CONFIG_ELOG
+       u8 reason = ec_mem_read(EC_SHUTDOWN_REASON);
+       if (reason)
+               elog_add_event_byte(ELOG_TYPE_EC_SHUTDOWN, reason);
+#endif
+}
+
+static void ene_kb3940q_init(device_t dev)
+{
+       struct ec_quanta_ene_kb3940q_config *conf = dev->chip_info;
+
+       if (!dev->enabled)
+               return;
+
+       printk(BIOS_DEBUG, "Quanta EnE KB3940Q: Initializing keyboard.\n");
+       pc_keyboard_init(&conf->keyboard);
+
+       ene_kb3940q_log_events();
+}
+
+
+static void ene_kb3940q_read_resources(device_t dev)
+{
+       /* This function avoids an error on serial console. */
+}
+
+
+static void ene_kb3940q_enable_resources(device_t dev)
+{
+       /* This function avoids an error on serial console. */
+}
+
+static struct device_operations ops = {
+       .init             = ene_kb3940q_init,
+       .read_resources   = ene_kb3940q_read_resources,
+       .enable_resources = ene_kb3940q_enable_resources
+};
+
+static struct pnp_info pnp_dev_info[] = {
+        { &ops, 0, 0, { 0, 0 }, }
+};
+
+static void enable_dev(device_t dev)
+{
+       pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info),
+                          pnp_dev_info);
+}
+
+struct chip_operations ec_quanta_ene_kb3940q_ops = {
+       CHIP_NAME("QUANTA EnE KB3940Q EC")
+       .enable_dev = enable_dev
+};
+#endif /* ! __SMM__ */
+#endif /* ! __PRE_RAM__ */
diff --git a/src/ec/quanta/ene_kb3940q/ec.h b/src/ec/quanta/ene_kb3940q/ec.h
new file mode 100644 (file)
index 0000000..ab01b29
--- /dev/null
@@ -0,0 +1,213 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * EC communication interface for QUANTA EnE KB3940Q Embedded Controller.
+ */
+
+#ifndef _EC_QUANTA_ENE_KB3940Q_EC_H
+#define _EC_QUANTA_ENE_KB3940Q_EC_H
+
+#define EC_IO 0x380 /* Mainboard specific. Could be Kconfig option */
+#define EC_IO_HIGH EC_IO + 1
+#define EC_IO_LOW  EC_IO + 2
+#define EC_IO_DATA EC_IO + 3
+
+
+
+// 60h/64h Command Interface
+#define KBD_DATA       0x60
+#define KBD_COMMAND    0x64
+#define KBD_STATUS     0x64
+#define   KBD_IBF      (1 << 1) // 1: input buffer full (data ready for ec)
+#define   KBD_OBF      (1 << 0) // 1: output buffer full (data ready for host)
+
+// 62h/66h Command Interface
+#define EC_DATA        0x62
+#define EC_COMMAND     0x66
+#define EC_SC  0x66
+
+/* Wait 400ms for keyboard controller answers */
+#define KBC_TIMEOUT_IN_MS 400
+
+u8 ec_kbc_read_ob(void);
+void ec_kbc_write_cmd(u8 cmd);
+void ec_kbc_write_ib(u8 data);
+u8 ec_read_ob(void);
+void ec_write_cmd(u8 cmd);
+void ec_write_ib(u8 data);
+
+u8 ec_mem_read(u8 addr);
+void ec_mem_write(u8 addr, u8 data);
+
+/*****************************************************************************
+ * EC Internal memory
+ */
+
+#define EC_BAT_DCAP_LO                 0x40
+#define EC_BAT_DCAP_HI                 0x41
+#define EC_BAT_DVOLT_LO                        0x42
+#define EC_BAT_DVOLT_HI                        0x43
+#define EC_BAT_FULL_CAP_LO             0x44
+#define EC_BAT_FULL_CAP_HI             0x45
+#define EC_BAT_RATE_LO                 0x46
+#define EC_BAT_RATE_HI                 0x47
+#define EC_BAT_RMC_LO                  0x48
+#define EC_BAT_RMC_HI                  0x49
+#define EC_BAT_VOLT_LO                 0x4A
+#define EC_BAT_VOLT_HI                 0x4B
+#define EC_BAT_CHRG_CURT_LO            0x4C
+#define EC_BAT_CHRG_CURT_HI            0x4D
+#define EC_BAT_CHRG_VOLT_LO            0x4E
+#define EC_BAT_CHRG_VOLT_HI            0x4F
+#define EC_BAT_TEMP_LO                 0x50
+#define EC_BAT_TEMP_HI                 0x51
+#define EC_BAT_SN_LO                   0x52
+#define EC_BAT_SN_HI                   0x53
+#define EC_BAT_RSOC_LO                 0x54
+#define EC_BAT_RSOC_HI                 0x55
+#define EC_BAT_STATUS_LO               0x56
+#define EC_BAT_STATUS_HI               0x57
+#define EC_BAT_CYCLE_COUNT_LO  0x58
+#define EC_BAT_CYCLE_COUNT_HI  0x59
+#define EC_BAT_MFG_DATE_LO             0x5A
+#define EC_BAT_MFG_DATE_HI             0x5B
+#define EC_BAT_CHEMISTRY0              0x60
+#define EC_BAT_CHEMISTRY1              0x61
+#define EC_BAT_CHEMISTRY2              0x62
+#define EC_BAT_CHEMISTRY3              0x63
+#define EC_BAT_DEVICE_NAME0            0x64
+#define EC_BAT_DEVICE_NAME1            0x65
+#define EC_BAT_DEVICE_NAME2            0x66
+#define EC_BAT_DEVICE_NAME3            0x67
+#define EC_BAT_DEVICE_NAME4            0x68
+#define EC_BAT_DEVICE_NAME5            0x69
+#define EC_BAT_DEVICE_NAME6            0x6A
+
+#define EC_POWER_FLAG                  0x70
+#define   EC_PF_ADAPTER_IN             (1 << 0)
+#define   EC_PF_ADAPTER_PIN            (1 << 1)
+#define   EC_PF_BATT_IN                        (1 << 2)
+#define   EC_PF_BATT_DESTROY   (1 << 3)
+#define   EC_PF_ACPI_MODE              (1 << 4)
+#define   EC_PF_X86_BIOS               (1 << 6)
+#define   EC_PF_COREBOOT               0
+#define   EC_PF_PASSIVE_THERM  (1 << 7)
+
+#define EC_CHARGER_STATUS              0x71
+#define   EC_CHS_BAT_DISCHARGING       (1 << 0)
+#define   EC_CHS_BAT_CHARGING          (1 << 1)
+#define   EC_CHS_BAT_CRITICAL          (1 << 2)
+
+#define EC_HW_GPI_STATUS                       0x72
+#define   EC_GPI_LID_STAT_BIT          0
+#define   EC_GPI_RECOVERY_MODE_BIT     1
+#define   EC_GPI_LID_OPEN                      (1 << EC_GPI_LID_STAT_BIT)
+#define   EC_GPI_RECOVERY_STATUS       (1 << EC_GPI_RECOVERY_MODE_BIT)
+
+#define EC_GPIO_STATUS                         0x73
+#define   EC_GPIO_TP_LED_ENABLE                (1 << 0)
+#define   EC_GPIO_TP_LED_STATUS                (1 << 1)
+
+#define EC_CPU_TMP                                     0x78
+#define EC_GPU_TMP                                     0x79
+#define EC_LOCAL_TMP1                          0x7A
+#define EC_LOCAL_TMP2                          0x7B
+#define EC_FAN_TACH_LO                         0x7C
+#define EC_FAN_TACH_HI                         0x7D
+#define EC_FAN_DBG_RPM_LO                      0x7E
+#define EC_FAN_DBG_RPM_HI                      0x7F
+
+#define EC_KBID_REG                    0x80
+#define   EC_KBD_EN                    0
+#define   EC_KBD_JP                    (1 << 1)
+#define EC_CURR_PS                     0x81
+#define EC_MAX_PS                      0x82
+
+#define EC_EC_PSW                      0x83
+#define   EC_PSW_IKB           (1 << 0)
+#define   EC_PSW_TP                    (1 << 1)
+#define   EC_PSW_LAN           (1 << 3)
+#define   EC_PSW_RTC           (1 << 4)
+#define   EC_PSW_USB           (1 << 5)
+
+#define EC_WAKE_EVEN_TID       0x84
+#define   EC_WID_IKB           (1 << 0)
+#define   EC_WID_TP                    (1 << 1)
+#define   EC_WID_LID           (1 << 2)
+#define   EC_WID_PWRSW         (1 << 7)
+
+#define EC_CODE_STATE                          0x85
+#define   EC_COS_INITIAL_STAGE         0xBB
+#define   EC_COS_EC_RO                         0xC0
+#define   EC_COS_EC_RW                         0xC1
+
+#define EC_FW_REASON_ID                                0x86
+#define   EC_FWR_NOT_RO                                0x00
+#define   EC_FWR_GPI_ASSERTED          0x01
+#define   EC_FWR_HOTKEY_PRESSED                0x02
+#define   EC_FWR_FIRMWARE_CORRUPT      0x03
+
+#define EC_SHUTDOWN_REASON             0xB9
+#define EC_FW_VER0                     0xBA
+#define EC_FW_VER1                     0xBB
+#define EC_FW_VER2                     0xBC
+#define EC_FW_VER3                     0xBD
+#define EC_FW_VER4                     0xBE
+#define EC_FW_VER5                     0xBF
+#define EC_SMBPTCL                     0xC0
+#define EC_SMBSTA                      0xC1
+#define EC_SMBADDR                     0xC2
+#define EC_SMBCMD                      0xC3
+#define EC_SMBDATA                     0xC4
+#define EC_SMBBCNT                     0xE4
+
+/*****************************************************************************
+ * SMI / SCI event status
+ */
+#define Q_EVENT_LID_STATUS                     0x06
+#define Q_EVENT_WIFI_BUTTON                    0x06
+#define Q_EVENT_THERM_EVENT                    0x08
+#define Q_EVENT_PSTATE_DOWN                    0x0E
+#define Q_EVENT_PSTATE_UP                      0x0F
+#define Q_EVENT_AC_PLUGGED                     0x10
+#define Q_EVENT_AC_UNPLUGGED           0x11
+#define Q_EVENT_BATTERY_PLUGGED                0x12
+#define Q_EVENT_BATTERY_UNPLUGGED      0x13
+#define Q_EVENT_BATTERY_STATUS         0x14
+
+/*****************************************************************************
+ * EC Commands
+ */
+#define EC_CMD_ENABLE_ACPI_MODE                0x71
+#define EC_CMD_DISABLE_ACPI_MODE       0x72
+#define EC_CMD_DISABLE_SMBUS_EVENT     0x73
+#define EC_CMD_ENABLE_SMBUS_EVENT      0x74
+#define EC_CMD_SYSTEM_RESET                    0x78
+#define EC_CMD_SYSTEM_SHUTDOWN         0x79
+#define EC_CMD_RESET_FOR_FW_UPDATE     0x7D
+#define EC_CMD_IDLE_FOR SPI_UPDATE     0x7E
+#define EC_CMD_READ_RAM                                0x80
+#define EC_CMD_WRITE_RAM                       0x81
+#define EC_CMD_BURST_ENABLE                    0x82
+#define EC_CMD_BURST_DISABLE           0x83
+#define EC_CMD_QUERY_EVENT                     0x84
+
+
+#endif /* _EC_QUANTA_ENE_KB3940Q_EC_H */
index 0603566..4fd695d 100644 (file)
@@ -21,6 +21,8 @@ if VENDOR_GOOGLE
 choice
        prompt "Mainboard model"
 
+config BOARD_GOOGLE_BUTTERFLY
+       bool "Butterfly"
 config BOARD_GOOGLE_PARROT
        bool "Parrot"
 config BOARD_GOOGLE_SNOW
@@ -28,6 +30,7 @@ config BOARD_GOOGLE_SNOW
 
 endchoice
 
+source "src/mainboard/google/butterfly/Kconfig"
 source "src/mainboard/google/parrot/Kconfig"
 source "src/mainboard/google/snow/Kconfig"
 
diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig
new file mode 100644 (file)
index 0000000..ea30174
--- /dev/null
@@ -0,0 +1,61 @@
+if BOARD_GOOGLE_BUTTERFLY
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+       def_bool y
+       select ARCH_X86
+       select CPU_INTEL_SOCKET_RPGA989
+       select NORTHBRIDGE_INTEL_IVYBRIDGE
+       select SOUTHBRIDGE_INTEL_C216
+       select EC_QUANTA_ENE_KB3940Q
+       select BOARD_HAS_FADT
+       select BOARD_ROMSIZE_KB_8192
+       select HAVE_ACPI_TABLES
+       select HAVE_OPTION_TABLE
+       select HAVE_ACPI_RESUME
+       select HAVE_MAINBOARD_RESOURCES
+       select MMCONF_SUPPORT
+       select HAVE_SMI_HANDLER
+       select GFXUMA
+       select CHROMEOS
+       select EXTERNAL_MRC_BLOB
+
+       # Workaround for EC/KBC IRQ1.
+       select SERIRQ_CONTINUOUS_MODE
+
+config MAINBOARD_DIR
+       string
+       default google/butterfly
+
+config MAINBOARD_PART_NUMBER
+       string
+       default "Butterfly"
+
+config MMCONF_BASE_ADDRESS
+       hex
+       default 0xf0000000
+
+config IRQ_SLOT_COUNT
+       int
+       default 18
+
+config MAX_CPUS
+       int
+       default 8
+
+config VGA_BIOS_FILE
+       string
+       default "pci8086,0106.rom"
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+       hex
+       default 0x1ae0
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+       hex
+       default 0xc000
+
+config MAINBOARD_VENDOR
+       string
+       default "Hewlett-Packard"
+
+endif # BOARD_GOOGLE_BUTTERFLY
diff --git a/src/mainboard/google/butterfly/Makefile.inc b/src/mainboard/google/butterfly/Makefile.inc
new file mode 100644 (file)
index 0000000..9e753fb
--- /dev/null
@@ -0,0 +1,27 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ramstage-y += ec.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
+
+SRC_ROOT = $(src)/mainboard/google/butterfly
diff --git a/src/mainboard/google/butterfly/acpi/chromeos.asl b/src/mainboard/google/butterfly/acpi/chromeos.asl
new file mode 100644 (file)
index 0000000..27373e1
--- /dev/null
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Name(OIPG, Package() {
+       Package() { 0x001, 1, 0xFF, "PantherPoint" }, // recovery button
+       Package() { 0x002, 1, 0xFF, "PantherPoint" }, // developer button
+       Package() { 0x003, 0,    6, "PantherPoint" }, // firmware write protect
+})
+
diff --git a/src/mainboard/google/butterfly/acpi/ec.asl b/src/mainboard/google/butterfly/acpi/ec.asl
new file mode 100644 (file)
index 0000000..bb053cd
--- /dev/null
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* mainboard configuration */
+#include "../ec.h"
+
+#define EC_SCI  13     // GPIO13 -> Runtime SCI
+
+/* ACPI code for EC functions */
+#include <ec/quanta/ene_kb3940q/acpi/ec.asl>
diff --git a/src/mainboard/google/butterfly/acpi/mainboard.asl b/src/mainboard/google/butterfly/acpi/mainboard.asl
new file mode 100644 (file)
index 0000000..c6e35e8
--- /dev/null
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Scope (\_SB) {
+       Device (LID0)
+       {
+               Name (_HID, EisaId("PNP0C0D"))
+               Method (_LID, 0)
+               {
+                       Store (\_SB.PCI0.LPCB.EC0.LIDF, \LIDS)
+                       Return (\LIDS)
+               }
+       }
+
+       Device (PWRB)
+       {
+               Name (_HID, EisaId("PNP0C0C"))
+       }
+
+       Device (TPAD)
+       {
+               Name (_ADR, 0x0)
+               Name (_UID, 1)
+
+               // Report as a Sleep Button device so Linux will
+               // automatically enable it as a wake source
+               Name(_HID, EisaId("PNP0C0E"))
+
+               // Trackpad Wake is GPIO11, wake from S3
+               Name(_PRW, Package(){0x1b, 0x03})
+
+               Name(_CRS, ResourceTemplate()
+               {
+                       // PIRQG -> GSI22
+                       Interrupt (ResourceConsumer, EDGE, ActiveLow) {22}
+
+                       // SMBUS Address 0x67
+                       VendorShort (ADDR) {0x67}
+               })
+       }
+
+}
+
+// Battery information
+Name (BATV, "GOOGLE")
diff --git a/src/mainboard/google/butterfly/acpi/platform.asl b/src/mainboard/google/butterfly/acpi/platform.asl
new file mode 100644 (file)
index 0000000..5c84ba1
--- /dev/null
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+       APMC, 8,        // APM command
+       APMS, 8         // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+       DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+       Store (Arg0, SMIF)      // SMI Function
+       Store (0, TRP0)         // Generate trap
+       Return (SMIF)           // Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+       // Remember the OS' IRQ routing choice.
+       Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+       /* Update in case state changed while asleep */
+       /* Update AC status */
+       Store (\_SB.PCI0.LPCB.EC0.ADPT, Local0)
+       if (LNotEqual (Local0, \PWRS)) {
+               Store (Local0, \PWRS)
+               Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80)
+       }
+
+       /* Update LID status */
+       Store (\_SB.PCI0.LPCB.EC0.LIDF, Local0)
+       if (LNotEqual (Local0, \LIDS)) {
+               Store (Local0, \LIDS)
+               Notify (\_SB.LID0, 0x80)
+       }
+
+       Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl
new file mode 100644 (file)
index 0000000..ba725ac
--- /dev/null
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+       If (PICM) {
+               Return (Package() {
+                       // Onboard graphics (IGD)       0:2.0
+                       Package() { 0x0002ffff, 0, 0, 16 },//              GFX    INTA -> PIRQA (MSI)
+                       // High Definition Audio        0:1b.0
+                       Package() { 0x001bffff, 0, 0, 16 },//  D27IP_ZIP   HDA    INTA -> PIRQA (MSI)
+                       // PCIe Root Ports              0:1c.x
+                       Package() { 0x001cffff, 0, 0, 17 },//  D28IP_P1IP  WLAN   INTA -> PIRQB
+                       Package() { 0x001cffff, 1, 0, 21 },//  D28IP_P2IP  ETH0   INTB -> PIRQF
+                       Package() { 0x001cffff, 2, 0, 19 },//  D28IP_P3IP  SDCARD INTC -> PIRQD
+                       // EHCI #1                      0:1d.0
+                       Package() { 0x001dffff, 0, 0, 19 },//  D29IP_E1P   EHCI1  INTA -> PIRQD
+                       // EHCI #2                      0:1a.0
+                       Package() { 0x001affff, 0, 0, 21 },//  D26IP_E2P   EHCI2  INTA -> PIRQF
+                       // LPC devices                  0:1f.0
+                       Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP   SATA   INTA -> PIRQB (MSI)
+                       Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP  SMBUS  INTB -> PIRQH
+                       Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP  THRT   INTC -> PIRQA
+               })
+       } Else {
+               Return (Package() {
+                       // Onboard graphics (IGD)       0:2.0
+                       Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+                       // High Definition Audio        0:1b.0
+                       Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+                       // PCIe Root Ports              0:1c.x
+                       Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+                       Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
+                       Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+                       // EHCI #1                      0:1d.0
+                       Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+                       // EHCI #2                      0:1a.0
+                       Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+                       // LPC device                   0:1f.0
+                       Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+                       Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
+                       Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+               })
+       }
+}
+
diff --git a/src/mainboard/google/butterfly/acpi/superio.asl b/src/mainboard/google/butterfly/acpi/superio.asl
new file mode 100644 (file)
index 0000000..2089604
--- /dev/null
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* mainboard configuration */
+#include "../ec.h"
+
+#define SIO_EC_ENABLE_PS2K       // Enable PS/2 Keyboard
+
+/* ACPI code for EC SuperIO functions */
+#include <ec/quanta/ene_kb3940q/acpi/superio.asl>
diff --git a/src/mainboard/google/butterfly/acpi/thermal.asl b/src/mainboard/google/butterfly/acpi/thermal.asl
new file mode 100644 (file)
index 0000000..5e0dd43
--- /dev/null
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+       ThermalZone (THRM)
+       {
+               Name (_TC1, 0x02)
+               Name (_TC2, 0x05)
+
+               // Thermal zone polling frequency: 10 seconds
+               Name (_TZP, 100)
+
+               // Thermal sampling period for passive cooling: 2 seconds
+               Name (_TSP, 20)
+
+               // Convert from Degrees C to 1/10 Kelvin for ACPI
+               Method (CTOK, 1) {
+                       // 10th of Degrees C
+                       Multiply (Arg0, 10, Local0)
+
+                       // Convert to Kelvin
+                       Add (Local0, 2732, Local0)
+
+                       Return (Local0)
+               }
+
+               // Threshold for OS to shutdown
+               Method (_CRT, 0, Serialized)
+               {
+                       Return (CTOK (\TCRT))
+               }
+
+               // Threshold for passive cooling
+               Method (_PSV, 0, Serialized)
+               {
+                       Return (CTOK (\TPSV))
+               }
+
+               // Processors used for passive cooling
+               Method (_PSL, 0, Serialized)
+               {
+                       Return (\PPKG ())
+               }
+
+               Method (_TMP, 0, Serialized)
+               {
+                       // Get CPU Temperature from EC
+                       Store (\_SB.PCI0.LPCB.EC0.CTMP, Local0)
+
+                       // Convert to 1/10 Kelvin
+                       Multiply (Local0, 10, Local0)
+
+                       // Adjust by offset to get Kelvin
+                       Add (Local0, 2732, Local0)
+
+                       Return (Local0)
+               }
+
+// The EC does all fan control. The is no Active Cooling Fan control (_ACx).
+       }
+}
+
diff --git a/src/mainboard/google/butterfly/acpi/video.asl b/src/mainboard/google/butterfly/acpi/video.asl
new file mode 100644 (file)
index 0000000..3ececa9
--- /dev/null
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+       // TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+       // TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+       // TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+       // TODO (no displays defined yet)
+}
+
diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c
new file mode 100644 (file)
index 0000000..ca4f949
--- /dev/null
@@ -0,0 +1,271 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+#include <ec/quanta/ene_kb3940q/ec.h>
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include "thermal.h"
+
+static void acpi_update_thermal_table(global_nvs_t *gnvs)
+{
+       /* EC handles all thermal and fan control on Butterfly. */
+       gnvs->tcrt = CRITICAL_TEMPERATURE;
+       gnvs->tpsv = PASSIVE_TEMPERATURE;
+}
+
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+       memset((void *)gnvs, 0, sizeof(*gnvs));
+       gnvs->apic = 1;
+       gnvs->mpen = 1; /* Enable Multi Processing */
+       gnvs->pcnt = dev_count_cpu();
+
+       /* Disable USB ports in S3 by default */
+       gnvs->s3u0 = 0;
+       gnvs->s3u1 = 0;
+
+       /* Disable USB ports in S5 by default */
+       gnvs->s5u0 = 0;
+       gnvs->s5u1 = 0;
+
+       /* CBMEM TOC */
+       gnvs->cmem = (u32)get_cbmem_toc();
+
+       /* IGD Displays */
+       gnvs->ndid = 3;
+       gnvs->did[0] = 0x80000100;
+       gnvs->did[1] = 0x80000240;
+       gnvs->did[2] = 0x80000410;
+       gnvs->did[3] = 0x80000410;
+       gnvs->did[4] = 0x00000005;
+
+       // TODO: MLR
+       // The firmware read/write status is a "virtual" switch and
+       // will be handled elsewhere.  Until then hard-code to
+       // read/write instead of read-only for developer mode.
+       gnvs->chromeos.vbt2 = ACTIVE_ECFW_RW;
+
+       // the lid is open by default.
+       gnvs->lids = 1;
+
+#if CONFIG_CHROMEOS
+       // TODO(reinauer) this could move elsewhere?
+       chromeos_init_vboot(&(gnvs->chromeos));
+#endif
+
+       acpi_update_thermal_table(gnvs);
+
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+       /* Local APICs */
+       current = acpi_create_madt_lapics(current);
+
+       /* IOAPIC */
+       current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+                               2, IO_APIC_ADDR, 0);
+
+       /* INT_SRC_OVR */
+       current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+                current, 0, 0, 2, 0);
+       current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+                current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+       return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current,
+                                       const char *oem_table_id)
+{
+       generate_cpu_entries();
+       return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+       // Not implemented
+       return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+       /* No NUMA, no SRAT */
+       return current;
+}
+
+#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
+unsigned long write_acpi_tables(unsigned long start)
+{
+       unsigned long current;
+       int i;
+       acpi_rsdp_t *rsdp;
+       acpi_rsdt_t *rsdt;
+       acpi_xsdt_t *xsdt;
+       acpi_hpet_t *hpet;
+       acpi_madt_t *madt;
+       acpi_mcfg_t *mcfg;
+       acpi_fadt_t *fadt;
+       acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+       acpi_header_t *slic;
+#endif
+       acpi_header_t *ssdt;
+       acpi_header_t *dsdt;
+
+       current = start;
+
+       /* Align ACPI tables to 16byte */
+       ALIGN_CURRENT;
+
+       printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+       /* We need at least an RSDP and an RSDT Table */
+       rsdp = (acpi_rsdp_t *) current;
+       current += sizeof(acpi_rsdp_t);
+       ALIGN_CURRENT;
+       rsdt = (acpi_rsdt_t *) current;
+       current += sizeof(acpi_rsdt_t);
+       ALIGN_CURRENT;
+       xsdt = (acpi_xsdt_t *) current;
+       current += sizeof(acpi_xsdt_t);
+       ALIGN_CURRENT;
+
+       /* clear all table memory */
+       memset((void *) start, 0, current - start);
+
+       acpi_write_rsdp(rsdp, rsdt, xsdt);
+       acpi_write_rsdt(rsdt);
+       acpi_write_xsdt(xsdt);
+
+       printk(BIOS_DEBUG, "ACPI:    * FACS\n");
+       facs = (acpi_facs_t *) current;
+       current += sizeof(acpi_facs_t);
+       ALIGN_CURRENT;
+       acpi_create_facs(facs);
+
+       printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
+       dsdt = (acpi_header_t *) current;
+       memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+       current += dsdt->length;
+       memcpy(dsdt, &AmlCode, dsdt->length);
+
+       ALIGN_CURRENT;
+
+       printk(BIOS_DEBUG, "ACPI:    * FADT\n");
+       fadt = (acpi_fadt_t *) current;
+       current += sizeof(acpi_fadt_t);
+       ALIGN_CURRENT;
+
+       acpi_create_fadt(fadt, facs, dsdt);
+       acpi_add_table(rsdp, fadt);
+
+       /*
+        * We explicitly add these tables later on:
+        */
+       printk(BIOS_DEBUG, "ACPI:    * HPET\n");
+
+       hpet = (acpi_hpet_t *) current;
+       current += sizeof(acpi_hpet_t);
+       ALIGN_CURRENT;
+       acpi_create_hpet(hpet);
+       acpi_add_table(rsdp, hpet);
+
+       /* If we want to use HPET Timers Linux wants an MADT */
+       printk(BIOS_DEBUG, "ACPI:    * MADT\n");
+
+       madt = (acpi_madt_t *) current;
+       acpi_create_madt(madt);
+       current += madt->header.length;
+       ALIGN_CURRENT;
+       acpi_add_table(rsdp, madt);
+
+       printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
+       mcfg = (acpi_mcfg_t *) current;
+       acpi_create_mcfg(mcfg);
+       current += mcfg->header.length;
+       ALIGN_CURRENT;
+       acpi_add_table(rsdp, mcfg);
+
+       /* Pack GNVS into the ACPI table area */
+       for (i=0; i < dsdt->length; i++) {
+               if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+                       printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
+                            "DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
+                       *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+                       acpi_save_gnvs(current);
+                       break;
+               }
+       }
+
+       /* And fill it */
+       acpi_create_gnvs((global_nvs_t *)current);
+
+       /* And tell SMI about it */
+       smm_setup_structures((void *)current, NULL, NULL);
+
+       current += sizeof(global_nvs_t);
+       ALIGN_CURRENT;
+
+       /* We patched up the DSDT, so we need to recalculate the checksum */
+       dsdt->checksum = 0;
+       dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+       printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
+                    dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+       printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
+       slic = (acpi_header_t *)current;
+       current += acpi_create_slic(current);
+       ALIGN_CURRENT;
+       acpi_add_table(rsdp, slic);
+#endif
+
+       printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
+       ssdt = (acpi_header_t *)current;
+       acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+       current += ssdt->length;
+       acpi_add_table(rsdp, ssdt);
+       ALIGN_CURRENT;
+
+       printk(BIOS_DEBUG, "current = %lx\n", current);
+       printk(BIOS_INFO, "ACPI: done.\n");
+       return current;
+}
diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c
new file mode 100644 (file)
index 0000000..41abd95
--- /dev/null
@@ -0,0 +1,171 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <arch/io.h>
+#ifdef __PRE_RAM__
+#include <arch/romcc_io.h>
+#else
+#include <device/device.h>
+#include <device/pci.h>
+#endif
+
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/quanta/ene_kb3940q/ec.h>
+#include "ec.h"
+
+#define ACTIVE_LOW     0
+#define ACTIVE_HIGH    1
+#define WP_GPIO                6
+#define DEVMODE_GPIO   54
+#define FORCE_RECOVERY_MODE    0
+#define FORCE_DEVELOPER_MODE   0
+
+
+int get_pch_gpio(unsigned char gpio_num);
+
+#ifndef __PRE_RAM__
+#include <boot/coreboot_tables.h>
+#include <arch/coreboot_tables.h>
+
+#define GPIO_COUNT     6
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+       device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+       u16 gpio_base = pci_read_config16(dev, GPIOBASE) & 0xfffe;
+
+       int lidswitch=0;
+       if (!gpio_base)
+               return;
+
+       gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
+       gpios->count = GPIO_COUNT;
+
+       /* Write Protect: GPIO active Low */
+       gpios->gpios[0].port = WP_GPIO;
+       gpios->gpios[0].polarity = ACTIVE_LOW;
+       gpios->gpios[0].value = get_pch_gpio(WP_GPIO);
+       strncpy((char *)gpios->gpios[0].name,"write protect",
+                                                       GPIO_MAX_NAME_LENGTH);
+
+       /* Recovery: virtual GPIO active high */
+       gpios->gpios[1].port = -1;
+       gpios->gpios[1].polarity = ACTIVE_HIGH;
+       gpios->gpios[1].value = get_recovery_mode_switch();
+       strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
+
+       /* Developer: virtual GPIO active high */
+       gpios->gpios[2].port = -1;
+       gpios->gpios[2].polarity = ACTIVE_HIGH;
+       gpios->gpios[2].value = get_developer_mode_switch();
+       strncpy((char *)gpios->gpios[2].name,"developer",
+                                                       GPIO_MAX_NAME_LENGTH);
+
+       /* lid switch value from EC */
+       lidswitch = (ec_mem_read(EC_HW_GPI_STATUS) >> EC_GPI_LID_STAT_BIT) & 1;
+       gpios->gpios[3].port = -1;
+       gpios->gpios[3].polarity = ACTIVE_HIGH;
+       gpios->gpios[3].value = lidswitch;
+       strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
+       printk(BIOS_DEBUG,"LID SWITCH FROM EC: %x\n", lidswitch);
+
+       /* Power Button - Hardcode Low as power button may still be pressed
+          when read here.*/
+       gpios->gpios[4].port = -1;
+       gpios->gpios[4].polarity = ACTIVE_HIGH;
+       gpios->gpios[4].value = 0;
+       strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
+
+       /* Was VGA Option ROM loaded? */
+       gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */
+       gpios->gpios[5].polarity = ACTIVE_HIGH;
+       gpios->gpios[5].value = oprom_is_loaded;
+       strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
+
+}
+#endif
+
+int get_pch_gpio(unsigned char gpio_num)
+{
+       device_t dev;
+       int retval = 0;
+
+#ifdef __PRE_RAM__
+       dev = PCI_DEV(0, 0x1f, 0);
+#else
+       dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+#endif
+       u16 gpio_base = pci_read_config16(dev, GPIOBASE) & 0xfffe;
+
+       if (!gpio_base)
+               return(0);
+
+       if (gpio_num > 64){
+               u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
+               retval = ((gp_lvl3 >> (gpio_num - 64)) & 1);
+       } else if (gpio_num > 32){
+               u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
+               retval = ((gp_lvl2 >> (gpio_num - 32)) & 1);
+       } else {
+               u32 gp_lvl = inl(gpio_base + GP_LVL);
+               retval = ((gp_lvl >> gpio_num) & 1);
+       }
+
+       return retval;
+}
+
+int get_developer_mode_switch(void)
+{
+       int dev_mode = 0;
+
+#if FORCE_DEVELOPER_MODE
+       printk(BIOS_DEBUG,"FORCING DEVELOPER MODE.\n");
+       return 1;
+#endif
+
+       /* Servo GPIO is active low, reverse it for intial state (request) */
+       dev_mode = !get_pch_gpio(DEVMODE_GPIO);
+       printk(BIOS_DEBUG,"DEVELOPER MODE FROM GPIO %d: %x\n",DEVMODE_GPIO,
+                                                                dev_mode);
+
+       return dev_mode;
+}
+
+int get_recovery_mode_switch(void)
+{
+       int ec_rec_mode = 0;
+
+#if FORCE_RECOVERY_MODE
+       printk(BIOS_DEBUG,"FORCING RECOVERY MODE.\n");
+       return 1;
+#endif
+
+
+#ifndef __PRE_RAM__
+       if (ec_mem_read(EC_CODE_STATE) == EC_COS_EC_RO) {
+               ec_rec_mode = 1;
+       }
+       printk(BIOS_DEBUG,"RECOVERY MODE FROM EC: %x\n", ec_rec_mode);
+#endif
+
+       return ec_rec_mode;
+}
diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout
new file mode 100644 (file)
index 0000000..afdd3c6
--- /dev/null
@@ -0,0 +1,139 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+# -----------------------------------------------------------------
+# Status Register A
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+388          4       r       0        reboot_bits
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: cpu
+400          1       e       2        hyper_threading
+#401          7       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          2       e       7        power_on_after_fail
+#411          5       r       0        unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416        128       r        0        vbnv
+#544        440       r       0        unused
+
+# SandyBridge MRC Scrambler Seed values
+896         32        r       0        mrc_scrambler_seed
+928         32        r       0        mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+#1000        24       r       0        amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb
new file mode 100644 (file)
index 0000000..d4e2ccd
--- /dev/null
@@ -0,0 +1,105 @@
+chip northbridge/intel/sandybridge
+
+       # Enable DisplayPort Hotplug with 6ms pulse
+       register "gpu_dp_d_hotplug" = "0x06"
+
+
+       # Enable Panel as LVDS and configure power delays
+       register "gpu_panel_port_select" = "0"                  # LVDS
+       register "gpu_panel_power_cycle_delay" = "6"            # T7: 500ms
+       register "gpu_panel_power_up_delay" = "100"             # T1+T2: 10ms
+       register "gpu_panel_power_down_delay" = "100"           # T5+T6: 10ms
+       register "gpu_panel_power_backlight_on_delay" = "2100"  # T3: 210ms
+       register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
+
+       device lapic_cluster 0 on
+               chip cpu/intel/socket_rPGA989
+                       device lapic 0 on end
+               end
+               chip cpu/intel/model_206ax
+                       # Magic APIC ID to locate this chip
+                       device lapic 0xACAC off end
+
+                       # Coordinate with HW_ALL
+                       register "pstate_coord_type" = "0xfe"
+
+                       register "c1_acpower" = "1"     # ACPI(C1) = MWAIT(C1)
+                       register "c2_acpower" = "3"     # ACPI(C2) = MWAIT(C3)
+                       register "c3_acpower" = "5"     # ACPI(C3) = MWAIT(C7)
+
+                       register "c1_battery" = "1"     # ACPI(C1) = MWAIT(C1)
+                       register "c2_battery" = "3"     # ACPI(C2) = MWAIT(C3)
+                       register "c3_battery" = "5"     # ACPI(C3) = MWAIT(C7)
+               end
+       end
+
+       device pci_domain 0 on
+               device pci 00.0 on end # host bridge
+               device pci 01.0 off end # PCIe Bridge for discrete graphics
+               device pci 02.0 on end # vga controller
+
+               chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+                       register "pirqa_routing" = "0x8b"
+                       register "pirqb_routing" = "0x8a"
+                       register "pirqc_routing" = "0x8b"
+                       register "pirqd_routing" = "0x8b"
+                       register "pirqe_routing" = "0x80"
+                       register "pirqf_routing" = "0x80"
+                       register "pirqg_routing" = "0x80"
+                       register "pirqh_routing" = "0x80"
+
+                       # GPI routing
+                       #  0 No effect (default)
+                       #  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+                       #  2 SCI (if corresponding GPIO_EN bit is also set)
+                       register "alt_gp_smi_en" = "0x0000"
+                       #register "gpi1_routing" = "1"  #SMI from EC
+                       register "gpi13_routing" = "2"  #SCI from EC
+
+                       register "ide_legacy_combined" = "0x0"
+                       register "sata_ahci" = "0x1"
+                       register "sata_port_map" = "0x3"        #enable SATA ports 0 & 1
+
+                       # Enable EC Port 0x68/0x6C
+                       register "gen1_dec" = "0x00040069"
+
+                       # EC range is 0x380-0387
+                       register "gen2_dec" = "0x00040381"
+
+                       # Enable zero-based linear PCIe root port functions
+                       register "pcie_port_coalesce" = "1"
+
+                       device pci 14.0 on end # USB 3.0 Controller
+                       device pci 16.0 on end # Management Engine Interface 1
+                       device pci 16.1 off end # Management Engine Interface 2
+                       device pci 16.2 off end # Management Engine IDE-R
+                       device pci 16.3 off end # Management Engine KT
+                       device pci 19.0 off end # Intel Gigabit Ethernet
+                       device pci 1a.0 on end # USB2 EHCI #2
+                       device pci 1b.0 on end # High Definition Audio
+                       device pci 1c.0 on end # PCIe Port #1 (mini PCIe Slot - WLAN & Serial debug)
+                       device pci 1c.1 on end # PCIe Port #2 (ETH0)
+                       device pci 1c.2 on end # PCIe Port #3 (Card Reader)
+                               #force ASPM for PCIe bridge to Card Reader
+                               register "pcie_aspm_f2" = "0x3"
+                       device pci 1c.3 off end # PCIe Port #4
+                       device pci 1c.4 off end # PCIe Port #5
+                       device pci 1c.5 off end # PCIe Port #6
+                       device pci 1c.6 off end # PCIe Port #7
+                       device pci 1c.7 off end # PCIe Port #8
+                       device pci 1d.0 on end # USB2 EHCI #1
+                       device pci 1e.0 off end # PCI bridge
+                       device pci 1f.0 on #LPC bridge
+                               chip ec/quanta/ene_kb3940q
+                                       # 60/64 KBC
+                                       device pnp ff.1 on # dummy address
+                                       end
+                               end
+                       end # LPC bridge
+                       device pci 1f.2 on end # SATA Controller 1
+                       device pci 1f.3 on end # SMBus
+                       device pci 1f.5 off end # SATA Controller 2
+                       device pci 1f.6 on end # Thermal
+               end
+       end
+end
diff --git a/src/mainboard/google/butterfly/dsdt.asl b/src/mainboard/google/butterfly/dsdt.asl
new file mode 100644 (file)
index 0000000..608827a
--- /dev/null
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+       "dsdt.aml",
+       "DSDT",
+       0x02,           // DSDT revision: ACPI v2.0
+       "COREv4",       // OEM id
+       "COREBOOT",     // OEM table id
+       0x20110725      // OEM revision
+)
+{
+       // Some generic macros
+       #include "acpi/platform.asl"
+       #include "acpi/mainboard.asl"
+
+       // global NVS and variables
+       #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+       // General Purpose Events
+       //#include "acpi/gpe.asl"
+
+       #include "acpi/thermal.asl"
+
+       #include <cpu/intel/model_206ax/acpi/cpu.asl>
+
+       Scope (\_SB) {
+               Device (PCI0)
+               {
+                       #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+                       #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+               }
+       }
+
+       #include "acpi/chromeos.asl"
+       #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+       /* Chipset specific sleep states */
+       #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/google/butterfly/ec.c b/src/mainboard/google/butterfly/ec.c
new file mode 100644 (file)
index 0000000..dd2298d
--- /dev/null
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <ec/quanta/ene_kb3940q/ec.h>
+#include "ec.h"
+
+void butterfly_ec_init(void)
+{
+       printk(BIOS_DEBUG, "Butterfly EC Init\n");
+
+       /* Report EC info */
+       /* EC version: 6 bytes */
+       printk(BIOS_DEBUG,"  EC version: %c%c%c%c%c%c\n",
+              ec_mem_read(EC_FW_VER0), ec_mem_read(EC_FW_VER1),
+              ec_mem_read(EC_FW_VER2), ec_mem_read(EC_FW_VER3),
+              ec_mem_read(EC_FW_VER4), ec_mem_read(EC_FW_VER5));
+
+       /* Disable wake on USB, LAN & RTC */
+       /* Enable Wake from Keyboard */
+       ec_mem_write(EC_EC_PSW, EC_PSW_IKB);
+
+}
diff --git a/src/mainboard/google/butterfly/ec.h b/src/mainboard/google/butterfly/ec.h
new file mode 100644 (file)
index 0000000..5bbbd5a
--- /dev/null
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef BUTTERFLY_EC_H
+#define BUTTERFLY_EC_H
+
+#define EC_SCI_GPI  13   /* GPIO13 is EC_SCI# */
+
+/* EC SMI sources TODO: MLR- make defines */
+
+#ifndef __ACPI__
+extern void butterfly_ec_init(void);
+#endif
+
+#endif // BUTTERFLY_EC_H
diff --git a/src/mainboard/google/butterfly/fadt.c b/src/mainboard/google/butterfly/fadt.c
new file mode 100644 (file)
index 0000000..59e67c2
--- /dev/null
@@ -0,0 +1,169 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+
+/* FIXME: This needs to go into a separate .h file
+ * to be included by the ich7 smi handler, ich7 smi init
+ * code and the mainboard fadt.
+ */
+#define   APM_CNT              0xb2
+#define   CST_CONTROL  0x85
+#define   PST_CONTROL  0x80
+#define   ACPI_DISABLE 0x1e
+#define   ACPI_ENABLE  0xe1
+#define   GNVS_UPDATE   0xea
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+       acpi_header_t *header = &(fadt->header);
+       u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),
+                                                               0x40) & 0xfffe;
+
+       memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+       memcpy(header->signature, "FACP", 4);
+       header->length = sizeof(acpi_fadt_t);
+       header->revision = 3;
+       memcpy(header->oem_id, OEM_ID, 6);
+       memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+       memcpy(header->asl_compiler_id, "CORE", 4);
+       header->asl_compiler_revision = 1;
+
+       fadt->firmware_ctrl = (unsigned long) facs;
+       fadt->dsdt = (unsigned long) dsdt;
+       fadt->model = 1;
+       fadt->preferred_pm_profile = PM_MOBILE;
+
+       fadt->sci_int = 0x9;
+       fadt->smi_cmd = APM_CNT;
+       fadt->acpi_enable = ACPI_ENABLE;
+       fadt->acpi_disable = ACPI_DISABLE;
+       fadt->s4bios_req = 0x0;
+       fadt->pstate_cnt = 0;
+
+       fadt->pm1a_evt_blk = pmbase;
+       fadt->pm1b_evt_blk = 0x0;
+       fadt->pm1a_cnt_blk = pmbase + 0x4;
+       fadt->pm1b_cnt_blk = 0x0;
+       fadt->pm2_cnt_blk = pmbase + 0x50;
+       fadt->pm_tmr_blk = pmbase + 0x8;
+       fadt->gpe0_blk = pmbase + 0x20;
+       fadt->gpe1_blk = 0;
+
+       fadt->pm1_evt_len = 4;
+       fadt->pm1_cnt_len = 2;
+       fadt->pm2_cnt_len = 1;
+       fadt->pm_tmr_len = 4;
+       fadt->gpe0_blk_len = 16;
+       fadt->gpe1_blk_len = 0;
+       fadt->gpe1_base = 0;
+       fadt->cst_cnt = 0;
+       fadt->p_lvl2_lat = 101;  /* c2 not supported */
+       fadt->p_lvl3_lat = 87;
+       fadt->flush_size = 1024;
+       fadt->flush_stride = 16;
+       fadt->duty_offset = 1;
+       fadt->duty_width = 3;
+       fadt->day_alrm = 0xd;
+       fadt->mon_alrm = 0x00;
+       fadt->century = 0x00;
+       fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+       fadt->flags = ACPI_FADT_WBINVD |
+                       ACPI_FADT_C1_SUPPORTED |
+                       ACPI_FADT_SLEEP_BUTTON |
+                       ACPI_FADT_RESET_REGISTER |
+                       ACPI_FADT_SEALED_CASE |
+                       ACPI_FADT_S4_RTC_WAKE |
+                       ACPI_FADT_PLATFORM_CLOCK;
+
+       fadt->reset_reg.space_id = 1;
+       fadt->reset_reg.bit_width = 8;
+       fadt->reset_reg.bit_offset = 0;
+       fadt->reset_reg.resv = 0;
+       fadt->reset_reg.addrl = 0xcf9;
+       fadt->reset_reg.addrh = 0;
+
+       fadt->reset_value = 6;
+       fadt->x_firmware_ctl_l = (unsigned long)facs;
+       fadt->x_firmware_ctl_h = 0;
+       fadt->x_dsdt_l = (unsigned long)dsdt;
+       fadt->x_dsdt_h = 0;
+
+       fadt->x_pm1a_evt_blk.space_id = 1;
+       fadt->x_pm1a_evt_blk.bit_width = 32;
+       fadt->x_pm1a_evt_blk.bit_offset = 0;
+       fadt->x_pm1a_evt_blk.resv = 0;
+       fadt->x_pm1a_evt_blk.addrl = pmbase;
+       fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+       fadt->x_pm1b_evt_blk.space_id = 1;
+       fadt->x_pm1b_evt_blk.bit_width = 0;
+       fadt->x_pm1b_evt_blk.bit_offset = 0;
+       fadt->x_pm1b_evt_blk.resv = 0;
+       fadt->x_pm1b_evt_blk.addrl = 0x0;
+       fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+       fadt->x_pm1a_cnt_blk.space_id = 1;
+       fadt->x_pm1a_cnt_blk.bit_width = 16;
+       fadt->x_pm1a_cnt_blk.bit_offset = 0;
+       fadt->x_pm1a_cnt_blk.resv = 0;
+       fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+       fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+       fadt->x_pm1b_cnt_blk.space_id = 1;
+       fadt->x_pm1b_cnt_blk.bit_width = 0;
+       fadt->x_pm1b_cnt_blk.bit_offset = 0;
+       fadt->x_pm1b_cnt_blk.resv = 0;
+       fadt->x_pm1b_cnt_blk.addrl = 0x0;
+       fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+       fadt->x_pm2_cnt_blk.space_id = 1;
+       fadt->x_pm2_cnt_blk.bit_width = 8;
+       fadt->x_pm2_cnt_blk.bit_offset = 0;
+       fadt->x_pm2_cnt_blk.resv = 0;
+       fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+       fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+       fadt->x_pm_tmr_blk.space_id = 1;
+       fadt->x_pm_tmr_blk.bit_width = 32;
+       fadt->x_pm_tmr_blk.bit_offset = 0;
+       fadt->x_pm_tmr_blk.resv = 0;
+       fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+       fadt->x_pm_tmr_blk.addrh = 0x0;
+
+       fadt->x_gpe0_blk.space_id = 1;
+       fadt->x_gpe0_blk.bit_width = 64;
+       fadt->x_gpe0_blk.bit_offset = 0;
+       fadt->x_gpe0_blk.resv = 0;
+       fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+       fadt->x_gpe0_blk.addrh = 0x0;
+
+       fadt->x_gpe1_blk.space_id = 1;
+       fadt->x_gpe1_blk.bit_width = 0;
+       fadt->x_gpe1_blk.bit_offset = 0;
+       fadt->x_gpe1_blk.resv = 0;
+       fadt->x_gpe1_blk.addrl = 0x0;
+       fadt->x_gpe1_blk.addrh = 0x0;
+
+       header->checksum =
+           acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/google/butterfly/gpio.h b/src/mainboard/google/butterfly/gpio.h
new file mode 100644 (file)
index 0000000..5448299
--- /dev/null
@@ -0,0 +1,304 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef BUTTERFLY_GPIO_H
+#define BUTTERFLY_GPIO_H
+
+#include "southbridge/intel/bd82x6x/gpio.h"
+
+const struct pch_gpio_set1 pch_gpio_set1_mode = {
+       .gpio0  = GPIO_MODE_NONE,   /* Unused */
+       .gpio1  = GPIO_MODE_NONE,   /* Unused */
+       .gpio2  = GPIO_MODE_NONE,   /* Unused */
+       .gpio3  = GPIO_MODE_NONE,   /* Unused */
+       .gpio4  = GPIO_MODE_NATIVE, /* Native - TPSINT# for TP SMBus IRQ */
+       .gpio5  = GPIO_MODE_NONE,   /* Unused */
+       .gpio6  = GPIO_MODE_GPIO,   /* Input - BOARD_ID4 */
+       .gpio7  = GPIO_MODE_GPIO,   /* Input - BOARD_ID5 */
+       .gpio8  = GPIO_MODE_GPIO,   /* Output - BT on/off */
+       .gpio9  = GPIO_MODE_NONE,   /* Unused */
+       .gpio10 = GPIO_MODE_NONE,   /* Unused */
+       .gpio11 = GPIO_MODE_GPIO,   /* Input - TP WAKEUP Event */
+       .gpio12 = GPIO_MODE_NONE,   /* Unused */
+       .gpio13 = GPIO_MODE_GPIO,   /* Input - SCI from EC */
+       .gpio14 = GPIO_MODE_GPIO,   /* Output - AOAC WLAN  power control */
+       .gpio15 = GPIO_MODE_GPIO,   /* Unused - Do not control WLAN*/
+       .gpio16 = GPIO_MODE_NONE,   /* Unused */
+       .gpio17 = GPIO_MODE_GPIO,   /* Input - DGPU_PWROK */
+       .gpio18 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ1# LAN clock pin*/
+       .gpio19 = GPIO_MODE_GPIO,   /* Input - Boot BIOS  Selection 0 */
+       .gpio20 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ2# SDCard clock pin */
+       .gpio21 = GPIO_MODE_GPIO,   /* Input - EC_ENTERING_RW for Google OS */
+       .gpio22 = GPIO_MODE_GPIO,   /* Input - BIOS RECOVERY */
+       .gpio23 = GPIO_MODE_NONE,   /* Unused */
+       .gpio24 = GPIO_MODE_GPIO,   /* Output - DGPU_HOLD_RST#  */
+       .gpio25 = GPIO_MODE_NONE,   /* Unused */
+       .gpio26 = GPIO_MODE_NONE,   /* Unused */
+       .gpio27 = GPIO_MODE_NONE,   /* Unused */
+       .gpio28 = GPIO_MODE_NONE,   /* Unused */
+       .gpio29 = GPIO_MODE_NONE,   /* Unused */
+       .gpio30 = GPIO_MODE_NATIVE, /* Native - SUSWARN_EC# */
+       .gpio31 = GPIO_MODE_NONE,   /* Unused */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_direction = {
+       .gpio0  = GPIO_DIR_INPUT,  /* Unused */
+       .gpio1  = GPIO_DIR_INPUT,  /* Unused */
+       .gpio2  = GPIO_DIR_INPUT,  /* Unused */
+       .gpio3  = GPIO_DIR_INPUT,  /* Unused */
+       .gpio4  = GPIO_DIR_INPUT,  /* Native */
+       .gpio5  = GPIO_DIR_INPUT,  /* Unused */
+       .gpio6  = GPIO_DIR_INPUT,  /* Input */
+       .gpio7  = GPIO_DIR_INPUT,  /* Input */
+       .gpio8  = GPIO_DIR_INPUT,  /* Output HIGH - set in mainboard.c */
+       .gpio9  = GPIO_DIR_INPUT,  /* Unused */
+       .gpio10 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio11 = GPIO_DIR_INPUT,  /* Input */
+       .gpio12 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio13 = GPIO_DIR_INPUT,  /* Input */
+       .gpio14 = GPIO_DIR_OUTPUT, /* Output HIGH */
+       .gpio15 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio16 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio17 = GPIO_DIR_INPUT,  /* Input */
+       .gpio18 = GPIO_DIR_INPUT,  /* Native */
+       .gpio19 = GPIO_DIR_INPUT,  /* Input */
+       .gpio20 = GPIO_DIR_INPUT,  /* Native */
+       .gpio21 = GPIO_DIR_INPUT,  /* Input */
+       .gpio22 = GPIO_DIR_INPUT,  /* Input */
+       .gpio23 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio24 = GPIO_DIR_OUTPUT, /* Output HIGH */
+       .gpio25 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio26 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio27 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio28 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio29 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio30 = GPIO_DIR_INPUT,  /* Native */
+       .gpio31 = GPIO_DIR_INPUT,  /* Unused */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_level = {
+       .gpio0  = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio1  = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio2  = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio3  = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio4  = GPIO_LEVEL_LOW,  /* Native */
+       .gpio5  = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio6  = GPIO_LEVEL_LOW,  /* Input */
+       .gpio7  = GPIO_LEVEL_LOW,  /* Input */
+       .gpio8  = GPIO_LEVEL_HIGH, /* Output HIGH - set in mainboard.c */
+       .gpio9  = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio10 = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio11 = GPIO_LEVEL_LOW,  /* Input */
+       .gpio12 = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio13 = GPIO_LEVEL_LOW,  /* Input */
+       .gpio14 = GPIO_LEVEL_HIGH, /* Output HIGH */
+       .gpio15 = GPIO_LEVEL_HIGH, /* Unused */
+       .gpio16 = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio17 = GPIO_LEVEL_LOW,  /* Input */
+       .gpio18 = GPIO_LEVEL_LOW,  /* Native */
+       .gpio19 = GPIO_LEVEL_LOW,  /* Input */
+       .gpio20 = GPIO_LEVEL_LOW,  /* Native */
+       .gpio21 = GPIO_LEVEL_LOW,  /* Input */
+       .gpio22 = GPIO_LEVEL_LOW,  /* Input */
+       .gpio23 = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio24 = GPIO_LEVEL_HIGH, /* Output HIGH */
+       .gpio25 = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio26 = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio27 = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio28 = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio29 = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio30 = GPIO_LEVEL_LOW,  /* Native */
+       .gpio31 = GPIO_LEVEL_LOW,  /* Unused */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_invert = {
+       .gpio11 = GPIO_INVERT,  /* invert touchpad wakeup pin */
+       .gpio13 = GPIO_INVERT,  /* invert EC SCI pin */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_mode = {
+       .gpio32 = GPIO_MODE_NATIVE, /* Native - Connect to EC Clock Run */
+       .gpio33 = GPIO_MODE_GPIO,   /* Input - (Google protect BIOS ROM) */
+       .gpio34 = GPIO_MODE_NONE,   /* Unused */
+       .gpio35 = GPIO_MODE_NONE,   /* Unused */
+       .gpio36 = GPIO_MODE_GPIO,   /* Output - DGPU_PWR_EN */
+       .gpio37 = GPIO_MODE_GPIO,   /* Input - FDI TERM / VOLTAGE OVERRIDE */
+       .gpio38 = GPIO_MODE_GPIO,   /* Input - MFG_MODE test */
+       .gpio39 = GPIO_MODE_GPIO,   /* Input - DGPU_PRSNT */
+       .gpio40 = GPIO_MODE_NONE,   /* Unused */
+       .gpio41 = GPIO_MODE_NONE,   /* Unused */
+       .gpio42 = GPIO_MODE_NONE,   /* Unused */
+       .gpio43 = GPIO_MODE_NONE,   /* Unused */
+       .gpio44 = GPIO_MODE_GPIO,   /* Input - BOARD_ID0 */
+       .gpio45 = GPIO_MODE_GPIO,   /* Input - BOARD_ID1 */
+       .gpio46 = GPIO_MODE_GPIO,   /* Input - BOARD_ID2 */
+       .gpio47 = GPIO_MODE_NATIVE, /* Native - PEGA_GPU clock request */
+       .gpio48 = GPIO_MODE_NONE,   /* Unused */
+       .gpio49 = GPIO_MODE_NONE,   /* Unused */
+       .gpio50 = GPIO_MODE_NONE,   /* Unused */
+       .gpio51 = GPIO_MODE_GPIO,   /* Input - Boot BIOS  Selection 1 */
+       .gpio52 = GPIO_MODE_GPIO,   /* Input - Google recovery, Pull up +3V */
+       .gpio53 = GPIO_MODE_GPIO,   /* Output - G Sensor LED */
+       .gpio54 = GPIO_MODE_GPIO,   /* Input - Google Development */
+       .gpio55 = GPIO_MODE_GPIO,   /* Input - Top-Block Swap Override */
+       .gpio56 = GPIO_MODE_NONE,   /* Unused */
+       .gpio57 = GPIO_MODE_GPIO,   /* Input - SV_DET */
+       .gpio58 = GPIO_MODE_NONE,   /* Unused */
+       .gpio59 = GPIO_MODE_NONE,   /* Unused */
+       .gpio60 = GPIO_MODE_NONE,   /* GPO - DRAMRST_CNTRL_PCH */
+       .gpio61 = GPIO_MODE_NONE,   /* Unused */
+       .gpio62 = GPIO_MODE_NATIVE, /* Native - Connect to EC 32.768KHz */
+       .gpio63 = GPIO_MODE_NATIVE, /* Native - SLP_S5 */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_direction = {
+       .gpio32 = GPIO_DIR_INPUT,  /* Native */
+       .gpio33 = GPIO_DIR_INPUT,  /* Input */
+       .gpio34 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio35 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio36 = GPIO_DIR_OUTPUT, /* Output  HIGH */
+       .gpio37 = GPIO_DIR_INPUT,  /* Input */
+       .gpio38 = GPIO_DIR_INPUT,  /* Input */
+       .gpio39 = GPIO_DIR_INPUT,  /* Input */
+       .gpio40 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio41 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio42 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio43 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio44 = GPIO_DIR_INPUT,  /* Input */
+       .gpio45 = GPIO_DIR_INPUT,  /* Input */
+       .gpio46 = GPIO_DIR_INPUT,  /* Input */
+       .gpio47 = GPIO_DIR_INPUT,  /* Native */
+       .gpio48 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio49 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio50 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio51 = GPIO_DIR_INPUT,  /* Input */
+       .gpio52 = GPIO_DIR_INPUT,  /* Input */
+       .gpio53 = GPIO_DIR_OUTPUT, /* Input */
+       .gpio54 = GPIO_DIR_INPUT,  /* Input */
+       .gpio55 = GPIO_DIR_INPUT,  /* Input */
+       .gpio56 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio57 = GPIO_DIR_INPUT,  /* Input */
+       .gpio58 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio59 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio60 = GPIO_DIR_OUTPUT, /* Output  HIGH */
+       .gpio61 = GPIO_DIR_INPUT,  /* Unused */
+       .gpio62 = GPIO_DIR_INPUT,  /* Native */
+       .gpio63 = GPIO_DIR_INPUT,  /* Native */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_level = {
+       .gpio32 = GPIO_LEVEL_LOW,  /* Native */
+       .gpio33 = GPIO_LEVEL_LOW,  /* Input */
+       .gpio34 = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio35 = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio36 = GPIO_LEVEL_HIGH, /* Output  HIGH */
+       .gpio37 = GPIO_LEVEL_LOW,  /* Input */
+       .gpio38 = GPIO_LEVEL_LOW,  /* Input */
+       .gpio39 = GPIO_LEVEL_LOW,  /* Input */
+       .gpio40 = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio41 = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio42 = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio43 = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio44 = GPIO_LEVEL_LOW,  /* Input */
+       .gpio45 = GPIO_LEVEL_LOW,  /* Input */
+       .gpio46 = GPIO_LEVEL_LOW,  /* Input */
+       .gpio47 = GPIO_LEVEL_LOW,  /* Native */
+       .gpio48 = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio49 = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio50 = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio51 = GPIO_LEVEL_LOW,  /* Input */
+       .gpio52 = GPIO_LEVEL_LOW,  /* Input */
+       .gpio53 = GPIO_LEVEL_HIGH, /* Input */
+       .gpio54 = GPIO_LEVEL_LOW,  /* Input */
+       .gpio55 = GPIO_LEVEL_LOW,  /* Input */
+       .gpio56 = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio57 = GPIO_LEVEL_LOW,  /* Input */
+       .gpio58 = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio59 = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio60 = GPIO_LEVEL_HIGH, /* Output  HIGH */
+       .gpio61 = GPIO_LEVEL_LOW,  /* Unused */
+       .gpio62 = GPIO_LEVEL_LOW,  /* Native */
+       .gpio63 = GPIO_LEVEL_LOW,  /* Native */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_mode = {
+       .gpio64 = GPIO_MODE_NONE,   /* Unused */
+       .gpio65 = GPIO_MODE_NONE,   /* Unused */
+       .gpio66 = GPIO_MODE_NONE,   /* Unused */
+       .gpio67 = GPIO_MODE_NONE,   /* Unused */
+       .gpio68 = GPIO_MODE_GPIO,   /* Input - DGPU_PWR_EN */
+       .gpio69 = GPIO_MODE_NONE,   /* Unused */
+       .gpio70 = GPIO_MODE_NONE,   /* Unused */
+       .gpio71 = GPIO_MODE_NONE,   /* Unused */
+       .gpio72 = GPIO_MODE_NONE,   /* Unused */
+       .gpio73 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ0# WLAN clock request */
+       .gpio74 = GPIO_MODE_NONE,   /* Unused */
+       .gpio75 = GPIO_MODE_GPIO,   /* Input - SMB_ME1_DAT */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_direction = {
+       .gpio64 = GPIO_DIR_INPUT,   /* Unused */
+       .gpio65 = GPIO_DIR_INPUT,   /* Unused */
+       .gpio66 = GPIO_DIR_INPUT,   /* Unused */
+       .gpio67 = GPIO_DIR_INPUT,   /* Unused */
+       .gpio68 = GPIO_DIR_INPUT,   /* Input */
+       .gpio69 = GPIO_DIR_INPUT,   /* Unused */
+       .gpio70 = GPIO_DIR_INPUT,   /* Unused */
+       .gpio71 = GPIO_DIR_INPUT,   /* Unused */
+       .gpio72 = GPIO_DIR_INPUT,   /* Unused */
+       .gpio73 = GPIO_DIR_INPUT,   /* Native */
+       .gpio74 = GPIO_DIR_INPUT,   /* Unused */
+       .gpio75 = GPIO_DIR_INPUT,   /* Input */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_level = {
+       .gpio64 = GPIO_LEVEL_LOW,   /* Unused */
+       .gpio65 = GPIO_LEVEL_LOW,   /* Unused */
+       .gpio66 = GPIO_LEVEL_LOW,   /* Unused */
+       .gpio67 = GPIO_LEVEL_LOW,   /* Unused */
+       .gpio68 = GPIO_LEVEL_LOW,   /* Input */
+       .gpio69 = GPIO_LEVEL_LOW,   /* Unused */
+       .gpio70 = GPIO_LEVEL_LOW,   /* Unused */
+       .gpio71 = GPIO_LEVEL_LOW,   /* Unused */
+       .gpio72 = GPIO_LEVEL_LOW,   /* Unused */
+       .gpio73 = GPIO_LEVEL_LOW,   /* Native */
+       .gpio74 = GPIO_LEVEL_LOW,   /* Unused */
+       .gpio75 = GPIO_LEVEL_LOW,   /* Input */
+};
+
+const struct pch_gpio_map butterfly_gpio_map = {
+       .set1 = {
+               .mode           = &pch_gpio_set1_mode,
+               .direction      = &pch_gpio_set1_direction,
+               .level          = &pch_gpio_set1_level,
+               .invert         = &pch_gpio_set1_invert,
+
+       },
+       .set2 = {
+               .mode           = &pch_gpio_set2_mode,
+               .direction      = &pch_gpio_set2_direction,
+               .level          = &pch_gpio_set2_level,
+       },
+       .set3 = {
+               .mode           = &pch_gpio_set3_mode,
+               .direction      = &pch_gpio_set3_direction,
+               .level          = &pch_gpio_set3_level,
+       },
+};
+#endif
diff --git a/src/mainboard/google/butterfly/hda_verb.h b/src/mainboard/google/butterfly/hda_verb.h
new file mode 100644 (file)
index 0000000..1901a68
--- /dev/null
@@ -0,0 +1,266 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*     Vendor Name    : IDT
+ *     Vendor ID      : 0x111d76e5
+ *     Subsystem ID   : 0x103c18f9
+ *     Revision ID    : 0x100303
+ */
+
+
+static const u32 mainboard_cim_verb_data[] = {
+       /* coreboot specific header */
+       0x111D76E5,     // Codec Vendor / Device ID: IDT 92HD99
+       0x103C18F9,     // Subsystem ID
+       0x00000073,     // Number of 4 dword sets
+
+/* Bits 31:28 - Codec Address */
+/* Bits 27:20 - NID */
+/* Bits 19:8 - Verb ID */
+/* Bits 7:0  - Payload */
+
+/* NID 0x01 - NodeInfo */
+       0x001720F9,
+       0x00172118,
+       0x0017223C,
+       0x00172310,
+
+/* NID 0x0A - External Microphone Connector
+ * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq)
+ */
+       0x00A71C20,
+       0x00A71D10,
+       0x00A71EA1,
+       0x00A71F04,
+
+/* NID 0x0B - Headphone Connector
+ * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq)
+ */
+       0x00B71C1F,
+       0x00B71D10,
+       0x00B71E21,
+       0x00B71F04,
+
+/* NID 0x0C - Not connected
+ * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq)
+ */
+       0x00C71CF0,
+       0x00C71D00,
+       0x00C71EF0,
+       0x00C71F40,
+
+/* NID 0x0D - Internal Speakers
+ * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq)
+ */
+       0x00D71C10,
+       0x00D71D01,
+       0x00D71E17,
+       0x00D71F90,
+
+/* NID 0x0F - Not connected
+ * Config=0x40F000F0
+ */
+       0x00F71CF0,
+       0x00F71D00,
+       0x00F71EF0,
+       0x00F71F40,
+
+/* NID 0x11 - Internal Microphone
+ * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq)
+ */
+       0x01171C40,
+       0x01171D01,
+       0x01171EA3,
+       0x01171FD5,
+
+       /*
+        * Hardware EQ Parameters
+        * Sample Rate 88200
+        */
+       0x0227A63F,     0x0227A73E,     0x0227A8EB,     0x0227A93F,
+       0x0227AA3E,     0x0227ABEB,     0x0227AC00,     0x0227AD80,
+       0x0227A681,     0x0227A782,     0x0227A829,     0x0227A981,
+       0x0227AA82,     0x0227AB29,     0x0227AC01,     0x0227AD80,
+       0x0227A63F,     0x0227A73E,     0x0227A8EB,     0x0227A93F,
+       0x0227AA3E,     0x0227ABEB,     0x0227AC02,     0x0227AD80,
+       0x0227A67E,     0x0227A77B,     0x0227A846,     0x0227A97E,
+       0x0227AA7B,     0x0227AB46,     0x0227AC03,     0x0227AD80,
+       0x0227A6C1,     0x0227A77F,     0x0227A898,     0x0227A9C1,
+       0x0227AA7F,     0x0227AB98,     0x0227AC04,     0x0227AD80,
+       0x0227A63E,     0x0227A7D1,     0x0227A84F,     0x0227A93E,
+       0x0227AAD1,     0x0227AB4F,     0x0227AC05,     0x0227AD80,
+       0x0227A683,     0x0227A7BE,     0x0227A855,     0x0227A983,
+       0x0227AABE,     0x0227AB55,     0x0227AC06,     0x0227AD80,
+       0x0227A63D,     0x0227A7B9,     0x0227A856,     0x0227A93D,
+       0x0227AAB9,     0x0227AB56,     0x0227AC07,     0x0227AD80,
+       0x0227A67C,     0x0227A741,     0x0227A8AB,     0x0227A97C,
+       0x0227AA41,     0x0227ABAB,     0x0227AC08,     0x0227AD80,
+       0x0227A6C3,     0x0227A775,     0x0227A85A,     0x0227A9C3,
+       0x0227AA75,     0x0227AB5A,     0x0227AC09,     0x0227AD80,
+       0x0227A63F,     0x0227A79E,     0x0227A829,     0x0227A93F,
+       0x0227AA9E,     0x0227AB29,     0x0227AC0A,     0x0227AD80,
+       0x0227A682,     0x0227A7E3,     0x0227A867,     0x0227A982,
+       0x0227AAE3,     0x0227AB67,     0x0227AC0B,     0x0227AD80,
+       0x0227A63E,     0x0227A74F,     0x0227A89D,     0x0227A93E,
+       0x0227AA4F,     0x0227AB9D,     0x0227AC0C,     0x0227AD80,
+       0x0227A67D,     0x0227A71C,     0x0227A899,     0x0227A97D,
+       0x0227AA1C,     0x0227AB99,     0x0227AC0D,     0x0227AD80,
+       0x0227A6C2,     0x0227A712,     0x0227A839,     0x0227A9C2,
+       0x0227AA12,     0x0227AB39,     0x0227AC0E,     0x0227AD80,
+       0x0227A63F,     0x0227A708,     0x0227A856,     0x0227A93F,
+       0x0227AA08,     0x0227AB56,     0x0227AC0F,     0x0227AD80,
+       0x0227A68E,     0x0227A7ED,     0x0227A89D,     0x0227A98E,
+       0x0227AAED,     0x0227AB9D,     0x0227AC10,     0x0227AD80,
+       0x0227A637,     0x0227A78F,     0x0227A853,     0x0227A937,
+       0x0227AA8F,     0x0227AB53,     0x0227AC11,     0x0227AD80,
+       0x0227A671,     0x0227A712,     0x0227A863,     0x0227A971,
+       0x0227AA12,     0x0227AB63,     0x0227AC12,     0x0227AD80,
+       0x0227A6C9,     0x0227A768,     0x0227A856,     0x0227A9C9,
+       0x0227AA68,     0x0227AB56,     0x0227AC13,     0x0227AD80,
+       0x0227A642,     0x0227A709,     0x0227A838,     0x0227A942,
+       0x0227AA09,     0x0227AB38,     0x0227AC14,     0x0227AD80,
+       0x0227A69C,     0x0227A78A,     0x0227A867,     0x0227A99C,
+       0x0227AA8A,     0x0227AB67,     0x0227AC15,     0x0227AD80,
+       0x0227A634,     0x0227A717,     0x0227A8E3,     0x0227A934,
+       0x0227AA17,     0x0227ABE3,     0x0227AC16,     0x0227AD80,
+       0x0227A663,     0x0227A775,     0x0227A899,     0x0227A963,
+       0x0227AA75,     0x0227AB99,     0x0227AC17,     0x0227AD80,
+       0x0227A6C9,     0x0227A7DE,     0x0227A8E5,     0x0227A9C9,
+       0x0227AADE,     0x0227ABE5,     0x0227AC18,     0x0227AD80,
+       0x0227A640,     0x0227A700,     0x0227A800,     0x0227A940,
+       0x0227AA00,     0x0227AB00,     0x0227AC19,     0x0227AD80,
+
+       /*
+        * Hardware EQ Parameters
+        * Sample Rate 96000
+        */
+       0x0227A63F,     0x0227A74E,     0x0227A888,     0x0227A93F,
+       0x0227AA4E,     0x0227AB88,     0x0227AC1A,     0x0227AD80,
+       0x0227A681,     0x0227A762,     0x0227A8EE,     0x0227A981,
+       0x0227AA62,     0x0227ABEE,     0x0227AC1B,     0x0227AD80,
+       0x0227A63F,     0x0227A74E,     0x0227A888,     0x0227A93F,
+       0x0227AA4E,     0x0227AB88,     0x0227AC1C,     0x0227AD80,
+       0x0227A67E,     0x0227A79A,     0x0227A8E7,     0x0227A97E,
+       0x0227AA9A,     0x0227ABE7,     0x0227AC1D,     0x0227AD80,
+       0x0227A6C1,     0x0227A760,     0x0227A8C3,     0x0227A9C1,
+       0x0227AA60,     0x0227ABC3,     0x0227AC1E,     0x0227AD80,
+       0x0227A63E,     0x0227A7E9,     0x0227A84B,     0x0227A93E,
+       0x0227AAE9,     0x0227AB4B,     0x0227AC1F,     0x0227AD80,
+       0x0227A683,     0x0227A76C,     0x0227A8F2,     0x0227A983,
+       0x0227AA6C,     0x0227ABF2,     0x0227AC20,     0x0227AD80,
+       0x0227A63D,     0x0227A7E7,     0x0227A880,     0x0227A93D,
+       0x0227AAE7,     0x0227AB80,     0x0227AC21,     0x0227AD80,
+       0x0227A67C,     0x0227A793,     0x0227A80E,     0x0227A97C,
+       0x0227AA93,     0x0227AB0E,     0x0227AC22,     0x0227AD80,
+       0x0227A6C3,     0x0227A72F,     0x0227A835,     0x0227A9C3,
+       0x0227AA2F,     0x0227AB35,     0x0227AC23,     0x0227AD80,
+       0x0227A63F,     0x0227A7A5,     0x0227A8FE,     0x0227A93F,
+       0x0227AAA5,     0x0227ABFE,     0x0227AC24,     0x0227AD80,
+       0x0227A682,     0x0227A798,     0x0227A89D,     0x0227A982,
+       0x0227AA98,     0x0227AB9D,     0x0227AC25,     0x0227AD80,
+       0x0227A63E,     0x0227A772,     0x0227A839,     0x0227A93E,
+       0x0227AA72,     0x0227AB39,     0x0227AC26,     0x0227AD80,
+       0x0227A67D,     0x0227A767,     0x0227A863,     0x0227A97D,
+       0x0227AA67,     0x0227AB63,     0x0227AC27,     0x0227AD80,
+       0x0227A6C1,     0x0227A7E7,     0x0227A8C8,     0x0227A9C1,
+       0x0227AAE7,     0x0227ABC8,     0x0227AC28,     0x0227AD80,
+       0x0227A63F,     0x0227A71B,     0x0227A81A,     0x0227A93F,
+       0x0227AA1B,     0x0227AB1A,     0x0227AC29,     0x0227AD80,
+       0x0227A68D,     0x0227A763,     0x0227A872,     0x0227A98D,
+       0x0227AA63,     0x0227AB72,     0x0227AC2A,     0x0227AD80,
+       0x0227A638,     0x0227A733,     0x0227A809,     0x0227A938,
+       0x0227AA33,     0x0227AB09,     0x0227AC2B,     0x0227AD80,
+       0x0227A672,     0x0227A79C,     0x0227A88E,     0x0227A972,
+       0x0227AA9C,     0x0227AB8E,     0x0227AC2C,     0x0227AD80,
+       0x0227A6C8,     0x0227A7B1,     0x0227A8DD,     0x0227A9C8,
+       0x0227AAB1,     0x0227ABDD,     0x0227AC2D,     0x0227AD80,
+       0x0227A641,     0x0227A7E1,     0x0227A8D8,     0x0227A941,
+       0x0227AAE1,     0x0227ABD8,     0x0227AC2E,     0x0227AD80,
+       0x0227A699,     0x0227A70D,     0x0227A820,     0x0227A999,
+       0x0227AA0D,     0x0227AB20,     0x0227AC2F,     0x0227AD80,
+       0x0227A634,     0x0227A7FE,     0x0227A823,     0x0227A934,
+       0x0227AAFE,     0x0227AB23,     0x0227AC30,     0x0227AD80,
+       0x0227A666,     0x0227A7F2,     0x0227A8E0,     0x0227A966,
+       0x0227AAF2,     0x0227ABE0,     0x0227AC31,     0x0227AD80,
+       0x0227A6C9,     0x0227A720,     0x0227A804,     0x0227A9C9,
+       0x0227AA20,     0x0227AB04,     0x0227AC32,     0x0227AD80,
+       0x0227A640,     0x0227A700,     0x0227A800,     0x0227A940,
+       0x0227AA00,     0x0227AB00,     0x0227AC33,     0x0227AD80,
+
+       /* SAFEDSP Parameters */
+       0x022782C1,     0x02277127,     0x02277227,     0x02278801,
+       0x02278C58,     0x02278E90,     0x0227890A,     0x02278A14,
+       0x02278B0F,     0x0017B008,
+
+       /* Misc entries */
+               0x00B707C0, /* Enable PortB as Output with HP amp */
+               0x00D70740, /* Enable PortD as Output */
+               0x0017A200, /* Disable ClkEn of PortSenseTst */
+               0x0017C621, /* Slave Port - Port A used as microphone input for
+                                           combo Jack
+                              Master Port - Port B used for Jack Presence Detect
+                              Enable Combo Jack Detection */
+               0x0017A208, /* Enable ClkEn of PortSenseTst */
+               0x00170500, /* Set power state to D0 */
+
+       /* --- Next Codec --- */
+
+/*     Vendor Name    : Intel
+ *     Vendor ID      : 0x80862806
+ *     Subsystem ID   : 0x80860101
+ *     Revision ID    : 0x100000
+ */
+       /* coreboot specific header */
+       0x80862806,     // Codec Vendor / Device ID: Intel PantherPoint HDMI
+       0x80860101,     // Subsystem ID
+       0x00000004,     // Number of IDs
+
+       /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+       0x30172001,
+       0x30172101,
+       0x30172286,
+       0x30172380,
+
+       /* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+       0x30571c10,
+       0x30571d00,
+       0x30571e56,
+       0x30571f18,
+
+       /* Pin Complex (NID 0x06) Digital Out at Int HDMI */
+       0x30671c20,
+       0x30671d00,
+       0x30671e56,
+       0x30671f18,
+
+       /* Pin Complex (NID 0x07) Digital Out at Int HDMI */
+       0x30771c30,
+       0x30771d00,
+       0x30771e56,
+       0x30771f18
+};
+
+static const u32 mainboard_pc_beep_verbs[] = {
+       0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */
+};
+
+static const u32 mainboard_pc_beep_verbs_size =
+       sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]);
+
+
diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c
new file mode 100644 (file)
index 0000000..acab762
--- /dev/null
@@ -0,0 +1,507 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011-2012 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <arch/coreboot_tables.h>
+#include "hda_verb.h"
+#include "onboard.h"
+#include "ec.h"
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <smbios.h>
+#include <device/pci.h>
+#include <ec/quanta/ene_kb3940q/ec.h>
+#include <vendorcode/google/chromeos/fmap.h>
+
+static unsigned int search(char *p, char *a, unsigned int lengthp,
+                          unsigned int lengtha)
+{
+       int i, j;
+
+       /* Searching */
+       for (j = 0; j <= lengtha - lengthp; j++) {
+               for (i = 0; i < lengthp && p[i] == a[i + j]; i++) ;
+               if (i >= lengthp)
+                       return j;
+       }
+       return lengtha;
+}
+
+static unsigned char get_hex_digit(char *offset)
+{
+       unsigned char retval = 0;
+
+       retval = *offset - '0';
+       if (retval > 0x09) {
+               retval = *offset - 'A' + 0x0A;
+               if (retval > 0x0F)
+                       retval = *offset - 'a' + 0x0a;
+       }
+       if (retval > 0x0F) {
+               printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n",
+                       *offset, (unsigned char)*offset);
+               retval = 0;
+       }
+
+       return retval;
+}
+
+static int get_mac_address(u32 *high_dword, u32 *low_dword,
+                          u32 search_address, u32 search_length)
+{
+       char key[] = "ethernet_mac";
+       unsigned int offset;
+       int i;
+
+       offset = search(key, (char *)search_address,
+                       sizeof(key) - 1, search_length);
+       if (offset == search_length) {
+               printk(BIOS_DEBUG,
+                      "Error: Could not locate '%s' in VPD\n", key);
+               return 0;
+       }
+       printk(BIOS_DEBUG, "Located '%s' in VPD\n", key);
+
+       offset += sizeof(key);  /* move to next character */
+       *high_dword = 0;
+
+       /* Fetch the MAC address and put the octets in the correct order to
+        * be programmed.
+        *
+        * From RTL8105E_Series_EEPROM-Less_App_Note_1.1
+        * If the MAC address is 001122334455h:
+        * Write 33221100h to I/O register offset 0x00 via double word access
+        * Write 00005544h to I/O register offset 0x04 via double word access
+        */
+
+       for (i = 0; i < 4; i++) {
+               *high_dword |= (get_hex_digit((char *)(search_address + offset))
+                               << (4 + (i * 8)));
+               *high_dword |= (get_hex_digit((char *)(search_address + offset + 1))
+                               << (i * 8));
+               offset += 3;
+       }
+
+       *low_dword = 0;
+       for (i = 0; i < 2; i++) {
+               *low_dword |= (get_hex_digit((char *)(search_address + offset))
+                              << (4 + (i * 8)));
+               *low_dword |= (get_hex_digit((char *)(search_address + offset + 1))
+                              << (i * 8));
+               offset += 3;
+       }
+
+       return *high_dword | *low_dword;
+}
+
+static void program_mac_address(u16 io_base, u32 search_address,
+                               u32 search_length)
+{
+       /* Default MAC Address of A0:00:BA:D0:0B:AD */
+       u32 high_dword = 0xD0BA00A0;    /* high dword of mac address */
+       u32 low_dword = 0x0000AD0B;     /* low word of mac address as a dword */
+
+       if (search_length != -1)
+               get_mac_address(&high_dword, &low_dword, search_address,
+                               search_length);
+
+       if (io_base) {
+               printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base);
+               printk(BIOS_DEBUG, "Programming MAC Address\n");
+
+               outb(0xc0, io_base + 0x50);     /* Disable register protection */
+               outl(high_dword, io_base);
+               outl(low_dword, io_base + 0x04);
+               outb(0x60, io_base + 54);
+               outb(0x00, io_base + 0x50);     /* Enable register protection again */
+       }
+}
+
+static void program_keyboard_type(u32 search_address, u32 search_length)
+{
+       char key[] = "keyboard_layout";
+       char kbd_jpn[] = "xkb:jp::jpn";
+       unsigned int offset;
+       char kbd_type = EC_KBD_EN;      /* Default keyboard type is English */
+
+       if (search_length != -1) {
+
+               /*
+                * Search for keyboard_layout identifier
+                * The only options in the EC are Japanese or English.
+                * The English keyboard layout is actually used for multiple
+                * different languages - English, Spanish, French...  Because
+                * of this the code only searches for Japanese, and sets the
+                * keyboard type to English if Japanese is not found.
+                */
+               offset = search(key, (char *)search_address, sizeof(key) - 1,
+                               search_length);
+               if (offset != search_length) {
+                       printk(BIOS_DEBUG, "Located '%s' in VPD\n", key);
+
+                       offset += sizeof(key);  /* move to next character */
+                       search_length = sizeof(kbd_jpn);
+                       offset = search(kbd_jpn, (char *)(search_address + offset),
+                                       sizeof(kbd_jpn) - 1, search_length);
+                       if (offset != search_length)
+                               kbd_type = EC_KBD_JP;
+               }
+       } else
+               printk(BIOS_DEBUG, "Error: Could not locate VPD area\n");
+
+
+       printk(BIOS_DEBUG, "Setting Keyboard type in EC to ");
+       printk(BIOS_DEBUG, (kbd_type == EC_KBD_JP) ? "Japanese" : "English");
+       printk(BIOS_DEBUG, ".\n");
+
+       ec_mem_write(EC_KBID_REG, kbd_type);
+}
+
+void mainboard_suspend_resume(void)
+{
+       /* Call SMM finalize() handlers before resume */
+       outb(0xcb, 0xb2);
+}
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static int int15_handler(struct eregs *regs)
+{
+       int res = -1;
+
+       printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
+              __func__, regs->eax & 0xffff);
+
+       switch (regs->eax & 0xffff) {
+       case 0x5f34:
+               /*
+                * Set Panel Fitting Hook:
+                *  bit 2 = Graphics Stretching
+                *  bit 1 = Text Stretching
+                *  bit 0 = Centering (do not set with bit1 or bit2)
+                *  0     = video bios default
+                */
+               regs->eax &= 0xffff0000;
+               regs->eax |= 0x005f;
+               regs->ecx &= 0xffffff00;
+               regs->ecx |= 0x00;      /* Use video bios default */
+               res = 0;
+               break;
+       case 0x5f35:
+               /*
+                * Boot Display Device Hook:
+                *  bit 0 = CRT
+                *  bit 1 = TV (eDP)
+                *  bit 2 = EFP
+                *  bit 3 = LFP
+                *  bit 4 = CRT2
+                *  bit 5 = TV2 (eDP)
+                *  bit 6 = EFP2
+                *  bit 7 = LFP2
+                */
+               regs->eax &= 0xffff0000;
+               regs->eax |= 0x005f;
+               regs->ecx &= 0xffff0000;
+               regs->ecx |= 0x0000;    /* Use video bios default */
+               res = 0;
+               break;
+       case 0x5f51:
+               /*
+                * Hook to select active LFP configuration:
+                *  00h = No LVDS, VBIOS does not enable LVDS
+                *  01h = Int-LVDS, LFP driven by integrated LVDS decoder
+                *  02h = SVDO-LVDS, LFP driven by SVDO decoder
+                *  03h = eDP, LFP Driven by Int-DisplayPort encoder
+                */
+               regs->eax &= 0xffff0000;
+               regs->eax |= 0x005f;
+               regs->ecx &= 0xffff0000;
+               regs->ecx |= 0x0001;    /* Int-LVDS */
+               res = 0;
+               break;
+       case 0x5f70:
+               switch ((regs->ecx >> 8) & 0xff) {
+               case 0:
+                       /* Get Mux */
+                       regs->eax &= 0xffff0000;
+                       regs->eax |= 0x005f;
+                       regs->ecx &= 0xffff0000;
+                       regs->ecx |= 0x0000;
+                       res = 0;
+                       break;
+               case 1:
+                       /* Set Mux */
+                       regs->eax &= 0xffff0000;
+                       regs->eax |= 0x005f;
+                       regs->ecx &= 0xffff0000;
+                       regs->ecx |= 0x0000;
+                       res = 0;
+                       break;
+               case 2:
+                       /* Get SG/Non-SG mode */
+                       regs->eax &= 0xffff0000;
+                       regs->eax |= 0x005f;
+                       regs->ecx &= 0xffff0000;
+                       regs->ecx |= 0x0000;
+                       res = 0;
+                       break;
+               default:
+                       /* Interrupt was not handled */
+                       printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+                              ((regs->ecx >> 8) & 0xff));
+                       return 0;
+               }
+               break;
+
+       default:
+               printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+                      regs->eax & 0xffff);
+               break;
+       }
+       return res;
+}
+#endif
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+static int int15_handler(void)
+{
+       printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+              __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+
+       switch (M.x86.R_AX) {
+       case 0x5f34:
+               /*
+                * Set Panel Fitting Hook:
+                *  bit 2 = Graphics Stretching
+                *  bit 1 = Text Stretching
+                *  bit 0 = Centering (do not set with bit1 or bit2)
+                */
+               M.x86.R_AX = 0x005f;
+               M.x86.R_CX = 0x00;
+               break;
+       case 0x5f35:
+               /*
+                * Boot Display Device Hook:
+                *  bit 0 = CRT
+                *  bit 1 = TV (eDP)
+                *  bit 2 = EFP
+                *  bit 3 = LFP
+                *  bit 4 = CRT2
+                *  bit 5 = TV2 (eDP)
+                *  bit 6 = EFP2
+                *  bit 7 = LFP2
+                */
+               M.x86.R_AX = 0x005f;
+               M.x86.R_CX = 0x0000;    /* Use video bios default */
+               break;
+       case 0x5f51:
+               /*
+                * Hook to select active LFP configuration:
+                *  00h = No LVDS, VBIOS does not enable LVDS
+                *  01h = Int-LVDS, LFP driven by integrated LVDS decoder
+                *  02h = SVDO-LVDS, LFP driven by SVDO decoder
+                *  03h = eDP, LFP Driven by Int-DisplayPort encoder
+                */
+               M.x86.R_AX = 0x005f;
+               M.x86.R_CX = 1; /* Int-LVDS */
+               break;
+       case 0x5f70:
+               switch (M.x86.R_CH) {
+               case 0:
+                       /* Get Mux */
+                       M.x86.R_AX = 0x005f;
+                       M.x86.R_CL = 0;
+                       break;
+               case 1:
+                       /* Set Mux */
+                       M.x86.R_AX = 0x005f;
+                       M.x86.R_CX = 0;
+                       break;
+               case 2:
+                       /* Get SG/Non-SG mode */
+                       M.x86.R_AX = 0x005f;
+                       M.x86.R_CX = 0;
+                       break;
+               default:
+                       /* Interrupt was not handled */
+                       printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+                              M.x86.R_CH);
+                       return 0;
+               }
+               break;
+       default:
+               /* Interrupt was not handled */
+               printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n",
+                      M.x86.R_AX);
+               return 0;
+       }
+
+       /* Interrupt handled */
+       return 1;
+}
+#endif
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static void int15_install(void)
+{
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+       typedef int (*yabel_handleIntFunc)(void);
+       extern yabel_handleIntFunc yabel_intFuncArray[256];
+       yabel_intFuncArray[0x15] = int15_handler;
+#endif
+#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+       mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+}
+#endif
+
+/* Audio Setup */
+
+extern const u32 *cim_verb_data;
+extern u32 cim_verb_data_size;
+extern const u32 *pc_beep_verbs;
+extern u32 pc_beep_verbs_size;
+
+static void verb_setup(void)
+{
+       cim_verb_data = mainboard_cim_verb_data;
+       cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+       pc_beep_verbs = mainboard_pc_beep_verbs;
+       pc_beep_verbs_size = mainboard_pc_beep_verbs_size;
+
+}
+
+static void mainboard_init(device_t dev)
+{
+       char **vpd_region_ptr = NULL;
+       u32 search_length = find_fmap_entry("RO_VPD", (void **)vpd_region_ptr);
+       u32 search_address = (unsigned long)(*vpd_region_ptr);
+       u16 io_base = 0;
+       struct device *ethernet_dev = NULL;
+
+       /* Initialize the Embedded Controller */
+       butterfly_ec_init();
+
+       /* Program EC Keyboard locale based on VPD data */
+       program_keyboard_type(search_address, search_length);
+
+       /* Get NIC's IO base address */
+       ethernet_dev = dev_find_device(BUTTERFLY_NIC_VENDOR_ID,
+                                      BUTTERFLY_NIC_DEVICE_ID, dev);
+       if (ethernet_dev != NULL) {
+               io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe;
+
+               /*
+                * Battery life time - LAN PCIe should enter ASPM L1 to save
+                * power when LAN connection is idle.
+                * enable CLKREQ: LAN pci config space 0x81h=01
+                */
+               pci_write_config8(ethernet_dev, 0x81, 0x01);
+       }
+
+       if (io_base) {
+               /* Program MAC address based on VPD data */
+               program_mac_address(io_base, search_address, search_length);
+
+               /*
+                * Program NIC LEDS
+                *
+                * RTL8105E Series EEPROM-Less Application Note,
+                * Section 5.6 LED Mode Configuration
+                *
+                * Step1: Write C0h to I/O register 0x50 via byte access to
+                *        disable 'register protection'
+                * Step2: Write xx001111b to I/O register 0x52 via byte access
+                *        (bit7 is LEDS1 and bit6 is LEDS0)
+                * Step3: Write 0x00 to I/O register 0x50 via byte access to
+                *        enable 'register protection'
+                */
+               outb(0xc0, io_base + 0x50);     /* Disable protection */
+               outb((BUTTERFLY_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52);
+               outb(0x00, io_base + 0x50);     /* Enable register protection */
+       }
+}
+
+static int butterfly_smbios_type41(int *handle, unsigned long *current,
+                                  const char *name, u8 irq, u8 addr)
+{
+       struct smbios_type41 *t = (struct smbios_type41 *)*current;
+       int len = sizeof(struct smbios_type41);
+
+       memset(t, 0, sizeof(struct smbios_type41));
+       t->type = SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION;
+       t->handle = *handle;
+       t->length = len - 2;
+       t->reference_designation = smbios_add_string(t->eos, name);
+       t->device_type = SMBIOS_DEVICE_TYPE_OTHER;
+       t->device_status = 1;
+       t->device_type_instance = irq;
+       t->segment_group_number = 0;
+       t->bus_number = addr;
+       t->function_number = 0;
+       t->device_number = 0;
+
+       len = t->length + smbios_string_table_len(t->eos);
+       *current += len;
+       *handle += 1;
+       return len;
+}
+
+static int butterfly_onboard_smbios_data(device_t dev, int *handle,
+                                        unsigned long *current)
+{
+       int len = 0;
+
+       len += butterfly_smbios_type41(handle, current,
+                                      BUTTERFLY_TRACKPAD_NAME,
+                                      BUTTERFLY_TRACKPAD_IRQ,
+                                      BUTTERFLY_TRACKPAD_I2C_ADDR);
+
+       return len;
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+       dev->ops->init = mainboard_init;
+       dev->ops->get_smbios_data = butterfly_onboard_smbios_data;
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+       /* Install custom int15 handler for VGA OPROM */
+       int15_install();
+#endif
+       verb_setup();
+}
+
+struct chip_operations mainboard_ops = {
+       CHIP_NAME("Google Butterfly ChromeBook")
+       .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/google/butterfly/mainboard_smi.c b/src/mainboard/google/butterfly/mainboard_smi.c
new file mode 100644 (file)
index 0000000..4e02a3c
--- /dev/null
@@ -0,0 +1,115 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/me.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+
+/* Include EC functions */
+#include <ec/quanta/ene_kb3940q/ec.h>
+#include "ec.h"
+
+int mainboard_io_trap_handler(int smif)
+{
+       printk(BIOS_DEBUG, "mainboard_io_trap_handler: %x\n", smif);
+       switch (smif) {
+       case 0x99:
+               printk(BIOS_DEBUG, "Sample\n");
+               smm_get_gnvs()->smif = 0;
+               break;
+       default:
+               return 0;
+       }
+
+       /* On success, the IO Trap Handler returns 0
+        * On failure, the IO Trap Handler returns a value != 0
+        *
+        * For now, we force the return value to 0 and log all traps to
+        * see what's going on.
+        */
+       //gnvs->smif = 0;
+       return 1;
+}
+
+void mainboard_smi_gpi(u16 gpi_sts)
+{
+       printk(BIOS_DEBUG, "warn: unknown mainboard_smi_gpi: %x\n", gpi_sts);
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+       printk(BIOS_DEBUG, "mainboard_smi_sleep: %x\n", slp_typ);
+
+       /* Tell the EC to Enable USB power for S3 if requested */
+       if (smm_get_gnvs()->s3u0 != 0 || smm_get_gnvs()->s3u1 != 0)
+               ec_mem_write(EC_EC_PSW, ec_mem_read(EC_EC_PSW) | EC_PSW_USB);
+
+       /* Disable wake on USB, LAN & RTC */
+       /* Enable Wake from Keyboard */
+       if ((slp_typ == 4) || (slp_typ == 5)) {
+               printk(BIOS_DEBUG, "Disabling wake on RTC\n");
+               ec_mem_write(EC_EC_PSW, EC_PSW_IKB);
+       }
+}
+
+#define APMC_FINALIZE 0xcb
+#define APMC_ACPI_EN  0xe1
+#define APMC_ACPI_DIS 0x1e
+
+static int mainboard_finalized = 0;
+
+int mainboard_smi_apmc(u8 apmc)
+{
+       printk(BIOS_DEBUG, "mainboard_smi_apmc: %x\n", apmc);
+       switch (apmc) {
+       case APMC_FINALIZE:
+               printk(BIOS_DEBUG, "APMC: FINALIZE\n");
+               if (mainboard_finalized) {
+                       printk(BIOS_DEBUG, "APMC#: Already finalized\n");
+                       return 0;
+               }
+
+               intel_me_finalize_smm();
+               intel_pch_finalize_smm();
+               intel_sandybridge_finalize_smm();
+               intel_model_206ax_finalize_smm();
+
+               mainboard_finalized = 1;
+               break;
+
+       case APMC_ACPI_EN:
+               printk(BIOS_DEBUG, "APMC: ACPI_EN\n");
+               /* Clear all pending events and enable SCI */
+               ec_write_cmd(EC_CMD_ENABLE_ACPI_MODE);
+               break;
+
+       case APMC_ACPI_DIS:
+               printk(BIOS_DEBUG, "APMC: ACPI_DIS\n");
+               /* Clear all pending events and tell the EC that ACPI is disabled */
+               ec_write_cmd(EC_CMD_DISABLE_ACPI_MODE);
+               break;
+       }
+       return 0;
+}
diff --git a/src/mainboard/google/butterfly/onboard.h b/src/mainboard/google/butterfly/onboard.h
new file mode 100644 (file)
index 0000000..e32e023
--- /dev/null
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef BUTTERFLY_ONBOARD_H
+#define BUTTERFLY_ONBOARD_H
+
+#include <arch/smp/mpspec.h>
+/* uses 7-bit I2C address */
+/* must be set to edge triggered */
+#define BUTTERFLY_TRACKPAD_NAME         "trackpad"
+#define BUTTERFLY_TRACKPAD_I2C_ADDR     0x67
+#define BUTTERFLY_TRACKPAD_IRQ          22             /* PIRQG - 22 Edge triggered */
+
+/* defines for programming the MAC address */
+#define BUTTERFLY_NIC_VENDOR_ID                0x10EC
+#define BUTTERFLY_NIC_DEVICE_ID                0x8136
+
+/* 0x00: White LINK LED and Amber ACTIVE LED */
+#define BUTTERFLY_NIC_LED_MODE         0x00
+#endif
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
new file mode 100644 (file)
index 0000000..352f8d6
--- /dev/null
@@ -0,0 +1,307 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/byteorder.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include "southbridge/intel/bd82x6x/gpio.h"
+#include <arch/cpu.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/msr.h>
+#include "gpio.h"
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
+#include <cbfs.h>
+
+static void pch_enable_lpc(void)
+{
+       /* EC Decode Range Port60/64 and Port62/66 */
+       /* Enable EC and PS/2 Keyboard/Mouse*/
+       pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN);
+
+       /* EC Decode Range Port68/6C */
+       pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x40001);
+
+       /* EC Decode Range Port 380-387 */
+       pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x380 | 0x40001);
+
+}
+
+static void rcba_config(void)
+{
+       u32 reg32;
+
+       /*
+        *             GFX    INTA -> PIRQA (MSI)
+        * D28IP_P1IP  WLAN   INTA -> PIRQB
+        * D28IP_P2IP  ETH0   INTB -> PIRQF
+        * D28IP_P3IP  SDCARD INTC -> PIRQD
+        * D29IP_E1P   EHCI1  INTA -> PIRQD
+        * D26IP_E2P   EHCI2  INTA -> PIRQF
+        * D31IP_SIP   SATA   INTA -> PIRQB (MSI)
+        * D31IP_SMIP  SMBUS  INTB -> PIRQH
+        * D31IP_TTIP  THRT   INTC -> PIRQA
+        * D27IP_ZIP   HDA    INTA -> PIRQA (MSI)
+        *
+        * Trackpad interrupt is edge triggered and cannot be shared.
+        * TRACKPAD                -> PIRQG
+
+        */
+
+       /* Device interrupt pin register (board specific) */
+       RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+                       (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+       RCBA32(D29IP) = (INTA << D29IP_E1P);
+       RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
+                       (INTC << D28IP_P3IP);
+       RCBA32(D27IP) = (INTA << D27IP_ZIP);
+       RCBA32(D26IP) = (INTA << D26IP_E2P);
+       RCBA32(D25IP) = (NOINT << D25IP_LIP);
+       RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+       /* Device interrupt route registers */
+       DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
+       DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+       DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
+       DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
+       DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
+       DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+       DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+
+       /* Enable IOAPIC (generic) */
+       RCBA16(OIC) = 0x0100;
+       /* PCH BWG says to read back the IOAPIC enable register */
+       (void) RCBA16(OIC);
+
+       /* Disable unused devices (board specific) */
+       reg32 = RCBA32(FD);
+       reg32 |= PCH_DISABLE_ALWAYS;
+       /* Disable PCI bridge so MRC does not probe this bus */
+       reg32 |= PCH_DISABLE_P2P;
+       RCBA32(FD) = reg32;
+}
+
+void main(unsigned long bist)
+{
+       int boot_mode = 0;
+       int cbmem_was_initted;
+       u32 pm1_cnt;
+       u16 pm1_sts;
+
+#if CONFIG_COLLECT_TIMESTAMPS
+       tsc_t start_romstage_time;
+       tsc_t before_dram_time;
+       tsc_t after_dram_time;
+       tsc_t base_time = {
+               .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
+               .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
+       };
+#endif
+       struct pei_data pei_data = {
+               pei_version: PEI_VERSION,
+               mchbar: DEFAULT_MCHBAR,
+               dmibar: DEFAULT_DMIBAR,
+               epbar: DEFAULT_EPBAR,
+               pciexbar: CONFIG_MMCONF_BASE_ADDRESS,
+               smbusbar: SMBUS_IO_BASE,
+               wdbbar: 0x4000000,
+               wdbsize: 0x1000,
+               hpet_address: CONFIG_HPET_ADDRESS,
+               rcba: DEFAULT_RCBABASE,
+               pmbase: DEFAULT_PMBASE,
+               gpiobase: DEFAULT_GPIOBASE,
+               thermalbase: 0xfed08000,
+               system_type: 0, // 0 Mobile, 1 Desktop/Server
+               tseg_size: CONFIG_SMM_TSEG_SIZE,
+               spd_addresses: { 0xA0, 0x00,0xA4,0x00 },
+               ts_addresses: { 0x00, 0x00, 0x00, 0x00 },
+               ec_present: 1,
+               ddr3lv_support: 0,
+               // 0 = leave channel enabled
+               // 1 = disable dimm 0 on channel
+               // 2 = disable dimm 1 on channel
+               // 3 = disable dimm 0+1 on channel
+               dimm_channel0_disabled: 2,
+               dimm_channel1_disabled: 2,
+               max_ddr3_freq: 1600,
+               usb_port_config: {
+                        /* enabled   usb oc pin    length */
+                       { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */
+                       { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */
+                       { 1, 0, 0x0040 }, /* P2: Camera (no OC) */
+                       { 0, 0, 0x0000 }, /* P3: Empty */
+                       { 0, 0, 0x0000 }, /* P4: Empty */
+                       { 0, 0, 0x0000 }, /* P5: Empty */
+                       { 0, 0, 0x0000 }, /* P6: Empty */
+                       { 0, 0, 0x0000 }, /* P7: Empty */
+                       { 0, 4, 0x0000 }, /* P8: Empty */
+                       { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */
+                       { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */
+                       { 0, 4, 0x0000 }, /* P11: Empty */
+                       { 0, 4, 0x0000 }, /* P12: Empty */
+                       { 0, 4, 0x0000 }, /* P13: Empty */
+               },
+       };
+
+#if CONFIG_COLLECT_TIMESTAMPS
+       start_romstage_time = rdtsc();
+#endif
+
+       if (bist == 0)
+               enable_lapic();
+
+       pch_enable_lpc();
+
+       /* Enable GPIOs */
+       pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
+       pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+       setup_pch_gpios(&butterfly_gpio_map);
+
+       /* Initialize console device(s) */
+       console_init();
+
+       /* Halt if there was a built in self test failure */
+       report_bist_failure(bist);
+
+       if (MCHBAR16(SSKPD) == 0xCAFE) {
+               printk(BIOS_DEBUG, "soft reset detected\n");
+               boot_mode = 1;
+
+               /* System is not happy after keyboard reset... */
+               printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
+               outb(0x6, 0xcf9);
+               hlt();
+       }
+
+       /* Perform some early chipset initialization required
+        * before RAM initialization can work
+        */
+       sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
+       printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
+
+       /* Check PM1_STS[15] to see if we are waking from Sx */
+       pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
+
+       /* Read PM1_CNT[12:10] to determine which Sx state */
+       pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
+
+       if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+               printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+               boot_mode = 2;
+               /* Clear SLP_TYPE. This will break stage2 but
+                * we care for that when we get there.
+                */
+               outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
+#else
+               printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif
+       }
+
+       post_code(0x38);
+       /* Enable SPD ROMs and DDR-III DRAM */
+       enable_smbus();
+
+       /* Prepare USB controller early in S3 resume */
+       if (boot_mode == 2)
+               enable_usb_bar();
+
+       post_code(0x39);
+
+       post_code(0x3a);
+       pei_data.boot_mode = boot_mode;
+#if CONFIG_COLLECT_TIMESTAMPS
+       before_dram_time = rdtsc();
+#endif
+       sdram_initialize(&pei_data);
+
+#if CONFIG_COLLECT_TIMESTAMPS
+       after_dram_time = rdtsc();
+#endif
+       post_code(0x3c);
+
+       rcba_config();
+       post_code(0x3d);
+
+       quick_ram_check();
+       post_code(0x3e);
+
+       MCHBAR16(SSKPD) = 0xCAFE;
+#if CONFIG_EARLY_CBMEM_INIT
+       cbmem_was_initted = !cbmem_initialize();
+#else
+       cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram()
+                                                    - HIGH_MEMORY_SIZE));
+#endif
+
+#if CONFIG_HAVE_ACPI_RESUME
+       /* If there is no high memory area, we didn't boot before, so
+        * this is not a resume. In that case we just create the cbmem toc.
+        */
+
+       *(u32 *)CBMEM_BOOT_MODE = 0;
+       *(u32 *)CBMEM_RESUME_BACKUP = 0;
+
+       if ((boot_mode == 2) && cbmem_was_initted) {
+               void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+               if (resume_backup_memory) {
+                       *(u32 *)CBMEM_BOOT_MODE = boot_mode;
+                       *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
+               }
+               /* Magic for S3 resume */
+               pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+       } else if (boot_mode == 2) {
+               /* Failed S3 resume, reset to come up cleanly */
+               outb(0x6, 0xcf9);
+               hlt();
+       } else {
+               pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+       }
+#endif
+       post_code(0x3f);
+#if CONFIG_CHROMEOS
+       init_chromeos(boot_mode);
+#endif
+#if CONFIG_COLLECT_TIMESTAMPS
+       timestamp_init(base_time);
+       timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
+       timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
+       timestamp_add(TS_AFTER_INITRAM, after_dram_time );
+       timestamp_add_now(TS_END_ROMSTAGE);
+#endif
+#if CONFIG_CONSOLE_CBMEM
+       /* Keep this the last thing this function does. */
+       cbmemc_reinit();
+#endif
+}
diff --git a/src/mainboard/google/butterfly/thermal.h b/src/mainboard/google/butterfly/thermal.h
new file mode 100644 (file)
index 0000000..c8ff1f4
--- /dev/null
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef BUTTERFLY_THERMAL_H
+#define BUTTERFLY_THERMAL_H
+
+/* Active Thermal and fans are controlled by the EC. */
+
+       /* Temperature which OS will shutdown at */
+       #define CRITICAL_TEMPERATURE    100
+
+       /* Temperature which OS will throttle CPU */
+       #define PASSIVE_TEMPERATURE             90
+
+#endif