AGESA f15tn f16kb: Fix HUDSON_XHCI_ENABLE
[coreboot.git] / src / mainboard / amd / thatcher / dsdt.asl
1 /*
2  * This file is part of the coreboot project.
3  *
4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; version 2 of the License.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
18  */
19
20 /* DefinitionBlock Statement */
21 DefinitionBlock (
22         "DSDT.AML",           /* Output filename */
23         "DSDT",                 /* Signature */
24         0x02,           /* DSDT Revision, needs to be 2 for 64bit */
25         "AMD   ",               /* OEMID */
26         "PARMER  ",          /* TABLE ID */
27         0x00010001      /* OEM Revision */
28         )
29 {       /* Start of ASL file */
30         /* #include "../../../arch/x86/acpi/debug.asl" */               /* Include global debug methods if needed */
31
32         /* Data to be patched by the BIOS during POST */
33         /* FIXME the patching is not done yet! */
34         /* Memory related values */
35         Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
36         Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
37         Name(PBLN, 0x0) /* Length of BIOS area */
38
39         Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)  /* Base address of PCIe config space */
40         Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
41         Name(HPBA, 0xFED00000)  /* Base address of HPET table */
42
43         Name(SSFG, 0x0D)                /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
44
45         /* USB overcurrent mapping pins.   */
46         Name(UOM0, 0)
47         Name(UOM1, 2)
48         Name(UOM2, 0)
49         Name(UOM3, 7)
50         Name(UOM4, 2)
51         Name(UOM5, 2)
52         Name(UOM6, 6)
53         Name(UOM7, 2)
54         Name(UOM8, 6)
55         Name(UOM9, 6)
56
57         /* Some global data */
58         Name(OSTP, 3)           /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
59         Name(OSV, Ones) /* Assume nothing */
60         Name(PMOD, One) /* Assume APIC */
61
62         /*
63          * Processor Object
64          *
65          */
66         Scope (\_PR) {          /* define processor scope */
67                 Processor(
68                         P000,           /* name space name */
69                         0,              /* Unique number for this processor */
70                         0x810,          /* PBLK system I/O address !hardcoded! */
71                         0x06            /* PBLKLEN for boot processor */
72                         ) {
73                 }
74
75                 Processor(
76                         P001,           /* name space name */
77                         1,              /* Unique number for this processor */
78                         0x0810,         /* PBLK system I/O address !hardcoded! */
79                         0x06            /* PBLKLEN for boot processor */
80                         ) {
81                 }
82                 Processor(
83                         P002,           /* name space name */
84                         2,              /* Unique number for this processor */
85                         0x0810,         /* PBLK system I/O address !hardcoded! */
86                         0x06            /* PBLKLEN for boot processor */
87                         ) {
88                 }
89                 Processor(
90                         P003,           /* name space name */
91                         3,              /* Unique number for this processor */
92                         0x0810,         /* PBLK system I/O address !hardcoded! */
93                         0x06            /* PBLKLEN for boot processor */
94                         ) {
95                 }
96                 Processor(
97                         P004,           /* name space name */
98                         4,              /* Unique number for this processor */
99                         0x0810,         /* PBLK system I/O address !hardcoded! */
100                         0x06            /* PBLKLEN for boot processor */
101                         ) {
102                 }
103                 Processor(
104                         P005,           /* name space name */
105                         5,              /* Unique number for this processor */
106                         0x0810,         /* PBLK system I/O address !hardcoded! */
107                         0x06            /* PBLKLEN for boot processor */
108                         ) {
109                 }
110                 Processor(
111                         P006,           /* name space name */
112                         6,              /* Unique number for this processor */
113                         0x0810,         /* PBLK system I/O address !hardcoded! */
114                         0x06            /* PBLKLEN for boot processor */
115                         ) {
116                 }
117                 Processor(
118                         P007,           /* name space name */
119                         7,              /* Unique number for this processor */
120                         0x0810,         /* PBLK system I/O address !hardcoded! */
121                         0x06            /* PBLKLEN for boot processor */
122                         ) {
123                 }
124         } /* End _PR scope */
125
126         /* PIC IRQ mapping registers, C00h-C01h. */
127         OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
128                 Field(PRQM, ByteAcc, NoLock, Preserve) {
129                 PRQI, 0x00000008,
130                 PRQD, 0x00000008,  /* Offset: 1h */
131         }
132         IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
133                 PIRA, 0x00000008,       /* Index 0 */
134                 PIRB, 0x00000008,       /* Index 1 */
135                 PIRC, 0x00000008,       /* Index 2 */
136                 PIRD, 0x00000008,       /* Index 3 */
137                 PIRE, 0x00000008,       /* Index 4 */
138                 PIRF, 0x00000008,       /* Index 5 */
139                 PIRG, 0x00000008,       /* Index 6 */
140                 PIRH, 0x00000008,       /* Index 7 */
141         }
142
143         /* PCI Error control register */
144         OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
145                 Field(PERC, ByteAcc, NoLock, Preserve) {
146                 SENS, 0x00000001,
147                 PENS, 0x00000001,
148                 SENE, 0x00000001,
149                 PENE, 0x00000001,
150         }
151
152         /* Client Management index/data registers */
153         OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
154                 Field(CMT, ByteAcc, NoLock, Preserve) {
155                 CMTI,      8,
156                 /* Client Management Data register */
157                 G64E,   1,
158                 G64O,      1,
159                 G32O,      2,
160                 ,       2,
161                 GPSL,     2,
162         }
163
164         /* GPM Port register */
165         OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
166                 Field(GPT, ByteAcc, NoLock, Preserve) {
167                 GPB0,1,
168                 GPB1,1,
169                 GPB2,1,
170                 GPB3,1,
171                 GPB4,1,
172                 GPB5,1,
173                 GPB6,1,
174                 GPB7,1,
175         }
176
177         /* Flash ROM program enable register */
178         OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
179                 Field(FRE, ByteAcc, NoLock, Preserve) {
180                 ,     0x00000006,
181                 FLRE, 0x00000001,
182         }
183
184         /* PM2 index/data registers */
185         OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
186                 Field(PM2R, ByteAcc, NoLock, Preserve) {
187                 PM2I, 0x00000008,
188                 PM2D, 0x00000008,
189         }
190
191         /* Power Management I/O registers. */
192         OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
193                 Field(PIOR, ByteAcc, NoLock, Preserve) {
194                 PIOI, 0x00000008,
195                 PIOD, 0x00000008,
196         }
197         IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
198                 Offset(0xEE),
199                 UPWS, 3,
200         }
201
202         /* PM1 Event Block
203         * First word is PM1_Status, Second word is PM1_Enable
204         */
205         Scope(\_SB) {
206                 /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
207                 OperationRegion(PCFG, SystemMemory, PCBA, PCLN)
208                         Field(PCFG, ByteAcc, NoLock, Preserve) {
209                         /* Byte offsets are computed using the following technique:
210                          * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
211                          * The 8 comes from 8 functions per device, and 4096 bytes per function config space
212                         */
213                         Offset(0x00088024),     /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
214                         STB5, 32,
215                         Offset(0x00098042),     /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
216                         PT0D, 1,
217                         PT1D, 1,
218                         PT2D, 1,
219                         PT3D, 1,
220                         PT4D, 1,
221                         PT5D, 1,
222                         PT6D, 1,
223                         PT7D, 1,
224                         PT8D, 1,
225                         PT9D, 1,
226                         Offset(0x000A0004),     /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
227                         SBIE, 1,
228                         SBME, 1,
229                         Offset(0x000A0008),     /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
230                         SBRI, 8,
231                         Offset(0x000A0014),     /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
232                         SBB1, 32,
233                         Offset(0x000A0078),     /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
234                         ,14,
235                         P92E, 1,                /* Port92 decode enable */
236                 }
237
238                 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
239                         Field(SB5, AnyAcc, NoLock, Preserve){
240                         /* Port 0 */
241                         Offset(0x120),          /* Port 0 Task file status */
242                         P0ER, 1,
243                         , 2,
244                         P0DQ, 1,
245                         , 3,
246                         P0BY, 1,
247                         Offset(0x128),          /* Port 0 Serial ATA status */
248                         P0DD, 4,
249                         , 4,
250                         P0IS, 4,
251                         Offset(0x12C),          /* Port 0 Serial ATA control */
252                         P0DI, 4,
253                         Offset(0x130),          /* Port 0 Serial ATA error */
254                         , 16,
255                         P0PR, 1,
256
257                         /* Port 1 */
258                         offset(0x1A0),          /* Port 1 Task file status */
259                         P1ER, 1,
260                         , 2,
261                         P1DQ, 1,
262                         , 3,
263                         P1BY, 1,
264                         Offset(0x1A8),          /* Port 1 Serial ATA status */
265                         P1DD, 4,
266                         , 4,
267                         P1IS, 4,
268                         Offset(0x1AC),          /* Port 1 Serial ATA control */
269                         P1DI, 4,
270                         Offset(0x1B0),          /* Port 1 Serial ATA error */
271                         , 16,
272                         P1PR, 1,
273
274                         /* Port 2 */
275                         Offset(0x220),          /* Port 2 Task file status */
276                         P2ER, 1,
277                         , 2,
278                         P2DQ, 1,
279                         , 3,
280                         P2BY, 1,
281                         Offset(0x228),          /* Port 2 Serial ATA status */
282                         P2DD, 4,
283                         , 4,
284                         P2IS, 4,
285                         Offset(0x22C),          /* Port 2 Serial ATA control */
286                         P2DI, 4,
287                         Offset(0x230),          /* Port 2 Serial ATA error */
288                         , 16,
289                         P2PR, 1,
290
291                         /* Port 3 */
292                         Offset(0x2A0),          /* Port 3 Task file status */
293                         P3ER, 1,
294                         , 2,
295                         P3DQ, 1,
296                         , 3,
297                         P3BY, 1,
298                         Offset(0x2A8),          /* Port 3 Serial ATA status */
299                         P3DD, 4,
300                         , 4,
301                         P3IS, 4,
302                         Offset(0x2AC),          /* Port 3 Serial ATA control */
303                         P3DI, 4,
304                         Offset(0x2B0),          /* Port 3 Serial ATA error */
305                         , 16,
306                         P3PR, 1,
307                 }
308         }
309
310         #include "acpi/routing.asl"
311
312         Scope(\_SB) {
313
314                 Method(CkOT, 0){
315
316                         if(LNotEqual(OSTP, Ones)) {Return(OSTP)}        /* OS version was already detected */
317
318                         if(CondRefOf(\_OSI,Local1))
319                         {
320                                 Store(1, OSTP)                /* Assume some form of XP */
321                                 if (\_OSI("Windows 2006"))      /* Vista */
322                                 {
323                                         Store(2, OSTP)
324                                 }
325                         } else {
326                                 If(WCMP(\_OS,"Linux")) {
327                                         Store(3, OSTP)            /* Linux */
328                                 } Else {
329                                         Store(4, OSTP)            /* Gotta be WinCE */
330                                 }
331                         }
332                         Return(OSTP)
333                 }
334
335                 Method(_PIC, 0x01, NotSerialized)
336                 {
337                         If (Arg0)
338                         {
339                                 \_SB.CIRQ()
340                         }
341                         Store(Arg0, PMOD)
342                 }
343                 Method(CIRQ, 0x00, NotSerialized){
344                         //Store(0, PIRA)
345                         //Store(0, PIRB)
346                         //Store(0, PIRC)
347                         //Store(0, PIRD)
348                         //Store(0, PIRE)
349                         //Store(0, PIRF)
350                         //Store(0, PIRG)
351                         //Store(0, PIRH)
352                 }
353
354                 Name(IRQB, ResourceTemplate(){
355                         IRQ(Level,ActiveLow,Shared){15}
356                 })
357
358                 Name(IRQP, ResourceTemplate(){
359                         IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
360                 })
361
362                 Name(PITF, ResourceTemplate(){
363                         IRQ(Level,ActiveLow,Exclusive){9}
364                 })
365
366                 Device(INTA) {
367                         Name(_HID, EISAID("PNP0C0F"))
368                         Name(_UID, 1)
369
370                         Method(_STA, 0) {
371                                 if (PIRA) {
372                                         Return(0x0B) /* sata is invisible */
373                                 } else {
374                                         Return(0x09) /* sata is disabled */
375                                 }
376                         } /* End Method(_SB.INTA._STA) */
377
378                         Method(_DIS ,0) {
379                                 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
380                                 //Store(0x1F, PIRA)
381                         } /* End Method(_SB.INTA._DIS) */
382
383                         Method(_PRS ,0) {
384                                 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
385                                 Return(IRQP)
386                         } /* Method(_SB.INTA._PRS) */
387
388                         Method(_CRS ,0) {
389                                 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
390                                 CreateWordField(IRQB, 0x1, IRQN)
391                                 ShiftLeft(1, PIRA, IRQN)
392                                 Return(IRQB)
393                         } /* Method(_SB.INTA._CRS) */
394
395                         Method(_SRS, 1) {
396                                 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
397                                 CreateWordField(ARG0, 1, IRQM)
398
399                                 /* Use lowest available IRQ */
400                                 FindSetRightBit(IRQM, Local0)
401                                 if (Local0) {
402                                         Decrement(Local0)
403                                 }
404                                 //Store(Local0, PIRA)
405                         } /* End Method(_SB.INTA._SRS) */
406                 } /* End Device(INTA) */
407
408                 Device(INTB) {
409                         Name(_HID, EISAID("PNP0C0F"))
410                         Name(_UID, 2)
411
412                         Method(_STA, 0) {
413                                 if (PIRB) {
414                                         Return(0x0B) /* sata is invisible */
415                                 } else {
416                                         Return(0x09) /* sata is disabled */
417                                 }
418                         } /* End Method(_SB.INTB._STA) */
419
420                         Method(_DIS ,0) {
421                                 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
422                                 //Store(0, PIRB)
423                         } /* End Method(_SB.INTB._DIS) */
424
425                         Method(_PRS ,0) {
426                                 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
427                                 Return(IRQP)
428                         } /* Method(_SB.INTB._PRS) */
429
430                         Method(_CRS ,0) {
431                                 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
432                                 CreateWordField(IRQB, 0x1, IRQN)
433                                 ShiftLeft(1, PIRB, IRQN)
434                                 Return(IRQB)
435                         } /* Method(_SB.INTB._CRS) */
436
437                         Method(_SRS, 1) {
438                                 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
439                                 CreateWordField(ARG0, 1, IRQM)
440
441                                 /* Use lowest available IRQ */
442                                 FindSetRightBit(IRQM, Local0)
443                                 if (Local0) {
444                                         Decrement(Local0)
445                                 }
446                                 Store(Local0, PIRB)
447                         } /* End Method(_SB.INTB._SRS) */
448                 } /* End Device(INTB)  */
449
450                 Device(INTC) {
451                         Name(_HID, EISAID("PNP0C0F"))
452                         Name(_UID, 3)
453
454                         Method(_STA, 0) {
455                                 if (PIRC) {
456                                         Return(0x0B) /* sata is invisible */
457                                 } else {
458                                         Return(0x09) /* sata is disabled */
459                                 }
460                         } /* End Method(_SB.INTC._STA) */
461
462                         Method(_DIS ,0) {
463                                 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
464                                 //Store(0, PIRC)
465                         } /* End Method(_SB.INTC._DIS) */
466
467                         Method(_PRS ,0) {
468                                 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
469                                 Return(IRQP)
470                         } /* Method(_SB.INTC._PRS) */
471
472                         Method(_CRS ,0) {
473                                 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
474                                 CreateWordField(IRQB, 0x1, IRQN)
475                                 ShiftLeft(1, PIRC, IRQN)
476                                 Return(IRQB)
477                         } /* Method(_SB.INTC._CRS) */
478
479                         Method(_SRS, 1) {
480                                 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
481                                 CreateWordField(ARG0, 1, IRQM)
482
483                                 /* Use lowest available IRQ */
484                                 FindSetRightBit(IRQM, Local0)
485                                 if (Local0) {
486                                         Decrement(Local0)
487                                 }
488                                 Store(Local0, PIRC)
489                         } /* End Method(_SB.INTC._SRS) */
490                 } /* End Device(INTC)  */
491
492                 Device(INTD) {
493                         Name(_HID, EISAID("PNP0C0F"))
494                         Name(_UID, 4)
495
496                         Method(_STA, 0) {
497                                 if (PIRD) {
498                                         Return(0x0B) /* sata is invisible */
499                                 } else {
500                                         Return(0x09) /* sata is disabled */
501                                 }
502                         } /* End Method(_SB.INTD._STA) */
503
504                         Method(_DIS ,0) {
505                                 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
506                                 //Store(0, PIRD)
507                         } /* End Method(_SB.INTD._DIS) */
508
509                         Method(_PRS ,0) {
510                                 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
511                                 Return(IRQP)
512                         } /* Method(_SB.INTD._PRS) */
513
514                         Method(_CRS ,0) {
515                                 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
516                                 CreateWordField(IRQB, 0x1, IRQN)
517                                 ShiftLeft(1, PIRD, IRQN)
518                                 Return(IRQB)
519                         } /* Method(_SB.INTD._CRS) */
520
521                         Method(_SRS, 1) {
522                                 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
523                                 CreateWordField(ARG0, 1, IRQM)
524
525                                 /* Use lowest available IRQ */
526                                 FindSetRightBit(IRQM, Local0)
527                                 if (Local0) {
528                                         Decrement(Local0)
529                                 }
530                                 Store(Local0, PIRD)
531                         } /* End Method(_SB.INTD._SRS) */
532                 } /* End Device(INTD)  */
533
534                 Device(INTE) {
535                         Name(_HID, EISAID("PNP0C0F"))
536                         Name(_UID, 5)
537
538                         Method(_STA, 0) {
539                                 if (PIRE) {
540                                         Return(0x0B) /* sata is invisible */
541                                 } else {
542                                         Return(0x09) /* sata is disabled */
543                                 }
544                         } /* End Method(_SB.INTE._STA) */
545
546                         Method(_DIS ,0) {
547                                 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
548                                 //Store(0, PIRE)
549                         } /* End Method(_SB.INTE._DIS) */
550
551                         Method(_PRS ,0) {
552                                 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
553                                 Return(IRQP)
554                         } /* Method(_SB.INTE._PRS) */
555
556                         Method(_CRS ,0) {
557                                 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
558                                 CreateWordField(IRQB, 0x1, IRQN)
559                                 ShiftLeft(1, PIRE, IRQN)
560                                 Return(IRQB)
561                         } /* Method(_SB.INTE._CRS) */
562
563                         Method(_SRS, 1) {
564                                 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
565                                 CreateWordField(ARG0, 1, IRQM)
566
567                                 /* Use lowest available IRQ */
568                                 FindSetRightBit(IRQM, Local0)
569                                 if (Local0) {
570                                         Decrement(Local0)
571                                 }
572                                 Store(Local0, PIRE)
573                         } /* End Method(_SB.INTE._SRS) */
574                 } /* End Device(INTE)  */
575
576                 Device(INTF) {
577                         Name(_HID, EISAID("PNP0C0F"))
578                         Name(_UID, 6)
579
580                         Method(_STA, 0) {
581                                 if (PIRF) {
582                                         Return(0x0B) /* sata is invisible */
583                                 } else {
584                                         Return(0x09) /* sata is disabled */
585                                 }
586                         } /* End Method(_SB.INTF._STA) */
587
588                         Method(_DIS ,0) {
589                                 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
590                                 //Store(0, PIRF)
591                         } /* End Method(_SB.INTF._DIS) */
592
593                         Method(_PRS ,0) {
594                                 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
595                                 Return(PITF)
596                         } /* Method(_SB.INTF._PRS) */
597
598                         Method(_CRS ,0) {
599                                 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
600                                 CreateWordField(IRQB, 0x1, IRQN)
601                                 ShiftLeft(1, PIRF, IRQN)
602                                 Return(IRQB)
603                         } /* Method(_SB.INTF._CRS) */
604
605                         Method(_SRS, 1) {
606                                 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
607                                 CreateWordField(ARG0, 1, IRQM)
608
609                                 /* Use lowest available IRQ */
610                                 FindSetRightBit(IRQM, Local0)
611                                 if (Local0) {
612                                         Decrement(Local0)
613                                 }
614                                 Store(Local0, PIRF)
615                         } /*  End Method(_SB.INTF._SRS) */
616                 } /* End Device(INTF)  */
617
618                 Device(INTG) {
619                         Name(_HID, EISAID("PNP0C0F"))
620                         Name(_UID, 7)
621
622                         Method(_STA, 0) {
623                                 if (PIRG) {
624                                         Return(0x0B) /* sata is invisible */
625                                 } else {
626                                         Return(0x09) /* sata is disabled */
627                                 }
628                         } /* End Method(_SB.INTG._STA)  */
629
630                         Method(_DIS ,0) {
631                                 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
632                                 //Store(0, PIRG)
633                         } /* End Method(_SB.INTG._DIS)  */
634
635                         Method(_PRS ,0) {
636                                 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
637                                 Return(IRQP)
638                         } /* Method(_SB.INTG._CRS)  */
639
640                         Method(_CRS ,0) {
641                                 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
642                                 CreateWordField(IRQB, 0x1, IRQN)
643                                 ShiftLeft(1, PIRG, IRQN)
644                                 Return(IRQB)
645                         } /* Method(_SB.INTG._CRS)  */
646
647                         Method(_SRS, 1) {
648                                 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
649                                 CreateWordField(ARG0, 1, IRQM)
650
651                                 /* Use lowest available IRQ */
652                                 FindSetRightBit(IRQM, Local0)
653                                 if (Local0) {
654                                         Decrement(Local0)
655                                 }
656                                 Store(Local0, PIRG)
657                         } /* End Method(_SB.INTG._SRS)  */
658                 } /* End Device(INTG)  */
659
660                 Device(INTH) {
661                         Name(_HID, EISAID("PNP0C0F"))
662                         Name(_UID, 8)
663
664                         Method(_STA, 0) {
665                                 if (PIRH) {
666                                         Return(0x0B) /* sata is invisible */
667                                 } else {
668                                         Return(0x09) /* sata is disabled */
669                                 }
670                         } /* End Method(_SB.INTH._STA)  */
671
672                         Method(_DIS ,0) {
673                                 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
674                                 //Store(0, PIRH)
675                         } /* End Method(_SB.INTH._DIS)  */
676
677                         Method(_PRS ,0) {
678                                 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
679                                 Return(IRQP)
680                         } /* Method(_SB.INTH._CRS)  */
681
682                         Method(_CRS ,0) {
683                                 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
684                                 CreateWordField(IRQB, 0x1, IRQN)
685                                 ShiftLeft(1, PIRH, IRQN)
686                                 Return(IRQB)
687                         } /* Method(_SB.INTH._CRS)  */
688
689                         Method(_SRS, 1) {
690                                 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
691                                 CreateWordField(ARG0, 1, IRQM)
692
693                                 /* Use lowest available IRQ */
694                                 FindSetRightBit(IRQM, Local0)
695                                 if (Local0) {
696                                         Decrement(Local0)
697                                 }
698                                 //Store(Local0, PIRH)
699                         } /* End Method(_SB.INTH._SRS)  */
700                 } /* End Device(INTH)   */
701
702         }   /* End Scope(_SB)  */
703
704         /* Supported sleep states: */
705         Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )        /* (S0) - working state */
706
707         If (LAnd(SSFG, 0x01)) {
708                 Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )        /* (S1) - sleeping w/CPU context */
709         }
710         If (LAnd(SSFG, 0x02)) {
711                 Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} )        /* (S2) - "light" Suspend to RAM */
712         }
713         If (LAnd(SSFG, 0x04)) {
714                 Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} )        /* (S3) - Suspend to RAM */
715         }
716         If (LAnd(SSFG, 0x08)) {
717                 Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} )        /* (S4) - Suspend to Disk */
718         }
719
720         Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} )        /* (S5) - Soft Off */
721
722         Name(\_SB.CSPS ,0)                              /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
723         Name(CSMS, 0)                   /* Current System State */
724
725         /* Wake status package */
726         Name(WKST,Package(){Zero, Zero})
727
728         /*
729         * \_PTS - Prepare to Sleep method
730         *
731         *       Entry:
732         *               Arg0=The value of the sleeping state S1=1, S2=2, etc
733         *
734         * Exit:
735         *               -none-
736         *
737         * The _PTS control method is executed at the beginning of the sleep process
738         * for S1-S5. The sleeping value is passed to the _PTS control method.   This
739         * control method may be executed a relatively long time before entering the
740         * sleep state and the OS may abort      the operation without notification to
741         * the ACPI driver.  This method cannot modify the configuration or power
742         * state of any device in the system.
743         */
744         Method(_PTS, 1) {
745                 /* DBGO("\\_PTS\n") */
746                 /* DBGO("From S0 to S") */
747                 /* DBGO(Arg0) */
748                 /* DBGO("\n") */
749
750                 /* Don't allow PCIRST# to reset USB */
751                 //if (LEqual(Arg0,3)){
752                 //      Store(0,URRE)
753                 //}
754
755                 /* Clear sleep SMI status flag and enable sleep SMI trap. */
756                 /*Store(One, CSSM)
757                 Store(One, SSEN)*/
758
759                 /* On older chips, clear PciExpWakeDisEn */
760                 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
761                 *       Store(0,\_SB.PWDE)
762                 *}
763                 */
764
765                 /* Clear wake status structure. */
766                 Store(0, Index(WKST,0))
767                 Store(0, Index(WKST,1))
768                 Store(7, UPWS)
769         } /* End Method(\_PTS) */
770
771         /*
772         *  The following method results in a "not a valid reserved NameSeg"
773         *  warning so I have commented it out for the duration.  It isn't
774         *  used, so it could be removed.
775         *
776         *
777         *       \_GTS OEM Going To Sleep method
778         *
779         *       Entry:
780         *               Arg0=The value of the sleeping state S1=1, S2=2
781         *
782         *       Exit:
783         *               -none-
784         *
785         *  Method(\_GTS, 1) {
786         *  DBGO("\\_GTS\n")
787         *  DBGO("From S0 to S")
788         *  DBGO(Arg0)
789         *  DBGO("\n")
790         *  }
791         */
792
793         /*
794         *       \_BFS OEM Back From Sleep method
795         *
796         *       Entry:
797         *               Arg0=The value of the sleeping state S1=1, S2=2
798         *
799         *       Exit:
800         *               -none-
801         */
802         Method(\_BFS, 1) {
803                 /* DBGO("\\_BFS\n") */
804                 /* DBGO("From S") */
805                 /* DBGO(Arg0) */
806                 /* DBGO(" to S0\n") */
807         }
808
809         /*
810         *  \_WAK System Wake method
811         *
812         *       Entry:
813         *               Arg0=The value of the sleeping state S1=1, S2=2
814         *
815         *       Exit:
816         *               Return package of 2 DWords
817         *               Dword 1 - Status
818         *                       0x00000000      wake succeeded
819         *                       0x00000001      Wake was signaled but failed due to lack of power
820         *                       0x00000002      Wake was signaled but failed due to thermal condition
821         *               Dword 2 - Power Supply state
822         *                       if non-zero the effective S-state the power supply entered
823         */
824         Method(\_WAK, 1) {
825                 /* DBGO("\\_WAK\n") */
826                 /* DBGO("From S") */
827                 /* DBGO(Arg0) */
828                 /* DBGO(" to S0\n") */
829
830                 /* Re-enable HPET */
831                 //Store(1,HPDE)
832
833                 /* Restore PCIRST# so it resets USB */
834                 //if (LEqual(Arg0,3)){
835                 //      Store(1,URRE)
836                 //}
837
838                 /* Arbitrarily clear PciExpWakeStatus */
839                 //Store(PWST, PWST)
840
841                 /* if(DeRefOf(Index(WKST,0))) {
842                 *       Store(0, Index(WKST,1))
843                 * } else {
844                 *       Store(Arg0, Index(WKST,1))
845                 * }
846                 */
847                 Return(WKST)
848         } /* End Method(\_WAK) */
849
850         Scope(\_GPE) {  /* Start Scope GPE */
851                 /*  General event 0  */
852                 /* Method(_L00) {
853                 *       DBGO("\\_GPE\\_L00\n")
854                 * }
855                 */
856
857                 /*  General event 1  */
858                 /* Method(_L01) {
859                 *       DBGO("\\_GPE\\_L00\n")
860                 * }
861                 */
862
863                 /*  General event 2  */
864                 /* Method(_L02) {
865                 *       DBGO("\\_GPE\\_L00\n")
866                 * }
867                 */
868
869                 /*  General event 3  */
870                 Method(_L03) {
871                         /* DBGO("\\_GPE\\_L00\n") */
872                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
873                 }
874
875                 /*  General event 4  */
876                 /* Method(_L04) {
877                 *       DBGO("\\_GPE\\_L00\n")
878                 * }
879                 */
880
881                 /*  General event 5  */
882                 /* Method(_L05) {
883                 *       DBGO("\\_GPE\\_L00\n")
884                 * }
885                 */
886
887                 /*  General event 6 - Used for GPM6, moved to USB.asl */
888                 /* Method(_L06) {
889                 *       DBGO("\\_GPE\\_L00\n")
890                 * }
891                 */
892
893                 /*  General event 7 - Used for GPM7, moved to USB.asl */
894                 /* Method(_L07) {
895                 *       DBGO("\\_GPE\\_L07\n")
896                 * }
897                 */
898
899                 /*  Legacy PM event  */
900                 Method(_L08) {
901                         /* DBGO("\\_GPE\\_L08\n") */
902                 }
903
904                 /*  Temp warning (TWarn) event  */
905                 Method(_L09) {
906                         /* DBGO("\\_GPE\\_L09\n") */
907                         /* Notify (\_TZ.TZ00, 0x80) */
908                 }
909
910                 /*  Reserved  */
911                 /* Method(_L0A) {
912                 *       DBGO("\\_GPE\\_L0A\n")
913                 * }
914                 */
915
916                 /*  USB controller PME#  */
917                 Method(_L0B) {
918                         /* DBGO("\\_GPE\\_L0B\n") */
919                         Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
920                         Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
921                         Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
922                         Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
923                         Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
924                         Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
925                         Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
926                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
927                 }
928
929                 /*  AC97 controller PME#  */
930                 /* Method(_L0C) {
931                 *       DBGO("\\_GPE\\_L0C\n")
932                 * }
933                 */
934
935                 /*  OtherTherm PME#  */
936                 /* Method(_L0D) {
937                 *       DBGO("\\_GPE\\_L0D\n")
938                 * }
939                 */
940
941                 /*  GPM9 SCI event - Moved to USB.asl */
942                 /* Method(_L0E) {
943                 *       DBGO("\\_GPE\\_L0E\n")
944                 * }
945                 */
946
947                 /*  PCIe HotPlug event  */
948                 /* Method(_L0F) {
949                 *       DBGO("\\_GPE\\_L0F\n")
950                 * }
951                 */
952
953                 /*  ExtEvent0 SCI event  */
954                 Method(_L10) {
955                         /* DBGO("\\_GPE\\_L10\n") */
956                 }
957
958                 /*  ExtEvent1 SCI event  */
959                 Method(_L11) {
960                         /* DBGO("\\_GPE\\_L11\n") */
961                 }
962
963                 /*  PCIe PME# event  */
964                 /* Method(_L12) {
965                 *       DBGO("\\_GPE\\_L12\n")
966                 * }
967                 */
968
969                 /*  GPM0 SCI event - Moved to USB.asl */
970                 /* Method(_L13) {
971                 *       DBGO("\\_GPE\\_L13\n")
972                 * }
973                 */
974
975                 /*  GPM1 SCI event - Moved to USB.asl */
976                 /* Method(_L14) {
977                 *       DBGO("\\_GPE\\_L14\n")
978                 * }
979                 */
980
981                 /*  GPM2 SCI event - Moved to USB.asl */
982                 /* Method(_L15) {
983                 *       DBGO("\\_GPE\\_L15\n")
984                 * }
985                 */
986
987                 /*  GPM3 SCI event - Moved to USB.asl */
988                 /* Method(_L16) {
989                 *       DBGO("\\_GPE\\_L16\n")
990                 * }
991                 */
992
993                 /*  GPM8 SCI event - Moved to USB.asl */
994                 /* Method(_L17) {
995                 *       DBGO("\\_GPE\\_L17\n")
996                 * }
997                 */
998
999                 /*  GPIO0 or GEvent8 event  */
1000                 Method(_L18) {
1001                         /* DBGO("\\_GPE\\_L18\n") */
1002                         Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
1003                         Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
1004                         Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
1005                         Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
1006                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1007                 }
1008
1009                 /*  GPM4 SCI event - Moved to USB.asl */
1010                 /* Method(_L19) {
1011                 *       DBGO("\\_GPE\\_L19\n")
1012                 * }
1013                 */
1014
1015                 /*  GPM5 SCI event - Moved to USB.asl */
1016                 /* Method(_L1A) {
1017                 *       DBGO("\\_GPE\\_L1A\n")
1018                 * }
1019                 */
1020
1021                 /*  Azalia SCI event  */
1022                 Method(_L1B) {
1023                         /* DBGO("\\_GPE\\_L1B\n") */
1024                         Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
1025                         Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1026                 }
1027
1028                 /*  GPM6 SCI event - Reassigned to _L06 */
1029                 /* Method(_L1C) {
1030                 *       DBGO("\\_GPE\\_L1C\n")
1031                 * }
1032                 */
1033
1034                 /*  GPM7 SCI event - Reassigned to _L07 */
1035                 /* Method(_L1D) {
1036                 *       DBGO("\\_GPE\\_L1D\n")
1037                 * }
1038                 */
1039
1040                 /*  GPIO2 or GPIO66 SCI event  */
1041                 /* Method(_L1E) {
1042                 *       DBGO("\\_GPE\\_L1E\n")
1043                 * }
1044                 */
1045
1046                 /*  SATA SCI event - Moved to sata.asl */
1047                 /* Method(_L1F) {
1048                 *        DBGO("\\_GPE\\_L1F\n")
1049                 * }
1050                 */
1051
1052         }       /* End Scope GPE */
1053
1054         //#include "acpi/usb.asl"
1055
1056         /* System Bus */
1057         Scope(\_SB) { /* Start \_SB scope */
1058                 #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
1059
1060                 /*  _SB.PCI0 */
1061                 /* Note: Only need HID on Primary Bus */
1062                 Device(PCI0) {
1063                         External (TOM1)
1064                         External (TOM2)
1065                         Name(_HID, EISAID("PNP0A03"))
1066                         Name(_ADR, 0x00180000)  /* Dev# = BSP Dev#, Func# = 0 */
1067                         Method(_BBN, 0) { /* Bus number = 0 */
1068                                 Return(0)
1069                         }
1070                         Method(_STA, 0) {
1071                                 /* DBGO("\\_SB\\PCI0\\_STA\n") */
1072                                 Return(0x0B)     /* Status is visible */
1073                         }
1074
1075                         Method(_PRT,0) {
1076                                 If(PMOD){ Return(APR0) }   /* APIC mode */
1077                                 Return (PR0)                  /* PIC Mode */
1078                         } /* end _PRT */
1079
1080                         /* Describe the Northbridge devices Dev0 ,Func0*/
1081                         Device(AMRT) {
1082                                 Name(_ADR, 0x00000000)
1083                         } /* end AMRT */
1084
1085 #if 0 //not used in Parmer
1086                         /* Dev3 is also an external GFX bridge */
1087                         Device(PBR3) {
1088                                 Name(_ADR, 0x00030000)
1089                                 Name(_PRW, Package() {0x18, 4})
1090                                 Method(_PRT,0) {
1091                                         If(PMOD){ Return(APS3) }   /* APIC mode */
1092                                         Return (PS3)                  /* PIC Mode */
1093                                 } /* end _PRT */
1094                         } /* end PBR3 */
1095 #endif
1096
1097                         Device(PBR4) {
1098                                 Name(_ADR, 0x00040000)
1099                                 Name(_PRW, Package() {0x18, 4})
1100                                 Method(_PRT,0) {
1101                                         If(PMOD){ Return(APS4) }   /* APIC mode */
1102                                         Return (PS4)                  /* PIC Mode */
1103                                 } /* end _PRT */
1104                         } /* end PBR4 */
1105
1106                         Device(PBR5) {
1107                                 Name(_ADR, 0x00050000)
1108                                 Name(_PRW, Package() {0x18, 4})
1109                                 Method(_PRT,0) {
1110                                         If(PMOD){ Return(APS5) }   /* APIC mode */
1111                                         Return (PS5)                  /* PIC Mode */
1112                                 } /* end _PRT */
1113                         } /* end PBR5 */
1114
1115                         Device(PBR6) {
1116                                 Name(_ADR, 0x00060000)
1117                                 Name(_PRW, Package() {0x18, 4})
1118                                 Method(_PRT,0) {
1119                                         If(PMOD){ Return(APS6) }   /* APIC mode */
1120                                         Return (PS6)                  /* PIC Mode */
1121                                 } /* end _PRT */
1122                         } /* end PBR6 */
1123
1124                         /* The onboard EtherNet chip */
1125                         Device(PBR7) {
1126                                 Name(_ADR, 0x00070000)
1127                                 Name(_PRW, Package() {0x18, 4})
1128                                 Method(_PRT,0) {
1129                                         If(PMOD){ Return(APS7) }   /* APIC mode */
1130                                         Return (PS7)                  /* PIC Mode */
1131                                 } /* end _PRT */
1132                         } /* end PBR7 */
1133
1134                         /* PCI slot 1, 2, 3 */
1135                         Device(PIBR) {
1136                                 Name(_ADR, 0x00140004)
1137                                 Name(_PRW, Package() {0x18, 4})
1138
1139                                 Method(_PRT, 0) {
1140                                         Return (PCIB)
1141                                 }
1142                         }
1143
1144                         /* Describe the Southbridge devices */
1145                         Device(STCR) {
1146                                 Name(_ADR, 0x00110000)
1147                                 //#include "acpi/sata.asl"
1148                         } /* end STCR */
1149
1150                         Device(UOH1) {
1151                                 Name(_ADR, 0x00120000)
1152                                 Name(_PRW, Package() {0x0B, 3})
1153                         } /* end UOH1 */
1154
1155                         Device(UOH2) {
1156                                 Name(_ADR, 0x00120002)
1157                                 Name(_PRW, Package() {0x0B, 3})
1158                         } /* end UOH2 */
1159
1160                         Device(UOH3) {
1161                                 Name(_ADR, 0x00130000)
1162                                 Name(_PRW, Package() {0x0B, 3})
1163                         } /* end UOH3 */
1164
1165                         Device(UOH4) {
1166                                 Name(_ADR, 0x00130002)
1167                                 Name(_PRW, Package() {0x0B, 3})
1168                         } /* end UOH4 */
1169
1170                         Device(UOH5) {
1171                                 Name(_ADR, 0x00160000)
1172                                 Name(_PRW, Package() {0x0B, 3})
1173                         } /* end UOH5 */
1174
1175                         Device(UOH6) {
1176                                 Name(_ADR, 0x00160002)
1177                                 Name(_PRW, Package() {0x0B, 3})
1178                         } /* end UOH5 */
1179
1180                         Device(UEH1) {
1181                                 Name(_ADR, 0x00140005)
1182                                 Name(_PRW, Package() {0x0B, 3})
1183                         } /* end UEH1 */
1184
1185                         Device(XHC0) {
1186                                 Name(_ADR, 0x00100000)
1187                                 Name(_PRW, Package() {0x0B, 4})
1188                         } /* end XHC0 */
1189                         Device(XHC1) {
1190                                 Name(_ADR, 0x00100001)
1191                                 Name(_PRW, Package() {0x0B, 4})
1192                         } /* end XHC1 */
1193
1194                         Device(SBUS) {
1195                                 Name(_ADR, 0x00140000)
1196                         } /* end SBUS */
1197
1198                         /* Primary (and only) IDE channel */
1199                         Device(IDEC) {
1200                                 Name(_ADR, 0x00140001)
1201                                 //#include "acpi/ide.asl"
1202                         } /* end IDEC */
1203
1204                         Device(AZHD) {
1205                                 Name(_ADR, 0x00140002)
1206                                 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
1207                                         Field(AZPD, AnyAcc, NoLock, Preserve) {
1208                                         offset (0x42),
1209                                         NSDI, 1,
1210                                         NSDO, 1,
1211                                         NSEN, 1,
1212                                         offset (0x44),
1213                                         IPCR, 4,
1214                                         offset (0x54),
1215                                         PWST, 2,
1216                                         , 6,
1217                                         PMEB, 1,
1218                                         , 6,
1219                                         PMST, 1,
1220                                         offset (0x62),
1221                                         MMCR, 1,
1222                                         offset (0x64),
1223                                         MMLA, 32,
1224                                         offset (0x68),
1225                                         MMHA, 32,
1226                                         offset (0x6C),
1227                                         MMDT, 16,
1228                                 }
1229
1230                                 Method(_INI) {
1231                                         If(LEqual(OSTP,3)){   /* If we are running Linux */
1232                                                 Store(zero, NSEN)
1233                                                 Store(one, NSDO)
1234                                                 Store(one, NSDI)
1235                                         }
1236                                 }
1237                         } /* end AZHD */
1238
1239                         Device(LIBR) {
1240                                 Name(_ADR, 0x00140003)
1241                                 /* Method(_INI) {
1242                                 *       DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
1243                                 } */ /* End Method(_SB.SBRDG._INI) */
1244
1245                                 /* Real Time Clock Device */
1246                                 Device(RTC0) {
1247                                         Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */
1248                                         Name(_CRS, ResourceTemplate() {
1249                                                 IRQNoFlags(){8}
1250                                                 IO(Decode16,0x0070, 0x0070, 0, 2)
1251                                                 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
1252                                         })
1253                                 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
1254
1255                                 Device(TMR) {   /* Timer */
1256                                         Name(_HID,EISAID("PNP0100"))    /* System Timer */
1257                                         Name(_CRS, ResourceTemplate() {
1258                                                 IRQNoFlags(){0}
1259                                                 IO(Decode16, 0x0040, 0x0040, 0, 4)
1260                                                 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
1261                                         })
1262                                 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1263
1264                                 Device(SPKR) {  /* Speaker */
1265                                         Name(_HID,EISAID("PNP0800"))    /* AT style speaker */
1266                                         Name(_CRS, ResourceTemplate() {
1267                                                 IO(Decode16, 0x0061, 0x0061, 0, 1)
1268                                         })
1269                                 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1270
1271                                 Device(PIC) {
1272                                         Name(_HID,EISAID("PNP0000"))    /* AT Interrupt Controller */
1273                                         Name(_CRS, ResourceTemplate() {
1274                                                 IRQNoFlags(){2}
1275                                                 IO(Decode16,0x0020, 0x0020, 0, 2)
1276                                                 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1277                                                 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1278                                                 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1279                                         })
1280                                 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1281
1282                                 Device(MAD) { /* 8257 DMA */
1283                                         Name(_HID,EISAID("PNP0200"))    /* Hardware Device ID */
1284                                         Name(_CRS, ResourceTemplate() {
1285                                                 DMA(Compatibility,BusMaster,Transfer8){4}
1286                                                 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1287                                                 IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
1288                                                 IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
1289                                                 IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
1290                                                 IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
1291                                                 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1292                                         }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1293                                 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1294
1295                                 Device(COPR) {
1296                                         Name(_HID,EISAID("PNP0C04"))    /* Math Coprocessor */
1297                                         Name(_CRS, ResourceTemplate() {
1298                                                 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1299                                                 IRQNoFlags(){13}
1300                                         })
1301                                 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1302                         } /* end LIBR */
1303
1304                         Device(HPBR) {
1305                                 Name(_ADR, 0x00140004)
1306                         } /* end HostPciBr */
1307
1308                         Device(ACAD) {
1309                                 Name(_ADR, 0x00140005)
1310                         } /* end Ac97audio */
1311
1312                         Device(ACMD) {
1313                                 Name(_ADR, 0x00140006)
1314                         } /* end Ac97modem */
1315
1316                         Name(CRES, ResourceTemplate() {
1317                                 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1318
1319                                 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1320                                         0x0000,                 /* address granularity */
1321                                         0x0000,                 /* range minimum */
1322                                         0x0CF7,                 /* range maximum */
1323                                         0x0000,                 /* translation */
1324                                         0x0CF8                  /* length */
1325                                 )
1326                                 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1327                                         0x0000,                 /* address granularity */
1328                                         0x03B0,                 /* range minimum */
1329                                         0x03DF,                 /* range maximum */
1330                                         0x0000,                 /* translation */
1331                                         0x0030                  /* length */
1332                                 )
1333
1334                                 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1335                                         0x0000,                 /* address granularity */
1336                                         0x0D00,                 /* range minimum */
1337                                         0xFFFF,                 /* range maximum */
1338                                         0x0000,                 /* translation */
1339                                         0xF300                  /* length */
1340                                 )
1341
1342                                 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM)   /* VGA memory space */
1343                                 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)   /* Assume C0000-E0000 empty */
1344                                 /* memory space for PCI BARs below 4GB */
1345                                 Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
1346                         }) /* End Name(_SB.PCI0.CRES) */
1347
1348                         Method(_CRS, 0) {
1349                                 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1350                                 CreateDWordField(CRES, ^MMIO._BAS, MM1B)
1351                                 CreateDWordField(CRES, ^MMIO._LEN, MM1L)
1352                                 /*
1353                                  * Declare memory between TOM1 and 4GB as available
1354                                  * for PCI MMIO.
1355                                  * Use ShiftLeft to avoid 64bit constant (for XP).
1356                                  * This will work even if the OS does 32bit arithmetic, as
1357                                  * 32bit (0x00000000 - TOM1) will wrap and give the same
1358                                  * result as 64bit (0x100000000 - TOM1).
1359                                  */
1360                                 Store(TOM1, MM1B)
1361                                 ShiftLeft(0x10000000, 4, Local0)
1362                                 Subtract(Local0, TOM1, Local0)
1363                                 Store(Local0, MM1L)
1364
1365                                 Return(CRES) /* note to change the Name buffer */
1366                         } /* end of Method(_SB.PCI0._CRS) */
1367
1368                         /*
1369                         *
1370                         *               FIRST METHOD CALLED UPON BOOT
1371                         *
1372                         *  1. If debugging, print current OS and ACPI interpreter.
1373                         *  2. Get PCI Interrupt routing from ACPI VSM, this
1374                         *     value is based on user choice in BIOS setup.
1375                         */
1376                         Method(_INI, 0) {
1377                                 /* DBGO("\\_SB\\_INI\n") */
1378                                 /* DBGO("   DSDT.ASL code from ") */
1379                                 /* DBGO(__DATE__) */
1380                                 /* DBGO(" ") */
1381                                 /* DBGO(__TIME__) */
1382                                 /* DBGO("\n   Sleep states supported: ") */
1383                                 /* DBGO("\n") */
1384                                 /* DBGO("   \\_OS=") */
1385                                 /* DBGO(\_OS) */
1386                                 /* DBGO("\n   \\_REV=") */
1387                                 /* DBGO(\_REV) */
1388                                 /* DBGO("\n") */
1389
1390                                 /* Determine the OS we're running on */
1391                                 CkOT()
1392
1393                                 /* On older chips, clear PciExpWakeDisEn */
1394                                 /*if (LLessEqual(\SBRI, 0x13)) {
1395                                 *       Store(0,\PWDE)
1396                                 * }
1397                                 */
1398                                 /* TODO: It is unstable. */
1399                                 //#include "acpi/AmdImc.asl" /* Hudson IMC function */
1400                                 //ITZE() /* enable IMC Fan Control*/
1401                         } /* End Method(_SB._INI) */
1402                 } /* End Device(PCI0)  */
1403
1404                 Device(PWRB) {  /* Start Power button device */
1405                         Name(_HID, EISAID("PNP0C0C"))
1406                         Name(_UID, 0xAA)
1407                         Name(_PRW, Package () {3, 0x04})        /* wake from S1-S4 */
1408                         Name(_STA, 0x0B) /* sata is invisible */
1409                 }
1410         } /* End \_SB scope */
1411
1412         Scope(\_SI) {
1413                 Method(_SST, 1) {
1414                         /* DBGO("\\_SI\\_SST\n") */
1415                         /* DBGO("   New Indicator state: ") */
1416                         /* DBGO(Arg0) */
1417                         /* DBGO("\n") */
1418                 }
1419         } /* End Scope SI */
1420 }
1421 /* End of ASL file */