2 * This file is part of the coreboot project.
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 /* DefinitionBlock Statement */
22 "DSDT.AML", /* Output filename */
23 "DSDT", /* Signature */
24 0x02, /* DSDT Revision, needs to be 2 for 64bit */
26 "PARMER ", /* TABLE ID */
27 0x00010001 /* OEM Revision */
29 { /* Start of ASL file */
30 /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */
32 /* Data to be patched by the BIOS during POST */
33 /* FIXME the patching is not done yet! */
34 /* Memory related values */
35 Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
36 Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
37 Name(PBLN, 0x0) /* Length of BIOS area */
39 Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
40 Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
41 Name(HPBA, 0xFED00000) /* Base address of HPET table */
43 Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
45 /* USB overcurrent mapping pins. */
57 /* Some global data */
58 Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
59 Name(OSV, Ones) /* Assume nothing */
60 Name(PMOD, One) /* Assume APIC */
66 Scope (\_PR) { /* define processor scope */
68 P000, /* name space name */
69 0, /* Unique number for this processor */
70 0x810, /* PBLK system I/O address !hardcoded! */
71 0x06 /* PBLKLEN for boot processor */
76 P001, /* name space name */
77 1, /* Unique number for this processor */
78 0x0810, /* PBLK system I/O address !hardcoded! */
79 0x06 /* PBLKLEN for boot processor */
83 P002, /* name space name */
84 2, /* Unique number for this processor */
85 0x0810, /* PBLK system I/O address !hardcoded! */
86 0x06 /* PBLKLEN for boot processor */
90 P003, /* name space name */
91 3, /* Unique number for this processor */
92 0x0810, /* PBLK system I/O address !hardcoded! */
93 0x06 /* PBLKLEN for boot processor */
97 P004, /* name space name */
98 4, /* Unique number for this processor */
99 0x0810, /* PBLK system I/O address !hardcoded! */
100 0x06 /* PBLKLEN for boot processor */
104 P005, /* name space name */
105 5, /* Unique number for this processor */
106 0x0810, /* PBLK system I/O address !hardcoded! */
107 0x06 /* PBLKLEN for boot processor */
111 P006, /* name space name */
112 6, /* Unique number for this processor */
113 0x0810, /* PBLK system I/O address !hardcoded! */
114 0x06 /* PBLKLEN for boot processor */
118 P007, /* name space name */
119 7, /* Unique number for this processor */
120 0x0810, /* PBLK system I/O address !hardcoded! */
121 0x06 /* PBLKLEN for boot processor */
124 } /* End _PR scope */
126 /* PIC IRQ mapping registers, C00h-C01h. */
127 OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
128 Field(PRQM, ByteAcc, NoLock, Preserve) {
130 PRQD, 0x00000008, /* Offset: 1h */
132 IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
133 PIRA, 0x00000008, /* Index 0 */
134 PIRB, 0x00000008, /* Index 1 */
135 PIRC, 0x00000008, /* Index 2 */
136 PIRD, 0x00000008, /* Index 3 */
137 PIRE, 0x00000008, /* Index 4 */
138 PIRF, 0x00000008, /* Index 5 */
139 PIRG, 0x00000008, /* Index 6 */
140 PIRH, 0x00000008, /* Index 7 */
143 /* PCI Error control register */
144 OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
145 Field(PERC, ByteAcc, NoLock, Preserve) {
152 /* Client Management index/data registers */
153 OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
154 Field(CMT, ByteAcc, NoLock, Preserve) {
156 /* Client Management Data register */
164 /* GPM Port register */
165 OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
166 Field(GPT, ByteAcc, NoLock, Preserve) {
177 /* Flash ROM program enable register */
178 OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
179 Field(FRE, ByteAcc, NoLock, Preserve) {
184 /* PM2 index/data registers */
185 OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
186 Field(PM2R, ByteAcc, NoLock, Preserve) {
191 /* Power Management I/O registers. */
192 OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
193 Field(PIOR, ByteAcc, NoLock, Preserve) {
197 IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
203 * First word is PM1_Status, Second word is PM1_Enable
206 /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
207 OperationRegion(PCFG, SystemMemory, PCBA, PCLN)
208 Field(PCFG, ByteAcc, NoLock, Preserve) {
209 /* Byte offsets are computed using the following technique:
210 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
211 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
213 Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
215 Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
226 Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
229 Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
231 Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
233 Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
235 P92E, 1, /* Port92 decode enable */
238 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
239 Field(SB5, AnyAcc, NoLock, Preserve){
241 Offset(0x120), /* Port 0 Task file status */
247 Offset(0x128), /* Port 0 Serial ATA status */
251 Offset(0x12C), /* Port 0 Serial ATA control */
253 Offset(0x130), /* Port 0 Serial ATA error */
258 offset(0x1A0), /* Port 1 Task file status */
264 Offset(0x1A8), /* Port 1 Serial ATA status */
268 Offset(0x1AC), /* Port 1 Serial ATA control */
270 Offset(0x1B0), /* Port 1 Serial ATA error */
275 Offset(0x220), /* Port 2 Task file status */
281 Offset(0x228), /* Port 2 Serial ATA status */
285 Offset(0x22C), /* Port 2 Serial ATA control */
287 Offset(0x230), /* Port 2 Serial ATA error */
292 Offset(0x2A0), /* Port 3 Task file status */
298 Offset(0x2A8), /* Port 3 Serial ATA status */
302 Offset(0x2AC), /* Port 3 Serial ATA control */
304 Offset(0x2B0), /* Port 3 Serial ATA error */
310 #include "acpi/routing.asl"
316 if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */
318 if(CondRefOf(\_OSI,Local1))
320 Store(1, OSTP) /* Assume some form of XP */
321 if (\_OSI("Windows 2006")) /* Vista */
326 If(WCMP(\_OS,"Linux")) {
327 Store(3, OSTP) /* Linux */
329 Store(4, OSTP) /* Gotta be WinCE */
335 Method(_PIC, 0x01, NotSerialized)
343 Method(CIRQ, 0x00, NotSerialized){
354 Name(IRQB, ResourceTemplate(){
355 IRQ(Level,ActiveLow,Shared){15}
358 Name(IRQP, ResourceTemplate(){
359 IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
362 Name(PITF, ResourceTemplate(){
363 IRQ(Level,ActiveLow,Exclusive){9}
367 Name(_HID, EISAID("PNP0C0F"))
372 Return(0x0B) /* sata is invisible */
374 Return(0x09) /* sata is disabled */
376 } /* End Method(_SB.INTA._STA) */
379 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
381 } /* End Method(_SB.INTA._DIS) */
384 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
386 } /* Method(_SB.INTA._PRS) */
389 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
390 CreateWordField(IRQB, 0x1, IRQN)
391 ShiftLeft(1, PIRA, IRQN)
393 } /* Method(_SB.INTA._CRS) */
396 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
397 CreateWordField(ARG0, 1, IRQM)
399 /* Use lowest available IRQ */
400 FindSetRightBit(IRQM, Local0)
404 //Store(Local0, PIRA)
405 } /* End Method(_SB.INTA._SRS) */
406 } /* End Device(INTA) */
409 Name(_HID, EISAID("PNP0C0F"))
414 Return(0x0B) /* sata is invisible */
416 Return(0x09) /* sata is disabled */
418 } /* End Method(_SB.INTB._STA) */
421 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
423 } /* End Method(_SB.INTB._DIS) */
426 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
428 } /* Method(_SB.INTB._PRS) */
431 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
432 CreateWordField(IRQB, 0x1, IRQN)
433 ShiftLeft(1, PIRB, IRQN)
435 } /* Method(_SB.INTB._CRS) */
438 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
439 CreateWordField(ARG0, 1, IRQM)
441 /* Use lowest available IRQ */
442 FindSetRightBit(IRQM, Local0)
447 } /* End Method(_SB.INTB._SRS) */
448 } /* End Device(INTB) */
451 Name(_HID, EISAID("PNP0C0F"))
456 Return(0x0B) /* sata is invisible */
458 Return(0x09) /* sata is disabled */
460 } /* End Method(_SB.INTC._STA) */
463 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
465 } /* End Method(_SB.INTC._DIS) */
468 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
470 } /* Method(_SB.INTC._PRS) */
473 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
474 CreateWordField(IRQB, 0x1, IRQN)
475 ShiftLeft(1, PIRC, IRQN)
477 } /* Method(_SB.INTC._CRS) */
480 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
481 CreateWordField(ARG0, 1, IRQM)
483 /* Use lowest available IRQ */
484 FindSetRightBit(IRQM, Local0)
489 } /* End Method(_SB.INTC._SRS) */
490 } /* End Device(INTC) */
493 Name(_HID, EISAID("PNP0C0F"))
498 Return(0x0B) /* sata is invisible */
500 Return(0x09) /* sata is disabled */
502 } /* End Method(_SB.INTD._STA) */
505 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
507 } /* End Method(_SB.INTD._DIS) */
510 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
512 } /* Method(_SB.INTD._PRS) */
515 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
516 CreateWordField(IRQB, 0x1, IRQN)
517 ShiftLeft(1, PIRD, IRQN)
519 } /* Method(_SB.INTD._CRS) */
522 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
523 CreateWordField(ARG0, 1, IRQM)
525 /* Use lowest available IRQ */
526 FindSetRightBit(IRQM, Local0)
531 } /* End Method(_SB.INTD._SRS) */
532 } /* End Device(INTD) */
535 Name(_HID, EISAID("PNP0C0F"))
540 Return(0x0B) /* sata is invisible */
542 Return(0x09) /* sata is disabled */
544 } /* End Method(_SB.INTE._STA) */
547 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
549 } /* End Method(_SB.INTE._DIS) */
552 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
554 } /* Method(_SB.INTE._PRS) */
557 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
558 CreateWordField(IRQB, 0x1, IRQN)
559 ShiftLeft(1, PIRE, IRQN)
561 } /* Method(_SB.INTE._CRS) */
564 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
565 CreateWordField(ARG0, 1, IRQM)
567 /* Use lowest available IRQ */
568 FindSetRightBit(IRQM, Local0)
573 } /* End Method(_SB.INTE._SRS) */
574 } /* End Device(INTE) */
577 Name(_HID, EISAID("PNP0C0F"))
582 Return(0x0B) /* sata is invisible */
584 Return(0x09) /* sata is disabled */
586 } /* End Method(_SB.INTF._STA) */
589 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
591 } /* End Method(_SB.INTF._DIS) */
594 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
596 } /* Method(_SB.INTF._PRS) */
599 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
600 CreateWordField(IRQB, 0x1, IRQN)
601 ShiftLeft(1, PIRF, IRQN)
603 } /* Method(_SB.INTF._CRS) */
606 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
607 CreateWordField(ARG0, 1, IRQM)
609 /* Use lowest available IRQ */
610 FindSetRightBit(IRQM, Local0)
615 } /* End Method(_SB.INTF._SRS) */
616 } /* End Device(INTF) */
619 Name(_HID, EISAID("PNP0C0F"))
624 Return(0x0B) /* sata is invisible */
626 Return(0x09) /* sata is disabled */
628 } /* End Method(_SB.INTG._STA) */
631 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
633 } /* End Method(_SB.INTG._DIS) */
636 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
638 } /* Method(_SB.INTG._CRS) */
641 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
642 CreateWordField(IRQB, 0x1, IRQN)
643 ShiftLeft(1, PIRG, IRQN)
645 } /* Method(_SB.INTG._CRS) */
648 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
649 CreateWordField(ARG0, 1, IRQM)
651 /* Use lowest available IRQ */
652 FindSetRightBit(IRQM, Local0)
657 } /* End Method(_SB.INTG._SRS) */
658 } /* End Device(INTG) */
661 Name(_HID, EISAID("PNP0C0F"))
666 Return(0x0B) /* sata is invisible */
668 Return(0x09) /* sata is disabled */
670 } /* End Method(_SB.INTH._STA) */
673 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
675 } /* End Method(_SB.INTH._DIS) */
678 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
680 } /* Method(_SB.INTH._CRS) */
683 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
684 CreateWordField(IRQB, 0x1, IRQN)
685 ShiftLeft(1, PIRH, IRQN)
687 } /* Method(_SB.INTH._CRS) */
690 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
691 CreateWordField(ARG0, 1, IRQM)
693 /* Use lowest available IRQ */
694 FindSetRightBit(IRQM, Local0)
698 //Store(Local0, PIRH)
699 } /* End Method(_SB.INTH._SRS) */
700 } /* End Device(INTH) */
702 } /* End Scope(_SB) */
704 /* Supported sleep states: */
705 Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
707 If (LAnd(SSFG, 0x01)) {
708 Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
710 If (LAnd(SSFG, 0x02)) {
711 Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
713 If (LAnd(SSFG, 0x04)) {
714 Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
716 If (LAnd(SSFG, 0x08)) {
717 Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
720 Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
722 Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
723 Name(CSMS, 0) /* Current System State */
725 /* Wake status package */
726 Name(WKST,Package(){Zero, Zero})
729 * \_PTS - Prepare to Sleep method
732 * Arg0=The value of the sleeping state S1=1, S2=2, etc
737 * The _PTS control method is executed at the beginning of the sleep process
738 * for S1-S5. The sleeping value is passed to the _PTS control method. This
739 * control method may be executed a relatively long time before entering the
740 * sleep state and the OS may abort the operation without notification to
741 * the ACPI driver. This method cannot modify the configuration or power
742 * state of any device in the system.
745 /* DBGO("\\_PTS\n") */
746 /* DBGO("From S0 to S") */
750 /* Don't allow PCIRST# to reset USB */
751 //if (LEqual(Arg0,3)){
755 /* Clear sleep SMI status flag and enable sleep SMI trap. */
759 /* On older chips, clear PciExpWakeDisEn */
760 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
765 /* Clear wake status structure. */
766 Store(0, Index(WKST,0))
767 Store(0, Index(WKST,1))
769 } /* End Method(\_PTS) */
772 * The following method results in a "not a valid reserved NameSeg"
773 * warning so I have commented it out for the duration. It isn't
774 * used, so it could be removed.
777 * \_GTS OEM Going To Sleep method
780 * Arg0=The value of the sleeping state S1=1, S2=2
787 * DBGO("From S0 to S")
794 * \_BFS OEM Back From Sleep method
797 * Arg0=The value of the sleeping state S1=1, S2=2
803 /* DBGO("\\_BFS\n") */
806 /* DBGO(" to S0\n") */
810 * \_WAK System Wake method
813 * Arg0=The value of the sleeping state S1=1, S2=2
816 * Return package of 2 DWords
818 * 0x00000000 wake succeeded
819 * 0x00000001 Wake was signaled but failed due to lack of power
820 * 0x00000002 Wake was signaled but failed due to thermal condition
821 * Dword 2 - Power Supply state
822 * if non-zero the effective S-state the power supply entered
825 /* DBGO("\\_WAK\n") */
828 /* DBGO(" to S0\n") */
833 /* Restore PCIRST# so it resets USB */
834 //if (LEqual(Arg0,3)){
838 /* Arbitrarily clear PciExpWakeStatus */
841 /* if(DeRefOf(Index(WKST,0))) {
842 * Store(0, Index(WKST,1))
844 * Store(Arg0, Index(WKST,1))
848 } /* End Method(\_WAK) */
850 Scope(\_GPE) { /* Start Scope GPE */
851 /* General event 0 */
853 * DBGO("\\_GPE\\_L00\n")
857 /* General event 1 */
859 * DBGO("\\_GPE\\_L00\n")
863 /* General event 2 */
865 * DBGO("\\_GPE\\_L00\n")
869 /* General event 3 */
871 /* DBGO("\\_GPE\\_L00\n") */
872 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
875 /* General event 4 */
877 * DBGO("\\_GPE\\_L00\n")
881 /* General event 5 */
883 * DBGO("\\_GPE\\_L00\n")
887 /* General event 6 - Used for GPM6, moved to USB.asl */
889 * DBGO("\\_GPE\\_L00\n")
893 /* General event 7 - Used for GPM7, moved to USB.asl */
895 * DBGO("\\_GPE\\_L07\n")
899 /* Legacy PM event */
901 /* DBGO("\\_GPE\\_L08\n") */
904 /* Temp warning (TWarn) event */
906 /* DBGO("\\_GPE\\_L09\n") */
907 /* Notify (\_TZ.TZ00, 0x80) */
912 * DBGO("\\_GPE\\_L0A\n")
916 /* USB controller PME# */
918 /* DBGO("\\_GPE\\_L0B\n") */
919 Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
920 Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
921 Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
922 Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
923 Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
924 Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
925 Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
926 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
929 /* AC97 controller PME# */
931 * DBGO("\\_GPE\\_L0C\n")
935 /* OtherTherm PME# */
937 * DBGO("\\_GPE\\_L0D\n")
941 /* GPM9 SCI event - Moved to USB.asl */
943 * DBGO("\\_GPE\\_L0E\n")
947 /* PCIe HotPlug event */
949 * DBGO("\\_GPE\\_L0F\n")
953 /* ExtEvent0 SCI event */
955 /* DBGO("\\_GPE\\_L10\n") */
958 /* ExtEvent1 SCI event */
960 /* DBGO("\\_GPE\\_L11\n") */
963 /* PCIe PME# event */
965 * DBGO("\\_GPE\\_L12\n")
969 /* GPM0 SCI event - Moved to USB.asl */
971 * DBGO("\\_GPE\\_L13\n")
975 /* GPM1 SCI event - Moved to USB.asl */
977 * DBGO("\\_GPE\\_L14\n")
981 /* GPM2 SCI event - Moved to USB.asl */
983 * DBGO("\\_GPE\\_L15\n")
987 /* GPM3 SCI event - Moved to USB.asl */
989 * DBGO("\\_GPE\\_L16\n")
993 /* GPM8 SCI event - Moved to USB.asl */
995 * DBGO("\\_GPE\\_L17\n")
999 /* GPIO0 or GEvent8 event */
1001 /* DBGO("\\_GPE\\_L18\n") */
1002 Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
1003 Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
1004 Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
1005 Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
1006 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1009 /* GPM4 SCI event - Moved to USB.asl */
1011 * DBGO("\\_GPE\\_L19\n")
1015 /* GPM5 SCI event - Moved to USB.asl */
1017 * DBGO("\\_GPE\\_L1A\n")
1021 /* Azalia SCI event */
1023 /* DBGO("\\_GPE\\_L1B\n") */
1024 Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
1025 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1028 /* GPM6 SCI event - Reassigned to _L06 */
1030 * DBGO("\\_GPE\\_L1C\n")
1034 /* GPM7 SCI event - Reassigned to _L07 */
1036 * DBGO("\\_GPE\\_L1D\n")
1040 /* GPIO2 or GPIO66 SCI event */
1042 * DBGO("\\_GPE\\_L1E\n")
1046 /* SATA SCI event - Moved to sata.asl */
1048 * DBGO("\\_GPE\\_L1F\n")
1052 } /* End Scope GPE */
1054 //#include "acpi/usb.asl"
1057 Scope(\_SB) { /* Start \_SB scope */
1058 #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
1061 /* Note: Only need HID on Primary Bus */
1065 Name(_HID, EISAID("PNP0A03"))
1066 Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
1067 Method(_BBN, 0) { /* Bus number = 0 */
1071 /* DBGO("\\_SB\\PCI0\\_STA\n") */
1072 Return(0x0B) /* Status is visible */
1076 If(PMOD){ Return(APR0) } /* APIC mode */
1077 Return (PR0) /* PIC Mode */
1080 /* Describe the Northbridge devices Dev0 ,Func0*/
1082 Name(_ADR, 0x00000000)
1085 #if 0 //not used in Parmer
1086 /* Dev3 is also an external GFX bridge */
1088 Name(_ADR, 0x00030000)
1089 Name(_PRW, Package() {0x18, 4})
1091 If(PMOD){ Return(APS3) } /* APIC mode */
1092 Return (PS3) /* PIC Mode */
1098 Name(_ADR, 0x00040000)
1099 Name(_PRW, Package() {0x18, 4})
1101 If(PMOD){ Return(APS4) } /* APIC mode */
1102 Return (PS4) /* PIC Mode */
1107 Name(_ADR, 0x00050000)
1108 Name(_PRW, Package() {0x18, 4})
1110 If(PMOD){ Return(APS5) } /* APIC mode */
1111 Return (PS5) /* PIC Mode */
1116 Name(_ADR, 0x00060000)
1117 Name(_PRW, Package() {0x18, 4})
1119 If(PMOD){ Return(APS6) } /* APIC mode */
1120 Return (PS6) /* PIC Mode */
1124 /* The onboard EtherNet chip */
1126 Name(_ADR, 0x00070000)
1127 Name(_PRW, Package() {0x18, 4})
1129 If(PMOD){ Return(APS7) } /* APIC mode */
1130 Return (PS7) /* PIC Mode */
1134 /* PCI slot 1, 2, 3 */
1136 Name(_ADR, 0x00140004)
1137 Name(_PRW, Package() {0x18, 4})
1144 /* Describe the Southbridge devices */
1146 Name(_ADR, 0x00110000)
1147 //#include "acpi/sata.asl"
1151 Name(_ADR, 0x00120000)
1152 Name(_PRW, Package() {0x0B, 3})
1156 Name(_ADR, 0x00120002)
1157 Name(_PRW, Package() {0x0B, 3})
1161 Name(_ADR, 0x00130000)
1162 Name(_PRW, Package() {0x0B, 3})
1166 Name(_ADR, 0x00130002)
1167 Name(_PRW, Package() {0x0B, 3})
1171 Name(_ADR, 0x00160000)
1172 Name(_PRW, Package() {0x0B, 3})
1176 Name(_ADR, 0x00160002)
1177 Name(_PRW, Package() {0x0B, 3})
1181 Name(_ADR, 0x00140005)
1182 Name(_PRW, Package() {0x0B, 3})
1186 Name(_ADR, 0x00100000)
1187 Name(_PRW, Package() {0x0B, 4})
1190 Name(_ADR, 0x00100001)
1191 Name(_PRW, Package() {0x0B, 4})
1195 Name(_ADR, 0x00140000)
1198 /* Primary (and only) IDE channel */
1200 Name(_ADR, 0x00140001)
1201 //#include "acpi/ide.asl"
1205 Name(_ADR, 0x00140002)
1206 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
1207 Field(AZPD, AnyAcc, NoLock, Preserve) {
1231 If(LEqual(OSTP,3)){ /* If we are running Linux */
1240 Name(_ADR, 0x00140003)
1242 * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
1243 } */ /* End Method(_SB.SBRDG._INI) */
1245 /* Real Time Clock Device */
1247 Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
1248 Name(_CRS, ResourceTemplate() {
1250 IO(Decode16,0x0070, 0x0070, 0, 2)
1251 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
1253 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
1255 Device(TMR) { /* Timer */
1256 Name(_HID,EISAID("PNP0100")) /* System Timer */
1257 Name(_CRS, ResourceTemplate() {
1259 IO(Decode16, 0x0040, 0x0040, 0, 4)
1260 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
1262 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1264 Device(SPKR) { /* Speaker */
1265 Name(_HID,EISAID("PNP0800")) /* AT style speaker */
1266 Name(_CRS, ResourceTemplate() {
1267 IO(Decode16, 0x0061, 0x0061, 0, 1)
1269 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1272 Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
1273 Name(_CRS, ResourceTemplate() {
1275 IO(Decode16,0x0020, 0x0020, 0, 2)
1276 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1277 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1278 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1280 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1282 Device(MAD) { /* 8257 DMA */
1283 Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
1284 Name(_CRS, ResourceTemplate() {
1285 DMA(Compatibility,BusMaster,Transfer8){4}
1286 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1287 IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
1288 IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
1289 IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
1290 IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
1291 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1292 }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1293 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1296 Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
1297 Name(_CRS, ResourceTemplate() {
1298 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1301 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1305 Name(_ADR, 0x00140004)
1306 } /* end HostPciBr */
1309 Name(_ADR, 0x00140005)
1310 } /* end Ac97audio */
1313 Name(_ADR, 0x00140006)
1314 } /* end Ac97modem */
1316 Name(CRES, ResourceTemplate() {
1317 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1319 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1320 0x0000, /* address granularity */
1321 0x0000, /* range minimum */
1322 0x0CF7, /* range maximum */
1323 0x0000, /* translation */
1326 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1327 0x0000, /* address granularity */
1328 0x03B0, /* range minimum */
1329 0x03DF, /* range maximum */
1330 0x0000, /* translation */
1334 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1335 0x0000, /* address granularity */
1336 0x0D00, /* range minimum */
1337 0xFFFF, /* range maximum */
1338 0x0000, /* translation */
1342 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
1343 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
1344 /* memory space for PCI BARs below 4GB */
1345 Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
1346 }) /* End Name(_SB.PCI0.CRES) */
1349 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1350 CreateDWordField(CRES, ^MMIO._BAS, MM1B)
1351 CreateDWordField(CRES, ^MMIO._LEN, MM1L)
1353 * Declare memory between TOM1 and 4GB as available
1355 * Use ShiftLeft to avoid 64bit constant (for XP).
1356 * This will work even if the OS does 32bit arithmetic, as
1357 * 32bit (0x00000000 - TOM1) will wrap and give the same
1358 * result as 64bit (0x100000000 - TOM1).
1361 ShiftLeft(0x10000000, 4, Local0)
1362 Subtract(Local0, TOM1, Local0)
1365 Return(CRES) /* note to change the Name buffer */
1366 } /* end of Method(_SB.PCI0._CRS) */
1370 * FIRST METHOD CALLED UPON BOOT
1372 * 1. If debugging, print current OS and ACPI interpreter.
1373 * 2. Get PCI Interrupt routing from ACPI VSM, this
1374 * value is based on user choice in BIOS setup.
1377 /* DBGO("\\_SB\\_INI\n") */
1378 /* DBGO(" DSDT.ASL code from ") */
1379 /* DBGO(__DATE__) */
1381 /* DBGO(__TIME__) */
1382 /* DBGO("\n Sleep states supported: ") */
1384 /* DBGO(" \\_OS=") */
1386 /* DBGO("\n \\_REV=") */
1390 /* Determine the OS we're running on */
1393 /* On older chips, clear PciExpWakeDisEn */
1394 /*if (LLessEqual(\SBRI, 0x13)) {
1398 /* TODO: It is unstable. */
1399 //#include "acpi/AmdImc.asl" /* Hudson IMC function */
1400 //ITZE() /* enable IMC Fan Control*/
1401 } /* End Method(_SB._INI) */
1402 } /* End Device(PCI0) */
1404 Device(PWRB) { /* Start Power button device */
1405 Name(_HID, EISAID("PNP0C0C"))
1407 Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
1408 Name(_STA, 0x0B) /* sata is invisible */
1410 } /* End \_SB scope */
1414 /* DBGO("\\_SI\\_SST\n") */
1415 /* DBGO(" New Indicator state: ") */
1419 } /* End Scope SI */
1421 /* End of ASL file */